BEGIN radio_controller

## Peripheral Options
OPTION IPTYPE = PERIPHERAL
OPTION IMP_NETLIST = TRUE
OPTION HDL = MIXED
OPTION IP_GROUP = MICROBLAZE:PPC:USER
OPTION DESC = "WARP Radio Controller (PLB46)"
OPTION USAGE_LEVEL = BASE_USER #Enable this core in base system builder

IO_INTERFACE IO_IF = radio_controller_ports, IO_TYPE = WARP_RADIOCONTROLLER_V1

## Bus Interfaces
BUS_INTERFACE BUS = SPLB, BUS_TYPE = SLAVE, BUS_STD = PLBV46
BUS_INTERFACE BUS = RC2RB_RAD1, BUS_STD = WARP_RC2RB_V1, BUS_TYPE = INITIATOR
BUS_INTERFACE BUS = RC2RB_RAD2, BUS_STD = WARP_RC2RB_V1, BUS_TYPE = INITIATOR
BUS_INTERFACE BUS = RC2RB_RAD3, BUS_STD = WARP_RC2RB_V1, BUS_TYPE = INITIATOR
BUS_INTERFACE BUS = RC2RB_RAD4, BUS_STD = WARP_RC2RB_V1, BUS_TYPE = INITIATOR

## Generics for VHDL or Parameters for Verilog
PARAMETER C_BASEADDR = 0xffffffff, DT = std_logic_vector, MIN_SIZE = 0x100, BUS = SPLB, ADDRESS = BASE, PAIR = C_HIGHADDR
PARAMETER C_HIGHADDR = 0x00000000, DT = std_logic_vector, BUS = SPLB, ADDRESS = HIGH, PAIR = C_BASEADDR
PARAMETER C_SPLB_AWIDTH = 32, DT = INTEGER, BUS = SPLB, ASSIGNMENT = CONSTANT
PARAMETER C_SPLB_DWIDTH = 128, DT = INTEGER, BUS = SPLB, RANGE = (32, 64, 128)
PARAMETER C_SPLB_NUM_MASTERS = 8, DT = INTEGER, BUS = SPLB, RANGE = (1:16)
PARAMETER C_SPLB_MID_WIDTH = 3, DT = INTEGER, BUS = SPLB, RANGE = (1:4)
PARAMETER C_SPLB_NATIVE_DWIDTH = 32, DT = INTEGER, BUS = SPLB, RANGE = (32, 64, 128), ASSIGNMENT = CONSTANT
PARAMETER C_SPLB_P2P = 0, DT = INTEGER, BUS = SPLB, RANGE = (0, 1)
PARAMETER C_SPLB_SUPPORT_BURSTS = 0, DT = INTEGER, BUS = SPLB, RANGE = (0, 1), ASSIGNMENT = CONSTANT
PARAMETER C_SPLB_SMALLEST_MASTER = 32, DT = INTEGER, BUS = SPLB, RANGE = (32, 64, 128)
PARAMETER C_SPLB_CLK_PERIOD_PS = 10000, DT = INTEGER, BUS = SPLB
PARAMETER C_FAMILY = virtex4, DT = STRING

## Ports
PORT SPLB_Clk = "", DIR = I, SIGIS = CLK, BUS = SPLB
PORT SPLB_Rst = SPLB_Rst, DIR = I, SIGIS = RST, BUS = SPLB
PORT PLB_ABus = PLB_ABus, DIR = I, VEC = [0:31], BUS = SPLB
PORT PLB_UABus = PLB_UABus, DIR = I, VEC = [0:31], BUS = SPLB
PORT PLB_PAValid = PLB_PAValid, DIR = I, BUS = SPLB
PORT PLB_SAValid = PLB_SAValid, DIR = I, BUS = SPLB
PORT PLB_rdPrim = PLB_rdPrim, DIR = I, BUS = SPLB
PORT PLB_wrPrim = PLB_wrPrim, DIR = I, BUS = SPLB
PORT PLB_masterID = PLB_masterID, DIR = I, VEC = [0:(C_SPLB_MID_WIDTH-1)], BUS = SPLB
PORT PLB_abort = PLB_abort, DIR = I, BUS = SPLB
PORT PLB_busLock = PLB_busLock, DIR = I, BUS = SPLB
PORT PLB_RNW = PLB_RNW, DIR = I, BUS = SPLB
PORT PLB_BE = PLB_BE, DIR = I, VEC = [0:((C_SPLB_DWIDTH/8)-1)], BUS = SPLB
PORT PLB_MSize = PLB_MSize, DIR = I, VEC = [0:1], BUS = SPLB
PORT PLB_size = PLB_size, DIR = I, VEC = [0:3], BUS = SPLB
PORT PLB_type = PLB_type, DIR = I, VEC = [0:2], BUS = SPLB
PORT PLB_lockErr = PLB_lockErr, DIR = I, BUS = SPLB
PORT PLB_wrDBus = PLB_wrDBus, DIR = I, VEC = [0:(C_SPLB_DWIDTH-1)], BUS = SPLB
PORT PLB_wrBurst = PLB_wrBurst, DIR = I, BUS = SPLB
PORT PLB_rdBurst = PLB_rdBurst, DIR = I, BUS = SPLB
PORT PLB_wrPendReq = PLB_wrPendReq, DIR = I, BUS = SPLB
PORT PLB_rdPendReq = PLB_rdPendReq, DIR = I, BUS = SPLB
PORT PLB_wrPendPri = PLB_wrPendPri, DIR = I, VEC = [0:1], BUS = SPLB
PORT PLB_rdPendPri = PLB_rdPendPri, DIR = I, VEC = [0:1], BUS = SPLB
PORT PLB_reqPri = PLB_reqPri, DIR = I, VEC = [0:1], BUS = SPLB
PORT PLB_TAttribute = PLB_TAttribute, DIR = I, VEC = [0:15], BUS = SPLB
PORT Sl_addrAck = Sl_addrAck, DIR = O, BUS = SPLB
PORT Sl_SSize = Sl_SSize, DIR = O, VEC = [0:1], BUS = SPLB
PORT Sl_wait = Sl_wait, DIR = O, BUS = SPLB
PORT Sl_rearbitrate = Sl_rearbitrate, DIR = O, BUS = SPLB
PORT Sl_wrDAck = Sl_wrDAck, DIR = O, BUS = SPLB
PORT Sl_wrComp = Sl_wrComp, DIR = O, BUS = SPLB
PORT Sl_wrBTerm = Sl_wrBTerm, DIR = O, BUS = SPLB
PORT Sl_rdDBus = Sl_rdDBus, DIR = O, VEC = [0:(C_SPLB_DWIDTH-1)], BUS = SPLB
PORT Sl_rdWdAddr = Sl_rdWdAddr, DIR = O, VEC = [0:3], BUS = SPLB
PORT Sl_rdDAck = Sl_rdDAck, DIR = O, BUS = SPLB
PORT Sl_rdComp = Sl_rdComp, DIR = O, BUS = SPLB
PORT Sl_rdBTerm = Sl_rdBTerm, DIR = O, BUS = SPLB
PORT Sl_MBusy = Sl_MBusy, DIR = O, VEC = [0:(C_SPLB_NUM_MASTERS-1)], BUS = SPLB
PORT Sl_MWrErr = Sl_MWrErr, DIR = O, VEC = [0:(C_SPLB_NUM_MASTERS-1)], BUS = SPLB
PORT Sl_MRdErr = Sl_MRdErr, DIR = O, VEC = [0:(C_SPLB_NUM_MASTERS-1)], BUS = SPLB
PORT Sl_MIRQ = Sl_MIRQ, DIR = O, VEC = [0:(C_SPLB_NUM_MASTERS-1)], BUS = SPLB


#Copy of PLB clock, driven out to radio_bridges
# (which need the clock to stay synchronous with the radio_controller, but aren't otherwise attached to the PLB)
PORT controller_logic_clk1 = "controller_logic_clk", DIR = O, BUS = RC2RB_RAD1
PORT controller_logic_clk2 = "controller_logic_clk", DIR = O, BUS = RC2RB_RAD2
PORT controller_logic_clk3 = "controller_logic_clk", DIR = O, BUS = RC2RB_RAD3
PORT controller_logic_clk4 = "controller_logic_clk", DIR = O, BUS = RC2RB_RAD4

#SPI clock and data outputs, shared by all radio_bridges
PORT spi_clk1 = "controller_spi_clk", DIR = O, BUS = RC2RB_RAD1
PORT spi_clk2 = "controller_spi_clk", DIR = O, BUS = RC2RB_RAD2
PORT spi_clk3 = "controller_spi_clk", DIR = O, BUS = RC2RB_RAD3
PORT spi_clk4 = "controller_spi_clk", DIR = O, BUS = RC2RB_RAD4

PORT data_out1 = "controller_spi_data", DIR = O, BUS = RC2RB_RAD1
PORT data_out2 = "controller_spi_data", DIR = O, BUS = RC2RB_RAD2
PORT data_out3 = "controller_spi_data", DIR = O, BUS = RC2RB_RAD3
PORT data_out4 = "controller_spi_data", DIR = O, BUS = RC2RB_RAD4

PORT radio1_cs = "controller_radio_cs", DIR = O, BUS = RC2RB_RAD1
PORT dac1_cs = "controller_dac_cs", DIR = O, BUS = RC2RB_RAD1
PORT radio1_SHDN = "controller_SHDN", DIR = O, BUS = RC2RB_RAD1
PORT radio1_TxEn = "controller_TxEn", DIR = O, BUS = RC2RB_RAD1
PORT radio1_RxEn = "controller_RxEn", DIR = O, BUS = RC2RB_RAD1
PORT radio1_RxHP = "controller_RxHP", DIR = O, BUS = RC2RB_RAD1
PORT radio1_24PA = "controller_24PA", DIR = O, BUS = RC2RB_RAD1
PORT radio1_5PA = "controller_5PA", DIR = O, BUS = RC2RB_RAD1
PORT radio1_ANTSW = "controller_ANTSW", DIR = O, VEC = [0:1], BUS = RC2RB_RAD1
PORT radio1_LED = "controller_LED", DIR = O, VEC = [0:2], BUS = RC2RB_RAD1
PORT radio1_ADC_RX_DCS = "controller_RX_ADC_DCS", DIR = O, BUS = RC2RB_RAD1
PORT radio1_ADC_RX_DFS = "controller_RX_ADC_DFS", DIR = O, BUS = RC2RB_RAD1
PORT radio1_ADC_RX_OTRA = "controller_RX_ADC_OTRA", DIR = I, BUS = RC2RB_RAD1
PORT radio1_ADC_RX_OTRB = "controller_RX_ADC_OTRB", DIR = I, BUS = RC2RB_RAD1
PORT radio1_ADC_RX_PWDNA = "controller_RX_ADC_PWDNA", DIR = O, BUS = RC2RB_RAD1
PORT radio1_ADC_RX_PWDNB = "controller_RX_ADC_PWDNB", DIR = O, BUS = RC2RB_RAD1
PORT radio1_DIPSW = "controller_DIPSW", DIR = I, VEC = [0:3], BUS = RC2RB_RAD1
PORT radio1_RSSI_ADC_CLAMP = "controller_RSSI_ADC_CLAMP", DIR = O, BUS = RC2RB_RAD1
PORT radio1_RSSI_ADC_HIZ = "controller_RSSI_ADC_HIZ", DIR = O, BUS = RC2RB_RAD1
PORT radio1_RSSI_ADC_OTR = "controller_RSSI_ADC_OTR", DIR = I, BUS = RC2RB_RAD1
PORT radio1_RSSI_ADC_SLEEP = "controller_RSSI_ADC_SLEEP", DIR = O, BUS = RC2RB_RAD1
PORT radio1_RSSI_ADC_D = "controller_RSSI_ADC_D", DIR = I, VEC = [0:9], BUS = RC2RB_RAD1
PORT radio1_LD = "controller_LD", DIR = I, BUS = RC2RB_RAD1
PORT radio1_TX_DAC_PLL_LOCK = "controller_DAC_PLL_LOCK", DIR = I, BUS = RC2RB_RAD1
PORT radio1_TX_DAC_RESET = "controller_DAC_RESET", DIR = O, BUS = RC2RB_RAD1
PORT radio1_SHDN_external = "controller_SHDN_external", DIR = I, BUS = RC2RB_RAD1
PORT radio1_TxEn_external = "controller_TxEn_external", DIR = I, BUS = RC2RB_RAD1
PORT radio1_RxEn_external = "controller_RxEn_external", DIR = I, BUS = RC2RB_RAD1
PORT radio1_RxHP_external = "controller_RxHP_external", DIR = I, BUS = RC2RB_RAD1
PORT radio1_TxStart = "controller_TxStart", DIR = O, BUS = RC2RB_RAD1
PORT radio1_TxGain = "controller_Tx_gain", DIR = O, VEC = [0:5], BUS = RC2RB_RAD1

PORT radio2_cs = "controller_radio_cs", DIR = O, BUS = RC2RB_RAD2
PORT dac2_cs = "controller_dac_cs", DIR = O, BUS = RC2RB_RAD2
PORT radio2_SHDN = "controller_SHDN", DIR = O, BUS = RC2RB_RAD2
PORT radio2_TxEn = "controller_TxEn", DIR = O, BUS = RC2RB_RAD2
PORT radio2_RxEn = "controller_RxEn", DIR = O, BUS = RC2RB_RAD2
PORT radio2_RxHP = "controller_RxHP", DIR = O, BUS = RC2RB_RAD2
PORT radio2_24PA = "controller_24PA", DIR = O, BUS = RC2RB_RAD2
PORT radio2_5PA = "controller_5PA", DIR = O, BUS = RC2RB_RAD2
PORT radio2_ANTSW = "controller_ANTSW", DIR = O, VEC = [0:1], BUS = RC2RB_RAD2
PORT radio2_LED = "controller_LED", DIR = O, VEC = [0:2], BUS = RC2RB_RAD2
PORT radio2_ADC_RX_DCS = "controller_RX_ADC_DCS", DIR = O, BUS = RC2RB_RAD2
PORT radio2_ADC_RX_DFS = "controller_RX_ADC_DFS", DIR = O, BUS = RC2RB_RAD2
PORT radio2_ADC_RX_OTRA = "controller_RX_ADC_OTRA", DIR = I, BUS = RC2RB_RAD2
PORT radio2_ADC_RX_OTRB = "controller_RX_ADC_OTRB", DIR = I, BUS = RC2RB_RAD2
PORT radio2_ADC_RX_PWDNA = "controller_RX_ADC_PWDNA", DIR = O, BUS = RC2RB_RAD2
PORT radio2_ADC_RX_PWDNB = "controller_RX_ADC_PWDNB", DIR = O, BUS = RC2RB_RAD2
PORT radio2_DIPSW = "controller_DIPSW", DIR = I, VEC = [0:3], BUS = RC2RB_RAD2
PORT radio2_RSSI_ADC_CLAMP = "controller_RSSI_ADC_CLAMP", DIR = O, BUS = RC2RB_RAD2
PORT radio2_RSSI_ADC_HIZ = "controller_RSSI_ADC_HIZ", DIR = O, BUS = RC2RB_RAD2
PORT radio2_RSSI_ADC_OTR = "controller_RSSI_ADC_OTR", DIR = I, BUS = RC2RB_RAD2
PORT radio2_RSSI_ADC_SLEEP = "controller_RSSI_ADC_SLEEP", DIR = O, BUS = RC2RB_RAD2
PORT radio2_RSSI_ADC_D = "controller_RSSI_ADC_D", DIR = I, VEC = [0:9], BUS = RC2RB_RAD2
PORT radio2_LD = "controller_LD", DIR = I, BUS = RC2RB_RAD2
PORT radio2_TX_DAC_PLL_LOCK = "controller_DAC_PLL_LOCK", DIR = I, BUS = RC2RB_RAD2
PORT radio2_TX_DAC_RESET = "controller_DAC_RESET", DIR = O, BUS = RC2RB_RAD2
PORT radio2_SHDN_external = "controller_SHDN_external", DIR = I, BUS = RC2RB_RAD2
PORT radio2_TxEn_external = "controller_TxEn_external", DIR = I, BUS = RC2RB_RAD2
PORT radio2_RxEn_external = "controller_RxEn_external", DIR = I, BUS = RC2RB_RAD2
PORT radio2_RxHP_external = "controller_RxHP_external", DIR = I, BUS = RC2RB_RAD2
PORT radio2_TxStart = "controller_TxStart", DIR = O, BUS = RC2RB_RAD2
PORT radio2_TxGain = "controller_Tx_gain", DIR = O, VEC = [0:5], BUS = RC2RB_RAD2

PORT radio3_cs = "controller_radio_cs", DIR = O, BUS = RC2RB_RAD3
PORT dac3_cs = "controller_dac_cs", DIR = O, BUS = RC2RB_RAD3
PORT radio3_SHDN = "controller_SHDN", DIR = O, BUS = RC2RB_RAD3
PORT radio3_TxEn = "controller_TxEn", DIR = O, BUS = RC2RB_RAD3
PORT radio3_RxEn = "controller_RxEn", DIR = O, BUS = RC2RB_RAD3
PORT radio3_RxHP = "controller_RxHP", DIR = O, BUS = RC2RB_RAD3
PORT radio3_24PA = "controller_24PA", DIR = O, BUS = RC2RB_RAD3
PORT radio3_5PA = "controller_5PA", DIR = O, BUS = RC2RB_RAD3
PORT radio3_ANTSW = "controller_ANTSW", DIR = O, VEC = [0:1], BUS = RC2RB_RAD3
PORT radio3_LED = "controller_LED", DIR = O, VEC = [0:2], BUS = RC2RB_RAD3
PORT radio3_ADC_RX_DCS = "controller_RX_ADC_DCS", DIR = O, BUS = RC2RB_RAD3
PORT radio3_ADC_RX_DFS = "controller_RX_ADC_DFS", DIR = O, BUS = RC2RB_RAD3
PORT radio3_ADC_RX_OTRA = "controller_RX_ADC_OTRA", DIR = I, BUS = RC2RB_RAD3
PORT radio3_ADC_RX_OTRB = "controller_RX_ADC_OTRB", DIR = I, BUS = RC2RB_RAD3
PORT radio3_ADC_RX_PWDNA = "controller_RX_ADC_PWDNA", DIR = O, BUS = RC2RB_RAD3
PORT radio3_ADC_RX_PWDNB = "controller_RX_ADC_PWDNB", DIR = O, BUS = RC2RB_RAD3
PORT radio3_DIPSW = "controller_DIPSW", DIR = I, VEC = [0:3], BUS = RC2RB_RAD3
PORT radio3_RSSI_ADC_CLAMP = "controller_RSSI_ADC_CLAMP", DIR = O, BUS = RC2RB_RAD3
PORT radio3_RSSI_ADC_HIZ = "controller_RSSI_ADC_HIZ", DIR = O, BUS = RC2RB_RAD3
PORT radio3_RSSI_ADC_OTR = "controller_RSSI_ADC_OTR", DIR = I, BUS = RC2RB_RAD3
PORT radio3_RSSI_ADC_SLEEP = "controller_RSSI_ADC_SLEEP", DIR = O, BUS = RC2RB_RAD3
PORT radio3_RSSI_ADC_D = "controller_RSSI_ADC_D", DIR = I, VEC = [0:9], BUS = RC2RB_RAD3
PORT radio3_LD = "controller_LD", DIR = I, BUS = RC2RB_RAD3
PORT radio3_TX_DAC_PLL_LOCK = "controller_DAC_PLL_LOCK", DIR = I, BUS = RC2RB_RAD3
PORT radio3_TX_DAC_RESET = "controller_DAC_RESET", DIR = O, BUS = RC2RB_RAD3
PORT radio3_SHDN_external = "controller_SHDN_external", DIR = I, BUS = RC2RB_RAD3
PORT radio3_TxEn_external = "controller_TxEn_external", DIR = I, BUS = RC2RB_RAD3
PORT radio3_RxEn_external = "controller_RxEn_external", DIR = I, BUS = RC2RB_RAD3
PORT radio3_RxHP_external = "controller_RxHP_external", DIR = I, BUS = RC2RB_RAD3
PORT radio3_TxStart = "controller_TxStart", DIR = O, BUS = RC2RB_RAD3
PORT radio3_TxGain = "controller_Tx_gain", DIR = O, VEC = [0:5], BUS = RC2RB_RAD3

PORT radio4_cs = "controller_radio_cs", DIR = O, BUS = RC2RB_RAD4
PORT dac4_cs = "controller_dac_cs", DIR = O, BUS = RC2RB_RAD4
PORT radio4_SHDN = "controller_SHDN", DIR = O, BUS = RC2RB_RAD4
PORT radio4_TxEn = "controller_TxEn", DIR = O, BUS = RC2RB_RAD4
PORT radio4_RxEn = "controller_RxEn", DIR = O, BUS = RC2RB_RAD4
PORT radio4_RxHP = "controller_RxHP", DIR = O, BUS = RC2RB_RAD4
PORT radio4_24PA = "controller_24PA", DIR = O, BUS = RC2RB_RAD4
PORT radio4_5PA = "controller_5PA", DIR = O, BUS = RC2RB_RAD4
PORT radio4_ANTSW = "controller_ANTSW", DIR = O, VEC = [0:1], BUS = RC2RB_RAD4
PORT radio4_LED = "controller_LED", DIR = O, VEC = [0:2], BUS = RC2RB_RAD4
PORT radio4_ADC_RX_DCS = "controller_RX_ADC_DCS", DIR = O, BUS = RC2RB_RAD4
PORT radio4_ADC_RX_DFS = "controller_RX_ADC_DFS", DIR = O, BUS = RC2RB_RAD4
PORT radio4_ADC_RX_OTRA = "controller_RX_ADC_OTRA", DIR = I, BUS = RC2RB_RAD4
PORT radio4_ADC_RX_OTRB = "controller_RX_ADC_OTRB", DIR = I, BUS = RC2RB_RAD4
PORT radio4_ADC_RX_PWDNA = "controller_RX_ADC_PWDNA", DIR = O, BUS = RC2RB_RAD4
PORT radio4_ADC_RX_PWDNB = "controller_RX_ADC_PWDNB", DIR = O, BUS = RC2RB_RAD4
PORT radio4_DIPSW = "controller_DIPSW", DIR = I, VEC = [0:3], BUS = RC2RB_RAD4
PORT radio4_RSSI_ADC_CLAMP = "controller_RSSI_ADC_CLAMP", DIR = O, BUS = RC2RB_RAD4
PORT radio4_RSSI_ADC_HIZ = "controller_RSSI_ADC_HIZ", DIR = O, BUS = RC2RB_RAD4
PORT radio4_RSSI_ADC_OTR = "controller_RSSI_ADC_OTR", DIR = I, BUS = RC2RB_RAD4
PORT radio4_RSSI_ADC_SLEEP = "controller_RSSI_ADC_SLEEP", DIR = O, BUS = RC2RB_RAD4
PORT radio4_RSSI_ADC_D = "controller_RSSI_ADC_D", DIR = I, VEC = [0:9], BUS = RC2RB_RAD4
PORT radio4_LD = "controller_LD", DIR = I, BUS = RC2RB_RAD4
PORT radio4_TX_DAC_PLL_LOCK = "controller_DAC_PLL_LOCK", DIR = I, BUS = RC2RB_RAD4
PORT radio4_TX_DAC_RESET = "controller_DAC_RESET", DIR = O, BUS = RC2RB_RAD4
PORT radio4_SHDN_external = "controller_SHDN_external", DIR = I, BUS = RC2RB_RAD4
PORT radio4_TxEn_external = "controller_TxEn_external", DIR = I, BUS = RC2RB_RAD4
PORT radio4_RxEn_external = "controller_RxEn_external", DIR = I, BUS = RC2RB_RAD4
PORT radio4_RxHP_external = "controller_RxHP_external", DIR = I, BUS = RC2RB_RAD4
PORT radio4_TxStart = "controller_TxStart", DIR = O, BUS = RC2RB_RAD4
PORT radio4_TxGain = "controller_Tx_gain", DIR = O, VEC = [0:5], BUS = RC2RB_RAD4

END
