## Copyright (c) 2004 Xilinx, Inc. All Rights Reserved.
## You may copy and modify these files for your own internal use solely with
## Xilinx programmable logic devices and  Xilinx EDK system or create IP
## modules solely for Xilinx programmable logic devices and Xilinx EDK system.
## No rights are granted to distribute any files unless they are distributed in
## Xilinx programmable logic devices.
###################################################################
##
## Name     : ourspi
## Desc     : Microprocessor Peripheral Description
##          : Automatically generated by PsfUtility
##
###################################################################

BEGIN ourspi

## Peripheral Options
OPTION IPTYPE = PERIPHERAL
OPTION IMP_NETLIST = TRUE
OPTION HDL = VERILOG
OPTION CORE_STATE = ACTIVE
OPTION IP_GROUP = MICROBLAZE:PPC:USER
OPTION STYLE = MIX
OPTION RUN_NGCBUILD = TRUE


## Bus Interfaces
BUS_INTERFACE BUS = SOPB, BUS_TYPE = SLAVE, BUS_STD = OPB

## Generics for VHDL or Parameters for Verilog
PARAMETER C_BASEADDR = 0x80000000, BUS = SOPB, ADDRESS = BASE, PAIR = C_HIGHADDR, MIN_SIZE = 0x100
PARAMETER C_HIGHADDR = 0x800000ff, BUS = SOPB, ADDRESS = HIGH, PAIR = C_BASEADDR

## Ports
PORT OPB_Clk = "", DIR = I, BUS = SOPB
PORT rst = OPB_Rst, DIR = I, BUS = SOPB
PORT opb_abus = OPB_ABus, DIR = I, VEC = [31:0], BUS = SOPB
PORT opb_be = OPB_BE, DIR = I, VEC = [3:0], BUS = SOPB
PORT opb_dbus = OPB_DBus, DIR = I, VEC = [31:0], BUS = SOPB
PORT opb_rnw = OPB_RNW, DIR = I, BUS = SOPB
PORT opb_select = OPB_select, DIR = I, BUS = SOPB
PORT opb_seqaddr = OPB_seqAddr, DIR = I, BUS = SOPB
PORT sl_dbus = Sl_DBus, DIR = O, VEC = [31:0], BUS = SOPB
PORT sl_errack = Sl_errAck, DIR = O, BUS = SOPB
PORT sl_retry = Sl_retry, DIR = O, BUS = SOPB
PORT sl_toutsup = Sl_toutSup, DIR = O, BUS = SOPB
PORT sl_xferack = Sl_xferAck, DIR = O, BUS = SOPB
PORT radio1_sclk = "", DIR = O
PORT radio1_dout = "", DIR = O
PORT radio1_cs = "", DIR = O
PORT radio2_sclk = "", DIR = O
PORT radio2_dout = "", DIR = O
PORT radio2_cs = "", DIR = O
PORT radio3_sclk = "", DIR = O
PORT radio3_dout = "", DIR = O
PORT radio3_cs = "", DIR = O
PORT radio4_sclk = "", DIR = O
PORT radio4_dout = "", DIR = O
PORT radio4_cs = "", DIR = O
PORT dac1_sclk = "", DIR = O
PORT dac1_dout = "", DIR = O
PORT dac1_cs = "", DIR = O
PORT dac2_sclk = "", DIR = O
PORT dac2_dout = "", DIR = O
PORT dac2_cs = "", DIR = O
PORT dac3_sclk = "", DIR = O
PORT dac3_dout = "", DIR = O
PORT dac3_cs = "", DIR = O
PORT dac4_sclk = "", DIR = O
PORT dac4_dout = "", DIR = O
PORT dac4_cs = "", DIR = O

END
