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## ***************************************************************************
## **                                                                       **
## ** Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.            **
## **                                                                       **
## ** You may copy and modify these files for your own internal use solely  **
## ** with Xilinx programmable logic devices and Xilinx EDK system or       **
## ** create IP modules solely for Xilinx programmable logic devices and    **
## ** Xilinx EDK system. No rights are granted to distribute any files      **
## ** unless they are distributed in Xilinx programmable logic devices.     **
## **                                                                       **
## ***************************************************************************
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## Filename:          C:\edk_user_repository\MyProcessorIPLib\pcores\ourspi\data\ourspi_v2_1_0.pao
## Description:       Peripheral Analysis Order
## Date:              Wed Jun 22 10:30:03 2005 (by Create and Import Peripheral Wizard)
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lib ourspi opb2wb_shell verilog
lib ourspi spi_clgen verilog
lib ourspi spi_defines verilog
lib ourspi spi_shift verilog
lib ourspi timescale verilog
lib ourspi spi_top verilog
lib ourspi ourspi verilog