###################################################################
##
## Name     : linkport
## Desc     : Microprocessor Peripheral Description
##          : Automatically generated by PsfUtility
##
###################################################################

BEGIN linkport

## Peripheral Options
OPTION IPTYPE = PERIPHERAL
OPTION IMP_NETLIST = TRUE
OPTION HDL = VHDL
OPTION USAGE_LEVEL = BASE_USER
OPTION ARCH_SUPPORT_MAP = (virtex2p=PREFERRED, virtex4=PREFERRED, others=AVAILABLE)
OPTION IP_GROUP = USER
OPTION STYLE = MIX
OPTION RUN_NGCBUILD = TRUE

IO_INTERFACE IO_IF = mgt_linkport1_0, IO_TYPE = WARP_MGTLINKPORT1_V1

## Bus Interfaces

## Generics for VHDL or Parameters for Verilog

## Ports
PORT tx_data = "", DIR = I, VEC = [15:0]
PORT tx_clk = "", DIR = I
PORT tx_wr = "", DIR = I
PORT tx_first = "", DIR = I
PORT tx_last = "", DIR = I
PORT tx_rdy = "", DIR = O
PORT link_en = "", DIR = I
PORT rx_clk = "", DIR = I
PORT rx_drdy = "", DIR = O
PORT rx_first = "", DIR = O
PORT rx_last = "", DIR = O
PORT rx_data = "", DIR = O, VEC = [15:0]
PORT fc_req = "", DIR = I
PORT fc_nb = "", DIR = I, VEC = [3:0]
PORT fc_ack = "", DIR = O
PORT top_ref_clk_i = mgt_top_ref_clk, DIR = I
PORT user_clk_i = mgt_usr_clk, DIR = I
PORT mgt_rxp = "", DIR = I , IO_IS = rec_pos
PORT mgt_rxn = "", DIR = I , IO_IS = rec_neg
PORT mgt_txn = "", DIR = O , IO_IS = trans_neg
PORT mgt_txp = "", DIR = O , IO_IS = trans_pos
PORT grst = "", DIR = I
PORT mgt_pwdn = "", DIR = I

END
