## Copyright (c) 2004 Xilinx, Inc. All Rights Reserved.
## You may copy and modify these files for your own internal use solely with
## Xilinx programmable logic devices and  Xilinx EDK system or create IP
## modules solely for Xilinx programmable logic devices and Xilinx EDK system.
## No rights are granted to distribute any files unless they are distributed in
## Xilinx programmable logic devices.
###################################################################
##
## Name     : radio_bridge
## Desc     : Microprocessor Peripheral Description
##          : Automatically generated by PsfUtility
##
###################################################################

BEGIN radio_bridge

## Peripheral Options
OPTION IPTYPE = PERIPHERAL
OPTION IMP_NETLIST = TRUE
OPTION HDL = VERILOG
OPTION CORE_STATE = ACTIVE
OPTION IP_GROUP = USER
OPTION USAGE_LEVEL = BASE_USER

IO_INTERFACE IO_IF = radio_bridge, IO_TYPE = WARP_RADIOBRIDGE_V1

## Bus Interfaces

## Generics for VHDL or Parameters for Verilog

## Ports
PORT converter_clock_in = "sys_clk_s", DIR = I
PORT converter_clock_out = "", DIR = O

PORT user_ADC_I = "", DIR = O, VEC = [0:13], IO_IS = userADCI
PORT user_ADC_Q = "", DIR = O, VEC = [0:13], IO_IS = userADCQ

PORT radio_DAC_I = "", DIR = O, VEC = [0:15], IO_IS = radioDACI
PORT radio_DAC_Q = "", DIR = O, VEC = [0:15], IO_IS = radioDACQ

PORT user_DAC_I = "", DIR = I, VEC = [0:15], IO_IS = userDACI
PORT user_DAC_Q = "", DIR = I, VEC = [0:15], IO_IS = userDACQ

PORT radio_ADC_I = "", DIR = I, VEC = [0:13], IO_IS = radioADCI
PORT radio_ADC_Q = "", DIR = I, VEC = [0:13], IO_IS = radioADCQ


PORT user_RF_gain = "", DIR = I, VEC = [0:1], IO_IS = userRFG
PORT user_BB_gain = "", DIR = I, VEC = [0:4], IO_IS = userBBG
PORT radio_RF_gain = "", DIR = O, VEC = [0:1], IO_IS = radioRFG
PORT radio_BB_gain = "", DIR = O, VEC = [0:4], IO_IS = radioBBG

PORT controller_spi_clk = "", DIR = I
PORT controller_spi_data = "", DIR = I
PORT controller_radio_cs = "", DIR = I
PORT controller_dac_cs = "", DIR = I
PORT controller_SHDN = "", DIR = I
PORT controller_TxEn = "", DIR = I
PORT controller_RxEn = "", DIR = I
PORT controller_RxHP = "", DIR = I
PORT controller_24PA = "", DIR = I
PORT controller_5PA = "", DIR = I
PORT controller_ANTSW = "", DIR = I, VEC = [0:1], IO_IS = c2b_ANTSW
PORT controller_LED = "", DIR = I, VEC = [0:2], IO_IS = c2b_LED
PORT controller_RX_ADC_DCS = "", DIR = I
PORT controller_RX_ADC_DFS = "", DIR = I
PORT controller_RX_ADC_PWDNA = "", DIR = I
PORT controller_RX_ADC_PWDNB = "", DIR = I
PORT controller_RSSI_ADC_CLAMP = "", DIR = I
PORT controller_RSSI_ADC_HIZ = "", DIR = I
PORT controller_RSSI_ADC_SLEEP = "", DIR = I
PORT controller_DIPSW = "", DIR = O, VEC = [0:3], IO_IS = c2b_DIPSW
PORT controller_RSSI_ADC_D = "", DIR = O, VEC = [0:9], IO_IS = c2b_RSSI_ADC_D
PORT controller_LD = "", DIR = O
PORT controller_RX_ADC_OTRA = "", DIR = O
PORT controller_RX_ADC_OTRB = "", DIR = O
PORT controller_RSSI_ADC_OTR = "", DIR = O
PORT controller_DAC_PLL_LOCK = "", DIR = O
PORT controller_DAC_RESET = "", DIR = I
PORT dac_spi_data = "", DIR = O
PORT dac_spi_cs = "", DIR = O
PORT dac_spi_clk = "", DIR = O
PORT radio_spi_clk = "", DIR = O
PORT radio_spi_data = "", DIR = O
PORT radio_spi_cs = "", DIR = O
PORT radio_SHDN = "", DIR = O
PORT radio_TxEn = "", DIR = O
PORT radio_RxEn = "", DIR = O
PORT radio_RxHP = "", DIR = O
PORT radio_24PA = "", DIR = O
PORT radio_5PA = "", DIR = O
PORT radio_ANTSW = "", DIR = O, VEC = [0:1], IO_IS = b2r_ANTSW
PORT radio_LED = "", DIR = O, VEC = [0:2], IO_IS = b2r_LED
PORT radio_RX_ADC_DCS = "", DIR = O
PORT radio_RX_ADC_DFS = "", DIR = O
PORT radio_RX_ADC_PWDNA = "", DIR = O
PORT radio_RX_ADC_PWDNB = "", DIR = O
PORT radio_DIPSW = "", DIR = O, VEC = [0:3], IO_IS = b2r_DIPSW
PORT radio_RSSI_ADC_CLAMP = "", DIR = O
PORT radio_RSSI_ADC_HIZ = "", DIR = O
PORT radio_RSSI_ADC_SLEEP = "", DIR = O
PORT radio_RSSI_ADC_D = "", DIR = I, VEC = [0:9], IO_IS = b2r_RSSI_ADC_D
PORT radio_LD = "", DIR = I
PORT radio_RX_ADC_OTRA = "", DIR = I
PORT radio_RX_ADC_OTRB = "", DIR = I
PORT radio_RSSI_ADC_OTR = "", DIR = I
PORT radio_DAC_PLL_LOCK = "", DIR = I
PORT radio_DAC_RESET = "", DIR = O

END
