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## ***************************************************************************
## **                                                                       **
## ** Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.            **
## **                                                                       **
## ** You may copy and modify these files for your own internal use solely  **
## ** with Xilinx programmable logic devices and Xilinx EDK system or       **
## ** create IP modules solely for Xilinx programmable logic devices and    **
## ** Xilinx EDK system. No rights are granted to distribute any files      **
## ** unless they are distributed in Xilinx programmable logic devices.     **
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## ***************************************************************************
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## Filename:          C:\edk_user_repository\MyProcessorIPLib\pcores\radio_bridge_v1_03_a\data\radio_bridge_v2_1_0.pao
## Description:       Peripheral Analysis Order
## Date:              Fri May 26 20:52:44 2006 (by Create and Import Peripheral Wizard)
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lib radio_bridge_v1_03_a radio_bridge verilog