----------------------------------------------------------------------------
--                            Design Analysis                             --
----------------------------------------------------------------------------
Analyze pcore radio_controller ...


----------------------------------------------------------------------------
--                            File Generation                             --
----------------------------------------------------------------------------
Creating HDL source directory ...
Generating top peripheral VHDL template ...
Generating stub user logic Verilog template ...
HDL templates successfully generated ...
Creating data directory ...
Generating XPS inteface files ...
WARNING:HDLParsers:3497 - Ignoring Verilog File
   "C:\edk_user_repository\MyProcessorIPLib\pcores\radio_controller_v1_02_a\data
   /..\hdl\verilog\user_logic.v"
Compiling vhdl file
"C:/EDK//hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/inferred_lu
t4.vhd" in Library proc_common_v2_00_a.
Entity <inferred_lut4> compiled.
Entity <inferred_lut4> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/EDK//hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_counter_
bit.vhd" in Library proc_common_v2_00_a.
Entity <pf_counter_bit> compiled.
Entity <pf_counter_bit> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/EDK//hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_adder_bi
t.vhd" in Library proc_common_v2_00_a.
Entity <pf_adder_bit> compiled.
Entity <pf_adder_bit> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/EDK//hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_counter.
vhd" in Library proc_common_v2_00_a.
Entity <pf_counter> compiled.
Entity <pf_counter> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/EDK//hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_occ_coun
ter.vhd" in Library proc_common_v2_00_a.
Entity <pf_occ_counter> compiled.
Entity <pf_occ_counter> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/EDK//hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_occ_coun
ter_top.vhd" in Library proc_common_v2_00_a.
Entity <pf_occ_counter_top> compiled.
Entity <pf_occ_counter_top> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/EDK//hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_counter_
top.vhd" in Library proc_common_v2_00_a.
Entity <pf_counter_top> compiled.
Entity <pf_counter_top> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/EDK//hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_adder.vh
d" in Library proc_common_v2_00_a.
Entity <pf_adder> compiled.
Entity <pf_adder> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/EDK//hw/XilinxProcessorIPLib/pcores/wrpfifo_v1_01_b/hdl/vhdl/pf_dly1_mux.vhd
" in Library wrpfifo_v1_01_b.
Entity <pf_dly1_mux> compiled.
Entity <pf_dly1_mux> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/EDK//hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/proc_common
_pkg.vhd" in Library proc_common_v2_00_a.
Package <proc_common_pkg> compiled.
Package body <proc_common_pkg> compiled.
Compiling vhdl file
"C:/EDK//hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/counter_bit
.vhd" in Library proc_common_v2_00_a.
Entity <counter_bit> compiled.
Entity <counter_bit> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/EDK//hw/XilinxProcessorIPLib/pcores/wrpfifo_v1_01_b/hdl/vhdl/ipif_control_wr
.vhd" in Library wrpfifo_v1_01_b.
Entity <ipif_control_wr> compiled.
Entity <ipif_control_wr> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/EDK//hw/XilinxProcessorIPLib/pcores/wrpfifo_v1_01_b/hdl/vhdl/wrpfifo_dp_cntl
.vhd" in Library wrpfifo_v1_01_b.
Entity <wrpfifo_dp_cntl> compiled.
Entity <wrpfifo_dp_cntl> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/EDK//hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pf_dpram_se
lect.vhd" in Library proc_common_v2_00_a.
Entity <pf_dpram_select> compiled.
Entity <pf_dpram_select> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/EDK//hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/srl16_fifo.
vhd" in Library proc_common_v2_00_a.
Entity <srl16_fifo> compiled.
Entity <srl16_fifo> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/EDK//hw/XilinxProcessorIPLib/pcores/rdpfifo_v1_01_b/hdl/vhdl/ipif_control_rd
.vhd" in Library rdpfifo_v1_01_b.
Entity <ipif_control_rd> compiled.
Entity <ipif_control_rd> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/EDK//hw/XilinxProcessorIPLib/pcores/rdpfifo_v1_01_b/hdl/vhdl/rdpfifo_dp_cntl
.vhd" in Library rdpfifo_v1_01_b.
Entity <rdpfifo_dp_cntl> compiled.
Entity <rdpfifo_dp_cntl> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/EDK//hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/ipif_pkg.vh
d" in Library proc_common_v2_00_a.
Package <ipif_pkg> compiled.
Package body <ipif_pkg> compiled.
Compiling vhdl file
"C:/EDK//hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_a/hdl/vhdl/srl_fifo3.vhd"
in Library opb_ipif_v3_01_a.
Entity <srl_fifo3> compiled.
Entity <srl_fifo3> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/EDK//hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/counter.vhd
" in Library proc_common_v2_00_a.
Entity <Counter> compiled.
Entity <Counter> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/EDK//hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_a/hdl/vhdl/opb_flex_addr_
cntr.vhd" in Library opb_ipif_v3_01_a.
Entity <opb_flex_addr_cntr> compiled.
Entity <opb_flex_addr_cntr> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/EDK//hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/direct_path
_cntr_ai.vhd" in Library proc_common_v2_00_a.
Entity <direct_path_cntr_ai> compiled.
Entity <direct_path_cntr_ai> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/EDK//hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/pselect.vhd
" in Library proc_common_v2_00_a.
Entity <pselect> compiled.
Entity <pselect> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/EDK//hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_a/hdl/vhdl/opb_be_gen.vhd
" in Library opb_ipif_v3_01_a.
Entity <opb_be_gen> compiled.
Entity <opb_be_gen> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/EDK//hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_a/hdl/vhdl/brst_addr_cntr
.vhd" in Library opb_ipif_v3_01_a.
Entity <brst_addr_cntr> compiled.
Entity <brst_addr_cntr> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/EDK//hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_a/hdl/vhdl/brst_addr_cntr
_reg.vhd" in Library opb_ipif_v3_01_a.
Entity <brst_addr_cntr_reg> compiled.
Entity <brst_addr_cntr_reg> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/EDK//hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_a/hdl/vhdl/write_buffer.v
hd" in Library opb_ipif_v3_01_a.
Entity <write_buffer> compiled.
Entity <write_buffer> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/EDK//hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/or_muxcy.vh
d" in Library proc_common_v2_00_a.
Entity <or_muxcy> compiled.
Entity <or_muxcy> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/EDK//hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/ipif_steer.
vhd" in Library proc_common_v2_00_a.
Entity <IPIF_Steer> compiled.
Entity <IPIF_Steer> (Architecture <IMP>) compiled.
Compiling vhdl file
"C:/EDK//hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_a/hdl/vhdl/reset_mir.vhd"
in Library opb_ipif_v3_01_a.
Entity <reset_mir> compiled.
Entity <reset_mir> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/EDK//hw/XilinxProcessorIPLib/pcores/interrupt_control_v1_00_a/hdl/vhdl/inter
rupt_control.vhd" in Library interrupt_control_v1_00_a.
Entity <interrupt_control> compiled.
Entity <interrupt_control> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/EDK//hw/XilinxProcessorIPLib/pcores/rdpfifo_v1_01_b/hdl/vhdl/rdpfifo_top.vhd
" in Library rdpfifo_v1_01_b.
Entity <rdpfifo_top> compiled.
Entity <rdpfifo_top> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/EDK//hw/XilinxProcessorIPLib/pcores/wrpfifo_v1_01_b/hdl/vhdl/wrpfifo_top.vhd
" in Library wrpfifo_v1_01_b.
Entity <wrpfifo_top> compiled.
Entity <wrpfifo_top> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/EDK//hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/family.vhd"
in Library proc_common_v2_00_a.
Package <family> compiled.
Package body <family> compiled.
Compiling vhdl file
"C:/EDK//hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_a/hdl/vhdl/opb_bam.vhd"
in Library opb_ipif_v3_01_a.
Entity <opb_bam> compiled.
Entity <opb_bam> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/EDK//hw/XilinxProcessorIPLib/pcores/opb_ipif_v3_01_a/hdl/vhdl/opb_ipif.vhd"
in Library opb_ipif_v3_01_a.
Entity <opb_ipif> compiled.
Entity <opb_ipif> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/edk_user_repository/MyProcessorIPLib/pcores/radio_controller_v1_02_a/data/..
/hdl/vhdl/radio_controller.vhd" in Library radio_controller_v1_02_a.
Entity <radio_controller> compiled.
Entity <radio_controller> (Architecture <IMP>) compiled.
Compiling vhdl file
"C:/EDK//hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/down_counte
r.vhd" in Library proc_common_v2_00_a.
Entity <down_counter> compiled.
Entity <down_counter> (Architecture <simulation>) compiled.
Compiling vhdl file
"C:/EDK//hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/mux_onehot.
vhd" in Library proc_common_v2_00_a.
Entity <mux_onehot> compiled.
Entity <mux_onehot> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/EDK//hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/ld_arith_re
g.vhd" in Library proc_common_v2_00_a.
Entity <ld_arith_reg> compiled.
Entity <ld_arith_reg> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/EDK//hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/valid_be.vh
d" in Library proc_common_v2_00_a.
Entity <valid_be> compiled.
Entity <valid_be> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/EDK//hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/srl_fifo2.v
hd" in Library proc_common_v2_00_a.
Entity <srl_fifo2> compiled.
Entity <srl_fifo2> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/EDK//hw/XilinxProcessorIPLib/pcores/proc_common_v2_00_a/hdl/vhdl/or_gate.vhd
" in Library proc_common_v2_00_a.
Entity <or_gate> compiled.
Entity <or_gate> (Architecture <imp>) compiled.


Analyzing HDL attributes ...
INFO:MDT - IPTYPE set to value : PERIPHERAL
INFO:MDT - IMP_NETLIST set to value : TRUE
INFO:MDT - HDL set to value : VHDL
XPS interface files successfully generated ...
Creating development directory ...
Generating command option file ...
Generating readme file ...
Development misc files successfully generated ...
Creating projnav directory ...
Generating ProjNav support files ...
ProjNav support files successfully generated ...
Creating synthesis directory ...
Generating XST synthesis support files ...
XST synthesis support files successfully generated ...
No BFM simulation files will be generated at this time ...
Creating software driver data directory ...
Generating software driver XPS interface (mdd/tcl) files ...
Software driver data definition file (.mdd) successfully generated ...
Software driver data generation file (.tcl) successfully generated ...
Creating software driver src directory ...
Generating software driver template files ...
Software driver compile file (Makefile) successfully generated ...
output user slave register(s) offset to software driver header ...
Software driver header file (.h) successfully generated ...
Software driver source file (.c) successfully generated ...
Software driver SelfTest file (.c) successfully generated ...
Software driver template files successfully generated ...

----------------------------------------------------------------------------
--                              Final Report                              --
----------------------------------------------------------------------------
Thank you for using Create and Import Peripheral Wizard!

Peripheral summary

  top name       : radio_controller
  version        : 1.02.a
  type           : OPB slave
  features       : slave attachement
                   user s/w registers

Address Block Summary

  user logic slv : C_BASEADDR + 0x00000000
                 : C_BASEADDR + 0x000000FF

File Summary

  - HDL source -
  C:\edk_user_repository\MyProcessorIPLib/pcores/radio_controller_v1_02_a/hdl
  top entity     : vhdl/radio_controller.vhd
  user logic     : verilog/user_logic.v

  - XPS interface -
  C:\edk_user_repository\MyProcessorIPLib/pcores/radio_controller_v1_02_a/data
  mpd            : radio_controller_v2_1_0.mpd
  pao            : radio_controller_v2_1_0.pao

  - ISE project -
C:\edk_user_repository\MyProcessorIPLib/pcores/radio_controller_v1_02_a/devl/pro
jnav
  ise project    : radio_controller.npl
  cli command    : radio_controller.cli


  - XST synthesis -
C:\edk_user_repository\MyProcessorIPLib/pcores/radio_controller_v1_02_a/devl/syn
thesis
  xst script     : radio_controller_xst.scr
  xst project    : radio_controller_xst.prj

  - Misc file -
  C:\edk_user_repository\MyProcessorIPLib/pcores/radio_controller_v1_02_a/devl
  help           : README.txt
  option         : ipwiz.opt
  log            : ipwiz.log

  - Driver source -
  C:\edk_user_repository\MyProcessorIPLib/drivers/radio_controller_v1_02_a/src
  makefile       : Makefile
  header         : radio_controller.h
  source         : radio_controller.c
  selftest       : radio_controller_selftest.c

  - Driver interface -
  C:\edk_user_repository\MyProcessorIPLib/drivers/radio_controller_v1_02_a/data
  mdd            : radio_controller_v2_1_0.mdd
  tcl            : radio_controller_v2_1_0.tcl