(edif test (edifVersion 2 0 0) (edifLevel 0) (keywordMap (keywordLevel 0))
(status (written (timeStamp 2007 8 25 21 25 13)
   (author "Xilinx, Inc.")
   (program "Xilinx CORE Generator" (version "Xilinx CORE Generator 8.2.03i"))))
   (comment "                                                                                
      This file is owned and controlled by Xilinx and must be used              
      solely for design, simulation, implementation and creation of             
      design files limited to Xilinx devices or technologies. Use               
      with non-Xilinx devices or technologies is expressly prohibited           
      and immediately terminates your license.                                  
                                                                                
      XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION 'AS IS'             
      SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                   
      XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION           
      AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION               
      OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS                 
      IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                   
      AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE          
      FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY                  
      WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                   
      IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR            
      REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF           
      INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS           
      FOR A PARTICULAR PURPOSE.                                                 
                                                                                
      Xilinx products are not intended for use in life support                  
      appliances, devices, or systems. Use in such applications are             
      expressly prohibited.                                                     
                                                                                
      (c) Copyright 1995-2006 Xilinx, Inc.                                      
      All rights reserved.                                                      
                                                                                
   ")
   (comment "Core parameters: ")
       (comment "c_has_bypass_with_cin = false ")
       (comment "c_a_type = 0 ")
       (comment "c_has_sclr = false ")
       (comment "c_sync_priority = 1 ")
       (comment "c_has_aset = false ")
       (comment "c_has_b_out = false ")
       (comment "c_has_s = true ")
       (comment "c_has_q = false ")
       (comment "InstanceName = adder_subtracter_virtex2p_7_0_cb748602b0616a72 ")
       (comment "c_family = virtex2p ")
       (comment "c_bypass_enable = false ")
       (comment "c_b_constant = false ")
       (comment "c_has_ovfl = false ")
       (comment "c_high_bit = 4 ")
       (comment "c_latency = 0 ")
       (comment "c_sinit_val = 0 ")
       (comment "c_has_bypass = false ")
       (comment "c_pipe_stages = 1 ")
       (comment "c_has_sset = false ")
       (comment "c_has_ainit = false ")
       (comment "c_has_a_signed = false ")
       (comment "c_has_q_c_out = false ")
       (comment "c_b_type = 0 ")
       (comment "c_has_add = false ")
       (comment "c_has_sinit = false ")
       (comment "c_has_b_in = false ")
       (comment "c_has_b_signed = false ")
       (comment "c_bypass_low = false ")
       (comment "c_enable_rlocs = true ")
       (comment "c_b_value = 0 ")
       (comment "c_add_mode = 1 ")
       (comment "c_has_aclr = false ")
       (comment "c_out_width = 5 ")
       (comment "c_ainit_val = 0000 ")
       (comment "c_low_bit = 0 ")
       (comment "c_has_q_ovfl = false ")
       (comment "c_has_q_b_out = false ")
       (comment "c_has_c_out = false ")
       (comment "c_b_width = 5 ")
       (comment "c_a_width = 5 ")
       (comment "c_sync_enable = 0 ")
       (comment "c_has_ce = true ")
       (comment "c_has_c_in = false ")
   (external xilinxun (edifLevel 0)
      (technology (numberDefinition))
       (cell VCC (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port P (direction OUTPUT))
               )
           )
       )
       (cell GND (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port G (direction OUTPUT))
               )
           )
       )
       (cell LUT4 (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port I0 (direction INPUT))
                   (port I1 (direction INPUT))
                   (port I2 (direction INPUT))
                   (port I3 (direction INPUT))
                   (port O (direction OUTPUT))
               )
           )
       )
       (cell MUXCY (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port DI (direction INPUT))
                   (port CI (direction INPUT))
                   (port S (direction INPUT))
                   (port O (direction OUTPUT))
               )
           )
       )
       (cell XORCY (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port LI (direction INPUT))
                   (port CI (direction INPUT))
                   (port O (direction OUTPUT))
               )
           )
       )
   )
(library test_lib (edifLevel 0) (technology (numberDefinition (scale 1 (E 1 -12) (unit Time))))
(cell adder_subtracter_virtex2p_7_0_cb748602b0616a72
 (cellType GENERIC) (view view_1 (viewType NETLIST)
  (interface
   (port ( rename A_0_ "A(0)") (direction INPUT))
   (port ( rename A_1_ "A(1)") (direction INPUT))
   (port ( rename A_2_ "A(2)") (direction INPUT))
   (port ( rename A_3_ "A(3)") (direction INPUT))
   (port ( rename A_4_ "A(4)") (direction INPUT))
   (port ( rename B_0_ "B(0)") (direction INPUT))
   (port ( rename B_1_ "B(1)") (direction INPUT))
   (port ( rename B_2_ "B(2)") (direction INPUT))
   (port ( rename B_3_ "B(3)") (direction INPUT))
   (port ( rename B_4_ "B(4)") (direction INPUT))
   (port ( rename S_0_ "S(0)") (direction OUTPUT))
   (port ( rename S_1_ "S(1)") (direction OUTPUT))
   (port ( rename S_2_ "S(2)") (direction OUTPUT))
   (port ( rename S_3_ "S(3)") (direction OUTPUT))
   (port ( rename S_4_ "S(4)") (direction OUTPUT))
   )
  (contents
   (instance VCC (viewRef view_1 (cellRef VCC  (libraryRef xilinxun))))
   (instance GND (viewRef view_1 (cellRef GND  (libraryRef xilinxun))))
   (instance BU3
      (viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
      (property RLOC (string "x3y4"))
      (property RPM_GRID (string "GRID"))
      (property INIT (string "9999"))
   )
   (instance BU4
      (viewRef view_1 (cellRef MUXCY (libraryRef xilinxun)))
      (property RLOC (string "x3y4"))
      (property RPM_GRID (string "GRID"))
   )
   (instance BU5
      (viewRef view_1 (cellRef XORCY (libraryRef xilinxun)))
      (property RLOC (string "x3y4"))
      (property RPM_GRID (string "GRID"))
   )
   (instance BU7
      (viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
      (property RLOC (string "x3y4"))
      (property RPM_GRID (string "GRID"))
      (property INIT (string "9999"))
   )
   (instance BU8
      (viewRef view_1 (cellRef MUXCY (libraryRef xilinxun)))
      (property RLOC (string "x3y4"))
      (property RPM_GRID (string "GRID"))
   )
   (instance BU9
      (viewRef view_1 (cellRef XORCY (libraryRef xilinxun)))
      (property RLOC (string "x3y4"))
      (property RPM_GRID (string "GRID"))
   )
   (instance BU11
      (viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
      (property RLOC (string "x3y5"))
      (property RPM_GRID (string "GRID"))
      (property INIT (string "9999"))
   )
   (instance BU12
      (viewRef view_1 (cellRef MUXCY (libraryRef xilinxun)))
      (property RLOC (string "x3y5"))
      (property RPM_GRID (string "GRID"))
   )
   (instance BU13
      (viewRef view_1 (cellRef XORCY (libraryRef xilinxun)))
      (property RLOC (string "x3y5"))
      (property RPM_GRID (string "GRID"))
   )
   (instance BU15
      (viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
      (property RLOC (string "x3y5"))
      (property RPM_GRID (string "GRID"))
      (property INIT (string "9999"))
   )
   (instance BU16
      (viewRef view_1 (cellRef MUXCY (libraryRef xilinxun)))
      (property RLOC (string "x3y5"))
      (property RPM_GRID (string "GRID"))
   )
   (instance BU17
      (viewRef view_1 (cellRef XORCY (libraryRef xilinxun)))
      (property RLOC (string "x3y5"))
      (property RPM_GRID (string "GRID"))
   )
   (instance BU19
      (viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
      (property RLOC (string "x3y8"))
      (property RPM_GRID (string "GRID"))
      (property INIT (string "9999"))
   )
   (instance BU20
      (viewRef view_1 (cellRef XORCY (libraryRef xilinxun)))
      (property RLOC (string "x3y8"))
      (property RPM_GRID (string "GRID"))
   )
   (net N0
    (joined
      (portRef G (instanceRef GND))
      (portRef I2 (instanceRef BU3))
      (portRef I3 (instanceRef BU3))
      (portRef I2 (instanceRef BU7))
      (portRef I3 (instanceRef BU7))
      (portRef I2 (instanceRef BU11))
      (portRef I3 (instanceRef BU11))
      (portRef I2 (instanceRef BU15))
      (portRef I3 (instanceRef BU15))
      (portRef I2 (instanceRef BU19))
      (portRef I3 (instanceRef BU19))
    )
   )
   (net N1
    (joined
      (portRef P (instanceRef VCC))
      (portRef CI (instanceRef BU4))
      (portRef CI (instanceRef BU5))
    )
   )
   (net N2
    (joined
      (portRef S (instanceRef BU4))
      (portRef LI (instanceRef BU5))
      (portRef O (instanceRef BU3))
    )
   )
   (net N5
    (joined
      (portRef O (instanceRef BU4))
      (portRef CI (instanceRef BU8))
      (portRef CI (instanceRef BU9))
    )
   )
   (net N7
    (joined
      (portRef S (instanceRef BU8))
      (portRef LI (instanceRef BU9))
      (portRef O (instanceRef BU7))
    )
   )
   (net N10
    (joined
      (portRef O (instanceRef BU8))
      (portRef CI (instanceRef BU12))
      (portRef CI (instanceRef BU13))
    )
   )
   (net N12
    (joined
      (portRef S (instanceRef BU12))
      (portRef LI (instanceRef BU13))
      (portRef O (instanceRef BU11))
    )
   )
   (net N15
    (joined
      (portRef O (instanceRef BU12))
      (portRef CI (instanceRef BU16))
      (portRef CI (instanceRef BU17))
    )
   )
   (net N17
    (joined
      (portRef S (instanceRef BU16))
      (portRef LI (instanceRef BU17))
      (portRef O (instanceRef BU15))
    )
   )
   (net N20
    (joined
      (portRef O (instanceRef BU16))
      (portRef CI (instanceRef BU20))
    )
   )
   (net N22
    (joined
      (portRef LI (instanceRef BU20))
      (portRef O (instanceRef BU19))
    )
   )
   (net (rename N26 "A(0)")
    (joined
      (portRef A_0_)
      (portRef DI (instanceRef BU4))
      (portRef I0 (instanceRef BU3))
    )
   )
   (net (rename N27 "A(1)")
    (joined
      (portRef A_1_)
      (portRef DI (instanceRef BU8))
      (portRef I0 (instanceRef BU7))
    )
   )
   (net (rename N28 "A(2)")
    (joined
      (portRef A_2_)
      (portRef DI (instanceRef BU12))
      (portRef I0 (instanceRef BU11))
    )
   )
   (net (rename N29 "A(3)")
    (joined
      (portRef A_3_)
      (portRef DI (instanceRef BU16))
      (portRef I0 (instanceRef BU15))
    )
   )
   (net (rename N30 "A(4)")
    (joined
      (portRef A_4_)
      (portRef I0 (instanceRef BU19))
    )
   )
   (net (rename N31 "B(0)")
    (joined
      (portRef B_0_)
      (portRef I1 (instanceRef BU3))
    )
   )
   (net (rename N32 "B(1)")
    (joined
      (portRef B_1_)
      (portRef I1 (instanceRef BU7))
    )
   )
   (net (rename N33 "B(2)")
    (joined
      (portRef B_2_)
      (portRef I1 (instanceRef BU11))
    )
   )
   (net (rename N34 "B(3)")
    (joined
      (portRef B_3_)
      (portRef I1 (instanceRef BU15))
    )
   )
   (net (rename N35 "B(4)")
    (joined
      (portRef B_4_)
      (portRef I1 (instanceRef BU19))
    )
   )
   (net (rename N36 "S(0)")
    (joined
      (portRef S_0_)
      (portRef O (instanceRef BU5))
    )
   )
   (net (rename N37 "S(1)")
    (joined
      (portRef S_1_)
      (portRef O (instanceRef BU9))
    )
   )
   (net (rename N38 "S(2)")
    (joined
      (portRef S_2_)
      (portRef O (instanceRef BU13))
    )
   )
   (net (rename N39 "S(3)")
    (joined
      (portRef S_3_)
      (portRef O (instanceRef BU17))
    )
   )
   (net (rename N40 "S(4)")
    (joined
      (portRef S_4_)
      (portRef O (instanceRef BU20))
    )
   )
))))
(design adder_subtracter_virtex2p_7_0_cb748602b0616a72 (cellRef adder_subtracter_virtex2p_7_0_cb748602b0616a72 (libraryRef test_lib))
  (property X_CORE_INFO (string "C_ADDSUB_V7_0, Coregen 8.2.03i"))
  (property PART (string "xc2vp2-fg256-7") (owner "Xilinx")))
)