(edif test (edifVersion 2 0 0) (edifLevel 0) (keywordMap (keywordLevel 0))
(status (written (timeStamp 2007 8 28 1 57 8)
   (author "Xilinx, Inc.")
   (program "Xilinx CORE Generator" (version "Xilinx CORE Generator 8.2.03i"))))
   (comment "                                                                                
      This file is owned and controlled by Xilinx and must be used              
      solely for design, simulation, implementation and creation of             
      design files limited to Xilinx devices or technologies. Use               
      with non-Xilinx devices or technologies is expressly prohibited           
      and immediately terminates your license.                                  
                                                                                
      XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION 'AS IS'             
      SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                   
      XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION           
      AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION               
      OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS                 
      IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                   
      AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE          
      FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY                  
      WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                   
      IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR            
      REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF           
      INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS           
      FOR A PARTICULAR PURPOSE.                                                 
                                                                                
      Xilinx products are not intended for use in life support                  
      appliances, devices, or systems. Use in such applications are             
      expressly prohibited.                                                     
                                                                                
      (c) Copyright 1995-2006 Xilinx, Inc.                                      
      All rights reserved.                                                      
                                                                                
   ")
   (comment "Core parameters: ")
       (comment "c_reg_inputsb = 0 ")
       (comment "c_reg_inputsa = 0 ")
       (comment "c_has_ndb = 0 ")
       (comment "c_has_nda = 0 ")
       (comment "c_ytop_addr = 1024 ")
       (comment "c_has_rfdb = 0 ")
       (comment "c_has_rfda = 0 ")
       (comment "c_ywea_is_high = 1 ")
       (comment "c_yena_is_high = 1 ")
       (comment "InstanceName = dual_port_block_memory_virtex2p_6_1_299a9f537bb5a43d ")
       (comment "c_yclka_is_rising = 1 ")
       (comment "c_yhierarchy = hierarchy1 ")
       (comment "c_family = virtex2p ")
       (comment "c_ysinita_is_high = 1 ")
       (comment "c_ybottom_addr = 0 ")
       (comment "c_width_b = 32 ")
       (comment "c_width_a = 16 ")
       (comment "c_sinita_value = 0 ")
       (comment "c_sinitb_value = 0 ")
       (comment "c_limit_data_pitch = 18 ")
       (comment "c_write_modeb = 0 ")
       (comment "c_write_modea = 0 ")
       (comment "c_has_rdyb = 0 ")
       (comment "c_yuse_single_primitive = 0 ")
       (comment "c_has_rdya = 0 ")
       (comment "c_addra_width = 9 ")
       (comment "c_addrb_width = 8 ")
       (comment "c_has_limit_data_pitch = 0 ")
       (comment "c_default_data = 0 ")
       (comment "c_pipe_stages_b = 0 ")
       (comment "c_yweb_is_high = 1 ")
       (comment "c_yenb_is_high = 1 ")
       (comment "c_pipe_stages_a = 0 ")
       (comment "c_yclkb_is_rising = 1 ")
       (comment "c_yydisable_warnings = 1 ")
       (comment "c_enable_rlocs = 0 ")
       (comment "c_ysinitb_is_high = 1 ")
       (comment "c_has_default_data = 0 ")
       (comment "c_has_web = 1 ")
       (comment "c_has_sinitb = 0 ")
       (comment "c_has_wea = 1 ")
       (comment "c_has_sinita = 0 ")
       (comment "c_has_dinb = 1 ")
       (comment "c_has_dina = 1 ")
       (comment "c_ymake_bmm = 0 ")
       (comment "c_has_enb = 1 ")
       (comment "c_has_ena = 1 ")
       (comment "c_mem_init_file = dual_port_block_memory_virtex2p_6_1_299a9f537bb5a43d.mif ")
       (comment "c_depth_b = 256 ")
       (comment "c_depth_a = 512 ")
       (comment "c_has_doutb = 1 ")
       (comment "c_has_douta = 1 ")
       (comment "c_yprimitive_type = 16kx1 ")
   (external xilinxun (edifLevel 0)
      (technology (numberDefinition))
       (cell VCC (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port P (direction OUTPUT))
               )
           )
       )
       (cell GND (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port G (direction OUTPUT))
               )
           )
       )
       (cell RAMB16_S18_S36 (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port WEA (direction INPUT))
                   (port ENA (direction INPUT))
                   (port SSRA (direction INPUT))
                   (port CLKA (direction INPUT))
                   (port (rename DIA_0_ "DIA(0)") (direction INPUT))
                   (port (rename DIA_1_ "DIA(1)") (direction INPUT))
                   (port (rename DIA_2_ "DIA(2)") (direction INPUT))
                   (port (rename DIA_3_ "DIA(3)") (direction INPUT))
                   (port (rename DIA_4_ "DIA(4)") (direction INPUT))
                   (port (rename DIA_5_ "DIA(5)") (direction INPUT))
                   (port (rename DIA_6_ "DIA(6)") (direction INPUT))
                   (port (rename DIA_7_ "DIA(7)") (direction INPUT))
                   (port (rename DIA_8_ "DIA(8)") (direction INPUT))
                   (port (rename DIA_9_ "DIA(9)") (direction INPUT))
                   (port (rename DIA_10_ "DIA(10)") (direction INPUT))
                   (port (rename DIA_11_ "DIA(11)") (direction INPUT))
                   (port (rename DIA_12_ "DIA(12)") (direction INPUT))
                   (port (rename DIA_13_ "DIA(13)") (direction INPUT))
                   (port (rename DIA_14_ "DIA(14)") (direction INPUT))
                   (port (rename DIA_15_ "DIA(15)") (direction INPUT))
                   (port (rename DOA_0_ "DOA(0)") (direction OUTPUT))
                   (port (rename DOA_1_ "DOA(1)") (direction OUTPUT))
                   (port (rename DOA_2_ "DOA(2)") (direction OUTPUT))
                   (port (rename DOA_3_ "DOA(3)") (direction OUTPUT))
                   (port (rename DOA_4_ "DOA(4)") (direction OUTPUT))
                   (port (rename DOA_5_ "DOA(5)") (direction OUTPUT))
                   (port (rename DOA_6_ "DOA(6)") (direction OUTPUT))
                   (port (rename DOA_7_ "DOA(7)") (direction OUTPUT))
                   (port (rename DOA_8_ "DOA(8)") (direction OUTPUT))
                   (port (rename DOA_9_ "DOA(9)") (direction OUTPUT))
                   (port (rename DOA_10_ "DOA(10)") (direction OUTPUT))
                   (port (rename DOA_11_ "DOA(11)") (direction OUTPUT))
                   (port (rename DOA_12_ "DOA(12)") (direction OUTPUT))
                   (port (rename DOA_13_ "DOA(13)") (direction OUTPUT))
                   (port (rename DOA_14_ "DOA(14)") (direction OUTPUT))
                   (port (rename DOA_15_ "DOA(15)") (direction OUTPUT))
                   (port (rename ADDRA_0_ "ADDRA(0)") (direction INPUT))
                   (port (rename ADDRA_1_ "ADDRA(1)") (direction INPUT))
                   (port (rename ADDRA_2_ "ADDRA(2)") (direction INPUT))
                   (port (rename ADDRA_3_ "ADDRA(3)") (direction INPUT))
                   (port (rename ADDRA_4_ "ADDRA(4)") (direction INPUT))
                   (port (rename ADDRA_5_ "ADDRA(5)") (direction INPUT))
                   (port (rename ADDRA_6_ "ADDRA(6)") (direction INPUT))
                   (port (rename ADDRA_7_ "ADDRA(7)") (direction INPUT))
                   (port (rename ADDRA_8_ "ADDRA(8)") (direction INPUT))
                   (port (rename ADDRA_9_ "ADDRA(9)") (direction INPUT))
                   (port (rename DIPA_0_ "DIPA(0)") (direction INPUT))
                   (port (rename DIPA_1_ "DIPA(1)") (direction INPUT))
                   (port (rename DOPA_0_ "DOPA(0)") (direction OUTPUT))
                   (port (rename DOPA_1_ "DOPA(1)") (direction OUTPUT))
                   (port WEB (direction INPUT))
                   (port ENB (direction INPUT))
                   (port SSRB (direction INPUT))
                   (port CLKB (direction INPUT))
                   (port (rename DIB_0_ "DIB(0)") (direction INPUT))
                   (port (rename DIB_1_ "DIB(1)") (direction INPUT))
                   (port (rename DIB_2_ "DIB(2)") (direction INPUT))
                   (port (rename DIB_3_ "DIB(3)") (direction INPUT))
                   (port (rename DIB_4_ "DIB(4)") (direction INPUT))
                   (port (rename DIB_5_ "DIB(5)") (direction INPUT))
                   (port (rename DIB_6_ "DIB(6)") (direction INPUT))
                   (port (rename DIB_7_ "DIB(7)") (direction INPUT))
                   (port (rename DIB_8_ "DIB(8)") (direction INPUT))
                   (port (rename DIB_9_ "DIB(9)") (direction INPUT))
                   (port (rename DIB_10_ "DIB(10)") (direction INPUT))
                   (port (rename DIB_11_ "DIB(11)") (direction INPUT))
                   (port (rename DIB_12_ "DIB(12)") (direction INPUT))
                   (port (rename DIB_13_ "DIB(13)") (direction INPUT))
                   (port (rename DIB_14_ "DIB(14)") (direction INPUT))
                   (port (rename DIB_15_ "DIB(15)") (direction INPUT))
                   (port (rename DIB_16_ "DIB(16)") (direction INPUT))
                   (port (rename DIB_17_ "DIB(17)") (direction INPUT))
                   (port (rename DIB_18_ "DIB(18)") (direction INPUT))
                   (port (rename DIB_19_ "DIB(19)") (direction INPUT))
                   (port (rename DIB_20_ "DIB(20)") (direction INPUT))
                   (port (rename DIB_21_ "DIB(21)") (direction INPUT))
                   (port (rename DIB_22_ "DIB(22)") (direction INPUT))
                   (port (rename DIB_23_ "DIB(23)") (direction INPUT))
                   (port (rename DIB_24_ "DIB(24)") (direction INPUT))
                   (port (rename DIB_25_ "DIB(25)") (direction INPUT))
                   (port (rename DIB_26_ "DIB(26)") (direction INPUT))
                   (port (rename DIB_27_ "DIB(27)") (direction INPUT))
                   (port (rename DIB_28_ "DIB(28)") (direction INPUT))
                   (port (rename DIB_29_ "DIB(29)") (direction INPUT))
                   (port (rename DIB_30_ "DIB(30)") (direction INPUT))
                   (port (rename DIB_31_ "DIB(31)") (direction INPUT))
                   (port (rename DOB_0_ "DOB(0)") (direction OUTPUT))
                   (port (rename DOB_1_ "DOB(1)") (direction OUTPUT))
                   (port (rename DOB_2_ "DOB(2)") (direction OUTPUT))
                   (port (rename DOB_3_ "DOB(3)") (direction OUTPUT))
                   (port (rename DOB_4_ "DOB(4)") (direction OUTPUT))
                   (port (rename DOB_5_ "DOB(5)") (direction OUTPUT))
                   (port (rename DOB_6_ "DOB(6)") (direction OUTPUT))
                   (port (rename DOB_7_ "DOB(7)") (direction OUTPUT))
                   (port (rename DOB_8_ "DOB(8)") (direction OUTPUT))
                   (port (rename DOB_9_ "DOB(9)") (direction OUTPUT))
                   (port (rename DOB_10_ "DOB(10)") (direction OUTPUT))
                   (port (rename DOB_11_ "DOB(11)") (direction OUTPUT))
                   (port (rename DOB_12_ "DOB(12)") (direction OUTPUT))
                   (port (rename DOB_13_ "DOB(13)") (direction OUTPUT))
                   (port (rename DOB_14_ "DOB(14)") (direction OUTPUT))
                   (port (rename DOB_15_ "DOB(15)") (direction OUTPUT))
                   (port (rename DOB_16_ "DOB(16)") (direction OUTPUT))
                   (port (rename DOB_17_ "DOB(17)") (direction OUTPUT))
                   (port (rename DOB_18_ "DOB(18)") (direction OUTPUT))
                   (port (rename DOB_19_ "DOB(19)") (direction OUTPUT))
                   (port (rename DOB_20_ "DOB(20)") (direction OUTPUT))
                   (port (rename DOB_21_ "DOB(21)") (direction OUTPUT))
                   (port (rename DOB_22_ "DOB(22)") (direction OUTPUT))
                   (port (rename DOB_23_ "DOB(23)") (direction OUTPUT))
                   (port (rename DOB_24_ "DOB(24)") (direction OUTPUT))
                   (port (rename DOB_25_ "DOB(25)") (direction OUTPUT))
                   (port (rename DOB_26_ "DOB(26)") (direction OUTPUT))
                   (port (rename DOB_27_ "DOB(27)") (direction OUTPUT))
                   (port (rename DOB_28_ "DOB(28)") (direction OUTPUT))
                   (port (rename DOB_29_ "DOB(29)") (direction OUTPUT))
                   (port (rename DOB_30_ "DOB(30)") (direction OUTPUT))
                   (port (rename DOB_31_ "DOB(31)") (direction OUTPUT))
                   (port (rename ADDRB_0_ "ADDRB(0)") (direction INPUT))
                   (port (rename ADDRB_1_ "ADDRB(1)") (direction INPUT))
                   (port (rename ADDRB_2_ "ADDRB(2)") (direction INPUT))
                   (port (rename ADDRB_3_ "ADDRB(3)") (direction INPUT))
                   (port (rename ADDRB_4_ "ADDRB(4)") (direction INPUT))
                   (port (rename ADDRB_5_ "ADDRB(5)") (direction INPUT))
                   (port (rename ADDRB_6_ "ADDRB(6)") (direction INPUT))
                   (port (rename ADDRB_7_ "ADDRB(7)") (direction INPUT))
                   (port (rename ADDRB_8_ "ADDRB(8)") (direction INPUT))
                   (port (rename DIPB_0_ "DIPB(0)") (direction INPUT))
                   (port (rename DIPB_1_ "DIPB(1)") (direction INPUT))
                   (port (rename DIPB_2_ "DIPB(2)") (direction INPUT))
                   (port (rename DIPB_3_ "DIPB(3)") (direction INPUT))
                   (port (rename DOPB_0_ "DOPB(0)") (direction OUTPUT))
                   (port (rename DOPB_1_ "DOPB(1)") (direction OUTPUT))
                   (port (rename DOPB_2_ "DOPB(2)") (direction OUTPUT))
                   (port (rename DOPB_3_ "DOPB(3)") (direction OUTPUT))
               )
           )
       )
   )
(library test_lib (edifLevel 0) (technology (numberDefinition (scale 1 (E 1 -12) (unit Time))))
(cell dual_port_block_memory_virtex2p_6_1_299a9f537bb5a43d
 (cellType GENERIC) (view view_1 (viewType NETLIST)
  (interface
   (port ( rename addra_8_ "addra(8)") (direction INPUT))
   (port ( rename addra_7_ "addra(7)") (direction INPUT))
   (port ( rename addra_6_ "addra(6)") (direction INPUT))
   (port ( rename addra_5_ "addra(5)") (direction INPUT))
   (port ( rename addra_4_ "addra(4)") (direction INPUT))
   (port ( rename addra_3_ "addra(3)") (direction INPUT))
   (port ( rename addra_2_ "addra(2)") (direction INPUT))
   (port ( rename addra_1_ "addra(1)") (direction INPUT))
   (port ( rename addra_0_ "addra(0)") (direction INPUT))
   (port ( rename addrb_7_ "addrb(7)") (direction INPUT))
   (port ( rename addrb_6_ "addrb(6)") (direction INPUT))
   (port ( rename addrb_5_ "addrb(5)") (direction INPUT))
   (port ( rename addrb_4_ "addrb(4)") (direction INPUT))
   (port ( rename addrb_3_ "addrb(3)") (direction INPUT))
   (port ( rename addrb_2_ "addrb(2)") (direction INPUT))
   (port ( rename addrb_1_ "addrb(1)") (direction INPUT))
   (port ( rename addrb_0_ "addrb(0)") (direction INPUT))
   (port ( rename clka "clka") (direction INPUT))
   (port ( rename clkb "clkb") (direction INPUT))
   (port ( rename dina_15_ "dina(15)") (direction INPUT))
   (port ( rename dina_14_ "dina(14)") (direction INPUT))
   (port ( rename dina_13_ "dina(13)") (direction INPUT))
   (port ( rename dina_12_ "dina(12)") (direction INPUT))
   (port ( rename dina_11_ "dina(11)") (direction INPUT))
   (port ( rename dina_10_ "dina(10)") (direction INPUT))
   (port ( rename dina_9_ "dina(9)") (direction INPUT))
   (port ( rename dina_8_ "dina(8)") (direction INPUT))
   (port ( rename dina_7_ "dina(7)") (direction INPUT))
   (port ( rename dina_6_ "dina(6)") (direction INPUT))
   (port ( rename dina_5_ "dina(5)") (direction INPUT))
   (port ( rename dina_4_ "dina(4)") (direction INPUT))
   (port ( rename dina_3_ "dina(3)") (direction INPUT))
   (port ( rename dina_2_ "dina(2)") (direction INPUT))
   (port ( rename dina_1_ "dina(1)") (direction INPUT))
   (port ( rename dina_0_ "dina(0)") (direction INPUT))
   (port ( rename dinb_31_ "dinb(31)") (direction INPUT))
   (port ( rename dinb_30_ "dinb(30)") (direction INPUT))
   (port ( rename dinb_29_ "dinb(29)") (direction INPUT))
   (port ( rename dinb_28_ "dinb(28)") (direction INPUT))
   (port ( rename dinb_27_ "dinb(27)") (direction INPUT))
   (port ( rename dinb_26_ "dinb(26)") (direction INPUT))
   (port ( rename dinb_25_ "dinb(25)") (direction INPUT))
   (port ( rename dinb_24_ "dinb(24)") (direction INPUT))
   (port ( rename dinb_23_ "dinb(23)") (direction INPUT))
   (port ( rename dinb_22_ "dinb(22)") (direction INPUT))
   (port ( rename dinb_21_ "dinb(21)") (direction INPUT))
   (port ( rename dinb_20_ "dinb(20)") (direction INPUT))
   (port ( rename dinb_19_ "dinb(19)") (direction INPUT))
   (port ( rename dinb_18_ "dinb(18)") (direction INPUT))
   (port ( rename dinb_17_ "dinb(17)") (direction INPUT))
   (port ( rename dinb_16_ "dinb(16)") (direction INPUT))
   (port ( rename dinb_15_ "dinb(15)") (direction INPUT))
   (port ( rename dinb_14_ "dinb(14)") (direction INPUT))
   (port ( rename dinb_13_ "dinb(13)") (direction INPUT))
   (port ( rename dinb_12_ "dinb(12)") (direction INPUT))
   (port ( rename dinb_11_ "dinb(11)") (direction INPUT))
   (port ( rename dinb_10_ "dinb(10)") (direction INPUT))
   (port ( rename dinb_9_ "dinb(9)") (direction INPUT))
   (port ( rename dinb_8_ "dinb(8)") (direction INPUT))
   (port ( rename dinb_7_ "dinb(7)") (direction INPUT))
   (port ( rename dinb_6_ "dinb(6)") (direction INPUT))
   (port ( rename dinb_5_ "dinb(5)") (direction INPUT))
   (port ( rename dinb_4_ "dinb(4)") (direction INPUT))
   (port ( rename dinb_3_ "dinb(3)") (direction INPUT))
   (port ( rename dinb_2_ "dinb(2)") (direction INPUT))
   (port ( rename dinb_1_ "dinb(1)") (direction INPUT))
   (port ( rename dinb_0_ "dinb(0)") (direction INPUT))
   (port ( rename ena "ena") (direction INPUT))
   (port ( rename enb "enb") (direction INPUT))
   (port ( rename wea "wea") (direction INPUT))
   (port ( rename web "web") (direction INPUT))
   (port ( rename douta_15_ "douta(15)") (direction OUTPUT))
   (port ( rename douta_14_ "douta(14)") (direction OUTPUT))
   (port ( rename douta_13_ "douta(13)") (direction OUTPUT))
   (port ( rename douta_12_ "douta(12)") (direction OUTPUT))
   (port ( rename douta_11_ "douta(11)") (direction OUTPUT))
   (port ( rename douta_10_ "douta(10)") (direction OUTPUT))
   (port ( rename douta_9_ "douta(9)") (direction OUTPUT))
   (port ( rename douta_8_ "douta(8)") (direction OUTPUT))
   (port ( rename douta_7_ "douta(7)") (direction OUTPUT))
   (port ( rename douta_6_ "douta(6)") (direction OUTPUT))
   (port ( rename douta_5_ "douta(5)") (direction OUTPUT))
   (port ( rename douta_4_ "douta(4)") (direction OUTPUT))
   (port ( rename douta_3_ "douta(3)") (direction OUTPUT))
   (port ( rename douta_2_ "douta(2)") (direction OUTPUT))
   (port ( rename douta_1_ "douta(1)") (direction OUTPUT))
   (port ( rename douta_0_ "douta(0)") (direction OUTPUT))
   (port ( rename doutb_31_ "doutb(31)") (direction OUTPUT))
   (port ( rename doutb_30_ "doutb(30)") (direction OUTPUT))
   (port ( rename doutb_29_ "doutb(29)") (direction OUTPUT))
   (port ( rename doutb_28_ "doutb(28)") (direction OUTPUT))
   (port ( rename doutb_27_ "doutb(27)") (direction OUTPUT))
   (port ( rename doutb_26_ "doutb(26)") (direction OUTPUT))
   (port ( rename doutb_25_ "doutb(25)") (direction OUTPUT))
   (port ( rename doutb_24_ "doutb(24)") (direction OUTPUT))
   (port ( rename doutb_23_ "doutb(23)") (direction OUTPUT))
   (port ( rename doutb_22_ "doutb(22)") (direction OUTPUT))
   (port ( rename doutb_21_ "doutb(21)") (direction OUTPUT))
   (port ( rename doutb_20_ "doutb(20)") (direction OUTPUT))
   (port ( rename doutb_19_ "doutb(19)") (direction OUTPUT))
   (port ( rename doutb_18_ "doutb(18)") (direction OUTPUT))
   (port ( rename doutb_17_ "doutb(17)") (direction OUTPUT))
   (port ( rename doutb_16_ "doutb(16)") (direction OUTPUT))
   (port ( rename doutb_15_ "doutb(15)") (direction OUTPUT))
   (port ( rename doutb_14_ "doutb(14)") (direction OUTPUT))
   (port ( rename doutb_13_ "doutb(13)") (direction OUTPUT))
   (port ( rename doutb_12_ "doutb(12)") (direction OUTPUT))
   (port ( rename doutb_11_ "doutb(11)") (direction OUTPUT))
   (port ( rename doutb_10_ "doutb(10)") (direction OUTPUT))
   (port ( rename doutb_9_ "doutb(9)") (direction OUTPUT))
   (port ( rename doutb_8_ "doutb(8)") (direction OUTPUT))
   (port ( rename doutb_7_ "doutb(7)") (direction OUTPUT))
   (port ( rename doutb_6_ "doutb(6)") (direction OUTPUT))
   (port ( rename doutb_5_ "doutb(5)") (direction OUTPUT))
   (port ( rename doutb_4_ "doutb(4)") (direction OUTPUT))
   (port ( rename doutb_3_ "doutb(3)") (direction OUTPUT))
   (port ( rename doutb_2_ "doutb(2)") (direction OUTPUT))
   (port ( rename doutb_1_ "doutb(1)") (direction OUTPUT))
   (port ( rename doutb_0_ "doutb(0)") (direction OUTPUT))
   )
  (contents
   (instance VCC (viewRef view_1 (cellRef VCC  (libraryRef xilinxun))))
   (instance GND (viewRef view_1 (cellRef GND  (libraryRef xilinxun))))
   (instance B6
      (viewRef view_1 (cellRef RAMB16_S18_S36 (libraryRef xilinxun)))
      (property INIT_00 (string "0125012501250125012501250125012501250125012501250125012501250125"))
      (property INIT_01 (string "0125012501250125012501250125012501250125012501250125012501250125"))
      (property INIT_02 (string "0125012501250125012501250125012501250125012501250125012501250125"))
      (property INIT_03 (string "0125012501250125012501250125012501250125012501250125012501250125"))
      (property INIT_04 (string "0125012501250125012501250125012501250125012501250125012501250125"))
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      (property INIT_19 (string "0125012501250125012501250125012501250125012501250125012501250125"))
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   (net N0
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      (portRef ADDRA_5_ (instanceRef B6))
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      (portRef ADDRA_4_ (instanceRef B6))
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      (portRef ADDRA_3_ (instanceRef B6))
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      (portRef ADDRA_2_ (instanceRef B6))
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      (portRef ADDRA_1_ (instanceRef B6))
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   (net (rename N12 "addrb(6)")
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      (portRef ADDRB_6_ (instanceRef B6))
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      (portRef ADDRB_5_ (instanceRef B6))
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   (net (rename N14 "addrb(4)")
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      (portRef ADDRB_4_ (instanceRef B6))
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   (net (rename N15 "addrb(3)")
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      (portRef ADDRB_3_ (instanceRef B6))
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      (portRef CLKA (instanceRef B6))
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      (portRef dinb_31_)
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      (portRef dinb_30_)
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      (portRef dinb_25_)
      (portRef DIB_25_ (instanceRef B6))
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   (net (rename N44 "dinb(24)")
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      (portRef dinb_24_)
      (portRef DIB_24_ (instanceRef B6))
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   (net (rename N45 "dinb(23)")
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      (portRef dinb_23_)
      (portRef DIB_23_ (instanceRef B6))
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   (net (rename N46 "dinb(22)")
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      (portRef dinb_22_)
      (portRef DIB_22_ (instanceRef B6))
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   (net (rename N47 "dinb(21)")
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      (portRef DIB_21_ (instanceRef B6))
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   (net (rename N48 "dinb(20)")
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      (portRef dinb_20_)
      (portRef DIB_20_ (instanceRef B6))
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   (net (rename N49 "dinb(19)")
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      (portRef dinb_19_)
      (portRef DIB_19_ (instanceRef B6))
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   (net (rename N50 "dinb(18)")
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      (portRef dinb_18_)
      (portRef DIB_18_ (instanceRef B6))
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   (net (rename N51 "dinb(17)")
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      (portRef dinb_17_)
      (portRef DIB_17_ (instanceRef B6))
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   (net (rename N52 "dinb(16)")
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      (portRef dinb_16_)
      (portRef DIB_16_ (instanceRef B6))
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   (net (rename N53 "dinb(15)")
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      (portRef dinb_15_)
      (portRef DIB_15_ (instanceRef B6))
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   (net (rename N54 "dinb(14)")
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      (portRef dinb_14_)
      (portRef DIB_14_ (instanceRef B6))
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   (net (rename N55 "dinb(13)")
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      (portRef dinb_13_)
      (portRef DIB_13_ (instanceRef B6))
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   (net (rename N56 "dinb(12)")
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      (portRef dinb_12_)
      (portRef DIB_12_ (instanceRef B6))
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   (net (rename N57 "dinb(11)")
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      (portRef dinb_11_)
      (portRef DIB_11_ (instanceRef B6))
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   (net (rename N58 "dinb(10)")
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      (portRef dinb_10_)
      (portRef DIB_10_ (instanceRef B6))
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      (portRef dinb_9_)
      (portRef DIB_9_ (instanceRef B6))
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   (net (rename N60 "dinb(8)")
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      (portRef DIB_8_ (instanceRef B6))
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   (net (rename N61 "dinb(7)")
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      (portRef DIB_7_ (instanceRef B6))
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   (net (rename N62 "dinb(6)")
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      (portRef dinb_6_)
      (portRef DIB_6_ (instanceRef B6))
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   (net (rename N63 "dinb(5)")
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      (portRef dinb_5_)
      (portRef DIB_5_ (instanceRef B6))
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   (net (rename N64 "dinb(4)")
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      (portRef dinb_4_)
      (portRef DIB_4_ (instanceRef B6))
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      (portRef DIB_3_ (instanceRef B6))
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   (net (rename N66 "dinb(2)")
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      (portRef DIB_2_ (instanceRef B6))
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      (portRef DIB_1_ (instanceRef B6))
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      (portRef DIB_0_ (instanceRef B6))
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      (portRef douta_15_)
      (portRef DOA_15_ (instanceRef B6))
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      (portRef DOA_14_ (instanceRef B6))
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   (net (rename N71 "douta(13)")
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      (portRef DOA_13_ (instanceRef B6))
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      (portRef DOA_12_ (instanceRef B6))
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      (portRef DOA_11_ (instanceRef B6))
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      (portRef DOA_10_ (instanceRef B6))
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      (portRef DOA_9_ (instanceRef B6))
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      (portRef DOA_8_ (instanceRef B6))
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      (portRef DOA_7_ (instanceRef B6))
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      (portRef DOA_6_ (instanceRef B6))
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      (portRef DOA_5_ (instanceRef B6))
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      (portRef DOA_4_ (instanceRef B6))
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      (portRef DOA_3_ (instanceRef B6))
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   )
   (net (rename N109 "doutb(7)")
    (joined
      (portRef doutb_7_)
      (portRef DOB_7_ (instanceRef B6))
    )
   )
   (net (rename N110 "doutb(6)")
    (joined
      (portRef doutb_6_)
      (portRef DOB_6_ (instanceRef B6))
    )
   )
   (net (rename N111 "doutb(5)")
    (joined
      (portRef doutb_5_)
      (portRef DOB_5_ (instanceRef B6))
    )
   )
   (net (rename N112 "doutb(4)")
    (joined
      (portRef doutb_4_)
      (portRef DOB_4_ (instanceRef B6))
    )
   )
   (net (rename N113 "doutb(3)")
    (joined
      (portRef doutb_3_)
      (portRef DOB_3_ (instanceRef B6))
    )
   )
   (net (rename N114 "doutb(2)")
    (joined
      (portRef doutb_2_)
      (portRef DOB_2_ (instanceRef B6))
    )
   )
   (net (rename N115 "doutb(1)")
    (joined
      (portRef doutb_1_)
      (portRef DOB_1_ (instanceRef B6))
    )
   )
   (net (rename N116 "doutb(0)")
    (joined
      (portRef doutb_0_)
      (portRef DOB_0_ (instanceRef B6))
    )
   )
   (net (rename N117 "ena")
    (joined
      (portRef ena)
      (portRef ENA (instanceRef B6))
    )
   )
   (net (rename N118 "enb")
    (joined
      (portRef enb)
      (portRef ENB (instanceRef B6))
    )
   )
   (net (rename N127 "wea")
    (joined
      (portRef wea)
      (portRef WEA (instanceRef B6))
    )
   )
   (net (rename N128 "web")
    (joined
      (portRef web)
      (portRef WEB (instanceRef B6))
    )
   )
))))
(design dual_port_block_memory_virtex2p_6_1_299a9f537bb5a43d (cellRef dual_port_block_memory_virtex2p_6_1_299a9f537bb5a43d (libraryRef test_lib))
  (property X_CORE_INFO (string "blkmemdp_v6_1, Coregen 8.2.03i"))
  (property PART (string "xc2vp2-fg256-7") (owner "Xilinx")))
)