Model { Name "warp_timer" Version 7.7 MdlSubVersion 0 GraphicalInterface { NumRootInports 0 NumRootOutports 0 ParameterArgumentNames "" ComputedModelVersion "1.247" NumModelReferences 0 NumTestPointedSignals 0 } SavedCharacterEncoding "windows-1252" SaveDefaultBlockParams on ScopeRefreshTime 0.035000 OverrideScopeRefreshTime on DisableAllScopes off DataTypeOverride "UseLocalSettings" DataTypeOverrideAppliesTo "AllNumericTypes" MinMaxOverflowLogging "UseLocalSettings" MinMaxOverflowArchiveMode "Overwrite" MaxMDLFileLineLength 120 Created "Sun Feb 18 17:49:04 2007" Creator "CMC" UpdateHistory "UpdateHistoryNever" ModifiedByFormat "%" LastModifiedBy "murphpo" ModifiedDateFormat "%" LastModifiedDate "Wed Apr 25 11:41:13 2012" RTWModifiedTimeStamp 257253755 ModelVersionFormat "1.%" ConfigurationManager "None" SampleTimeColors on SampleTimeAnnotations off LibraryLinkDisplay "none" WideLines off ShowLineDimensions off ShowPortDataTypes off ShowLoopsOnError on IgnoreBidirectionalLines off ShowStorageClass off ShowTestPointIcons on ShowSignalResolutionIcons on ShowViewerIcons on SortedOrder off ExecutionContextIcon off ShowLinearizationAnnotations on BlockNameDataTip off BlockParametersDataTip off BlockDescriptionStringDataTip off ToolBar on StatusBar on BrowserShowLibraryLinks off BrowserLookUnderMasks off SimulationMode "normal" LinearizationMsg "none" Profile off ParamWorkspaceSource "MATLABWorkspace" AccelSystemTargetFile "accel.tlc" AccelTemplateMakefile "accel_default_tmf" AccelMakeCommand "make_rtw" TryForcingSFcnDF off RecordCoverage off CovPath "/" CovSaveName "covdata" CovMetricSettings "dw" CovNameIncrementing off CovHtmlReporting on CovForceBlockReductionOff on covSaveCumulativeToWorkspaceVar on CovSaveSingleToWorkspaceVar on CovCumulativeVarName "covCumulativeData" CovCumulativeReport off CovReportOnPause on CovModelRefEnable "Off" CovExternalEMLEnable off ExtModeBatchMode off ExtModeEnableFloating on ExtModeTrigType "manual" ExtModeTrigMode "normal" ExtModeTrigPort "1" ExtModeTrigElement "any" ExtModeTrigDuration 1000 ExtModeTrigDurationFloating "auto" ExtModeTrigHoldOff 0 ExtModeTrigDelay 0 ExtModeTrigDirection "rising" ExtModeTrigLevel 0 ExtModeArchiveMode "off" ExtModeAutoIncOneShot off ExtModeIncDirWhenArm off ExtModeAddSuffixToVar off ExtModeWriteAllDataToWs off ExtModeArmWhenConnect on ExtModeSkipDownloadWhenConnect off ExtModeLogAll on ExtModeAutoUpdateStatusClock on BufferReuse on ShowModelReferenceBlockVersion off ShowModelReferenceBlockIO off Array { Type "Handle" Dimension 1 Simulink.ConfigSet { $ObjectID 1 Version "1.11.0" Array { Type "Handle" Dimension 8 Simulink.SolverCC { $ObjectID 2 Version "1.11.0" StartTime "0.0" StopTime "1000" AbsTol "auto" FixedStep "auto" InitialStep "auto" MaxNumMinSteps "-1" MaxOrder 5 ZcThreshold "auto" ConsecutiveZCsStepRelTol "10*128*eps" MaxConsecutiveZCs "1000" ExtrapolationOrder 4 NumberNewtonIterations 1 MaxStep "auto" MinStep "auto" MaxConsecutiveMinStep "1" RelTol "1e-3" SolverMode "Auto" ConcurrentTasks off Solver "ode45" SolverName "ode45" SolverJacobianMethodControl "auto" ShapePreserveControl "DisableAll" ZeroCrossControl "UseLocalSettings" ZeroCrossAlgorithm "Nonadaptive" AlgebraicLoopSolver "TrustRegion" SolverResetMethod "Fast" PositivePriorityOrder off AutoInsertRateTranBlk off SampleTimeConstraint "Unconstrained" InsertRTBMode "Whenever possible" } Simulink.DataIOCC { $ObjectID 3 Version "1.11.0" Decimation "1" ExternalInput "[t, u]" FinalStateName "xFinal" InitialState "xInitial" LimitDataPoints on MaxDataPoints "1000" LoadExternalInput off LoadInitialState off SaveFinalState off SaveCompleteFinalSimState off SaveFormat "Array" SignalLoggingSaveFormat "ModelDataLogs" SaveOutput on SaveState off SignalLogging on DSMLogging on InspectSignalLogs off SaveTime on ReturnWorkspaceOutputs off StateSaveName "xout" TimeSaveName "tout" OutputSaveName "yout" SignalLoggingName "logsout" DSMLoggingName "dsmout" OutputOption "RefineOutputTimes" OutputTimes "[]" ReturnWorkspaceOutputsName "out" Refine "1" } Simulink.OptimizationCC { $ObjectID 4 Version "1.11.0" Array { Type "Cell" Dimension 4 Cell "ZeroExternalMemoryAtStartup" Cell "ZeroInternalMemoryAtStartup" Cell "NoFixptDivByZeroProtection" Cell "OptimizeModelRefInitCode" PropName "DisabledProps" } BlockReduction on BooleanDataType on ConditionallyExecuteInputs on InlineParams off UseIntDivNetSlope off UseSpecifiedMinMax off InlineInvariantSignals off OptimizeBlockIOStorage on BufferReuse on EnhancedBackFolding off StrengthReduction off ExpressionFolding on BooleansAsBitfields off BitfieldContainerType "uint_T" EnableMemcpy on MemcpyThreshold 64 PassReuseOutputArgsAs "Structure reference" ExpressionDepthLimit 2147483647 FoldNonRolledExpr on LocalBlockOutputs on RollThreshold 5 SystemCodeInlineAuto off StateBitsets off DataBitsets off UseTempVars off ZeroExternalMemoryAtStartup on ZeroInternalMemoryAtStartup on InitFltsAndDblsToZero on NoFixptDivByZeroProtection off EfficientFloat2IntCast off EfficientMapNaN2IntZero on OptimizeModelRefInitCode off LifeSpan "inf" MaxStackSize "Inherit from target" BufferReusableBoundary on SimCompilerOptimization "Off" AccelVerboseBuild off AccelParallelForEachSubsystem on } Simulink.DebuggingCC { $ObjectID 5 Version "1.11.0" RTPrefix "error" ConsistencyChecking "none" ArrayBoundsChecking "none" SignalInfNanChecking "none" SignalRangeChecking "none" ReadBeforeWriteMsg "UseLocalSettings" WriteAfterWriteMsg "UseLocalSettings" WriteAfterReadMsg "UseLocalSettings" AlgebraicLoopMsg "warning" ArtificialAlgebraicLoopMsg "warning" SaveWithDisabledLinksMsg "warning" SaveWithParameterizedLinksMsg "none" CheckSSInitialOutputMsg on UnderspecifiedInitializationDetection "Classic" MergeDetectMultiDrivingBlocksExec "none" CheckExecutionContextPreStartOutputMsg off CheckExecutionContextRuntimeOutputMsg off SignalResolutionControl "TryResolveAllWithWarning" BlockPriorityViolationMsg "warning" MinStepSizeMsg "warning" TimeAdjustmentMsg "none" MaxConsecutiveZCsMsg "error" MaskedZcDiagnostic "warning" IgnoredZcDiagnostic "warning" SolverPrmCheckMsg "warning" InheritedTsInSrcMsg "warning" DiscreteInheritContinuousMsg "warning" MultiTaskDSMMsg "warning" MultiTaskCondExecSysMsg "none" MultiTaskRateTransMsg "error" SingleTaskRateTransMsg "none" TasksWithSamePriorityMsg "warning" SigSpecEnsureSampleTimeMsg "warning" CheckMatrixSingularityMsg "none" IntegerOverflowMsg "warning" Int32ToFloatConvMsg "warning" ParameterDowncastMsg "error" ParameterOverflowMsg "error" ParameterUnderflowMsg "none" ParameterPrecisionLossMsg "warning" ParameterTunabilityLossMsg "warning" FixptConstUnderflowMsg "none" FixptConstOverflowMsg "none" FixptConstPrecisionLossMsg "none" UnderSpecifiedDataTypeMsg "none" UnnecessaryDatatypeConvMsg "none" VectorMatrixConversionMsg "none" InvalidFcnCallConnMsg "error" FcnCallInpInsideContextMsg "Use local settings" SignalLabelMismatchMsg "none" UnconnectedInputMsg "warning" UnconnectedOutputMsg "warning" UnconnectedLineMsg "warning" SFcnCompatibilityMsg "none" UniqueDataStoreMsg "none" BusObjectLabelMismatch "warning" RootOutportRequireBusObject "warning" AssertControl "UseLocalSettings" EnableOverflowDetection off ModelReferenceIOMsg "none" ModelReferenceMultiInstanceNormalModeStructChecksumCheck "error" ModelReferenceVersionMismatchMessage "none" ModelReferenceIOMismatchMessage "none" ModelReferenceCSMismatchMessage "none" UnknownTsInhSupMsg "warning" ModelReferenceDataLoggingMessage "warning" ModelReferenceSymbolNameMessage "warning" ModelReferenceExtraNoncontSigs "error" StateNameClashWarn "warning" SimStateInterfaceChecksumMismatchMsg "warning" SimStateOlderReleaseMsg "error" InitInArrayFormatMsg "warning" StrictBusMsg "Warning" BusNameAdapt "WarnAndRepair" NonBusSignalsTreatedAsBus "none" LoggingUnavailableSignals "error" BlockIODiagnostic "none" SFUnusedDataAndEventsDiag "warning" SFUnexpectedBacktrackingDiag "warning" SFInvalidInputDataAccessInChartInitDiag "warning" SFNoUnconditionalDefaultTransitionDiag "warning" SFTransitionOutsideNaturalParentDiag "warning" } Simulink.HardwareCC { $ObjectID 6 Version "1.11.0" ProdBitPerChar 8 ProdBitPerShort 16 ProdBitPerInt 32 ProdBitPerLong 32 ProdBitPerFloat 32 ProdBitPerDouble 64 ProdBitPerPointer 32 ProdLargestAtomicInteger "Char" ProdLargestAtomicFloat "None" ProdIntDivRoundTo "Undefined" ProdEndianess "Unspecified" ProdWordSize 32 ProdShiftRightIntArith on ProdHWDeviceType "32-bit Generic" TargetBitPerChar 8 TargetBitPerShort 16 TargetBitPerInt 32 TargetBitPerLong 32 TargetBitPerFloat 32 TargetBitPerDouble 64 TargetBitPerPointer 32 TargetLargestAtomicInteger "Char" TargetLargestAtomicFloat "None" TargetShiftRightIntArith on TargetIntDivRoundTo "Undefined" TargetEndianess "Unspecified" TargetWordSize 32 TargetTypeEmulationWarnSuppressLevel 0 TargetPreprocMaxBitsSint 32 TargetPreprocMaxBitsUint 32 TargetHWDeviceType "Specified" TargetUnknown off ProdEqTarget on } Simulink.ModelReferenceCC { $ObjectID 7 Version "1.11.0" UpdateModelReferenceTargets "IfOutOfDateOrStructuralChange" CheckModelReferenceTargetMessage "error" EnableParallelModelReferenceBuilds off ParallelModelReferenceErrorOnInvalidPool on ParallelModelReferenceMATLABWorkerInit "None" ModelReferenceNumInstancesAllowed "Multi" PropagateVarSize "Infer from blocks in model" ModelReferencePassRootInputsByReference on ModelReferenceMinAlgLoopOccurrences off PropagateSignalLabelsOutOfModel off SupportModelReferenceSimTargetCustomCode off } Simulink.SFSimCC { $ObjectID 8 Version "1.11.0" SFSimEnableDebug on SFSimOverflowDetection on SFSimEcho on SimBlas on SimCtrlC on SimExtrinsic on SimIntegrity on SimUseLocalCustomCode off SimParseCustomCode on SimBuildMode "sf_incremental_build" } Simulink.RTWCC { $BackupClass "Simulink.RTWCC" $ObjectID 9 Version "1.11.0" Array { Type "Cell" Dimension 1 Cell "IncludeHyperlinkInReport" PropName "DisabledProps" } SystemTargetFile "grt.tlc" GenCodeOnly off MakeCommand "make_rtw" GenerateMakefile on TemplateMakefile "grt_default_tmf" GenerateReport off SaveLog off RTWVerbose on RetainRTWFile off ProfileTLC off TLCDebug off TLCCoverage off TLCAssert off ProcessScriptMode "Default" ConfigurationMode "Optimized" ConfigAtBuild off RTWUseLocalCustomCode off RTWUseSimCustomCode off IncludeHyperlinkInReport off LaunchReport off TargetLang "C" IncludeBusHierarchyInRTWFileBlockHierarchyMap off IncludeERTFirstTime on GenerateTraceInfo off GenerateTraceReport off GenerateTraceReportSl off GenerateTraceReportSf off GenerateTraceReportEml off GenerateCodeInfo off GenerateSLWebview off GenerateCodeMetricsReport off RTWCompilerOptimization "Off" CheckMdlBeforeBuild "Off" CustomRebuildMode "OnUpdate" Array { Type "Handle" Dimension 2 Simulink.CodeAppCC { $ObjectID 10 Version "1.11.0" Array { Type "Cell" Dimension 9 Cell "IgnoreCustomStorageClasses" Cell "InsertBlockDesc" Cell "SFDataObjDesc" Cell "SimulinkDataObjDesc" Cell "DefineNamingRule" Cell "SignalNamingRule" Cell "ParamNamingRule" Cell "InlinedPrmAccess" Cell "CustomSymbolStr" PropName "DisabledProps" } ForceParamTrailComments off GenerateComments on IgnoreCustomStorageClasses on IgnoreTestpoints off IncHierarchyInIds off MaxIdLength 31 PreserveName off PreserveNameWithParent off ShowEliminatedStatement off IncAutoGenComments off SimulinkDataObjDesc off SFDataObjDesc off MATLABFcnDesc off IncDataTypeInIds off MangleLength 1 CustomSymbolStrGlobalVar "$R$N$M" CustomSymbolStrType "$N$R$M" CustomSymbolStrField "$N$M" CustomSymbolStrFcn "$R$N$M$F" CustomSymbolStrFcnArg "rt$I$N$M" CustomSymbolStrBlkIO "rtb_$N$M" CustomSymbolStrTmpVar "$N$M" CustomSymbolStrMacro "$R$N$M" DefineNamingRule "None" ParamNamingRule "None" SignalNamingRule "None" InsertBlockDesc off InsertPolySpaceComments off SimulinkBlockComments on MATLABSourceComments off EnableCustomComments off InlinedPrmAccess "Literals" ReqsInCode off UseSimReservedNames off } Simulink.GRTTargetCC { $BackupClass "Simulink.TargetCC" $ObjectID 11 Version "1.11.0" Array { Type "Cell" Dimension 11 Cell "IncludeMdlTerminateFcn" Cell "CombineOutputUpdateFcns" Cell "SuppressErrorStatus" Cell "ERTCustomFileBanners" Cell "GenerateSampleERTMain" Cell "MultiInstanceERTCode" Cell "PurelyIntegerCode" Cell "SupportNonInlinedSFcns" Cell "SupportComplex" Cell "SupportAbsoluteTime" Cell "SupportContinuousTime" PropName "DisabledProps" } TargetFcnLib "ansi_tfl_tmw.mat" TargetLibSuffix "" TargetPreCompLibLocation "" TargetFunctionLibrary "ANSI_C" UtilityFuncGeneration "Auto" ERTMultiwordTypeDef "System defined" FunctionExecutionProfile off CodeExecutionProfiling off ERTCodeCoverageTool "None" ERTMultiwordLength 256 MultiwordLength 2048 GenerateFullHeader on GenerateSampleERTMain off GenerateTestInterfaces off IsPILTarget off ModelReferenceCompliant on ParMdlRefBuildCompliant on CompOptLevelCompliant on IncludeMdlTerminateFcn on GeneratePreprocessorConditionals "Disable all" CombineOutputUpdateFcns off CombineSignalStateStructs off SuppressErrorStatus off ERTFirstTimeCompliant off IncludeFileDelimiter "Auto" ERTCustomFileBanners off SupportAbsoluteTime on LogVarNameModifier "rt_" MatFileLogging on MultiInstanceERTCode off SupportNonFinite on SupportComplex on PurelyIntegerCode off SupportContinuousTime on SupportNonInlinedSFcns on SupportVariableSizeSignals off EnableShiftOperators on ParenthesesLevel "Nominal" PortableWordSizes off ModelStepFunctionPrototypeControlCompliant off CPPClassGenCompliant off AutosarCompliant off UseMalloc off ExtMode off ExtModeStaticAlloc off ExtModeTesting off ExtModeStaticAllocSize 1000000 ExtModeTransport 0 ExtModeMexFile "ext_comm" ExtModeIntrfLevel "Level1" RTWCAPISignals off RTWCAPIParams off RTWCAPIStates off RTWCAPIRootIO off GenerateASAP2 off } PropName "Components" } } PropName "Components" } Name "Configuration" CurrentDlgPage "Solver" ConfigPrmDlgPosition [ 840, 485, 1720, 1115 ] } PropName "ConfigurationSets" } Simulink.ConfigSet { $PropName "ActiveConfigurationSet" $ObjectID 1 } BlockDefaults { ForegroundColor "black" BackgroundColor "white" DropShadow off NamePlacement "normal" FontName "Arial" FontSize 10 FontWeight "normal" FontAngle "normal" ShowName on BlockRotation 0 BlockMirror off } AnnotationDefaults { HorizontalAlignment "center" VerticalAlignment "middle" ForegroundColor "black" BackgroundColor "white" DropShadow off FontName "Arial" FontSize 10 FontWeight "normal" FontAngle "normal" UseDisplayTextAsClickCallback off } LineDefaults { FontName "Arial" FontSize 9 FontWeight "normal" FontAngle "normal" } BlockParameterDefaults { Block { BlockType Constant Value "1" VectorParams1D on SamplingMode "Sample based" OutMin "[]" OutMax "[]" OutDataTypeStr "Inherit: Inherit from 'Constant value'" LockScale off SampleTime "inf" FramePeriod "inf" PreserveConstantTs off } Block { BlockType From IconDisplay "Tag" TagVisibility "local" } Block { BlockType Goto IconDisplay "Tag" } Block { BlockType Inport Port "1" OutputFunctionCall off OutMin "[]" OutMax "[]" OutDataTypeStr "Inherit: auto" LockScale off BusOutputAsStruct off PortDimensions "-1" VarSizeSig "Inherit" SampleTime "-1" SignalType "auto" SamplingMode "auto" LatchByDelayingOutsideSignal off LatchInputForFeedbackSignals off Interpolate on } Block { BlockType Outport Port "1" OutMin "[]" OutMax "[]" OutDataTypeStr "Inherit: auto" LockScale off BusOutputAsStruct off PortDimensions "-1" VarSizeSig "Inherit" SampleTime "-1" SignalType "auto" SamplingMode "auto" SourceOfInitialOutputValue "Dialog" OutputWhenDisabled "held" InitialOutput "[]" } Block { BlockType Scope ModelBased off TickLabels "OneTimeTick" ZoomMode "on" Grid "on" TimeRange "auto" YMin "-5" YMax "5" SaveToWorkspace off SaveName "ScopeData" LimitDataPoints on MaxDataPoints "5000" Decimation "1" SampleInput off SampleTime "-1" } Block { BlockType SubSystem ShowPortLabels "FromPortIcon" Permissions "ReadWrite" PermitHierarchicalResolution "All" TreatAsAtomicUnit off CheckFcnCallInpInsideContextMsg off SystemSampleTime "-1" RTWFcnNameOpts "Auto" RTWFileNameOpts "Auto" RTWMemSecFuncInitTerm "Inherit from model" RTWMemSecFuncExecute "Inherit from model" RTWMemSecDataConstants "Inherit from model" RTWMemSecDataInternal "Inherit from model" RTWMemSecDataParameters "Inherit from model" SimViewingDevice off DataTypeOverride "UseLocalSettings" DataTypeOverrideAppliesTo "AllNumericTypes" MinMaxOverflowLogging "UseLocalSettings" Variant off GeneratePreprocessorConditionals off } Block { BlockType Terminator } } System { Name "warp_timer" Location [465, 259, 2161, 1341] Open on ModelBrowserVisibility on ModelBrowserWidth 212 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" ReportName "simulink-default.rpt" SIDHighWatermark "872" Block { BlockType Reference Name " System Generator" SID "1" Tag "genX" Ports [] Position [517, 687, 568, 737] ShowName off AttributesFormatString "System\\nGenerator" LibraryVersion "1.2" UserDataPersistent on UserData "DataTag0" SourceBlock "xbsIndex_r4/ System Generator" SourceType "Xilinx System Generator Block" ShowPortLabels "FromPortIcon" SystemSampleTime "-1" FunctionWithSeparateData off RTWMemSecFuncInitTerm "Inherit from model" RTWMemSecFuncExecute "Inherit from model" RTWMemSecDataConstants "Inherit from model" RTWMemSecDataInternal "Inherit from model" RTWMemSecDataParameters "Inherit from model" GeneratePreprocessorConditionals off infoedit " System Generator" xilinxfamily "virtex4" part "xc4vfx100" speed "-11" package "ff1517" synthesis_tool "XST" clock_wrapper "Clock Enables" directory "./pcore_v4_v10" proj_type "Project Navigator" Synth_file "XST Defaults" Impl_file "ISE Defaults" testbench off simulink_period "1" sysclk_period "10" dcm_input_clock_period "100" incr_netlist off trim_vbits "Everywhere in SubSystem" dbl_ovrd "According to Block Masks" core_generation "According to Block Masks" run_coregen off deprecated_control off eval_field "0" has_advanced_control "0" sggui_pos "326,241,464,470" block_type "sysgen" block_version "8.2" sg_icon_stat "51,50,0,0,token,white,0,58c5b5770fe5f7c311f53dbc6e73f0f6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 51 51 0 0 ],[0 0 50 50 0 ],[1 1 1 ]" ");\npatch([1.6375 16.81 27.31 37.81 48.31 27.31 12.1375 1.6375 ],[36.655 36.655 47.155 36.655 47.155 47.155 47.1" "55 36.655 ],[0.933333 0.203922 0.141176 ]);\npatch([12.1375 27.31 16.81 1.6375 12.1375 ],[26.155 26.155 36.655 3" "6.655 26.155 ],[0.698039 0.0313725 0.219608 ]);\npatch([1.6375 16.81 27.31 12.1375 1.6375 ],[15.655 15.655 26.15" "5 26.155 15.655 ],[0.933333 0.203922 0.141176 ]);\npatch([12.1375 48.31 37.81 27.31 16.81 1.6375 12.1375 ],[5.15" "5 5.155 15.655 5.155 15.655 15.655 5.155 ],[0.698039 0.0313725 0.219608 ]);\nfprintf('','COMMENT: end icon graph" "ics');\nfprintf('','COMMENT: begin icon text');\n\nfprintf('','COMMENT: end icon text');" sg_blockgui_xml "\n \n \n" " \n \n \n \n" " \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n \n " " \n \n \n \n \n \n \n \n \n\n" } Block { BlockType Reference Name "BitBasher" SID "2" Ports [3, 1] Position [480, 77, 515, 173] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/BitBasher" SourceType "Xilinx BitBasher Block" infoedit "Allows extraction, concatenation and augmentation of bits" bitexpr "\n

Q={1'b0,a,b,c}

" display_expr off sr_1 "1" arith_type1 "Unsigned" bin_pt1 "0" sr_2 "2" arith_type2 "Unsigned" bin_pt2 "0" sr_3 "3" arith_type3 "Unsigned" bin_pt3 "0" sr_4 "4" arith_type4 "Unsigned" bin_pt4 "0" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,336,351" block_type "bitbasher" block_version "10.1.3" sg_icon_stat "35,96,3,1,white,blue,0,b4ae94c9,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 96 96 0 ],[0.77 0." "82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 96 96 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[53.55 5" "3.55 58.55 53.55 58.55 58.55 58.55 53.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[48.55 48.55 53.55" " 53.55 48.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[43.55 43.55 48.55 48.55 43.55 ],[1" " 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[38.55 38.55 43.55 38.55 43.55 43.55 38.55 ],[0.931 0" ".946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('input',3,'c" "');\ncolor('black');port_label('output',1,'Q');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "BitBasher1" SID "3" Ports [3, 1] Position [480, 212, 515, 308] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/BitBasher" SourceType "Xilinx BitBasher Block" infoedit "Allows extraction, concatenation and augmentation of bits" bitexpr "\n

Q={1'b0,a,b,c}

" display_expr off sr_1 "1" arith_type1 "Unsigned" bin_pt1 "0" sr_2 "2" arith_type2 "Unsigned" bin_pt2 "0" sr_3 "3" arith_type3 "Unsigned" bin_pt3 "0" sr_4 "4" arith_type4 "Unsigned" bin_pt4 "0" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,336,351" block_type "bitbasher" block_version "10.1.3" sg_icon_stat "35,96,3,1,white,blue,0,b4ae94c9,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 96 96 0 ],[0.77 0." "82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 96 96 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[53.55 5" "3.55 58.55 53.55 58.55 58.55 58.55 53.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[48.55 48.55 53.55" " 53.55 48.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[43.55 43.55 48.55 48.55 43.55 ],[1" " 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[38.55 38.55 43.55 38.55 43.55 43.55 38.55 ],[0.931 0" ".946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('input',3,'c" "');\ncolor('black');port_label('output',1,'Q');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "BitBasher2" SID "4" Ports [3, 1] Position [480, 347, 515, 443] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/BitBasher" SourceType "Xilinx BitBasher Block" infoedit "Allows extraction, concatenation and augmentation of bits" bitexpr "\n

Q={1'b0,a,b,c}

" display_expr off sr_1 "1" arith_type1 "Unsigned" bin_pt1 "0" sr_2 "2" arith_type2 "Unsigned" bin_pt2 "0" sr_3 "3" arith_type3 "Unsigned" bin_pt3 "0" sr_4 "4" arith_type4 "Unsigned" bin_pt4 "0" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,336,351" block_type "bitbasher" block_version "10.1.3" sg_icon_stat "35,96,3,1,white,blue,0,b4ae94c9,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 96 96 0 ],[0.77 0." "82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 96 96 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[53.55 5" "3.55 58.55 53.55 58.55 58.55 58.55 53.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[48.55 48.55 53.55" " 53.55 48.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[43.55 43.55 48.55 48.55 43.55 ],[1" " 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[38.55 38.55 43.55 38.55 43.55 43.55 38.55 ],[0.931 0" ".946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('input',3,'c" "');\ncolor('black');port_label('output',1,'Q');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "BitBasher3" SID "5" Ports [3, 1] Position [480, 487, 515, 583] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/BitBasher" SourceType "Xilinx BitBasher Block" infoedit "Allows extraction, concatenation and augmentation of bits" bitexpr "\n

Q={1'b0,a,b,c}

" display_expr off sr_1 "1" arith_type1 "Unsigned" bin_pt1 "0" sr_2 "2" arith_type2 "Unsigned" bin_pt2 "0" sr_3 "3" arith_type3 "Unsigned" bin_pt3 "0" sr_4 "4" arith_type4 "Unsigned" bin_pt4 "0" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,336,351" block_type "bitbasher" block_version "10.1.3" sg_icon_stat "35,96,3,1,white,blue,0,b4ae94c9,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 96 96 0 ],[0.77 0." "82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 96 96 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[53.55 5" "3.55 58.55 53.55 58.55 58.55 58.55 53.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[48.55 48.55 53.55" " 53.55 48.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[43.55 43.55 48.55 48.55 43.55 ],[1" " 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[38.55 38.55 43.55 38.55 43.55 43.55 38.55 ],[0.931 0" ".946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('input',3,'c" "');\ncolor('black');port_label('output',1,'Q');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "BitBasher4" SID "6" Ports [3, 1] Position [1010, 67, 1045, 163] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/BitBasher" SourceType "Xilinx BitBasher Block" infoedit "Allows extraction, concatenation and augmentation of bits" bitexpr "\n

Q={1'b0,a,b,c}

" display_expr off sr_1 "1" arith_type1 "Unsigned" bin_pt1 "0" sr_2 "2" arith_type2 "Unsigned" bin_pt2 "0" sr_3 "3" arith_type3 "Unsigned" bin_pt3 "0" sr_4 "4" arith_type4 "Unsigned" bin_pt4 "0" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,336,351" block_type "bitbasher" block_version "10.1.3" sg_icon_stat "35,96,3,1,white,blue,0,b4ae94c9,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 96 96 0 ],[0.77 0." "82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 96 96 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[53.55 5" "3.55 58.55 53.55 58.55 58.55 58.55 53.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[48.55 48.55 53.55" " 53.55 48.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[43.55 43.55 48.55 48.55 43.55 ],[1" " 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[38.55 38.55 43.55 38.55 43.55 43.55 38.55 ],[0.931 0" ".946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('input',3,'c" "');\ncolor('black');port_label('output',1,'Q');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "BitBasher5" SID "7" Ports [3, 1] Position [1010, 202, 1045, 298] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/BitBasher" SourceType "Xilinx BitBasher Block" infoedit "Allows extraction, concatenation and augmentation of bits" bitexpr "\n

Q={1'b0,a,b,c}

" display_expr off sr_1 "1" arith_type1 "Unsigned" bin_pt1 "0" sr_2 "2" arith_type2 "Unsigned" bin_pt2 "0" sr_3 "3" arith_type3 "Unsigned" bin_pt3 "0" sr_4 "4" arith_type4 "Unsigned" bin_pt4 "0" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,336,351" block_type "bitbasher" block_version "10.1.3" sg_icon_stat "35,96,3,1,white,blue,0,b4ae94c9,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 96 96 0 ],[0.77 0." "82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 96 96 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[53.55 5" "3.55 58.55 53.55 58.55 58.55 58.55 53.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[48.55 48.55 53.55" " 53.55 48.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[43.55 43.55 48.55 48.55 43.55 ],[1" " 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[38.55 38.55 43.55 38.55 43.55 43.55 38.55 ],[0.931 0" ".946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('input',3,'c" "');\ncolor('black');port_label('output',1,'Q');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "BitBasher6" SID "8" Ports [3, 1] Position [1010, 337, 1045, 433] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/BitBasher" SourceType "Xilinx BitBasher Block" infoedit "Allows extraction, concatenation and augmentation of bits" bitexpr "\n

Q={1'b0,a,b,c}

" display_expr off sr_1 "1" arith_type1 "Unsigned" bin_pt1 "0" sr_2 "2" arith_type2 "Unsigned" bin_pt2 "0" sr_3 "3" arith_type3 "Unsigned" bin_pt3 "0" sr_4 "4" arith_type4 "Unsigned" bin_pt4 "0" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,336,351" block_type "bitbasher" block_version "10.1.3" sg_icon_stat "35,96,3,1,white,blue,0,b4ae94c9,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 96 96 0 ],[0.77 0." "82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 96 96 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[53.55 5" "3.55 58.55 53.55 58.55 58.55 58.55 53.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[48.55 48.55 53.55" " 53.55 48.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[43.55 43.55 48.55 48.55 43.55 ],[1" " 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[38.55 38.55 43.55 38.55 43.55 43.55 38.55 ],[0.931 0" ".946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('input',3,'c" "');\ncolor('black');port_label('output',1,'Q');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "BitBasher7" SID "9" Ports [3, 1] Position [1010, 477, 1045, 573] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/BitBasher" SourceType "Xilinx BitBasher Block" infoedit "Allows extraction, concatenation and augmentation of bits" bitexpr "\n

Q={1'b0,a,b,c}

" display_expr off sr_1 "1" arith_type1 "Unsigned" bin_pt1 "0" sr_2 "2" arith_type2 "Unsigned" bin_pt2 "0" sr_3 "3" arith_type3 "Unsigned" bin_pt3 "0" sr_4 "4" arith_type4 "Unsigned" bin_pt4 "0" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,336,351" block_type "bitbasher" block_version "10.1.3" sg_icon_stat "35,96,3,1,white,blue,0,b4ae94c9,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 96 96 0 ],[0.77 0." "82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 96 96 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[53.55 5" "3.55 58.55 53.55 58.55 58.55 58.55 53.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[48.55 48.55 53.55" " 53.55 48.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[43.55 43.55 48.55 48.55 43.55 ],[1" " 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[38.55 38.55 43.55 38.55 43.55 43.55 38.55 ],[0.931 0" ".946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('input',3,'c" "');\ncolor('black');port_label('output',1,'Q');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Constant Name "Constant" SID "10" Position [25, 176, 45, 194] ShowName off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType SubSystem Name "EDK Processor" SID "869" Ports [] Position [438, 692, 488, 741] CopyFcn "xlProcBlockCopyCallback(gcbh);xlBlockMoveCallback(gcbh);" DeleteFcn "xlDestroyGui(gcbh);" LoadFcn "xlBlockLoadCallback(gcbh);" ModelCloseFcn "xlDestroyGui(gcbh);" PreSaveFcn "xlBlockPreSaveCallback(gcbh);" PostSaveFcn "xlBlockPostSaveCallback(gcbh);" DestroyFcn "xlDestroyGui(gcbh);" OpenFcn "bh=gcbh;xlProcBlockCallbacks('populatesharedmemorylistbox',bh);xlOpenGui(bh, 'edkprocessor_gui.x" "ml', @xlProcBlockEnablement, @xlProcBlockAction);" CloseFcn "xlDestroyGui(gcbh);" MoveFcn "xlBlockMoveCallback(gcbh);" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskType "Xilinx EDK Processor Block" MaskDescription "Xilinx EDK Processor" MaskHelp "eval('');xlDoc('-book','sysgen','-topic','EDK_Processor');" MaskPromptString "Configure Processor for|XPS Project| |Available Memories| | |Bus Type|Base Address| |Loc" "k| |Dual Clocks| |Register Read-Back|Constraint File| |Inherit Device Type|Initial Program| |Enable Co-Debug wit" "h Xilinx SDK (Beta)| | | | | | | | | | | | | | | | " MaskStyleString "popup(EDK pcore generation|HDL netlisting),edit,edit,edit,edit,edit,popup(AXI|PLB),edit,e" "dit,checkbox,edit,checkbox,edit,checkbox,edit,edit,checkbox,edit,edit,checkbox,edit,edit,edit,edit,edit,edit,edi" "t,edit,edit,edit,edit,edit,edit,edit,edit,edit" MaskVariables "mode=&1;xmp=&2;MemVisToProc=&3;AvailableMemories=&4;portInterfaceTable=&5;bus_type_sgadvanc" "ed=&6;bus_type=&7;baseaddr=&8;baseaddr_lock_sgadvanced=&9;baseaddr_lock=@10;dual_clock_sgadvanced=&11;dual_clock" "=@12;reg_readback_sgadvanced=&13;reg_readback=@14;ucf_file=&15;inheritDeviceType_sgadvanced=&16;inheritDeviceTyp" "e=@17;elf_file=&18;codebug_sgadvanced=&19;codebug=@20;clock_name=&21;internalPortList=&22;resetPolarity=&23;memx" "table=&24;procinfo=&25;memmapdirty=&26;blockname=&27;xpsintstyle=&28;has_advanced_control=@29;sggui_pos=&30;bloc" "k_type=&31;block_version=&32;sg_icon_stat=&33;sg_mask_display=&34;sg_list_contents=&35;sg_blockgui_xml=&36;" MaskTunableValueString "on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on," "on,on,on,on,on,on,on" MaskCallbackString "|||||||||||||||||||||||||||||||||||" MaskEnableString "on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,o" "n,on,on,on,on,on,on" MaskVisibilityString "on,on,off,on,on,off,on,on,off,on,off,on,off,on,on,off,on,on,off,on,off,off,off,off,off," "off,off,off,off,off,off,off,off,off,off,off" MaskToolTipString "on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on," "on,on,on,on,on,on,on" MaskInitialization "try\n tmp_gcb = gcb;\n tmp_gcbh = gcbh;\n if (strcmp('SysGenIndex',get_param(bdroot(" "tmp_gcbh),'tag')) && ~isempty(regexp(bdroot(tmp_gcb), '^xbs', 'once')))\n return;\n end;\n xlMungeMaskParam" "s;\n\n block_type='edkprocessor';\n\n serialized_declarations = '{''block_type''=>''String''}';\n xledkproces" "sor_init();\n ptable_ = xlblockprep(get_param(tmp_gcb, 'MaskWSVariables'));\n try\n xlBlockMoveCallback(tmp" "_gcbh);\n catch \n clear global xl_updateicon_recursion_guard;\n end;\ncatch\n global dbgsysgen;\n if(~i" "sempty(dbgsysgen) && dbgsysgen)\n e = regexprep(lasterr, '\\n', '\\nError: ');\n disp(['Error: While runni" "ng MaskInit code on block ' tmp_gcb ': ' e]);\n error(e);\n end\nend\n" MaskSelfModifiable on MaskDisplay "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 49 49 0 ],[0.77 0.82 0" ".91 ]);\nplot([0 50 50 0 0 ],[0 0 49 49 0 ]);\npatch([9.425 19.54 26.54 33.54 40.54 26.54 16.425 9.425 ],[31.77 " "31.77 38.77 31.77 38.77 38.77 38.77 31.77 ],[1 1 1 ]);\npatch([16.425 26.54 19.54 9.425 16.425 ],[24.77 24.77 31" ".77 31.77 24.77 ],[0.931 0.946 0.973 ]);\npatch([9.425 19.54 26.54 16.425 9.425 ],[17.77 17.77 24.77 24.77 17.77" " ],[1 1 1 ]);\npatch([16.425 40.54 33.54 26.54 19.54 9.425 16.425 ],[10.77 10.77 17.77 10.77 17.77 17.77 10.77 ]" ",[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ndis" "p('');\n\nfprintf('','COMMENT: end icon text');" MaskIconFrame off MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" MaskValueString "EDK pcore generation||
<<timer0_slotCount>>
<<timer_control>>
<<timer4_slotCount>>
<<timer6_slotCount>>
<<timer7_slotCount>><" "br>
<<timer5_slotCou" "nt>>
<<tim" "er2_slotCount>>
" "<<timer3_slotCount>>
<<timers67_slotTime>>
<<timers45_slotTime>>
<<timers23_slotTime>>
<<timers01_slotTime>>
<<timer1_slotCount>>
<<timer_status>>
||{'exposed'=>[],'portdir'=>[],'portname'=>[],'shortname'=>[]}||PLB|0x80000000||off||off||on|||off|||on|" "plb|{}|0|{'mladdr'=>[0.00000000000000000,1.00000000000000000,2.00000000000000000,3.00000000000000000,4.000000000" "00000000,5.00000000000000000,6.00000000000000000,7.00000000000000000,8.00000000000000000,9.00000000000000000,10." "00000000000000000,11.00000000000000000,12.00000000000000000,0.00000000000000000],'mlist'=>['warp_timer/Registers" "/From Register9','warp_timer/Registers/From Register8','warp_timer/Registers/From Register7','warp_timer/Registe" "rs/From Register6','warp_timer/Registers/From Register5','warp_timer/Registers/From Register4','warp_timer/Regis" "ters/From Register3','warp_timer/Registers/From Register2','warp_timer/Registers/From Register14','warp_timer/Re" "gisters/From Register13','warp_timer/Registers/From Register12','warp_timer/Registers/From Register11','warp_tim" "er/Registers/From Register1','warp_timer/Registers/To Register4'],'mlname'=>['\\\\'timer0_slotCount\\\\'','\\\\'" "timer_control\\\\'','\\\\'timer4_slotCount\\\\'','\\\\'timer6_slotCount\\\\'','\\\\'timer7_slotCount\\\\'','\\\\" "'timer5_slotCount\\\\'','\\\\'timer2_slotCount\\\\'','\\\\'timer3_slotCount\\\\'','\\\\'timers67_slotTime\\\\''," "'\\\\'timers45_slotTime\\\\'','\\\\'timers23_slotTime\\\\'','\\\\'timers01_slotTime\\\\'','\\\\'timer1_slotCount" "\\\\'','\\\\'timer_status\\\\''],'mlstate'=>[0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000" "000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000" ",0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000]}|{}|off||d" "efault|0|-1,-1,-1,-1|edkprocessor|2.7|50,49,-1,-1,white,blue,0,07734,right,,[ ],[ ]|fprintf('','COMMENT: begin i" "con graphics');\npatch([0 50 50 0 0 ],[0 0 49 49 0 ],[0.77 0.82 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 49 49 0 ]);\n" "patch([9.425 19.54 26.54 33.54 40.54 26.54 16.425 9.425 ],[31.77 31.77 38.77 31.77 38.77 38.77 38.77 31.77 ],[1 " "1 1 ]);\npatch([16.425 26.54 19.54 9.425 16.425 ],[24.77 24.77 31.77 31.77 24.77 ],[0.931 0.946 0.973 ]);\npatch" "([9.425 19.54 26.54 16.425 9.425 ],[17.77 17.77 24.77 24.77 17.77 ],[1 1 1 ]);\npatch([16.425 40.54 33.54 26.54 " "19.54 9.425 16.425 ],[10.77 10.77 17.77 10.77 17.77 17.77 10.77 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: e" "nd icon graphics');\nfprintf('','COMMENT: begin icon text');\nfprintf('','COMMENT: end icon text');|{'table'=>{'" "AvailableMemories'=>'popup()'}}|" System { Name "EDK Processor" Location [514, 91, 900, 269] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" SIDHighWatermark "117" Block { BlockType Constant Name "Constant" SID "869:89" Position [40, 500, 60, 520] ShowName off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Constant Name "Constant1" SID "869:91" Position [40, 570, 60, 590] ShowName off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Constant Name "Constant2" SID "869:93" Position [40, 635, 60, 655] ShowName off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Constant Name "Constant3" SID "869:95" Position [40, 705, 60, 725] ShowName off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Constant Name "Constant4" SID "869:97" Position [40, 775, 60, 795] ShowName off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Constant5" SID "869:99" Ports [0, 1] Position [20, 427, 75, 453] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period on period "xlGetNormalizedPeriod()" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "55,26,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 55 55 0 0 ],[0 0 26 26 0 ]);\npatch([20.325 24.66 27.66 30.66 33.66 27.66 23.325 20.325 ],[16.33 16.3" "3 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([23.325 27.66 24.66 20.325 23.325 ],[13.33 13.33 16.33 16" ".33 13.33 ],[0.931 0.946 0.973 ]);\npatch([20.325 24.66 27.66 23.325 20.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1" " 1 ]);\npatch([23.325 33.66 30.66 27.66 24.66 20.325 23.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946" " 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port" "_label('output',1,'0');\nfprintf('','COMMENT: end icon text');" Port { PortNumber 1 Name "Sl_wait" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Constant Name "Constant6" SID "869:100" Position [40, 870, 60, 890] ShowName off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "From Register" SID "869:103" Ports [0, 1] Position [400, 962, 460, 1018] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/From Register" SourceType "Xilinx Shared Memory Based From Register Block" infoedit "Register block that reads data to a shared memory register. Delay of one sample period." shared_memory_name "'timer_status'" init "0" period "xlGetNormalizedPeriod()" ownership "Owned and initialized elsewhere" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "fromreg" sg_icon_stat "60,56,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.91" " ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36.88 44.8" "8 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36.88 28.88 ]," "[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]);\npatch([20." "2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0.973 ]);\nfprintf(" "'','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'d" "out');\nfprintf('','COMMENT: end icon text');" Port { PortNumber 1 Name "timer_status_dout" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "PLB_ABus" SID "869:92" Ports [1, 1] Position [175, 570, 245, 590] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed point to Xilinx" " fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top level input p" "orts." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "xlGetNormalizedPeriod()" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off UseAsADC off ADCChannel "'1'" hdl_port "on" sginterface "{'Xilinx'=>{'jtaghwcosim'=>{'non_memory_mapped_port'=>'PLB_ABus'}},'iopad'=>{'constraint'=>'#'}}" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "70,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 70 70 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 70 70 0 0 ],[0 0 20 20 0 ]);\npatch([30.55 33.44 35.44 37.44 39.44 35.44 32.55 30.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([32.55 35.44 33.44 30.55 32.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([30.55 33.44 35.44 32.55 30.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([32.55 39.44 37.44 35.44 33.44 30.55 32.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" "\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end ic" "on text');" Port { PortNumber 1 Name "PLB_ABus" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "PLB_PAValid" SID "869:94" Ports [1, 1] Position [175, 635, 245, 655] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed point to Xilinx" " fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top level input p" "orts." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "xlGetNormalizedPeriod()" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off UseAsADC off ADCChannel "'1'" hdl_port "on" sginterface "{'Xilinx'=>{'jtaghwcosim'=>{'non_memory_mapped_port'=>'PLB_PAValid'}},'iopad'=>{'constraint'=>'#'}}" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "70,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 70 70 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 70 70 0 0 ],[0 0 20 20 0 ]);\npatch([30.55 33.44 35.44 37.44 39.44 35.44 32.55 30.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([32.55 35.44 33.44 30.55 32.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([30.55 33.44 35.44 32.55 30.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([32.55 39.44 37.44 35.44 33.44 30.55 32.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" "\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end ic" "on text');" Port { PortNumber 1 Name "PLB_PAValid" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "PLB_RNW" SID "869:96" Ports [1, 1] Position [175, 705, 245, 725] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed point to Xilinx" " fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top level input p" "orts." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "xlGetNormalizedPeriod()" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off UseAsADC off ADCChannel "'1'" hdl_port "on" sginterface "{'Xilinx'=>{'jtaghwcosim'=>{'non_memory_mapped_port'=>'PLB_RNW'}},'iopad'=>{'constraint'=>'#'}}" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "70,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 70 70 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 70 70 0 0 ],[0 0 20 20 0 ]);\npatch([30.55 33.44 35.44 37.44 39.44 35.44 32.55 30.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([32.55 35.44 33.44 30.55 32.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([30.55 33.44 35.44 32.55 30.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([32.55 39.44 37.44 35.44 33.44 30.55 32.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" "\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end ic" "on text');" Port { PortNumber 1 Name "PLB_RNW" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "PLB_wrDBus" SID "869:98" Ports [1, 1] Position [175, 775, 245, 795] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed point to Xilinx" " fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top level input p" "orts." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "xlGetNormalizedPeriod()" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off UseAsADC off ADCChannel "'1'" hdl_port "on" sginterface "{'Xilinx'=>{'jtaghwcosim'=>{'non_memory_mapped_port'=>'PLB_wrDBus'}},'iopad'=>{'constraint'=>'#'}}" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "70,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 70 70 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 70 70 0 0 ],[0 0 20 20 0 ]);\npatch([30.55 33.44 35.44 37.44 39.44 35.44 32.55 30.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([32.55 35.44 33.44 30.55 32.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([30.55 33.44 35.44 32.55 30.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([32.55 39.44 37.44 35.44 33.44 30.55 32.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" "\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end ic" "on text');" Port { PortNumber 1 Name "PLB_wrDBus" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "SPLB_Rst" SID "869:90" Ports [1, 1] Position [175, 500, 245, 520] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed point to Xilinx" " fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top level input p" "orts." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "xlGetNormalizedPeriod()" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off UseAsADC off ADCChannel "'1'" hdl_port "on" sginterface "{'Xilinx'=>{'jtaghwcosim'=>{'non_memory_mapped_port'=>'SPLB_Rst'}},'iopad'=>{'constraint'=>'#'}}" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "70,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 70 70 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 70 70 0 0 ],[0 0 20 20 0 ]);\npatch([30.55 33.44 35.44 37.44 39.44 35.44 32.55 30.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([32.55 35.44 33.44 30.55 32.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([30.55 33.44 35.44 32.55 30.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([32.55 39.44 37.44 35.44 33.44 30.55 32.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" "\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end ic" "on text');" Port { PortNumber 1 Name "SPLB_Rst" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Sl_addrAck" SID "869:76" Ports [1, 1] Position [670, 75, 730, 95] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" UseAsDAC off DACChannel "'1'" sginterface "{'Xilinx'=>{'jtaghwcosim'=>{'non_memory_mapped_port'=>'Sl_addrAck'}},'iopad'=>{'constraint'=>'#'}}" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" " ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "Sl_rdComp" SID "869:78" Ports [1, 1] Position [670, 170, 730, 190] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" UseAsDAC off DACChannel "'1'" sginterface "{'Xilinx'=>{'jtaghwcosim'=>{'non_memory_mapped_port'=>'Sl_rdComp'}},'iopad'=>{'constraint'=>'#'}}" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" " ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "Sl_rdDAck" SID "869:80" Ports [1, 1] Position [670, 1260, 730, 1280] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" UseAsDAC off DACChannel "'1'" sginterface "{'Xilinx'=>{'jtaghwcosim'=>{'non_memory_mapped_port'=>'Sl_rdDAck'}},'iopad'=>{'constraint'=>'#'}}" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" " ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "Sl_rdDBus" SID "869:82" Ports [1, 1] Position [670, 1615, 730, 1635] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" UseAsDAC off DACChannel "'1'" sginterface "{'Xilinx'=>{'jtaghwcosim'=>{'non_memory_mapped_port'=>'Sl_rdDBus'}},'iopad'=>{'constraint'=>'#'}}" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" " ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "Sl_wait" SID "869:84" Ports [1, 1] Position [180, 430, 240, 450] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" UseAsDAC off DACChannel "'1'" sginterface "{'Xilinx'=>{'jtaghwcosim'=>{'non_memory_mapped_port'=>'Sl_wait'}},'iopad'=>{'constraint'=>'#'}}" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" " ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "Sl_wrComp" SID "869:88" Ports [1, 1] Position [670, 450, 730, 470] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" UseAsDAC off DACChannel "'1'" sginterface "{'Xilinx'=>{'jtaghwcosim'=>{'non_memory_mapped_port'=>'Sl_wrComp'}},'iopad'=>{'constraint'=>'#'}}" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" " ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "Sl_wrDAck" SID "869:86" Ports [1, 1] Position [670, 285, 730, 305] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" UseAsDAC off DACChannel "'1'" sginterface "{'Xilinx'=>{'jtaghwcosim'=>{'non_memory_mapped_port'=>'Sl_wrDAck'}},'iopad'=>{'constraint'=>'#'}}" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" " ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Terminator Name "Terminator" SID "869:75" Position [905, 50, 925, 70] ShowName off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Terminator Name "Terminator1" SID "869:77" Position [905, 115, 925, 135] ShowName off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Terminator Name "Terminator2" SID "869:79" Position [905, 1690, 925, 1710] ShowName off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Terminator Name "Terminator3" SID "869:81" Position [905, 1760, 925, 1780] ShowName off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Terminator Name "Terminator4" SID "869:83" Position [420, 430, 440, 450] ShowName off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Terminator Name "Terminator5" SID "869:85" Position [905, 185, 925, 205] ShowName off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Terminator Name "Terminator6" SID "869:87" Position [905, 255, 925, 275] ShowName off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "To Register" SID "869:104" Ports [2, 1] Position [885, 322, 945, 378] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/To Register" SourceType "Xilinx Shared Memory Based To Register Block" infoedit "Register block that writes data to a shared memory register. Delay of one sample period." shared_memory_name "'timer0_slotCount'" init "0" ownership "Owned and initialized elsewhere" explicit_data_type on gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "toreg" sg_icon_stat "60,56,2,1,white,blue,0,10ab453e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.91" " ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36.88 44.8" "8 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36.88 28.88 ]," "[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]);\npatch([20." "2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0.973 ]);\nfprintf(" "'','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'di" "n');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMEN" "T: end icon text');" Port { PortNumber 1 Name "timer0_slotCount_dout" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "To Register1" SID "869:105" Ports [2, 1] Position [885, 427, 945, 483] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/To Register" SourceType "Xilinx Shared Memory Based To Register Block" infoedit "Register block that writes data to a shared memory register. Delay of one sample period." shared_memory_name "'timer_control'" init "0" ownership "Owned and initialized elsewhere" explicit_data_type on gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "toreg" sg_icon_stat "60,56,2,1,white,blue,0,10ab453e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.91" " ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36.88 44.8" "8 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36.88 28.88 ]," "[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]);\npatch([20." "2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0.973 ]);\nfprintf(" "'','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'di" "n');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMEN" "T: end icon text');" Port { PortNumber 1 Name "timer_control_dout" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "To Register10" SID "869:114" Ports [2, 1] Position [885, 1377, 945, 1433] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/To Register" SourceType "Xilinx Shared Memory Based To Register Block" infoedit "Register block that writes data to a shared memory register. Delay of one sample period." shared_memory_name "'timers23_slotTime'" init "0" ownership "Owned and initialized elsewhere" explicit_data_type on gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "toreg" sg_icon_stat "60,56,2,1,white,blue,0,10ab453e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.91" " ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36.88 44.8" "8 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36.88 28.88 ]," "[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]);\npatch([20." "2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0.973 ]);\nfprintf(" "'','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'di" "n');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMEN" "T: end icon text');" Port { PortNumber 1 Name "timers23_slotTime_dout" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "To Register11" SID "869:115" Ports [2, 1] Position [885, 1482, 945, 1538] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/To Register" SourceType "Xilinx Shared Memory Based To Register Block" infoedit "Register block that writes data to a shared memory register. Delay of one sample period." shared_memory_name "'timers01_slotTime'" init "0" ownership "Owned and initialized elsewhere" explicit_data_type on gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "toreg" sg_icon_stat "60,56,2,1,white,blue,0,10ab453e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.91" " ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36.88 44.8" "8 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36.88 28.88 ]," "[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]);\npatch([20." "2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0.973 ]);\nfprintf(" "'','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'di" "n');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMEN" "T: end icon text');" Port { PortNumber 1 Name "timers01_slotTime_dout" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "To Register12" SID "869:116" Ports [2, 1] Position [885, 1587, 945, 1643] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/To Register" SourceType "Xilinx Shared Memory Based To Register Block" infoedit "Register block that writes data to a shared memory register. Delay of one sample period." shared_memory_name "'timer1_slotCount'" init "0" ownership "Owned and initialized elsewhere" explicit_data_type on gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "toreg" sg_icon_stat "60,56,2,1,white,blue,0,10ab453e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.91" " ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36.88 44.8" "8 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36.88 28.88 ]," "[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]);\npatch([20." "2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0.973 ]);\nfprintf(" "'','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'di" "n');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMEN" "T: end icon text');" Port { PortNumber 1 Name "timer1_slotCount_dout" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "To Register2" SID "869:106" Ports [2, 1] Position [885, 532, 945, 588] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/To Register" SourceType "Xilinx Shared Memory Based To Register Block" infoedit "Register block that writes data to a shared memory register. Delay of one sample period." shared_memory_name "'timer4_slotCount'" init "0" ownership "Owned and initialized elsewhere" explicit_data_type on gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "toreg" sg_icon_stat "60,56,2,1,white,blue,0,10ab453e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.91" " ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36.88 44.8" "8 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36.88 28.88 ]," "[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]);\npatch([20." "2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0.973 ]);\nfprintf(" "'','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'di" "n');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMEN" "T: end icon text');" Port { PortNumber 1 Name "timer4_slotCount_dout" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "To Register3" SID "869:107" Ports [2, 1] Position [885, 637, 945, 693] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/To Register" SourceType "Xilinx Shared Memory Based To Register Block" infoedit "Register block that writes data to a shared memory register. Delay of one sample period." shared_memory_name "'timer6_slotCount'" init "0" ownership "Owned and initialized elsewhere" explicit_data_type on gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "toreg" sg_icon_stat "60,56,2,1,white,blue,0,10ab453e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.91" " ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36.88 44.8" "8 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36.88 28.88 ]," "[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]);\npatch([20." "2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0.973 ]);\nfprintf(" "'','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'di" "n');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMEN" "T: end icon text');" Port { PortNumber 1 Name "timer6_slotCount_dout" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "To Register4" SID "869:108" Ports [2, 1] Position [885, 742, 945, 798] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/To Register" SourceType "Xilinx Shared Memory Based To Register Block" infoedit "Register block that writes data to a shared memory register. Delay of one sample period." shared_memory_name "'timer7_slotCount'" init "0" ownership "Owned and initialized elsewhere" explicit_data_type on gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "toreg" sg_icon_stat "60,56,2,1,white,blue,0,10ab453e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.91" " ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36.88 44.8" "8 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36.88 28.88 ]," "[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]);\npatch([20." "2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0.973 ]);\nfprintf(" "'','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'di" "n');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMEN" "T: end icon text');" Port { PortNumber 1 Name "timer7_slotCount_dout" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "To Register5" SID "869:109" Ports [2, 1] Position [885, 847, 945, 903] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/To Register" SourceType "Xilinx Shared Memory Based To Register Block" infoedit "Register block that writes data to a shared memory register. Delay of one sample period." shared_memory_name "'timer5_slotCount'" init "0" ownership "Owned and initialized elsewhere" explicit_data_type on gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "toreg" sg_icon_stat "60,56,2,1,white,blue,0,10ab453e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.91" " ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36.88 44.8" "8 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36.88 28.88 ]," "[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]);\npatch([20." "2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0.973 ]);\nfprintf(" "'','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'di" "n');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMEN" "T: end icon text');" Port { PortNumber 1 Name "timer5_slotCount_dout" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "To Register6" SID "869:110" Ports [2, 1] Position [885, 952, 945, 1008] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/To Register" SourceType "Xilinx Shared Memory Based To Register Block" infoedit "Register block that writes data to a shared memory register. Delay of one sample period." shared_memory_name "'timer2_slotCount'" init "0" ownership "Owned and initialized elsewhere" explicit_data_type on gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "toreg" sg_icon_stat "60,56,2,1,white,blue,0,10ab453e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.91" " ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36.88 44.8" "8 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36.88 28.88 ]," "[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]);\npatch([20." "2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0.973 ]);\nfprintf(" "'','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'di" "n');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMEN" "T: end icon text');" Port { PortNumber 1 Name "timer2_slotCount_dout" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "To Register7" SID "869:111" Ports [2, 1] Position [885, 1057, 945, 1113] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/To Register" SourceType "Xilinx Shared Memory Based To Register Block" infoedit "Register block that writes data to a shared memory register. Delay of one sample period." shared_memory_name "'timer3_slotCount'" init "0" ownership "Owned and initialized elsewhere" explicit_data_type on gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "toreg" sg_icon_stat "60,56,2,1,white,blue,0,10ab453e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.91" " ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36.88 44.8" "8 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36.88 28.88 ]," "[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]);\npatch([20." "2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0.973 ]);\nfprintf(" "'','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'di" "n');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMEN" "T: end icon text');" Port { PortNumber 1 Name "timer3_slotCount_dout" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "To Register8" SID "869:112" Ports [2, 1] Position [885, 1167, 945, 1223] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/To Register" SourceType "Xilinx Shared Memory Based To Register Block" infoedit "Register block that writes data to a shared memory register. Delay of one sample period." shared_memory_name "'timers67_slotTime'" init "0" ownership "Owned and initialized elsewhere" explicit_data_type on gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "toreg" sg_icon_stat "60,56,2,1,white,blue,0,10ab453e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.91" " ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36.88 44.8" "8 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36.88 28.88 ]," "[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]);\npatch([20." "2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0.973 ]);\nfprintf(" "'','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'di" "n');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMEN" "T: end icon text');" Port { PortNumber 1 Name "timers67_slotTime_dout" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "To Register9" SID "869:113" Ports [2, 1] Position [885, 1272, 945, 1328] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/To Register" SourceType "Xilinx Shared Memory Based To Register Block" infoedit "Register block that writes data to a shared memory register. Delay of one sample period." shared_memory_name "'timers45_slotTime'" init "0" ownership "Owned and initialized elsewhere" explicit_data_type on gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "toreg" sg_icon_stat "60,56,2,1,white,blue,0,10ab453e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.91" " ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36.88 44.8" "8 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36.88 28.88 ]," "[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]);\npatch([20." "2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0.973 ]);\nfprintf(" "'','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'di" "n');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMEN" "T: end icon text');" Port { PortNumber 1 Name "timers45_slotTime_dout" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "plb_decode" SID "869:102" Ports [7, 9] Position [345, 499, 515, 911] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/MCode" SourceType "Xilinx MCode Block Block" infoedit "Pass input values to a MATLAB function for evaluation in Xilinx fixed-point type. The input ports of t" "he block are input arguments of the function. The output ports of the block are output arguments of the function." mfname "xlmax" explicit_period off period "1" dbl_ovrd off enable_stdout off enable_debug off xl_use_area off xl_area "[0,0,0,0,0,0,0]" mfilecontent "function [wrDBusReg, addrAck, rdComp, wrDAck, bankAddr, RNWReg, rdDAck, rdDBus, linearAddr] = plb_" "bus_decode(plbRst, plbABus, plbPAValid, plbRNW, plbWrDBus, rdData, addrPref)\n\n% constant variables (TODO: should " "pass from outside)\nADDRPREF_LEN = 20;\nBANKADDR_LEN = 2;\nLINEARADDR_LEN = 8;\nABUS_LEN = 32;\nDBUS_LEN = 32;\n\n%" " declare and initialize persistent variables\n% register input bus signals\npersistent plbRstReg_, plbRstReg_ = xl_" "state(0, {xlBoolean});\npersistent plbABusReg_, plbABusReg_ = xl_state(0, {xlUnsigned, ABUS_LEN, 0});\npersistent p" "lbPAValidReg_, plbPAValidReg_ = xl_state(0, {xlBoolean});\npersistent plbRNWReg_, plbRNWReg_ = xl_state(0, {xlUnsig" "ned, 1, 0});\npersistent plbWrDBusReg_, plbWrDBusReg_ = xl_state(0, {xlUnsigned, DBUS_LEN, 0});\n\n% ===== rest of " "the outputs =====\n\nbankAddr = xl_slice(plbABusReg_, 2+BANKADDR_LEN+LINEARADDR_LEN-1, 2+LINEARADDR_LEN);\nlinear" "Addr = xl_slice(plbABusReg_, 2+LINEARADDR_LEN-1, 2);\nRNWReg = plbRNWReg_;\nwrDBusReg = plbWrDBusReg_;\n\n% ===== p" "_select =====\n\n% register PAValid\npersistent aValidReg, aValidReg = xl_state(0, {xlBoolean});\naValidReg = plbPA" "ValidReg_;\n\n% extract and register the address prefix\naddrPref_in = xl_slice(plbABusReg_, xl_nbits(plbABusReg_)-" "1, xl_nbits(plbABusReg_)-ADDRPREF_LEN);\nif addrPref_in == addrPref\n ps1 = true;\nelse \n ps1 = false;\nend " "\n\npersistent ps1Reg, ps1Reg = xl_state(0, ps1);\nps1Reg = ps1;\n\nps = xl_and(ps1Reg, aValidReg);\n\n% ===== addr" "Ack =====\n\n% register ps\npersistent psReg, psReg = xl_state(0, ps);\n\naddrAck = xfix({xlUnsigned, 1, 0}, xl_and" "(xl_not(plbRstReg_), ps, xl_not(psReg)));\n\npsReg = ps;\n\n% ===== rdComp, rd/wr DAck =====\n \nrdComp1 = xfix({xl" "Unsigned, 1, 0}, xl_and(addrAck, RNWReg));\n\nNUM_rdCompDelay = 3;\npersistent rdCompDelay, rdCompDelay = xl_state(" "zeros(1, NUM_rdCompDelay), rdComp1, NUM_rdCompDelay);\nrdComp2 = rdCompDelay.back;\nrdCompDelay.push_front_pop_back" "(rdComp1);\n\npersistent rdCompReg, rdCompReg = xl_state(0, rdComp1);\nrdComp = rdCompReg;\nrdCompReg = rdComp2;\n\n" "persistent rdDAckReg, rdDAckReg = xl_state(0, rdComp1);\nrdDAck = rdDAckReg;\nrdDAckReg = rdComp;\n\npersistent wrD" "AckReg, wrDAckReg = xl_state(0, addrAck);\nwrDAck = wrDAckReg;\nwrDAckReg = xl_and(addrAck, xl_not(RNWReg));\n\n% =" "==== rdDBus =====\n\nrdSel = xl_or(rdComp2, rdComp);\n\nif rdSel == 1\n rdDBus1 = rdData;\nelse\n rdDBus1 = 0" ";\nend % if\n\npersistent rdDBusReg, rdDBusReg = xl_state(0, rdDBus1);\nrdDBus = rdDBusReg;\nrdDBusReg = rdDBus1;\n" "\n% rdDBus = xl_concat(rdDBus32, rdDBus32);\n% rdDBus = rdDBus32;\n\n% ===== update the persistent variables =====\n" "\nplbRstReg_ = plbRst;\nplbABusReg_ = plbABus;\nplbPAValidReg_ = plbPAValid;\nplbRNWReg_ = plbRNW;\nplbWrDBusReg_ =" " xl_slice(plbWrDBus, DBUS_LEN-1, 0);\n" suppress_output "on" defparams "{}" hide_port_list "{}" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mcode" sg_icon_stat "170,412,7,9,white,blue,0,43a237d5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 170 170 0 0 ],[0 0 412 412 0 ],[0.77 0.82 " "0.91 ]);\nplot([0 170 170 0 0 ],[0 0 412 412 0 ]);\npatch([31.6 66.28 90.28 114.28 138.28 90.28 55.6 31.6 ],[232.64" " 232.64 256.64 232.64 256.64 256.64 256.64 232.64 ],[1 1 1 ]);\npatch([55.6 90.28 66.28 31.6 55.6 ],[208.64 208.64 " "232.64 232.64 208.64 ],[0.931 0.946 0.973 ]);\npatch([31.6 66.28 90.28 55.6 31.6 ],[184.64 184.64 208.64 208.64 184" ".64 ],[1 1 1 ]);\npatch([55.6 138.28 114.28 90.28 66.28 31.6 55.6 ],[160.64 160.64 184.64 160.64 184.64 184.64 160." "64 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\nco" "lor('black');port_label('input',1,'plbRst');\ncolor('black');port_label('input',2,'plbABus');\ncolor('black');port_" "label('input',3,'plbPAValid');\ncolor('black');port_label('input',4,'plbRNW');\ncolor('black');port_label('input',5" ",'plbWrDBus');\ncolor('black');port_label('input',6,'rdData');\ncolor('black');port_label('input',7,'addrPref');\nc" "olor('black');port_label('output',1,'wrDBusReg');\ncolor('black');port_label('output',2,'addrAck');\ncolor('black')" ";port_label('output',3,'rdComp');\ncolor('black');port_label('output',4,'wrDAck');\ncolor('black');port_label('outp" "ut',5,'bankAddr');\ncolor('black');port_label('output',6,'RNWReg');\ncolor('black');port_label('output',7,'rdDAck')" ";\ncolor('black');port_label('output',8,'rdDBus');\ncolor('black');port_label('output',9,'linearAddr');\ncolor('bla" "ck');disp('\\bf{xlmax}','texmode','on');\nfprintf('','COMMENT: end icon text');" Port { PortNumber 1 Name "wrDBusReg" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 2 Name "Sl_addrAck" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 3 Name "Sl_rdComp" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 4 Name "Sl_wrDAck" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 5 Name "bankAddr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 6 Name "RNWReg" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 7 Name "Sl_rdDAck" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 8 Name "Sl_rdDBus" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 9 Name "linearAddr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "plb_memmap" SID "869:117" Ports [19, 27] Position [615, 815, 785, 1065] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/MCode" SourceType "Xilinx MCode Block Block" infoedit "Pass input values to a MATLAB function for evaluation in Xilinx fixed-point type. The input ports of t" "he block are input arguments of the function. The output ports of the block are output arguments of the function." mfname "xlmax" explicit_period off period "1" dbl_ovrd off enable_stdout off enable_debug off xl_use_area off xl_area "[0,0,0,0,0,0,0]" mfilecontent "function [read_bank_out, sm_timer0_slotCount_din, sm_timer0_slotCount_en, sm_timer_control_din, sm" "_timer_control_en, sm_timer4_slotCount_din, sm_timer4_slotCount_en, sm_timer6_slotCount_din, sm_timer6_slotCount_en" ", sm_timer7_slotCount_din, sm_timer7_slotCount_en, sm_timer5_slotCount_din, sm_timer5_slotCount_en, sm_timer2_slotC" "ount_din, sm_timer2_slotCount_en, sm_timer3_slotCount_din, sm_timer3_slotCount_en, sm_timers67_slotTime_din, sm_tim" "ers67_slotTime_en, sm_timers45_slotTime_din, sm_timers45_slotTime_en, sm_timers23_slotTime_din, sm_timers23_slotTim" "e_en, sm_timers01_slotTime_din, sm_timers01_slotTime_en, sm_timer1_slotCount_din, sm_timer1_slotCount_en] = plb_mem" "map(wrDBus, bankAddr, linearAddr, RNWReg, addrAck, sm_timer_status, sm_timer0_slotCount, sm_timer_control, sm_timer" "4_slotCount, sm_timer6_slotCount, sm_timer7_slotCount, sm_timer5_slotCount, sm_timer2_slotCount, sm_timer3_slotCoun" "t, sm_timers67_slotTime, sm_timers45_slotTime, sm_timers23_slotTime, sm_timers01_slotTime, sm_timer1_slotCount)\n\n" "\n% connvert the input data to UFix_32_0 (the bus data type)\n% 'From Register' blocks\n% sm_timer_status_bus = xfi" "x({xlUnsigned, 32, 0}, 0);\nsm_timer_status_bus = xl_force(sm_timer_status, xlUnsigned, 0);\n\n% 'To Register' bloc" "ks\n\n% sm_timer0_slotCount_dout = xfix({xlUnsigned, 32, 0}, 0);\nsm_timer0_slotCount_dout = xl_force(sm_timer0_slo" "tCount, xlUnsigned, 0);\n\n% sm_timer_control_dout = xfix({xlUnsigned, 32, 0}, 0);\nsm_timer_control_dout = xl_forc" "e(sm_timer_control, xlUnsigned, 0);\n\n% sm_timer4_slotCount_dout = xfix({xlUnsigned, 32, 0}, 0);\nsm_timer4_slotCo" "unt_dout = xl_force(sm_timer4_slotCount, xlUnsigned, 0);\n\n% sm_timer6_slotCount_dout = xfix({xlUnsigned, 32, 0}, " "0);\nsm_timer6_slotCount_dout = xl_force(sm_timer6_slotCount, xlUnsigned, 0);\n\n% sm_timer7_slotCount_dout = xfix(" "{xlUnsigned, 32, 0}, 0);\nsm_timer7_slotCount_dout = xl_force(sm_timer7_slotCount, xlUnsigned, 0);\n\n% sm_timer5_s" "lotCount_dout = xfix({xlUnsigned, 32, 0}, 0);\nsm_timer5_slotCount_dout = xl_force(sm_timer5_slotCount, xlUnsigned," " 0);\n\n% sm_timer2_slotCount_dout = xfix({xlUnsigned, 32, 0}, 0);\nsm_timer2_slotCount_dout = xl_force(sm_timer2_s" "lotCount, xlUnsigned, 0);\n\n% sm_timer3_slotCount_dout = xfix({xlUnsigned, 32, 0}, 0);\nsm_timer3_slotCount_dout =" " xl_force(sm_timer3_slotCount, xlUnsigned, 0);\n\n% sm_timers67_slotTime_dout = xfix({xlUnsigned, 32, 0}, 0);\nsm_t" "imers67_slotTime_dout = xl_force(sm_timers67_slotTime, xlUnsigned, 0);\n\n% sm_timers45_slotTime_dout = xfix({xlUns" "igned, 32, 0}, 0);\nsm_timers45_slotTime_dout = xl_force(sm_timers45_slotTime, xlUnsigned, 0);\n\n% sm_timers23_slo" "tTime_dout = xfix({xlUnsigned, 32, 0}, 0);\nsm_timers23_slotTime_dout = xl_force(sm_timers23_slotTime, xlUnsigned, " "0);\n\n% sm_timers01_slotTime_dout = xfix({xlUnsigned, 32, 0}, 0);\nsm_timers01_slotTime_dout = xl_force(sm_timers0" "1_slotTime, xlUnsigned, 0);\n\n% sm_timer1_slotCount_dout = xfix({xlUnsigned, 32, 0}, 0);\nsm_timer1_slotCount_dout" " = xl_force(sm_timer1_slotCount, xlUnsigned, 0);\n\n\n% 'From FIFO' blocks\n% 'To FIFO' blocks\n% 'Shared Memory' b" "locks\n\n% 'dout' ports of 'From Register' blocks\n\n% registered register mux output\npersistent reg_bank_out_reg;" " reg_bank_out_reg = xl_state(0, {xlUnsigned, 32, 0});\nreg_bank_out = reg_bank_out_reg;\n\nif linearAddr == 13\n " " reg_bank_out_reg = sm_timer_status_bus;\nelseif linearAddr == 0\n reg_bank_out_reg = sm_timer0_slotCount_dout;\n" "elseif linearAddr == 1\n reg_bank_out_reg = sm_timer_control_dout;\nelseif linearAddr == 2\n reg_bank_out_reg" " = sm_timer4_slotCount_dout;\nelseif linearAddr == 3\n reg_bank_out_reg = sm_timer6_slotCount_dout;\nelseif line" "arAddr == 4\n reg_bank_out_reg = sm_timer7_slotCount_dout;\nelseif linearAddr == 5\n reg_bank_out_reg = sm_ti" "mer5_slotCount_dout;\nelseif linearAddr == 6\n reg_bank_out_reg = sm_timer2_slotCount_dout;\nelseif linearAddr =" "= 7\n reg_bank_out_reg = sm_timer3_slotCount_dout;\nelseif linearAddr == 8\n reg_bank_out_reg = sm_timers67_s" "lotTime_dout;\nelseif linearAddr == 9\n reg_bank_out_reg = sm_timers45_slotTime_dout;\nelseif linearAddr == 10\n" " reg_bank_out_reg = sm_timers23_slotTime_dout;\nelseif linearAddr == 11\n reg_bank_out_reg = sm_timers01_slot" "Time_dout;\nelseif linearAddr == 12\n reg_bank_out_reg = sm_timer1_slotCount_dout;\n\nend\n\n\n% 'From FIFO' and" " 'To FIFO' blocks\n\n\n\n\n\nopCode = xl_concat(addrAck, RNWReg, bankAddr, linearAddr);\n\n% 'Shared Memory' blocks" "\n\n\n\n\n\n% 'din' ports of 'Shared Memory' blocks\n\n\n% 'we' ports of 'Shared Memory' blocks\n\n\n% 'addr' ports" " of 'Shared Memory' blocks\n\n\n% 're' ports of 'From FIFO' blocks\n\n\n% 'en' ports of 'To Register' blocks\nif op" "Code == xl_concat(xfix({xlUnsigned, 4, 0}, 10), ...\n xfix({xlUnsigned, xl_nbits(linearAddr)," " 0}, 0))\n sm_timer0_slotCount_en = true;\nelse\n sm_timer0_slotCount_en = false;\nend\nif opCode == xl_conca" "t(xfix({xlUnsigned, 4, 0}, 10), ...\n xfix({xlUnsigned, xl_nbits(linearAddr), 0}, 1))\n sm" "_timer_control_en = true;\nelse\n sm_timer_control_en = false;\nend\nif opCode == xl_concat(xfix({xlUnsigned, 4," " 0}, 10), ...\n xfix({xlUnsigned, xl_nbits(linearAddr), 0}, 2))\n sm_timer4_slotCount_en =" " true;\nelse\n sm_timer4_slotCount_en = false;\nend\nif opCode == xl_concat(xfix({xlUnsigned, 4, 0}, 10), ...\n " " xfix({xlUnsigned, xl_nbits(linearAddr), 0}, 3))\n sm_timer6_slotCount_en = true;\nelse\n " " sm_timer6_slotCount_en = false;\nend\nif opCode == xl_concat(xfix({xlUnsigned, 4, 0}, 10), ...\n " " xfix({xlUnsigned, xl_nbits(linearAddr), 0}, 4))\n sm_timer7_slotCount_en = true;\nelse\n sm_timer7_slot" "Count_en = false;\nend\nif opCode == xl_concat(xfix({xlUnsigned, 4, 0}, 10), ...\n xfix({xlUn" "signed, xl_nbits(linearAddr), 0}, 5))\n sm_timer5_slotCount_en = true;\nelse\n sm_timer5_slotCount_en = false" ";\nend\nif opCode == xl_concat(xfix({xlUnsigned, 4, 0}, 10), ...\n xfix({xlUnsigned, xl_nbits" "(linearAddr), 0}, 6))\n sm_timer2_slotCount_en = true;\nelse\n sm_timer2_slotCount_en = false;\nend\nif opCod" "e == xl_concat(xfix({xlUnsigned, 4, 0}, 10), ...\n xfix({xlUnsigned, xl_nbits(linearAddr), 0}" ", 7))\n sm_timer3_slotCount_en = true;\nelse\n sm_timer3_slotCount_en = false;\nend\nif opCode == xl_concat(x" "fix({xlUnsigned, 4, 0}, 10), ...\n xfix({xlUnsigned, xl_nbits(linearAddr), 0}, 8))\n sm_ti" "mers67_slotTime_en = true;\nelse\n sm_timers67_slotTime_en = false;\nend\nif opCode == xl_concat(xfix({xlUnsigne" "d, 4, 0}, 10), ...\n xfix({xlUnsigned, xl_nbits(linearAddr), 0}, 9))\n sm_timers45_slotTim" "e_en = true;\nelse\n sm_timers45_slotTime_en = false;\nend\nif opCode == xl_concat(xfix({xlUnsigned, 4, 0}, 10)," " ...\n xfix({xlUnsigned, xl_nbits(linearAddr), 0}, 10))\n sm_timers23_slotTime_en = true;\n" "else\n sm_timers23_slotTime_en = false;\nend\nif opCode == xl_concat(xfix({xlUnsigned, 4, 0}, 10), ...\n " " xfix({xlUnsigned, xl_nbits(linearAddr), 0}, 11))\n sm_timers01_slotTime_en = true;\nelse\n sm_" "timers01_slotTime_en = false;\nend\nif opCode == xl_concat(xfix({xlUnsigned, 4, 0}, 10), ...\n " " xfix({xlUnsigned, xl_nbits(linearAddr), 0}, 12))\n sm_timer1_slotCount_en = true;\nelse\n sm_timer1_slotCou" "nt_en = false;\nend\n\n\n% 'din' ports of 'To FIFO' blocks\n\n\n% 'we' ports of 'To FIFO' blocks\n\n\n% 'din' ports" " of 'To Register' blocks\nsm_timer0_slotCount_din = xl_force(xl_slice(wrDBus, 32 - 1, 0), ...\n " " xlUnsigned, ...\n 0);\nsm_timer_control_din = xl_force(xl_slice(wrDBus" ", 32 - 1, 0), ...\n xlUnsigned, ...\n 0);\nsm_timer" "4_slotCount_din = xl_force(xl_slice(wrDBus, 32 - 1, 0), ...\n xlUnsigned, ...\n " " 0);\nsm_timer6_slotCount_din = xl_force(xl_slice(wrDBus, 32 - 1, 0), ...\n " " xlUnsigned, ...\n 0);\nsm_timer7_slotCount_din = xl_force(xl_s" "lice(wrDBus, 32 - 1, 0), ...\n xlUnsigned, ...\n 0)" ";\nsm_timer5_slotCount_din = xl_force(xl_slice(wrDBus, 32 - 1, 0), ...\n xlUnsigned" ", ...\n 0);\nsm_timer2_slotCount_din = xl_force(xl_slice(wrDBus, 32 - 1, 0), ...\n " " xlUnsigned, ...\n 0);\nsm_timer3_slotCount_din = xl" "_force(xl_slice(wrDBus, 32 - 1, 0), ...\n xlUnsigned, ...\n " " 0);\nsm_timers67_slotTime_din = xl_force(xl_slice(wrDBus, 32 - 1, 0), ...\n " " xlUnsigned, ...\n 0);\nsm_timers45_slotTime_din = xl_force(xl_slice(wrDBus, 32 - " "1, 0), ...\n xlUnsigned, ...\n 0);\nsm_timers23_slo" "tTime_din = xl_force(xl_slice(wrDBus, 32 - 1, 0), ...\n xlUnsigned, ...\n " " 0);\nsm_timers01_slotTime_din = xl_force(xl_slice(wrDBus, 32 - 1, 0), ...\n " " xlUnsigned, ...\n 0);\nsm_timer1_slotCount_din = xl_force(xl_slice(" "wrDBus, 32 - 1, 0), ...\n xlUnsigned, ...\n 0);\n\n" "\npersistent read_bank_out_reg; read_bank_out_reg = xl_state(0, {xlUnsigned, 32, 0});\nread_bank_out = read_bank_ou" "t_reg;\n\npersistent bankAddr_reg; bankAddr_reg = xl_state(0, bankAddr);\n\nif bankAddr_reg == 0\n % Bank 0: Sha" "red Memories\n read_bank_out_reg = 0;\nelseif bankAddr_reg == 1\n % Bank 1: From/To FIFOs\n read_bank_out_" "reg = 0;\nelseif bankAddr_reg == 2\n % Bank 2: From/To Registers\n read_bank_out_reg = reg_bank_out;\nelseif" " bankAddr_reg == 3\n % Bank 3: Configuration Registers\n read_bank_out_reg = 0;\nend\n\nbankAddr_reg = bankAd" "dr;\n" suppress_output "on" defparams "{}" hide_port_list "{}" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mcode" sg_icon_stat "170,250,19,27,white,blue,0,6b7f853d,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 170 170 0 0 ],[0 0 250 250 0 ],[0.77 0.82 " "0.91 ]);\nplot([0 170 170 0 0 ],[0 0 250 250 0 ]);\npatch([31.6 66.28 90.28 114.28 138.28 90.28 55.6 31.6 ],[151.64" " 151.64 175.64 151.64 175.64 175.64 175.64 151.64 ],[1 1 1 ]);\npatch([55.6 90.28 66.28 31.6 55.6 ],[127.64 127.64 " "151.64 151.64 127.64 ],[0.931 0.946 0.973 ]);\npatch([31.6 66.28 90.28 55.6 31.6 ],[103.64 103.64 127.64 127.64 103" ".64 ],[1 1 1 ]);\npatch([55.6 138.28 114.28 90.28 66.28 31.6 55.6 ],[79.64 79.64 103.64 79.64 103.64 103.64 79.64 ]" ",[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor(" "'black');port_label('input',1,'wrDBus');\ncolor('black');port_label('input',2,'bankAddr');\ncolor('black');port_lab" "el('input',3,'linearAddr');\ncolor('black');port_label('input',4,'RNWReg');\ncolor('black');port_label('input',5,'a" "ddrAck');\ncolor('black');port_label('input',6,'sm_timer_status');\ncolor('black');port_label('input',7,'sm_timer0_" "slotCount');\ncolor('black');port_label('input',8,'sm_timer_control');\ncolor('black');port_label('input',9,'sm_tim" "er4_slotCount');\ncolor('black');port_label('input',10,'sm_timer6_slotCount');\ncolor('black');port_label('input',1" "1,'sm_timer7_slotCount');\ncolor('black');port_label('input',12,'sm_timer5_slotCount');\ncolor('black');port_label(" "'input',13,'sm_timer2_slotCount');\ncolor('black');port_label('input',14,'sm_timer3_slotCount');\ncolor('black');po" "rt_label('input',15,'sm_timers67_slotTime');\ncolor('black');port_label('input',16,'sm_timers45_slotTime');\ncolor(" "'black');port_label('input',17,'sm_timers23_slotTime');\ncolor('black');port_label('input',18,'sm_timers01_slotTime" "');\ncolor('black');port_label('input',19,'sm_timer1_slotCount');\ncolor('black');port_label('output',1,'read_bank_" "out');\ncolor('black');port_label('output',2,'sm_timer0_slotCount_din');\ncolor('black');port_label('output',3,'sm_" "timer0_slotCount_en');\ncolor('black');port_label('output',4,'sm_timer_control_din');\ncolor('black');port_label('o" "utput',5,'sm_timer_control_en');\ncolor('black');port_label('output',6,'sm_timer4_slotCount_din');\ncolor('black');" "port_label('output',7,'sm_timer4_slotCount_en');\ncolor('black');port_label('output',8,'sm_timer6_slotCount_din');\n" "color('black');port_label('output',9,'sm_timer6_slotCount_en');\ncolor('black');port_label('output',10,'sm_timer7_s" "lotCount_din');\ncolor('black');port_label('output',11,'sm_timer7_slotCount_en');\ncolor('black');port_label('outpu" "t',12,'sm_timer5_slotCount_din');\ncolor('black');port_label('output',13,'sm_timer5_slotCount_en');\ncolor('black')" ";port_label('output',14,'sm_timer2_slotCount_din');\ncolor('black');port_label('output',15,'sm_timer2_slotCount_en'" ");\ncolor('black');port_label('output',16,'sm_timer3_slotCount_din');\ncolor('black');port_label('output',17,'sm_ti" "mer3_slotCount_en');\ncolor('black');port_label('output',18,'sm_timers67_slotTime_din');\ncolor('black');port_label" "('output',19,'sm_timers67_slotTime_en');\ncolor('black');port_label('output',20,'sm_timers45_slotTime_din');\ncolor" "('black');port_label('output',21,'sm_timers45_slotTime_en');\ncolor('black');port_label('output',22,'sm_timers23_sl" "otTime_din');\ncolor('black');port_label('output',23,'sm_timers23_slotTime_en');\ncolor('black');port_label('output" "',24,'sm_timers01_slotTime_din');\ncolor('black');port_label('output',25,'sm_timers01_slotTime_en');\ncolor('black'" ");port_label('output',26,'sm_timer1_slotCount_din');\ncolor('black');port_label('output',27,'sm_timer1_slotCount_en" "');\ncolor('black');disp('\\bf{xlmax}','texmode','on');\nfprintf('','COMMENT: end icon text');" Port { PortNumber 1 Name "rdData" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 2 Name "timer0_slotCount_din" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 3 Name "timer0_slotCount_en" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 4 Name "timer_control_din" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 5 Name "timer_control_en" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 6 Name "timer4_slotCount_din" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 7 Name "timer4_slotCount_en" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 8 Name "timer6_slotCount_din" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 9 Name "timer6_slotCount_en" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 10 Name "timer7_slotCount_din" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 11 Name "timer7_slotCount_en" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 12 Name "timer5_slotCount_din" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 13 Name "timer5_slotCount_en" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 14 Name "timer2_slotCount_din" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 15 Name "timer2_slotCount_en" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 16 Name "timer3_slotCount_din" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 17 Name "timer3_slotCount_en" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 18 Name "timers67_slotTime_din" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 19 Name "timers67_slotTime_en" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 20 Name "timers45_slotTime_din" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 21 Name "timers45_slotTime_en" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 22 Name "timers23_slotTime_din" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 23 Name "timers23_slotTime_en" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 24 Name "timers01_slotTime_din" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 25 Name "timers01_slotTime_en" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 26 Name "timer1_slotCount_din" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 27 Name "timer1_slotCount_en" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "sg_plb_addrpref" SID "869:101" Ports [1, 1] Position [175, 870, 245, 890] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed point to Xilinx" " fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top level input p" "orts." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "20" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "xlGetNormalizedPeriod()" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off UseAsADC off ADCChannel "'1'" hdl_port "on" sginterface "{'Xilinx'=>{'jtaghwcosim'=>{'non_memory_mapped_port'=>'sg_plb_addrpref'}},'iopad'=>{'constraint'=>'" "#'}}" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "70,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 70 70 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 70 70 0 0 ],[0 0 20 20 0 ]);\npatch([30.55 33.44 35.44 37.44 39.44 35.44 32.55 30.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([32.55 35.44 33.44 30.55 32.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([30.55 33.44 35.44 32.55 30.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([32.55 39.44 37.44 35.44 33.44 30.55 32.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" "\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end ic" "on text');" Port { PortNumber 1 Name "addrPref" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Line { Name "Sl_addrAck" SrcBlock "plb_decode" SrcPort 2 Points [0, 0] Branch { Labels [1, 0] DstBlock "plb_memmap" DstPort 5 } Branch { Labels [0, 0] DstBlock "Sl_addrAck" DstPort 1 } } Line { Name "Sl_wrDAck" SrcBlock "plb_decode" SrcPort 4 Points [0, 0] Branch { Labels [1, 0] DstBlock "Sl_wrDAck" DstPort 1 } Branch { Labels [0, 0] DstBlock "Sl_wrComp" DstPort 1 } } Line { Name "timer1_slotCount_en" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 27 DstBlock "To Register12" DstPort 2 } Line { Name "timer1_slotCount_din" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 26 DstBlock "To Register12" DstPort 1 } Line { Name "timers01_slotTime_en" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 25 DstBlock "To Register11" DstPort 2 } Line { Name "timers01_slotTime_din" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 24 DstBlock "To Register11" DstPort 1 } Line { Name "timers23_slotTime_en" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 23 DstBlock "To Register10" DstPort 2 } Line { Name "timers23_slotTime_din" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 22 DstBlock "To Register10" DstPort 1 } Line { Name "timers45_slotTime_en" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 21 DstBlock "To Register9" DstPort 2 } Line { Name "timers45_slotTime_din" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 20 DstBlock "To Register9" DstPort 1 } Line { Name "timers67_slotTime_en" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 19 DstBlock "To Register8" DstPort 2 } Line { Name "timers67_slotTime_din" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 18 DstBlock "To Register8" DstPort 1 } Line { Name "timer3_slotCount_en" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 17 DstBlock "To Register7" DstPort 2 } Line { Name "timer3_slotCount_din" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 16 DstBlock "To Register7" DstPort 1 } Line { Name "timer2_slotCount_en" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 15 DstBlock "To Register6" DstPort 2 } Line { Name "timer2_slotCount_din" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 14 DstBlock "To Register6" DstPort 1 } Line { Name "timer5_slotCount_en" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 13 DstBlock "To Register5" DstPort 2 } Line { Name "timer5_slotCount_din" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 12 DstBlock "To Register5" DstPort 1 } Line { Name "timer7_slotCount_en" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 11 DstBlock "To Register4" DstPort 2 } Line { Name "timer7_slotCount_din" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 10 DstBlock "To Register4" DstPort 1 } Line { Name "timer6_slotCount_en" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 9 DstBlock "To Register3" DstPort 2 } Line { Name "timer6_slotCount_din" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 8 DstBlock "To Register3" DstPort 1 } Line { Name "timer4_slotCount_en" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 7 DstBlock "To Register2" DstPort 2 } Line { Name "timer4_slotCount_din" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 6 DstBlock "To Register2" DstPort 1 } Line { Name "timer_control_en" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 5 DstBlock "To Register1" DstPort 2 } Line { Name "timer_control_din" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 4 DstBlock "To Register1" DstPort 1 } Line { Name "timer0_slotCount_en" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 3 DstBlock "To Register" DstPort 2 } Line { Name "timer0_slotCount_din" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 2 DstBlock "To Register" DstPort 1 } Line { Name "rdData" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 1 DstBlock "plb_decode" DstPort 6 } Line { Name "timer1_slotCount_dout" Labels [0, 0; 0, 0] SrcBlock "To Register12" SrcPort 1 DstBlock "plb_memmap" DstPort 19 } Line { Name "timers01_slotTime_dout" Labels [0, 0; 0, 0] SrcBlock "To Register11" SrcPort 1 DstBlock "plb_memmap" DstPort 18 } Line { Name "timers23_slotTime_dout" Labels [0, 0; 0, 0] SrcBlock "To Register10" SrcPort 1 DstBlock "plb_memmap" DstPort 17 } Line { Name "timers45_slotTime_dout" Labels [0, 0; 0, 0] SrcBlock "To Register9" SrcPort 1 DstBlock "plb_memmap" DstPort 16 } Line { Name "timers67_slotTime_dout" Labels [0, 0; 0, 0] SrcBlock "To Register8" SrcPort 1 DstBlock "plb_memmap" DstPort 15 } Line { Name "timer3_slotCount_dout" Labels [0, 0; 0, 0] SrcBlock "To Register7" SrcPort 1 DstBlock "plb_memmap" DstPort 14 } Line { Name "timer2_slotCount_dout" Labels [0, 0; 0, 0] SrcBlock "To Register6" SrcPort 1 DstBlock "plb_memmap" DstPort 13 } Line { Name "timer5_slotCount_dout" Labels [0, 0; 0, 0] SrcBlock "To Register5" SrcPort 1 DstBlock "plb_memmap" DstPort 12 } Line { Name "timer7_slotCount_dout" Labels [0, 0; 0, 0] SrcBlock "To Register4" SrcPort 1 DstBlock "plb_memmap" DstPort 11 } Line { Name "timer6_slotCount_dout" Labels [0, 0; 0, 0] SrcBlock "To Register3" SrcPort 1 DstBlock "plb_memmap" DstPort 10 } Line { Name "timer4_slotCount_dout" Labels [0, 0; 0, 0] SrcBlock "To Register2" SrcPort 1 DstBlock "plb_memmap" DstPort 9 } Line { Name "timer_control_dout" Labels [0, 0; 0, 0] SrcBlock "To Register1" SrcPort 1 DstBlock "plb_memmap" DstPort 8 } Line { Name "timer0_slotCount_dout" Labels [0, 0; 0, 0] SrcBlock "To Register" SrcPort 1 DstBlock "plb_memmap" DstPort 7 } Line { Name "timer_status_dout" Labels [0, 0; 0, 0] SrcBlock "From Register" SrcPort 1 DstBlock "plb_memmap" DstPort 6 } Line { Name "RNWReg" Labels [0, 0; 0, 0] SrcBlock "plb_decode" SrcPort 6 DstBlock "plb_memmap" DstPort 4 } Line { Name "linearAddr" Labels [0, 0; 0, 0] SrcBlock "plb_decode" SrcPort 9 DstBlock "plb_memmap" DstPort 3 } Line { Name "bankAddr" Labels [0, 0; 0, 0] SrcBlock "plb_decode" SrcPort 5 DstBlock "plb_memmap" DstPort 2 } Line { Name "wrDBusReg" Labels [0, 0; 0, 0] SrcBlock "plb_decode" SrcPort 1 DstBlock "plb_memmap" DstPort 1 } Line { Name "Sl_rdDBus" Labels [0, 0; 0, 0] SrcBlock "plb_decode" SrcPort 8 DstBlock "Sl_rdDBus" DstPort 1 } Line { Name "Sl_rdDAck" Labels [0, 0; 0, 0] SrcBlock "plb_decode" SrcPort 7 DstBlock "Sl_rdDAck" DstPort 1 } Line { Name "Sl_rdComp" Labels [0, 0; 0, 0] SrcBlock "plb_decode" SrcPort 3 DstBlock "Sl_rdComp" DstPort 1 } Line { Name "addrPref" Labels [0, 0; 0, 0] SrcBlock "sg_plb_addrpref" SrcPort 1 DstBlock "plb_decode" DstPort 7 } Line { Name "PLB_wrDBus" Labels [0, 0; 0, 0] SrcBlock "PLB_wrDBus" SrcPort 1 DstBlock "plb_decode" DstPort 5 } Line { Name "PLB_RNW" Labels [0, 0; 0, 0] SrcBlock "PLB_RNW" SrcPort 1 DstBlock "plb_decode" DstPort 4 } Line { Name "PLB_PAValid" Labels [0, 0; 0, 0] SrcBlock "PLB_PAValid" SrcPort 1 DstBlock "plb_decode" DstPort 3 } Line { Name "PLB_ABus" Labels [0, 0; 0, 0] SrcBlock "PLB_ABus" SrcPort 1 DstBlock "plb_decode" DstPort 2 } Line { Name "SPLB_Rst" Labels [0, 0; 0, 0] SrcBlock "SPLB_Rst" SrcPort 1 DstBlock "plb_decode" DstPort 1 } Line { SrcBlock "Constant6" SrcPort 1 DstBlock "sg_plb_addrpref" DstPort 1 } Line { Name "Sl_wait" Labels [0, 0; 0, 0] SrcBlock "Constant5" SrcPort 1 DstBlock "Sl_wait" DstPort 1 } Line { SrcBlock "Constant4" SrcPort 1 DstBlock "PLB_wrDBus" DstPort 1 } Line { SrcBlock "Constant3" SrcPort 1 DstBlock "PLB_RNW" DstPort 1 } Line { SrcBlock "Constant2" SrcPort 1 DstBlock "PLB_PAValid" DstPort 1 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "PLB_ABus" DstPort 1 } Line { SrcBlock "Constant" SrcPort 1 DstBlock "SPLB_Rst" DstPort 1 } Line { SrcBlock "Sl_wrComp" SrcPort 1 DstBlock "Terminator6" DstPort 1 } Line { SrcBlock "Sl_wrDAck" SrcPort 1 DstBlock "Terminator5" DstPort 1 } Line { SrcBlock "Sl_wait" SrcPort 1 DstBlock "Terminator4" DstPort 1 } Line { SrcBlock "Sl_rdDBus" SrcPort 1 DstBlock "Terminator3" DstPort 1 } Line { SrcBlock "Sl_rdDAck" SrcPort 1 DstBlock "Terminator2" DstPort 1 } Line { SrcBlock "Sl_rdComp" SrcPort 1 DstBlock "Terminator1" DstPort 1 } Line { SrcBlock "Sl_addrAck" SrcPort 1 DstBlock "Terminator" DstPort 1 } } } Block { BlockType From Name "From" SID "12" Position [150, 131, 265, 149] ShowName off CloseFcn "tagdialog Close" GotoTag "timer0_doneReset" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType From Name "From1" SID "13" Position [150, 116, 265, 134] ShowName off CloseFcn "tagdialog Close" GotoTag "timer0_mode" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType From Name "From10" SID "14" Position [150, 281, 265, 299] ShowName off CloseFcn "tagdialog Close" GotoTag "timer1_slotCount" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType From Name "From11" SID "15" Position [150, 296, 265, 314] ShowName off CloseFcn "tagdialog Close" GotoTag "timer1_slotTime" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType From Name "From12" SID "16" Position [150, 416, 265, 434] ShowName off CloseFcn "tagdialog Close" GotoTag "timer2_slotCount" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType From Name "From13" SID "17" Position [150, 431, 265, 449] ShowName off CloseFcn "tagdialog Close" GotoTag "timer2_slotTime" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType From Name "From14" SID "18" Position [150, 401, 265, 419] ShowName off CloseFcn "tagdialog Close" GotoTag "timer2_doneReset" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType From Name "From15" SID "19" Position [150, 386, 265, 404] ShowName off CloseFcn "tagdialog Close" GotoTag "timer2_mode" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType From Name "From16" SID "20" Position [150, 371, 265, 389] ShowName off CloseFcn "tagdialog Close" GotoTag "timer2_pause" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType From Name "From17" SID "21" Position [150, 356, 265, 374] ShowName off CloseFcn "tagdialog Close" GotoTag "timer2_start" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType From Name "From18" SID "22" Position [150, 556, 265, 574] ShowName off CloseFcn "tagdialog Close" GotoTag "timer3_slotCount" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType From Name "From19" SID "23" Position [150, 571, 265, 589] ShowName off CloseFcn "tagdialog Close" GotoTag "timer3_slotTime" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType From Name "From2" SID "24" Position [150, 101, 265, 119] ShowName off CloseFcn "tagdialog Close" GotoTag "timer0_pause" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType From Name "From20" SID "25" Position [150, 541, 265, 559] ShowName off CloseFcn "tagdialog Close" GotoTag "timer3_doneReset" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType From Name "From21" SID "26" Position [150, 526, 265, 544] ShowName off CloseFcn "tagdialog Close" GotoTag "timer3_mode" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType From Name "From22" SID "27" Position [150, 511, 265, 529] ShowName off CloseFcn "tagdialog Close" GotoTag "timer3_pause" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType From Name "From23" SID "28" Position [150, 496, 265, 514] ShowName off CloseFcn "tagdialog Close" GotoTag "timer3_start" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType From Name "From24" SID "29" Position [665, 121, 780, 139] ShowName off CloseFcn "tagdialog Close" GotoTag "timer4_doneReset" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType From Name "From25" SID "30" Position [665, 106, 780, 124] ShowName off CloseFcn "tagdialog Close" GotoTag "timer4_mode" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType From Name "From26" SID "31" Position [665, 271, 780, 289] ShowName off CloseFcn "tagdialog Close" GotoTag "timer5_slotCount" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType From Name "From27" SID "32" Position [665, 286, 780, 304] ShowName off CloseFcn "tagdialog Close" GotoTag "timer5_slotTime" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType From Name "From28" SID "33" Position [665, 406, 780, 424] ShowName off CloseFcn "tagdialog Close" GotoTag "timer6_slotCount" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType From Name "From29" SID "34" Position [665, 421, 780, 439] ShowName off CloseFcn "tagdialog Close" GotoTag "timer6_slotTime" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType From Name "From3" SID "35" Position [150, 86, 265, 104] ShowName off CloseFcn "tagdialog Close" GotoTag "timer0_start" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType From Name "From30" SID "36" Position [665, 391, 780, 409] ShowName off CloseFcn "tagdialog Close" GotoTag "timer6_doneReset" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType From Name "From31" SID "37" Position [665, 376, 780, 394] ShowName off CloseFcn "tagdialog Close" GotoTag "timer6_mode" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType From Name "From32" SID "38" Position [665, 361, 780, 379] ShowName off CloseFcn "tagdialog Close" GotoTag "timer6_pause" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType From Name "From33" SID "39" Position [665, 346, 780, 364] ShowName off CloseFcn "tagdialog Close" GotoTag "timer6_start" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType From Name "From34" SID "40" Position [665, 546, 780, 564] ShowName off CloseFcn "tagdialog Close" GotoTag "timer7_slotCount" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType From Name "From35" SID "41" Position [665, 561, 780, 579] ShowName off CloseFcn "tagdialog Close" GotoTag "timer7_slotTime" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType From Name "From36" SID "42" Position [665, 91, 780, 109] ShowName off CloseFcn "tagdialog Close" GotoTag "timer4_pause" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType From Name "From37" SID "43" Position [665, 531, 780, 549] ShowName off CloseFcn "tagdialog Close" GotoTag "timer7_doneReset" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType From Name "From38" SID "44" Position [665, 516, 780, 534] ShowName off CloseFcn "tagdialog Close" GotoTag "timer7_mode" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType From Name "From39" SID "45" Position [665, 501, 780, 519] ShowName off CloseFcn "tagdialog Close" GotoTag "timer7_pause" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType From Name "From4" SID "46" Position [150, 146, 265, 164] ShowName off CloseFcn "tagdialog Close" GotoTag "timer0_slotCount" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType From Name "From40" SID "47" Position [665, 486, 780, 504] ShowName off CloseFcn "tagdialog Close" GotoTag "timer7_start" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType From Name "From41" SID "48" Position [665, 76, 780, 94] ShowName off CloseFcn "tagdialog Close" GotoTag "timer4_start" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType From Name "From42" SID "49" Position [665, 136, 780, 154] ShowName off CloseFcn "tagdialog Close" GotoTag "timer4_slotCount" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType From Name "From43" SID "50" Position [665, 151, 780, 169] ShowName off CloseFcn "tagdialog Close" GotoTag "timer4_slotTime" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType From Name "From44" SID "51" Position [665, 256, 780, 274] ShowName off CloseFcn "tagdialog Close" GotoTag "timer5_doneReset" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType From Name "From45" SID "52" Position [665, 241, 780, 259] ShowName off CloseFcn "tagdialog Close" GotoTag "timer5_mode" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType From Name "From46" SID "53" Position [665, 226, 780, 244] ShowName off CloseFcn "tagdialog Close" GotoTag "timer5_pause" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType From Name "From47" SID "54" Position [665, 211, 780, 229] ShowName off CloseFcn "tagdialog Close" GotoTag "timer5_start" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType From Name "From5" SID "55" Position [150, 161, 265, 179] ShowName off CloseFcn "tagdialog Close" GotoTag "timer0_slotTime" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType From Name "From6" SID "56" Position [150, 266, 265, 284] ShowName off CloseFcn "tagdialog Close" GotoTag "timer1_doneReset" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType From Name "From7" SID "57" Position [150, 251, 265, 269] ShowName off CloseFcn "tagdialog Close" GotoTag "timer1_mode" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType From Name "From8" SID "58" Position [150, 236, 265, 254] ShowName off CloseFcn "tagdialog Close" GotoTag "timer1_pause" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType From Name "From9" SID "59" Position [150, 221, 265, 239] ShowName off CloseFcn "tagdialog Close" GotoTag "timer1_start" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "IDLEFORDIFS" SID "60" Ports [1, 1] Position [70, 177, 135, 193] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, double and fixed point to Xilinx " "fixed point type.

Hardware notes: In hardware these blocks become top level input ports." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off UseAsADC off ADCChannel "'1'" hdl_port "on" has_advanced_control "0" sggui_pos "20,20,356,432" block_type "gatewayin" block_version "8.2" sg_icon_stat "65,16,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 16 16 0 ],[0.95 0." "93 0.65 ]);\nplot([0 65 65 0 0 ],[0 0 16 16 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[10." "22 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[8.22 8.22 10." "22 10.22 8.22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 " "1 ]);\npatch([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.985 0.979 0.8" "95 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_" "label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf" "('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "Registers" SID "61" Ports [] Position [585, 687, 636, 737] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "Registers" Location [1101, 654, 1279, 882] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Reference Name "16LSB" SID "62" Ports [1, 1] Position [580, 254, 605, 266] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type " "is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardware " "notes: In hardware this block costs nothing." nbits "16" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "LSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,407" block_type "slice" block_version "9.1.01" sg_icon_stat "25,12,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 12 12 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 12 12 0 ]);\npatch([9.775 11.22 12.22 13.22 14.22 12.22 10.775 9.775 ],[7.11 7.11 8." "11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([10.775 12.22 11.22 9.775 10.775 ],[6.11 6.11 7.11 7.11 6.11 ],[0.9" "31 0.946 0.973 ]);\npatch([9.775 11.22 12.22 10.775 9.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch([10.775 1" "4.22 13.22 12.22 11.22 9.775 10.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.931 0.946 0.973 ]);\nfprintf('','COM" "MENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'[a:b]'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "16LSB1" SID "63" Ports [1, 1] Position [580, 319, 605, 331] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type " "is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardware " "notes: In hardware this block costs nothing." nbits "16" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "LSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,407" block_type "slice" block_version "9.1.01" sg_icon_stat "25,12,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 12 12 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 12 12 0 ]);\npatch([9.775 11.22 12.22 13.22 14.22 12.22 10.775 9.775 ],[7.11 7.11 8." "11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([10.775 12.22 11.22 9.775 10.775 ],[6.11 6.11 7.11 7.11 6.11 ],[0.9" "31 0.946 0.973 ]);\npatch([9.775 11.22 12.22 10.775 9.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch([10.775 1" "4.22 13.22 12.22 11.22 9.775 10.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.931 0.946 0.973 ]);\nfprintf('','COM" "MENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'[a:b]'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "16LSB2" SID "64" Ports [1, 1] Position [580, 384, 605, 396] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type " "is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardware " "notes: In hardware this block costs nothing." nbits "16" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "LSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,407" block_type "slice" block_version "9.1.01" sg_icon_stat "25,12,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 12 12 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 12 12 0 ]);\npatch([9.775 11.22 12.22 13.22 14.22 12.22 10.775 9.775 ],[7.11 7.11 8." "11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([10.775 12.22 11.22 9.775 10.775 ],[6.11 6.11 7.11 7.11 6.11 ],[0.9" "31 0.946 0.973 ]);\npatch([9.775 11.22 12.22 10.775 9.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch([10.775 1" "4.22 13.22 12.22 11.22 9.775 10.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.931 0.946 0.973 ]);\nfprintf('','COM" "MENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'[a:b]'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "16LSB3" SID "65" Ports [1, 1] Position [580, 449, 605, 461] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type " "is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardware " "notes: In hardware this block costs nothing." nbits "16" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "LSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,407" block_type "slice" block_version "9.1.01" sg_icon_stat "25,12,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 12 12 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 12 12 0 ]);\npatch([9.775 11.22 12.22 13.22 14.22 12.22 10.775 9.775 ],[7.11 7.11 8." "11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([10.775 12.22 11.22 9.775 10.775 ],[6.11 6.11 7.11 7.11 6.11 ],[0.9" "31 0.946 0.973 ]);\npatch([9.775 11.22 12.22 10.775 9.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch([10.775 1" "4.22 13.22 12.22 11.22 9.775 10.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.931 0.946 0.973 ]);\nfprintf('','COM" "MENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'[a:b]'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "16MSB" SID "66" Ports [1, 1] Position [580, 269, 605, 281] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type " "is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardware " "notes: In hardware this block costs nothing." nbits "16" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "LSB of Input" bit0 "16" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,407" block_type "slice" block_version "9.1.01" sg_icon_stat "25,12,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 12 12 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 12 12 0 ]);\npatch([9.775 11.22 12.22 13.22 14.22 12.22 10.775 9.775 ],[7.11 7.11 8." "11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([10.775 12.22 11.22 9.775 10.775 ],[6.11 6.11 7.11 7.11 6.11 ],[0.9" "31 0.946 0.973 ]);\npatch([9.775 11.22 12.22 10.775 9.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch([10.775 1" "4.22 13.22 12.22 11.22 9.775 10.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.931 0.946 0.973 ]);\nfprintf('','COM" "MENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'[a:b]'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "16MSB1" SID "67" Ports [1, 1] Position [580, 334, 605, 346] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type " "is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardware " "notes: In hardware this block costs nothing." nbits "16" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "LSB of Input" bit0 "16" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,407" block_type "slice" block_version "9.1.01" sg_icon_stat "25,12,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 12 12 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 12 12 0 ]);\npatch([9.775 11.22 12.22 13.22 14.22 12.22 10.775 9.775 ],[7.11 7.11 8." "11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([10.775 12.22 11.22 9.775 10.775 ],[6.11 6.11 7.11 7.11 6.11 ],[0.9" "31 0.946 0.973 ]);\npatch([9.775 11.22 12.22 10.775 9.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch([10.775 1" "4.22 13.22 12.22 11.22 9.775 10.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.931 0.946 0.973 ]);\nfprintf('','COM" "MENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'[a:b]'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "16MSB2" SID "68" Ports [1, 1] Position [580, 399, 605, 411] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type " "is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardware " "notes: In hardware this block costs nothing." nbits "16" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "LSB of Input" bit0 "16" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,407" block_type "slice" block_version "9.1.01" sg_icon_stat "25,12,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 12 12 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 12 12 0 ]);\npatch([9.775 11.22 12.22 13.22 14.22 12.22 10.775 9.775 ],[7.11 7.11 8." "11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([10.775 12.22 11.22 9.775 10.775 ],[6.11 6.11 7.11 7.11 6.11 ],[0.9" "31 0.946 0.973 ]);\npatch([9.775 11.22 12.22 10.775 9.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch([10.775 1" "4.22 13.22 12.22 11.22 9.775 10.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.931 0.946 0.973 ]);\nfprintf('','COM" "MENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'[a:b]'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "16MSB3" SID "69" Ports [1, 1] Position [580, 464, 605, 476] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type " "is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardware " "notes: In hardware this block costs nothing." nbits "16" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "LSB of Input" bit0 "16" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,407" block_type "slice" block_version "9.1.01" sg_icon_stat "25,12,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 12 12 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 12 12 0 ]);\npatch([9.775 11.22 12.22 13.22 14.22 12.22 10.775 9.775 ],[7.11 7.11 8." "11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([10.775 12.22 11.22 9.775 10.775 ],[6.11 6.11 7.11 7.11 6.11 ],[0.9" "31 0.946 0.973 ]);\npatch([9.775 11.22 12.22 10.775 9.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch([10.775 1" "4.22 13.22 12.22 11.22 9.775 10.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.931 0.946 0.973 ]);\nfprintf('','COM" "MENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'[a:b]'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant5" SID "70" Ports [0, 1] Position [560, 600, 595, 620] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,400,346" block_type "constant" block_version "8.2" sg_icon_stat "35,20,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.91" " ]);\nplot([0 35 35 0 0 ],[0 0 20 20 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1," "'1');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "From Register1" SID "71" Ports [0, 1] Position [120, 302, 145, 328] ShowName off AttributesFormatString "From Register\\n<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/From Register" SourceType "Xilinx Shared Memory Based From Register Block" infoedit "Register block that reads data to a shared memory register. Delay of one sample period." shared_memory_name "'timer1_slotCount'" init "500" period "1" ownership "Locally owned and initialized" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "514,418,383,246" block_type "fromreg" block_version "8.2" sg_icon_stat "25,26,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output'," "1,'dout');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "From Register11" SID "72" Ports [0, 1] Position [455, 262, 480, 288] ShowName off AttributesFormatString "From Register\\n<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/From Register" SourceType "Xilinx Shared Memory Based From Register Block" infoedit "Register block that reads data to a shared memory register. Delay of one sample period." shared_memory_name "'timers01_slotTime'" init "0" period "1" ownership "Locally owned and initialized" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "514,418,383,246" block_type "fromreg" block_version "8.2" sg_icon_stat "25,26,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output'," "1,'dout');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "From Register12" SID "73" Ports [0, 1] Position [455, 327, 480, 353] ShowName off AttributesFormatString "From Register\\n<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/From Register" SourceType "Xilinx Shared Memory Based From Register Block" infoedit "Register block that reads data to a shared memory register. Delay of one sample period." shared_memory_name "'timers23_slotTime'" init "0" period "1" ownership "Locally owned and initialized" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "514,418,383,246" block_type "fromreg" block_version "8.2" sg_icon_stat "25,26,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output'," "1,'dout');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "From Register13" SID "74" Ports [0, 1] Position [455, 392, 480, 418] ShowName off AttributesFormatString "From Register\\n<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/From Register" SourceType "Xilinx Shared Memory Based From Register Block" infoedit "Register block that reads data to a shared memory register. Delay of one sample period." shared_memory_name "'timers45_slotTime'" init "0" period "1" ownership "Locally owned and initialized" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "514,418,383,246" block_type "fromreg" block_version "8.2" sg_icon_stat "25,26,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output'," "1,'dout');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "From Register14" SID "75" Ports [0, 1] Position [455, 457, 480, 483] ShowName off AttributesFormatString "From Register\\n<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/From Register" SourceType "Xilinx Shared Memory Based From Register Block" infoedit "Register block that reads data to a shared memory register. Delay of one sample period." shared_memory_name "'timers67_slotTime'" init "0" period "1" ownership "Locally owned and initialized" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "514,418,383,246" block_type "fromreg" block_version "8.2" sg_icon_stat "25,26,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output'," "1,'dout');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "From Register2" SID "76" Ports [0, 1] Position [120, 427, 145, 453] ShowName off AttributesFormatString "From Register\\n<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/From Register" SourceType "Xilinx Shared Memory Based From Register Block" infoedit "Register block that reads data to a shared memory register. Delay of one sample period." shared_memory_name "'timer3_slotCount'" init "500" period "1" ownership "Locally owned and initialized" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "514,418,383,246" block_type "fromreg" block_version "8.2" sg_icon_stat "25,26,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output'," "1,'dout');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "From Register3" SID "77" Ports [0, 1] Position [120, 362, 145, 388] ShowName off AttributesFormatString "From Register\\n<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/From Register" SourceType "Xilinx Shared Memory Based From Register Block" infoedit "Register block that reads data to a shared memory register. Delay of one sample period." shared_memory_name "'timer2_slotCount'" init "500" period "1" ownership "Locally owned and initialized" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "514,418,383,246" block_type "fromreg" block_version "8.2" sg_icon_stat "25,26,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output'," "1,'dout');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "From Register4" SID "78" Ports [0, 1] Position [120, 557, 145, 583] ShowName off AttributesFormatString "From Register\\n<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/From Register" SourceType "Xilinx Shared Memory Based From Register Block" infoedit "Register block that reads data to a shared memory register. Delay of one sample period." shared_memory_name "'timer5_slotCount'" init "500" period "1" ownership "Locally owned and initialized" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "514,418,383,246" block_type "fromreg" block_version "8.2" sg_icon_stat "25,26,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output'," "1,'dout');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "From Register5" SID "79" Ports [0, 1] Position [120, 682, 145, 708] ShowName off AttributesFormatString "From Register\\n<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/From Register" SourceType "Xilinx Shared Memory Based From Register Block" infoedit "Register block that reads data to a shared memory register. Delay of one sample period." shared_memory_name "'timer7_slotCount'" init "500" period "1" ownership "Locally owned and initialized" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "514,418,383,246" block_type "fromreg" block_version "8.2" sg_icon_stat "25,26,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output'," "1,'dout');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "From Register6" SID "80" Ports [0, 1] Position [120, 617, 145, 643] ShowName off AttributesFormatString "From Register\\n<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/From Register" SourceType "Xilinx Shared Memory Based From Register Block" infoedit "Register block that reads data to a shared memory register. Delay of one sample period." shared_memory_name "'timer6_slotCount'" init "500" period "1" ownership "Locally owned and initialized" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "514,418,383,246" block_type "fromreg" block_version "8.2" sg_icon_stat "25,26,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output'," "1,'dout');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "From Register7" SID "81" Ports [0, 1] Position [120, 492, 145, 518] ShowName off AttributesFormatString "From Register\\n<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/From Register" SourceType "Xilinx Shared Memory Based From Register Block" infoedit "Register block that reads data to a shared memory register. Delay of one sample period." shared_memory_name "'timer4_slotCount'" init "500" period "1" ownership "Locally owned and initialized" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "514,418,383,246" block_type "fromreg" block_version "8.2" sg_icon_stat "25,26,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output'," "1,'dout');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "From Register8" SID "82" Ports [0, 1] Position [365, 132, 390, 158] ShowName off AttributesFormatString "From Register\\n<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/From Register" SourceType "Xilinx Shared Memory Based From Register Block" infoedit "Register block that reads data to a shared memory register. Delay of one sample period." shared_memory_name "'timer_control'" init "0" period "1" ownership "Locally owned and initialized" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "412,24,383,246" block_type "fromreg" block_version "8.2" sg_icon_stat "25,26,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output'," "1,'dout');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "From Register9" SID "83" Ports [0, 1] Position [120, 237, 145, 263] ShowName off AttributesFormatString "From Register\\n<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/From Register" SourceType "Xilinx Shared Memory Based From Register Block" infoedit "Register block that reads data to a shared memory register. Delay of one sample period." shared_memory_name "'timer0_slotCount'" init "500" period "1" ownership "Locally owned and initialized" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "514,418,383,246" block_type "fromreg" block_version "8.2" sg_icon_stat "25,26,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 26 26 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[16.33 16.33 19" ".33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[13.33 13.33 16.33 16.33 13.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output'," "1,'dout');\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From40" SID "84" Position [455, 576, 570, 594] ShowName off CloseFcn "tagdialog Close" GotoTag "timers_status" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Goto Name "Goto" SID "85" Position [200, 241, 335, 259] ShowName off GotoTag "timer0_slotCount" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Goto Name "Goto1" SID "86" Position [200, 306, 335, 324] ShowName off GotoTag "timer1_slotCount" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Goto Name "Goto10" SID "87" Position [670, 316, 805, 334] ShowName off GotoTag "timer2_slotTime" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Goto Name "Goto11" SID "88" Position [670, 331, 805, 349] ShowName off GotoTag "timer3_slotTime" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Goto Name "Goto12" SID "89" Position [670, 381, 805, 399] ShowName off GotoTag "timer4_slotTime" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Goto Name "Goto13" SID "90" Position [670, 396, 805, 414] ShowName off GotoTag "timer5_slotTime" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Goto Name "Goto14" SID "91" Position [670, 446, 805, 464] ShowName off GotoTag "timer6_slotTime" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Goto Name "Goto15" SID "92" Position [670, 461, 805, 479] ShowName off GotoTag "timer7_slotTime" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Goto Name "Goto2" SID "93" Position [200, 366, 335, 384] ShowName off GotoTag "timer2_slotCount" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Goto Name "Goto3" SID "94" Position [200, 431, 335, 449] ShowName off GotoTag "timer3_slotCount" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Goto Name "Goto4" SID "95" Position [200, 496, 335, 514] ShowName off GotoTag "timer4_slotCount" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Goto Name "Goto5" SID "96" Position [200, 561, 335, 579] ShowName off GotoTag "timer5_slotCount" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Goto Name "Goto6" SID "97" Position [200, 621, 335, 639] ShowName off GotoTag "timer6_slotCount" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Goto Name "Goto7" SID "98" Position [200, 686, 335, 704] ShowName off GotoTag "timer7_slotCount" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Goto Name "Goto8" SID "99" Position [670, 251, 805, 269] ShowName off GotoTag "timer0_slotTime" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Goto Name "Goto9" SID "100" Position [670, 266, 805, 284] ShowName off GotoTag "timer1_slotTime" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType SubSystem Name "Slices & Gotos" SID "101" Ports [1] Position [445, 134, 500, 156] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "Slices & Gotos" Location [494, 176, 924, 786] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "32b" SID "102" Position [25, 28, 55, 42] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "4LSB" SID "103" Ports [1, 1] Position [115, 29, 140, 41] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outp" "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

" "

Hardware notes: In hardware this block costs nothing." nbits "4" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "LSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,407" block_type "slice" block_version "9.1.01" sg_icon_stat "25,12,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 12 12 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 12 12 0 ]);\npatch([9.775 11.22 12.22 13.22 14.22 12.22 10.775 9.775 ],[" "7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([10.775 12.22 11.22 9.775 10.775 ],[6.11 6.11 7.11 " "7.11 6.11 ],[0.931 0.946 0.973 ]);\npatch([9.775 11.22 12.22 10.775 9.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 " "]);\npatch([10.775 14.22 13.22 12.22 11.22 9.775 10.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.931 0.946 0." "973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');p" "ort_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "4LSB+12" SID "104" Ports [1, 1] Position [115, 244, 140, 256] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outp" "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

" "

Hardware notes: In hardware this block costs nothing." nbits "4" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "LSB of Input" bit0 "12" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,407" block_type "slice" block_version "9.1.01" sg_icon_stat "25,12,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 12 12 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 12 12 0 ]);\npatch([9.775 11.22 12.22 13.22 14.22 12.22 10.775 9.775 ],[" "7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([10.775 12.22 11.22 9.775 10.775 ],[6.11 6.11 7.11 " "7.11 6.11 ],[0.931 0.946 0.973 ]);\npatch([9.775 11.22 12.22 10.775 9.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 " "]);\npatch([10.775 14.22 13.22 12.22 11.22 9.775 10.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.931 0.946 0." "973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');p" "ort_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "4LSB+16" SID "105" Ports [1, 1] Position [115, 314, 140, 326] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outp" "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

" "

Hardware notes: In hardware this block costs nothing." nbits "4" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "LSB of Input" bit0 "16" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,407" block_type "slice" block_version "9.1.01" sg_icon_stat "25,12,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 12 12 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 12 12 0 ]);\npatch([9.775 11.22 12.22 13.22 14.22 12.22 10.775 9.775 ],[" "7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([10.775 12.22 11.22 9.775 10.775 ],[6.11 6.11 7.11 " "7.11 6.11 ],[0.931 0.946 0.973 ]);\npatch([9.775 11.22 12.22 10.775 9.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 " "]);\npatch([10.775 14.22 13.22 12.22 11.22 9.775 10.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.931 0.946 0." "973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');p" "ort_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "4LSB+20" SID "106" Ports [1, 1] Position [115, 384, 140, 396] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outp" "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

" "

Hardware notes: In hardware this block costs nothing." nbits "4" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "LSB of Input" bit0 "20" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,407" block_type "slice" block_version "9.1.01" sg_icon_stat "25,12,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 12 12 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 12 12 0 ]);\npatch([9.775 11.22 12.22 13.22 14.22 12.22 10.775 9.775 ],[" "7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([10.775 12.22 11.22 9.775 10.775 ],[6.11 6.11 7.11 " "7.11 6.11 ],[0.931 0.946 0.973 ]);\npatch([9.775 11.22 12.22 10.775 9.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 " "]);\npatch([10.775 14.22 13.22 12.22 11.22 9.775 10.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.931 0.946 0." "973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');p" "ort_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "4LSB+24" SID "107" Ports [1, 1] Position [115, 454, 140, 466] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outp" "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

" "

Hardware notes: In hardware this block costs nothing." nbits "4" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "LSB of Input" bit0 "24" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,407" block_type "slice" block_version "9.1.01" sg_icon_stat "25,12,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 12 12 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 12 12 0 ]);\npatch([9.775 11.22 12.22 13.22 14.22 12.22 10.775 9.775 ],[" "7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([10.775 12.22 11.22 9.775 10.775 ],[6.11 6.11 7.11 " "7.11 6.11 ],[0.931 0.946 0.973 ]);\npatch([9.775 11.22 12.22 10.775 9.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 " "]);\npatch([10.775 14.22 13.22 12.22 11.22 9.775 10.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.931 0.946 0." "973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');p" "ort_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "4LSB+28" SID "108" Ports [1, 1] Position [115, 524, 140, 536] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outp" "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

" "

Hardware notes: In hardware this block costs nothing." nbits "4" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "LSB of Input" bit0 "28" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,407" block_type "slice" block_version "9.1.01" sg_icon_stat "25,12,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 12 12 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 12 12 0 ]);\npatch([9.775 11.22 12.22 13.22 14.22 12.22 10.775 9.775 ],[" "7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([10.775 12.22 11.22 9.775 10.775 ],[6.11 6.11 7.11 " "7.11 6.11 ],[0.931 0.946 0.973 ]);\npatch([9.775 11.22 12.22 10.775 9.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 " "]);\npatch([10.775 14.22 13.22 12.22 11.22 9.775 10.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.931 0.946 0." "973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');p" "ort_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "4LSB+4" SID "109" Ports [1, 1] Position [115, 99, 140, 111] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outp" "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

" "

Hardware notes: In hardware this block costs nothing." nbits "4" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "LSB of Input" bit0 "4" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,407" block_type "slice" block_version "9.1.01" sg_icon_stat "25,12,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 12 12 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 12 12 0 ]);\npatch([9.775 11.22 12.22 13.22 14.22 12.22 10.775 9.775 ],[" "7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([10.775 12.22 11.22 9.775 10.775 ],[6.11 6.11 7.11 " "7.11 6.11 ],[0.931 0.946 0.973 ]);\npatch([9.775 11.22 12.22 10.775 9.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 " "]);\npatch([10.775 14.22 13.22 12.22 11.22 9.775 10.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.931 0.946 0." "973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');p" "ort_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "4LSB+8" SID "110" Ports [1, 1] Position [115, 174, 140, 186] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outp" "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

" "

Hardware notes: In hardware this block costs nothing." nbits "4" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "LSB of Input" bit0 "8" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,407" block_type "slice" block_version "9.1.01" sg_icon_stat "25,12,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 12 12 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 12 12 0 ]);\npatch([9.775 11.22 12.22 13.22 14.22 12.22 10.775 9.775 ],[" "7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([10.775 12.22 11.22 9.775 10.775 ],[6.11 6.11 7.11 " "7.11 6.11 ],[0.931 0.946 0.973 ]);\npatch([9.775 11.22 12.22 10.775 9.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 " "]);\npatch([10.775 14.22 13.22 12.22 11.22 9.775 10.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.931 0.946 0." "973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');p" "ort_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Goto Name "Goto" SID "111" Position [270, 26, 405, 44] ShowName off GotoTag "timer0_start" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Goto Name "Goto1" SID "112" Position [270, 41, 405, 59] ShowName off GotoTag "timer0_pause" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Goto Name "Goto10" SID "113" Position [270, 202, 405, 218] ShowName off GotoTag "timer2_mode" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Goto Name "Goto11" SID "114" Position [270, 216, 405, 234] ShowName off GotoTag "timer2_doneReset" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Goto Name "Goto12" SID "115" Position [270, 272, 405, 288] ShowName off GotoTag "timer3_mode" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Goto Name "Goto13" SID "116" Position [270, 286, 405, 304] ShowName off GotoTag "timer3_doneReset" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Goto Name "Goto14" SID "117" Position [270, 241, 405, 259] ShowName off GotoTag "timer3_start" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Goto Name "Goto15" SID "118" Position [270, 256, 405, 274] ShowName off GotoTag "timer3_pause" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Goto Name "Goto16" SID "119" Position [270, 311, 405, 329] ShowName off GotoTag "timer4_start" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Goto Name "Goto17" SID "120" Position [270, 326, 405, 344] ShowName off GotoTag "timer4_pause" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Goto Name "Goto18" SID "121" Position [270, 482, 405, 498] ShowName off GotoTag "timer6_mode" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Goto Name "Goto19" SID "122" Position [270, 496, 405, 514] ShowName off GotoTag "timer6_doneReset" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Goto Name "Goto2" SID "123" Position [270, 57, 405, 73] ShowName off GotoTag "timer0_mode" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Goto Name "Goto20" SID "124" Position [270, 552, 405, 568] ShowName off GotoTag "timer7_mode" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Goto Name "Goto21" SID "125" Position [270, 566, 405, 584] ShowName off GotoTag "timer7_doneReset" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Goto Name "Goto22" SID "126" Position [270, 521, 405, 539] ShowName off GotoTag "timer7_start" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Goto Name "Goto23" SID "127" Position [270, 536, 405, 554] ShowName off GotoTag "timer7_pause" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Goto Name "Goto24" SID "128" Position [270, 342, 405, 358] ShowName off GotoTag "timer4_mode" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Goto Name "Goto25" SID "129" Position [270, 356, 405, 374] ShowName off GotoTag "timer4_doneReset" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Goto Name "Goto26" SID "130" Position [270, 381, 405, 399] ShowName off GotoTag "timer5_start" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Goto Name "Goto27" SID "131" Position [270, 396, 405, 414] ShowName off GotoTag "timer5_pause" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Goto Name "Goto28" SID "132" Position [270, 412, 405, 428] ShowName off GotoTag "timer5_mode" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Goto Name "Goto29" SID "133" Position [270, 426, 405, 444] ShowName off GotoTag "timer5_doneReset" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Goto Name "Goto3" SID "134" Position [270, 71, 405, 89] ShowName off GotoTag "timer0_doneReset" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Goto Name "Goto30" SID "135" Position [270, 451, 405, 469] ShowName off GotoTag "timer6_start" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Goto Name "Goto31" SID "136" Position [270, 466, 405, 484] ShowName off GotoTag "timer6_pause" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Goto Name "Goto4" SID "137" Position [270, 96, 405, 114] ShowName off GotoTag "timer1_start" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Goto Name "Goto5" SID "138" Position [270, 111, 405, 129] ShowName off GotoTag "timer1_pause" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Goto Name "Goto6" SID "139" Position [270, 127, 405, 143] ShowName off GotoTag "timer1_mode" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Goto Name "Goto7" SID "140" Position [270, 141, 405, 159] ShowName off GotoTag "timer1_doneReset" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Goto Name "Goto8" SID "141" Position [270, 171, 405, 189] ShowName off GotoTag "timer2_start" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Goto Name "Goto9" SID "142" Position [270, 186, 405, 204] ShowName off GotoTag "timer2_pause" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Slice" SID "143" Ports [1, 1] Position [190, 29, 215, 41] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outp" "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

" "

Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "LSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,407" block_type "slice" block_version "9.1.01" sg_icon_stat "25,12,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 12 12 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 12 12 0 ]);\npatch([9.775 11.22 12.22 13.22 14.22 12.22 10.775 9.775 ],[" "7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([10.775 12.22 11.22 9.775 10.775 ],[6.11 6.11 7.11 " "7.11 6.11 ],[0.931 0.946 0.973 ]);\npatch([9.775 11.22 12.22 10.775 9.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 " "]);\npatch([10.775 14.22 13.22 12.22 11.22 9.775 10.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.931 0.946 0." "973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');p" "ort_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Slice1" SID "144" Ports [1, 1] Position [190, 59, 215, 71] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outp" "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

" "

Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "LSB of Input" bit0 "2" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,407" block_type "slice" block_version "9.1.01" sg_icon_stat "25,12,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 12 12 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 12 12 0 ]);\npatch([9.775 11.22 12.22 13.22 14.22 12.22 10.775 9.775 ],[" "7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([10.775 12.22 11.22 9.775 10.775 ],[6.11 6.11 7.11 " "7.11 6.11 ],[0.931 0.946 0.973 ]);\npatch([9.775 11.22 12.22 10.775 9.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 " "]);\npatch([10.775 14.22 13.22 12.22 11.22 9.775 10.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.931 0.946 0." "973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');p" "ort_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Slice10" SID "145" Ports [1, 1] Position [190, 219, 215, 231] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outp" "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

" "

Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "LSB of Input" bit0 "3" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,407" block_type "slice" block_version "9.1.01" sg_icon_stat "25,12,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 12 12 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 12 12 0 ]);\npatch([9.775 11.22 12.22 13.22 14.22 12.22 10.775 9.775 ],[" "7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([10.775 12.22 11.22 9.775 10.775 ],[6.11 6.11 7.11 " "7.11 6.11 ],[0.931 0.946 0.973 ]);\npatch([9.775 11.22 12.22 10.775 9.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 " "]);\npatch([10.775 14.22 13.22 12.22 11.22 9.775 10.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.931 0.946 0." "973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');p" "ort_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Slice11" SID "146" Ports [1, 1] Position [190, 244, 215, 256] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outp" "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

" "

Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "LSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,407" block_type "slice" block_version "9.1.01" sg_icon_stat "25,12,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 12 12 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 12 12 0 ]);\npatch([9.775 11.22 12.22 13.22 14.22 12.22 10.775 9.775 ],[" "7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([10.775 12.22 11.22 9.775 10.775 ],[6.11 6.11 7.11 " "7.11 6.11 ],[0.931 0.946 0.973 ]);\npatch([9.775 11.22 12.22 10.775 9.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 " "]);\npatch([10.775 14.22 13.22 12.22 11.22 9.775 10.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.931 0.946 0." "973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');p" "ort_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Slice12" SID "147" Ports [1, 1] Position [190, 274, 215, 286] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outp" "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

" "

Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "LSB of Input" bit0 "2" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,407" block_type "slice" block_version "9.1.01" sg_icon_stat "25,12,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 12 12 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 12 12 0 ]);\npatch([9.775 11.22 12.22 13.22 14.22 12.22 10.775 9.775 ],[" "7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([10.775 12.22 11.22 9.775 10.775 ],[6.11 6.11 7.11 " "7.11 6.11 ],[0.931 0.946 0.973 ]);\npatch([9.775 11.22 12.22 10.775 9.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 " "]);\npatch([10.775 14.22 13.22 12.22 11.22 9.775 10.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.931 0.946 0." "973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');p" "ort_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Slice13" SID "148" Ports [1, 1] Position [190, 289, 215, 301] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outp" "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

" "

Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "LSB of Input" bit0 "3" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,407" block_type "slice" block_version "9.1.01" sg_icon_stat "25,12,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 12 12 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 12 12 0 ]);\npatch([9.775 11.22 12.22 13.22 14.22 12.22 10.775 9.775 ],[" "7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([10.775 12.22 11.22 9.775 10.775 ],[6.11 6.11 7.11 " "7.11 6.11 ],[0.931 0.946 0.973 ]);\npatch([9.775 11.22 12.22 10.775 9.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 " "]);\npatch([10.775 14.22 13.22 12.22 11.22 9.775 10.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.931 0.946 0." "973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');p" "ort_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Slice14" SID "149" Ports [1, 1] Position [190, 189, 215, 201] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outp" "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

" "

Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "LSB of Input" bit0 "1" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,407" block_type "slice" block_version "9.1.01" sg_icon_stat "25,12,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 12 12 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 12 12 0 ]);\npatch([9.775 11.22 12.22 13.22 14.22 12.22 10.775 9.775 ],[" "7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([10.775 12.22 11.22 9.775 10.775 ],[6.11 6.11 7.11 " "7.11 6.11 ],[0.931 0.946 0.973 ]);\npatch([9.775 11.22 12.22 10.775 9.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 " "]);\npatch([10.775 14.22 13.22 12.22 11.22 9.775 10.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.931 0.946 0." "973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');p" "ort_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Slice15" SID "150" Ports [1, 1] Position [190, 259, 215, 271] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outp" "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

" "

Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "LSB of Input" bit0 "1" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,407" block_type "slice" block_version "9.1.01" sg_icon_stat "25,12,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 12 12 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 12 12 0 ]);\npatch([9.775 11.22 12.22 13.22 14.22 12.22 10.775 9.775 ],[" "7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([10.775 12.22 11.22 9.775 10.775 ],[6.11 6.11 7.11 " "7.11 6.11 ],[0.931 0.946 0.973 ]);\npatch([9.775 11.22 12.22 10.775 9.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 " "]);\npatch([10.775 14.22 13.22 12.22 11.22 9.775 10.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.931 0.946 0." "973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');p" "ort_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Slice16" SID "151" Ports [1, 1] Position [190, 314, 215, 326] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outp" "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

" "

Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "LSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,407" block_type "slice" block_version "9.1.01" sg_icon_stat "25,12,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 12 12 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 12 12 0 ]);\npatch([9.775 11.22 12.22 13.22 14.22 12.22 10.775 9.775 ],[" "7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([10.775 12.22 11.22 9.775 10.775 ],[6.11 6.11 7.11 " "7.11 6.11 ],[0.931 0.946 0.973 ]);\npatch([9.775 11.22 12.22 10.775 9.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 " "]);\npatch([10.775 14.22 13.22 12.22 11.22 9.775 10.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.931 0.946 0." "973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');p" "ort_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Slice17" SID "152" Ports [1, 1] Position [190, 344, 215, 356] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outp" "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

" "

Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "LSB of Input" bit0 "2" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,407" block_type "slice" block_version "9.1.01" sg_icon_stat "25,12,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 12 12 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 12 12 0 ]);\npatch([9.775 11.22 12.22 13.22 14.22 12.22 10.775 9.775 ],[" "7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([10.775 12.22 11.22 9.775 10.775 ],[6.11 6.11 7.11 " "7.11 6.11 ],[0.931 0.946 0.973 ]);\npatch([9.775 11.22 12.22 10.775 9.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 " "]);\npatch([10.775 14.22 13.22 12.22 11.22 9.775 10.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.931 0.946 0." "973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');p" "ort_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Slice18" SID "153" Ports [1, 1] Position [190, 499, 215, 511] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outp" "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

" "

Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "LSB of Input" bit0 "3" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,407" block_type "slice" block_version "9.1.01" sg_icon_stat "25,12,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 12 12 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 12 12 0 ]);\npatch([9.775 11.22 12.22 13.22 14.22 12.22 10.775 9.775 ],[" "7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([10.775 12.22 11.22 9.775 10.775 ],[6.11 6.11 7.11 " "7.11 6.11 ],[0.931 0.946 0.973 ]);\npatch([9.775 11.22 12.22 10.775 9.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 " "]);\npatch([10.775 14.22 13.22 12.22 11.22 9.775 10.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.931 0.946 0." "973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');p" "ort_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Slice19" SID "154" Ports [1, 1] Position [190, 524, 215, 536] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outp" "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

" "

Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "LSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,407" block_type "slice" block_version "9.1.01" sg_icon_stat "25,12,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 12 12 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 12 12 0 ]);\npatch([9.775 11.22 12.22 13.22 14.22 12.22 10.775 9.775 ],[" "7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([10.775 12.22 11.22 9.775 10.775 ],[6.11 6.11 7.11 " "7.11 6.11 ],[0.931 0.946 0.973 ]);\npatch([9.775 11.22 12.22 10.775 9.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 " "]);\npatch([10.775 14.22 13.22 12.22 11.22 9.775 10.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.931 0.946 0." "973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');p" "ort_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Slice2" SID "155" Ports [1, 1] Position [190, 74, 215, 86] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outp" "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

" "

Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "LSB of Input" bit0 "3" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,407" block_type "slice" block_version "9.1.01" sg_icon_stat "25,12,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 12 12 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 12 12 0 ]);\npatch([9.775 11.22 12.22 13.22 14.22 12.22 10.775 9.775 ],[" "7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([10.775 12.22 11.22 9.775 10.775 ],[6.11 6.11 7.11 " "7.11 6.11 ],[0.931 0.946 0.973 ]);\npatch([9.775 11.22 12.22 10.775 9.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 " "]);\npatch([10.775 14.22 13.22 12.22 11.22 9.775 10.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.931 0.946 0." "973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');p" "ort_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Slice20" SID "156" Ports [1, 1] Position [190, 554, 215, 566] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outp" "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

" "

Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "LSB of Input" bit0 "2" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,407" block_type "slice" block_version "9.1.01" sg_icon_stat "25,12,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 12 12 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 12 12 0 ]);\npatch([9.775 11.22 12.22 13.22 14.22 12.22 10.775 9.775 ],[" "7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([10.775 12.22 11.22 9.775 10.775 ],[6.11 6.11 7.11 " "7.11 6.11 ],[0.931 0.946 0.973 ]);\npatch([9.775 11.22 12.22 10.775 9.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 " "]);\npatch([10.775 14.22 13.22 12.22 11.22 9.775 10.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.931 0.946 0." "973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');p" "ort_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Slice21" SID "157" Ports [1, 1] Position [190, 569, 215, 581] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outp" "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

" "

Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "LSB of Input" bit0 "3" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,407" block_type "slice" block_version "9.1.01" sg_icon_stat "25,12,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 12 12 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 12 12 0 ]);\npatch([9.775 11.22 12.22 13.22 14.22 12.22 10.775 9.775 ],[" "7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([10.775 12.22 11.22 9.775 10.775 ],[6.11 6.11 7.11 " "7.11 6.11 ],[0.931 0.946 0.973 ]);\npatch([9.775 11.22 12.22 10.775 9.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 " "]);\npatch([10.775 14.22 13.22 12.22 11.22 9.775 10.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.931 0.946 0." "973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');p" "ort_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Slice22" SID "158" Ports [1, 1] Position [190, 469, 215, 481] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outp" "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

" "

Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "LSB of Input" bit0 "1" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,407" block_type "slice" block_version "9.1.01" sg_icon_stat "25,12,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 12 12 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 12 12 0 ]);\npatch([9.775 11.22 12.22 13.22 14.22 12.22 10.775 9.775 ],[" "7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([10.775 12.22 11.22 9.775 10.775 ],[6.11 6.11 7.11 " "7.11 6.11 ],[0.931 0.946 0.973 ]);\npatch([9.775 11.22 12.22 10.775 9.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 " "]);\npatch([10.775 14.22 13.22 12.22 11.22 9.775 10.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.931 0.946 0." "973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');p" "ort_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Slice23" SID "159" Ports [1, 1] Position [190, 539, 215, 551] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outp" "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

" "

Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "LSB of Input" bit0 "1" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,407" block_type "slice" block_version "9.1.01" sg_icon_stat "25,12,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 12 12 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 12 12 0 ]);\npatch([9.775 11.22 12.22 13.22 14.22 12.22 10.775 9.775 ],[" "7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([10.775 12.22 11.22 9.775 10.775 ],[6.11 6.11 7.11 " "7.11 6.11 ],[0.931 0.946 0.973 ]);\npatch([9.775 11.22 12.22 10.775 9.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 " "]);\npatch([10.775 14.22 13.22 12.22 11.22 9.775 10.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.931 0.946 0." "973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');p" "ort_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Slice24" SID "160" Ports [1, 1] Position [190, 359, 215, 371] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outp" "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

" "

Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "LSB of Input" bit0 "3" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,407" block_type "slice" block_version "9.1.01" sg_icon_stat "25,12,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 12 12 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 12 12 0 ]);\npatch([9.775 11.22 12.22 13.22 14.22 12.22 10.775 9.775 ],[" "7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([10.775 12.22 11.22 9.775 10.775 ],[6.11 6.11 7.11 " "7.11 6.11 ],[0.931 0.946 0.973 ]);\npatch([9.775 11.22 12.22 10.775 9.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 " "]);\npatch([10.775 14.22 13.22 12.22 11.22 9.775 10.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.931 0.946 0." "973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');p" "ort_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Slice25" SID "161" Ports [1, 1] Position [190, 384, 215, 396] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outp" "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

" "

Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "LSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,407" block_type "slice" block_version "9.1.01" sg_icon_stat "25,12,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 12 12 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 12 12 0 ]);\npatch([9.775 11.22 12.22 13.22 14.22 12.22 10.775 9.775 ],[" "7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([10.775 12.22 11.22 9.775 10.775 ],[6.11 6.11 7.11 " "7.11 6.11 ],[0.931 0.946 0.973 ]);\npatch([9.775 11.22 12.22 10.775 9.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 " "]);\npatch([10.775 14.22 13.22 12.22 11.22 9.775 10.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.931 0.946 0." "973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');p" "ort_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Slice26" SID "162" Ports [1, 1] Position [190, 414, 215, 426] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outp" "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

" "

Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "LSB of Input" bit0 "2" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,407" block_type "slice" block_version "9.1.01" sg_icon_stat "25,12,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 12 12 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 12 12 0 ]);\npatch([9.775 11.22 12.22 13.22 14.22 12.22 10.775 9.775 ],[" "7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([10.775 12.22 11.22 9.775 10.775 ],[6.11 6.11 7.11 " "7.11 6.11 ],[0.931 0.946 0.973 ]);\npatch([9.775 11.22 12.22 10.775 9.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 " "]);\npatch([10.775 14.22 13.22 12.22 11.22 9.775 10.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.931 0.946 0." "973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');p" "ort_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Slice27" SID "163" Ports [1, 1] Position [190, 429, 215, 441] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outp" "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

" "

Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "LSB of Input" bit0 "3" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,407" block_type "slice" block_version "9.1.01" sg_icon_stat "25,12,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 12 12 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 12 12 0 ]);\npatch([9.775 11.22 12.22 13.22 14.22 12.22 10.775 9.775 ],[" "7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([10.775 12.22 11.22 9.775 10.775 ],[6.11 6.11 7.11 " "7.11 6.11 ],[0.931 0.946 0.973 ]);\npatch([9.775 11.22 12.22 10.775 9.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 " "]);\npatch([10.775 14.22 13.22 12.22 11.22 9.775 10.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.931 0.946 0." "973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');p" "ort_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Slice28" SID "164" Ports [1, 1] Position [190, 329, 215, 341] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outp" "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

" "

Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "LSB of Input" bit0 "1" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,407" block_type "slice" block_version "9.1.01" sg_icon_stat "25,12,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 12 12 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 12 12 0 ]);\npatch([9.775 11.22 12.22 13.22 14.22 12.22 10.775 9.775 ],[" "7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([10.775 12.22 11.22 9.775 10.775 ],[6.11 6.11 7.11 " "7.11 6.11 ],[0.931 0.946 0.973 ]);\npatch([9.775 11.22 12.22 10.775 9.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 " "]);\npatch([10.775 14.22 13.22 12.22 11.22 9.775 10.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.931 0.946 0." "973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');p" "ort_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Slice29" SID "165" Ports [1, 1] Position [190, 399, 215, 411] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outp" "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

" "

Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "LSB of Input" bit0 "1" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,407" block_type "slice" block_version "9.1.01" sg_icon_stat "25,12,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 12 12 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 12 12 0 ]);\npatch([9.775 11.22 12.22 13.22 14.22 12.22 10.775 9.775 ],[" "7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([10.775 12.22 11.22 9.775 10.775 ],[6.11 6.11 7.11 " "7.11 6.11 ],[0.931 0.946 0.973 ]);\npatch([9.775 11.22 12.22 10.775 9.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 " "]);\npatch([10.775 14.22 13.22 12.22 11.22 9.775 10.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.931 0.946 0." "973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');p" "ort_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Slice3" SID "166" Ports [1, 1] Position [190, 99, 215, 111] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outp" "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

" "

Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "LSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,407" block_type "slice" block_version "9.1.01" sg_icon_stat "25,12,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 12 12 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 12 12 0 ]);\npatch([9.775 11.22 12.22 13.22 14.22 12.22 10.775 9.775 ],[" "7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([10.775 12.22 11.22 9.775 10.775 ],[6.11 6.11 7.11 " "7.11 6.11 ],[0.931 0.946 0.973 ]);\npatch([9.775 11.22 12.22 10.775 9.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 " "]);\npatch([10.775 14.22 13.22 12.22 11.22 9.775 10.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.931 0.946 0." "973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');p" "ort_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Slice30" SID "167" Ports [1, 1] Position [190, 454, 215, 466] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outp" "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

" "

Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "LSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,407" block_type "slice" block_version "9.1.01" sg_icon_stat "25,12,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 12 12 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 12 12 0 ]);\npatch([9.775 11.22 12.22 13.22 14.22 12.22 10.775 9.775 ],[" "7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([10.775 12.22 11.22 9.775 10.775 ],[6.11 6.11 7.11 " "7.11 6.11 ],[0.931 0.946 0.973 ]);\npatch([9.775 11.22 12.22 10.775 9.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 " "]);\npatch([10.775 14.22 13.22 12.22 11.22 9.775 10.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.931 0.946 0." "973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');p" "ort_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Slice31" SID "168" Ports [1, 1] Position [190, 484, 215, 496] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outp" "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

" "

Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "LSB of Input" bit0 "2" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,407" block_type "slice" block_version "9.1.01" sg_icon_stat "25,12,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 12 12 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 12 12 0 ]);\npatch([9.775 11.22 12.22 13.22 14.22 12.22 10.775 9.775 ],[" "7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([10.775 12.22 11.22 9.775 10.775 ],[6.11 6.11 7.11 " "7.11 6.11 ],[0.931 0.946 0.973 ]);\npatch([9.775 11.22 12.22 10.775 9.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 " "]);\npatch([10.775 14.22 13.22 12.22 11.22 9.775 10.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.931 0.946 0." "973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');p" "ort_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Slice4" SID "169" Ports [1, 1] Position [190, 129, 215, 141] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outp" "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

" "

Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "LSB of Input" bit0 "2" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,407" block_type "slice" block_version "9.1.01" sg_icon_stat "25,12,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 12 12 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 12 12 0 ]);\npatch([9.775 11.22 12.22 13.22 14.22 12.22 10.775 9.775 ],[" "7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([10.775 12.22 11.22 9.775 10.775 ],[6.11 6.11 7.11 " "7.11 6.11 ],[0.931 0.946 0.973 ]);\npatch([9.775 11.22 12.22 10.775 9.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 " "]);\npatch([10.775 14.22 13.22 12.22 11.22 9.775 10.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.931 0.946 0." "973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');p" "ort_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Slice5" SID "170" Ports [1, 1] Position [190, 144, 215, 156] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outp" "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

" "

Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "LSB of Input" bit0 "3" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,407" block_type "slice" block_version "9.1.01" sg_icon_stat "25,12,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 12 12 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 12 12 0 ]);\npatch([9.775 11.22 12.22 13.22 14.22 12.22 10.775 9.775 ],[" "7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([10.775 12.22 11.22 9.775 10.775 ],[6.11 6.11 7.11 " "7.11 6.11 ],[0.931 0.946 0.973 ]);\npatch([9.775 11.22 12.22 10.775 9.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 " "]);\npatch([10.775 14.22 13.22 12.22 11.22 9.775 10.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.931 0.946 0." "973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');p" "ort_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Slice6" SID "171" Ports [1, 1] Position [190, 44, 215, 56] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outp" "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

" "

Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "LSB of Input" bit0 "1" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,407" block_type "slice" block_version "9.1.01" sg_icon_stat "25,12,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 12 12 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 12 12 0 ]);\npatch([9.775 11.22 12.22 13.22 14.22 12.22 10.775 9.775 ],[" "7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([10.775 12.22 11.22 9.775 10.775 ],[6.11 6.11 7.11 " "7.11 6.11 ],[0.931 0.946 0.973 ]);\npatch([9.775 11.22 12.22 10.775 9.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 " "]);\npatch([10.775 14.22 13.22 12.22 11.22 9.775 10.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.931 0.946 0." "973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');p" "ort_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Slice7" SID "172" Ports [1, 1] Position [190, 114, 215, 126] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outp" "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

" "

Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "LSB of Input" bit0 "1" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,407" block_type "slice" block_version "9.1.01" sg_icon_stat "25,12,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 12 12 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 12 12 0 ]);\npatch([9.775 11.22 12.22 13.22 14.22 12.22 10.775 9.775 ],[" "7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([10.775 12.22 11.22 9.775 10.775 ],[6.11 6.11 7.11 " "7.11 6.11 ],[0.931 0.946 0.973 ]);\npatch([9.775 11.22 12.22 10.775 9.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 " "]);\npatch([10.775 14.22 13.22 12.22 11.22 9.775 10.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.931 0.946 0." "973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');p" "ort_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Slice8" SID "173" Ports [1, 1] Position [190, 174, 215, 186] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outp" "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

" "

Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "LSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,407" block_type "slice" block_version "9.1.01" sg_icon_stat "25,12,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 12 12 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 12 12 0 ]);\npatch([9.775 11.22 12.22 13.22 14.22 12.22 10.775 9.775 ],[" "7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([10.775 12.22 11.22 9.775 10.775 ],[6.11 6.11 7.11 " "7.11 6.11 ],[0.931 0.946 0.973 ]);\npatch([9.775 11.22 12.22 10.775 9.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 " "]);\npatch([10.775 14.22 13.22 12.22 11.22 9.775 10.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.931 0.946 0." "973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');p" "ort_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Slice9" SID "174" Ports [1, 1] Position [190, 204, 215, 216] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outp" "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

" "

Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "LSB of Input" bit0 "2" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,407" block_type "slice" block_version "9.1.01" sg_icon_stat "25,12,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 12 12 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 12 12 0 ]);\npatch([9.775 11.22 12.22 13.22 14.22 12.22 10.775 9.775 ],[" "7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([10.775 12.22 11.22 9.775 10.775 ],[6.11 6.11 7.11 " "7.11 6.11 ],[0.931 0.946 0.973 ]);\npatch([9.775 11.22 12.22 10.775 9.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 " "]);\npatch([10.775 14.22 13.22 12.22 11.22 9.775 10.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.931 0.946 0." "973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');p" "ort_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Line { SrcBlock "32b" SrcPort 1 Points [15, 0] Branch { Points [0, 70] Branch { Points [0, 75] Branch { Points [0, 70] Branch { Points [0, 70] Branch { Points [0, 70] Branch { Points [0, 70] Branch { Points [0, 70] DstBlock "4LSB+28" DstPort 1 } Branch { DstBlock "4LSB+24" DstPort 1 } } Branch { DstBlock "4LSB+20" DstPort 1 } } Branch { DstBlock "4LSB+16" DstPort 1 } } Branch { DstBlock "4LSB+12" DstPort 1 } } Branch { DstBlock "4LSB+8" DstPort 1 } } Branch { DstBlock "4LSB+4" DstPort 1 } } Branch { DstBlock "4LSB" DstPort 1 } } Line { SrcBlock "4LSB" SrcPort 1 Points [15, 0] Branch { DstBlock "Slice" DstPort 1 } Branch { Points [0, 15] Branch { DstBlock "Slice6" DstPort 1 } Branch { Points [0, 15] Branch { Points [0, 15] DstBlock "Slice2" DstPort 1 } Branch { DstBlock "Slice1" DstPort 1 } } } } Line { SrcBlock "4LSB+4" SrcPort 1 Points [15, 0] Branch { Points [0, 15] Branch { Points [0, 15] Branch { DstBlock "Slice4" DstPort 1 } Branch { Points [0, 15] DstBlock "Slice5" DstPort 1 } } Branch { DstBlock "Slice7" DstPort 1 } } Branch { DstBlock "Slice3" DstPort 1 } } Line { SrcBlock "Slice" SrcPort 1 DstBlock "Goto" DstPort 1 } Line { SrcBlock "Slice6" SrcPort 1 DstBlock "Goto1" DstPort 1 } Line { SrcBlock "Slice1" SrcPort 1 DstBlock "Goto2" DstPort 1 } Line { SrcBlock "Slice2" SrcPort 1 DstBlock "Goto3" DstPort 1 } Line { SrcBlock "Slice3" SrcPort 1 DstBlock "Goto4" DstPort 1 } Line { SrcBlock "Slice7" SrcPort 1 DstBlock "Goto5" DstPort 1 } Line { SrcBlock "Slice4" SrcPort 1 DstBlock "Goto6" DstPort 1 } Line { SrcBlock "Slice5" SrcPort 1 DstBlock "Goto7" DstPort 1 } Line { SrcBlock "4LSB+8" SrcPort 1 Points [15, 0] Branch { Points [0, 15] Branch { Points [0, 15] Branch { DstBlock "Slice9" DstPort 1 } Branch { Points [0, 15] DstBlock "Slice10" DstPort 1 } } Branch { DstBlock "Slice14" DstPort 1 } } Branch { DstBlock "Slice8" DstPort 1 } } Line { SrcBlock "4LSB+12" SrcPort 1 Points [15, 0] Branch { DstBlock "Slice11" DstPort 1 } Branch { Points [0, 15] Branch { DstBlock "Slice15" DstPort 1 } Branch { Points [0, 15] Branch { Points [0, 15] DstBlock "Slice13" DstPort 1 } Branch { DstBlock "Slice12" DstPort 1 } } } } Line { SrcBlock "Slice8" SrcPort 1 DstBlock "Goto8" DstPort 1 } Line { SrcBlock "Slice14" SrcPort 1 DstBlock "Goto9" DstPort 1 } Line { SrcBlock "Slice9" SrcPort 1 DstBlock "Goto10" DstPort 1 } Line { SrcBlock "Slice10" SrcPort 1 DstBlock "Goto11" DstPort 1 } Line { SrcBlock "Slice11" SrcPort 1 DstBlock "Goto14" DstPort 1 } Line { SrcBlock "Slice15" SrcPort 1 DstBlock "Goto15" DstPort 1 } Line { SrcBlock "Slice12" SrcPort 1 DstBlock "Goto12" DstPort 1 } Line { SrcBlock "Slice13" SrcPort 1 DstBlock "Goto13" DstPort 1 } Line { SrcBlock "4LSB+16" SrcPort 1 Points [15, 0] Branch { Points [0, 15] Branch { Points [0, 15] Branch { DstBlock "Slice17" DstPort 1 } Branch { Points [0, 15] DstBlock "Slice24" DstPort 1 } } Branch { DstBlock "Slice28" DstPort 1 } } Branch { DstBlock "Slice16" DstPort 1 } } Line { SrcBlock "4LSB+20" SrcPort 1 Points [15, 0] Branch { DstBlock "Slice25" DstPort 1 } Branch { Points [0, 15] Branch { DstBlock "Slice29" DstPort 1 } Branch { Points [0, 15] Branch { Points [0, 15] DstBlock "Slice27" DstPort 1 } Branch { DstBlock "Slice26" DstPort 1 } } } } Line { SrcBlock "Slice16" SrcPort 1 DstBlock "Goto16" DstPort 1 } Line { SrcBlock "Slice28" SrcPort 1 DstBlock "Goto17" DstPort 1 } Line { SrcBlock "Slice17" SrcPort 1 DstBlock "Goto24" DstPort 1 } Line { SrcBlock "Slice24" SrcPort 1 DstBlock "Goto25" DstPort 1 } Line { SrcBlock "Slice25" SrcPort 1 DstBlock "Goto26" DstPort 1 } Line { SrcBlock "Slice29" SrcPort 1 DstBlock "Goto27" DstPort 1 } Line { SrcBlock "Slice26" SrcPort 1 DstBlock "Goto28" DstPort 1 } Line { SrcBlock "Slice27" SrcPort 1 DstBlock "Goto29" DstPort 1 } Line { SrcBlock "4LSB+24" SrcPort 1 Points [15, 0] Branch { DstBlock "Slice30" DstPort 1 } Branch { Points [0, 15] Branch { DstBlock "Slice22" DstPort 1 } Branch { Points [0, 15] Branch { Points [0, 15] DstBlock "Slice18" DstPort 1 } Branch { DstBlock "Slice31" DstPort 1 } } } } Line { SrcBlock "4LSB+28" SrcPort 1 Points [15, 0] Branch { Points [0, 15] Branch { Points [0, 15] Branch { DstBlock "Slice20" DstPort 1 } Branch { Points [0, 15] DstBlock "Slice21" DstPort 1 } } Branch { DstBlock "Slice23" DstPort 1 } } Branch { DstBlock "Slice19" DstPort 1 } } Line { SrcBlock "Slice30" SrcPort 1 DstBlock "Goto30" DstPort 1 } Line { SrcBlock "Slice22" SrcPort 1 DstBlock "Goto31" DstPort 1 } Line { SrcBlock "Slice31" SrcPort 1 DstBlock "Goto18" DstPort 1 } Line { SrcBlock "Slice18" SrcPort 1 DstBlock "Goto19" DstPort 1 } Line { SrcBlock "Slice19" SrcPort 1 DstBlock "Goto22" DstPort 1 } Line { SrcBlock "Slice23" SrcPort 1 DstBlock "Goto23" DstPort 1 } Line { SrcBlock "Slice20" SrcPort 1 DstBlock "Goto20" DstPort 1 } Line { SrcBlock "Slice21" SrcPort 1 DstBlock "Goto21" DstPort 1 } } } Block { BlockType Reference Name "To Register4" SID "175" Ports [2, 1] Position [615, 571, 670, 624] ShowName off AttributesFormatString "To Register\\n<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/To Register" SourceType "Xilinx Shared Memory Based To Register Block" infoedit "Register block that writes data to a shared memory register. Delay of one sample period." shared_memory_name "'timer_status'" init "0" ownership "Locally owned and initialized" explicit_data_type on gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "290,195,381,270" block_type "toreg" block_version "9.1.01" sg_icon_stat "55,53,2,1,white,blue,0,10ab453e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 53 53 0 ],[0.77 0.82 0.91" " ]);\nplot([0 55 55 0 0 ],[0 0 53 53 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ],[33.77 33.7" "7 40.77 33.77 40.77 40.77 40.77 33.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[26.77 26.77 33.77 33" ".77 26.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[19.77 19.77 26.77 26.77 19.77 ],[1 1" " 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[12.77 12.77 19.77 12.77 19.77 19.77 12.77 ],[0.931 0" ".946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');" "port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dou" "t');\nfprintf('','COMMENT: end icon text');" } Line { Labels [0, 0] SrcBlock "From Register8" SrcPort 1 DstBlock "Slices & Gotos" DstPort 1 } Line { SrcBlock "From Register9" SrcPort 1 DstBlock "Goto" DstPort 1 } Line { SrcBlock "From Register5" SrcPort 1 DstBlock "Goto7" DstPort 1 } Line { SrcBlock "From Register6" SrcPort 1 DstBlock "Goto6" DstPort 1 } Line { SrcBlock "From Register4" SrcPort 1 DstBlock "Goto5" DstPort 1 } Line { SrcBlock "From Register7" SrcPort 1 DstBlock "Goto4" DstPort 1 } Line { SrcBlock "From Register2" SrcPort 1 DstBlock "Goto3" DstPort 1 } Line { SrcBlock "From Register3" SrcPort 1 DstBlock "Goto2" DstPort 1 } Line { SrcBlock "From Register1" SrcPort 1 DstBlock "Goto1" DstPort 1 } Line { SrcBlock "From Register11" SrcPort 1 Points [55, 0] Branch { DstBlock "16MSB" DstPort 1 } Branch { Points [0, -15] DstBlock "16LSB" DstPort 1 } } Line { SrcBlock "16LSB" SrcPort 1 DstBlock "Goto8" DstPort 1 } Line { SrcBlock "16MSB" SrcPort 1 DstBlock "Goto9" DstPort 1 } Line { SrcBlock "16LSB1" SrcPort 1 DstBlock "Goto10" DstPort 1 } Line { SrcBlock "16MSB1" SrcPort 1 DstBlock "Goto11" DstPort 1 } Line { SrcBlock "16LSB2" SrcPort 1 DstBlock "Goto12" DstPort 1 } Line { SrcBlock "16MSB2" SrcPort 1 DstBlock "Goto13" DstPort 1 } Line { SrcBlock "16LSB3" SrcPort 1 DstBlock "Goto14" DstPort 1 } Line { SrcBlock "16MSB3" SrcPort 1 DstBlock "Goto15" DstPort 1 } Line { SrcBlock "From Register12" SrcPort 1 Points [55, 0] Branch { Points [0, -15] DstBlock "16LSB1" DstPort 1 } Branch { DstBlock "16MSB1" DstPort 1 } } Line { SrcBlock "From Register13" SrcPort 1 Points [60, 0] Branch { Points [0, -15] DstBlock "16LSB2" DstPort 1 } Branch { DstBlock "16MSB2" DstPort 1 } } Line { SrcBlock "From Register14" SrcPort 1 Points [60, 0] Branch { Points [0, -15] DstBlock "16LSB3" DstPort 1 } Branch { DstBlock "16MSB3" DstPort 1 } } Line { SrcBlock "Constant5" SrcPort 1 DstBlock "To Register4" DstPort 2 } Line { SrcBlock "From40" SrcPort 1 DstBlock "To Register4" DstPort 1 } Annotation { Name "Slot Count Registers\n(1 per timer)" Position [147, 210] } Annotation { Name "Timer Control Register\n(1 shared by all timers)" Position [397, 105] } Annotation { Name "Timer Slot Time Register\n(2 timers share each register)" Position [592, 210] } Annotation { Name "Timer Status Register\n(1 shared by all timers)" Position [597, 545] } } } Block { BlockType SubSystem Name "Status\nOutputs" SID "176" Ports [8] Position [1215, 257, 1250, 343] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "Status\nOutputs" Location [1449, 133, 1639, 374] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "T0" SID "177" Position [265, 313, 295, 327] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "T1" SID "178" Position [265, 288, 295, 302] Port "2" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "T2" SID "179" Position [265, 263, 295, 277] Port "3" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "T3" SID "180" Position [265, 238, 295, 252] Port "4" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "T4" SID "181" Position [265, 213, 295, 227] Port "5" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "T5" SID "182" Position [265, 188, 295, 202] Port "6" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "T6" SID "183" Position [265, 163, 295, 177] Port "7" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "T7" SID "184" Position [265, 138, 295, 152] Port "8" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Concat13" SID "185" Ports [8, 1] Position [390, 140, 420, 325] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point at ze" "ro." num_inputs "8" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,336,165" block_type "concat" block_version "9.1.01" sg_icon_stat "30,185,8,1,white,blue,0,6fe74153,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 185 185 0 ],[0.77 0.82 0." "91 ]);\nplot([0 30 30 0 0 ],[0 0 185 185 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[96.44 96.44 10" "0.44 96.44 100.44 100.44 100.44 96.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[92.44 92.44 96.44 96.44 92." "44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[88.44 88.44 92.44 92.44 88.44 ],[1 1 1 ]);\npatch([" "10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[84.44 84.44 88.44 84.44 88.44 88.44 84.44 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" "hi');\n\n\n\n\n\n\ncolor('black');port_label('input',8,'lo');\n\ncolor('black');disp('\\fontsize{20}\\}','texmode'," "'on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Goto Name "Goto" SID "186" Position [535, 226, 670, 244] ShowName off GotoTag "timers_status" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "LSB+1" SID "187" Ports [1, 1] Position [415, 409, 440, 421] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type " "is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardware " "notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "LSB of Input" bit0 "1" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,407" block_type "slice" block_version "9.1.01" sg_icon_stat "25,12,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 12 12 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 12 12 0 ]);\npatch([9.775 11.22 12.22 13.22 14.22 12.22 10.775 9.775 ],[7.11 7.11 8." "11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([10.775 12.22 11.22 9.775 10.775 ],[6.11 6.11 7.11 7.11 6.11 ],[0.9" "31 0.946 0.973 ]);\npatch([9.775 11.22 12.22 10.775 9.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch([10.775 1" "4.22 13.22 12.22 11.22 9.775 10.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.931 0.946 0.973 ]);\nfprintf('','COM" "MENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'[a:b]'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "LSB+2" SID "188" Ports [1, 1] Position [415, 379, 440, 391] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type " "is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardware " "notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "LSB of Input" bit0 "1" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,407" block_type "slice" block_version "9.1.01" sg_icon_stat "25,12,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 12 12 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 12 12 0 ]);\npatch([9.775 11.22 12.22 13.22 14.22 12.22 10.775 9.775 ],[7.11 7.11 8." "11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([10.775 12.22 11.22 9.775 10.775 ],[6.11 6.11 7.11 7.11 6.11 ],[0.9" "31 0.946 0.973 ]);\npatch([9.775 11.22 12.22 10.775 9.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch([10.775 1" "4.22 13.22 12.22 11.22 9.775 10.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.931 0.946 0.973 ]);\nfprintf('','COM" "MENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'[a:b]'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "LSB+3" SID "189" Ports [1, 1] Position [415, 439, 440, 451] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type " "is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardware " "notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "LSB of Input" bit0 "1" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,407" block_type "slice" block_version "9.1.01" sg_icon_stat "25,12,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 12 12 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 12 12 0 ]);\npatch([9.775 11.22 12.22 13.22 14.22 12.22 10.775 9.775 ],[7.11 7.11 8." "11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([10.775 12.22 11.22 9.775 10.775 ],[6.11 6.11 7.11 7.11 6.11 ],[0.9" "31 0.946 0.973 ]);\npatch([9.775 11.22 12.22 10.775 9.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch([10.775 1" "4.22 13.22 12.22 11.22 9.775 10.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.931 0.946 0.973 ]);\nfprintf('','COM" "MENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'[a:b]'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "LSB+4" SID "190" Ports [1, 1] Position [415, 499, 440, 511] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type " "is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardware " "notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "LSB of Input" bit0 "1" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,407" block_type "slice" block_version "9.1.01" sg_icon_stat "25,12,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 12 12 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 12 12 0 ]);\npatch([9.775 11.22 12.22 13.22 14.22 12.22 10.775 9.775 ],[7.11 7.11 8." "11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([10.775 12.22 11.22 9.775 10.775 ],[6.11 6.11 7.11 7.11 6.11 ],[0.9" "31 0.946 0.973 ]);\npatch([9.775 11.22 12.22 10.775 9.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch([10.775 1" "4.22 13.22 12.22 11.22 9.775 10.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.931 0.946 0.973 ]);\nfprintf('','COM" "MENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'[a:b]'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "LSB+5" SID "191" Ports [1, 1] Position [415, 469, 440, 481] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type " "is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardware " "notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "LSB of Input" bit0 "1" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,407" block_type "slice" block_version "9.1.01" sg_icon_stat "25,12,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 12 12 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 12 12 0 ]);\npatch([9.775 11.22 12.22 13.22 14.22 12.22 10.775 9.775 ],[7.11 7.11 8." "11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([10.775 12.22 11.22 9.775 10.775 ],[6.11 6.11 7.11 7.11 6.11 ],[0.9" "31 0.946 0.973 ]);\npatch([9.775 11.22 12.22 10.775 9.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch([10.775 1" "4.22 13.22 12.22 11.22 9.775 10.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.931 0.946 0.973 ]);\nfprintf('','COM" "MENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'[a:b]'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "LSB+6" SID "192" Ports [1, 1] Position [415, 529, 440, 541] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type " "is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardware " "notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "LSB of Input" bit0 "1" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,407" block_type "slice" block_version "9.1.01" sg_icon_stat "25,12,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 12 12 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 12 12 0 ]);\npatch([9.775 11.22 12.22 13.22 14.22 12.22 10.775 9.775 ],[7.11 7.11 8." "11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([10.775 12.22 11.22 9.775 10.775 ],[6.11 6.11 7.11 7.11 6.11 ],[0.9" "31 0.946 0.973 ]);\npatch([9.775 11.22 12.22 10.775 9.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch([10.775 1" "4.22 13.22 12.22 11.22 9.775 10.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.931 0.946 0.973 ]);\nfprintf('','COM" "MENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'[a:b]'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "LSB+7" SID "193" Ports [1, 1] Position [415, 559, 440, 571] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type " "is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardware " "notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "LSB of Input" bit0 "1" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,407" block_type "slice" block_version "9.1.01" sg_icon_stat "25,12,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 12 12 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 12 12 0 ]);\npatch([9.775 11.22 12.22 13.22 14.22 12.22 10.775 9.775 ],[7.11 7.11 8." "11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([10.775 12.22 11.22 9.775 10.775 ],[6.11 6.11 7.11 7.11 6.11 ],[0.9" "31 0.946 0.973 ]);\npatch([9.775 11.22 12.22 10.775 9.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch([10.775 1" "4.22 13.22 12.22 11.22 9.775 10.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.931 0.946 0.973 ]);\nfprintf('','COM" "MENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'[a:b]'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "LSB+8" SID "194" Ports [1, 1] Position [415, 589, 440, 601] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type " "is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardware " "notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "LSB of Input" bit0 "1" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,407" block_type "slice" block_version "9.1.01" sg_icon_stat "25,12,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 12 12 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 12 12 0 ]);\npatch([9.775 11.22 12.22 13.22 14.22 12.22 10.775 9.775 ],[7.11 7.11 8." "11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([10.775 12.22 11.22 9.775 10.775 ],[6.11 6.11 7.11 7.11 6.11 ],[0.9" "31 0.946 0.973 ]);\npatch([9.775 11.22 12.22 10.775 9.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch([10.775 1" "4.22 13.22 12.22 11.22 9.775 10.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.931 0.946 0.973 ]);\nfprintf('','COM" "MENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'[a:b]'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical" SID "195" Ports [8, 1] Position [500, 629, 535, 711] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "8" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,261" block_type "logical" block_version "10.1.3" sg_icon_stat "35,82,8,1,white,blue,0,8c57207a,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 82 82 0 ],[0.77 0.82 0.91" " ]);\nplot([0 35 35 0 0 ],[0 0 82 82 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[46.55 46.55 51.55" " 46.55 51.55 51.55 51.55 46.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[41.55 41.55 46.55 46.55 41.55 " "],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[36.55 36.55 41.55 41.55 36.55 ],[1 1 1 ]);\npatch(" "[10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[31.55 31.55 36.55 31.55 36.55 36.55 31.55 ],[0.931 0.946 0.973 ]);\nfpr" "intf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n\n\n\n\n\n\ncolor('black');d" "isp('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "TIMEREXPIRE" SID "196" Ports [1, 1] Position [575, 660, 635, 680] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, double, o" "r fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarded, depen" "ding on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" UseAsDAC off DACChannel "'1'" has_advanced_control "0" sggui_pos "20,20,356,352" block_type "gatewayout" block_version "8.2" sg_icon_stat "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" " ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "timer0_active" SID "197" Ports [1, 1] Position [515, 378, 575, 392] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, double, o" "r fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarded, depen" "ding on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" UseAsDAC off DACChannel "'1'" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "9.1.01" sg_icon_stat "60,14,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 14 14 0 ],[0.95 0.93 0.65" " ]);\nplot([0 60 60 0 0 ],[0 0 14 14 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[9.22 9.22 11." "22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[7.22 7.22 9.22 9.22 7.22 ],[0." "985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([27.55 34" ".44 32.44 30.44 28.44 25.55 27.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.985 0.979 0.895 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ');\ncolor" "('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "timer1_active" SID "198" Ports [1, 1] Position [515, 408, 575, 422] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, double, o" "r fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarded, depen" "ding on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" UseAsDAC off DACChannel "'1'" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "9.1.01" sg_icon_stat "60,14,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 14 14 0 ],[0.95 0.93 0.65" " ]);\nplot([0 60 60 0 0 ],[0 0 14 14 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[9.22 9.22 11." "22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[7.22 7.22 9.22 9.22 7.22 ],[0." "985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([27.55 34" ".44 32.44 30.44 28.44 25.55 27.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.985 0.979 0.895 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ');\ncolor" "('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "timer2_active" SID "199" Ports [1, 1] Position [515, 438, 575, 452] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, double, o" "r fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarded, depen" "ding on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" UseAsDAC off DACChannel "'1'" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "9.1.01" sg_icon_stat "60,14,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 14 14 0 ],[0.95 0.93 0.65" " ]);\nplot([0 60 60 0 0 ],[0 0 14 14 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[9.22 9.22 11." "22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[7.22 7.22 9.22 9.22 7.22 ],[0." "985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([27.55 34" ".44 32.44 30.44 28.44 25.55 27.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.985 0.979 0.895 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ');\ncolor" "('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "timer3_active" SID "200" Ports [1, 1] Position [515, 468, 575, 482] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, double, o" "r fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarded, depen" "ding on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" UseAsDAC off DACChannel "'1'" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "9.1.01" sg_icon_stat "60,14,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 14 14 0 ],[0.95 0.93 0.65" " ]);\nplot([0 60 60 0 0 ],[0 0 14 14 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[9.22 9.22 11." "22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[7.22 7.22 9.22 9.22 7.22 ],[0." "985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([27.55 34" ".44 32.44 30.44 28.44 25.55 27.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.985 0.979 0.895 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ');\ncolor" "('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "timer4_active" SID "201" Ports [1, 1] Position [515, 498, 575, 512] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, double, o" "r fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarded, depen" "ding on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" UseAsDAC off DACChannel "'1'" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "9.1.01" sg_icon_stat "60,14,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 14 14 0 ],[0.95 0.93 0.65" " ]);\nplot([0 60 60 0 0 ],[0 0 14 14 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[9.22 9.22 11." "22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[7.22 7.22 9.22 9.22 7.22 ],[0." "985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([27.55 34" ".44 32.44 30.44 28.44 25.55 27.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.985 0.979 0.895 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ');\ncolor" "('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "timer5_active" SID "202" Ports [1, 1] Position [515, 528, 575, 542] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, double, o" "r fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarded, depen" "ding on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" UseAsDAC off DACChannel "'1'" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "9.1.01" sg_icon_stat "60,14,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 14 14 0 ],[0.95 0.93 0.65" " ]);\nplot([0 60 60 0 0 ],[0 0 14 14 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[9.22 9.22 11." "22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[7.22 7.22 9.22 9.22 7.22 ],[0." "985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([27.55 34" ".44 32.44 30.44 28.44 25.55 27.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.985 0.979 0.895 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ');\ncolor" "('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "timer6_active" SID "203" Ports [1, 1] Position [515, 558, 575, 572] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, double, o" "r fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarded, depen" "ding on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" UseAsDAC off DACChannel "'1'" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "9.1.01" sg_icon_stat "60,14,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 14 14 0 ],[0.95 0.93 0.65" " ]);\nplot([0 60 60 0 0 ],[0 0 14 14 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[9.22 9.22 11." "22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[7.22 7.22 9.22 9.22 7.22 ],[0." "985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([27.55 34" ".44 32.44 30.44 28.44 25.55 27.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.985 0.979 0.895 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ');\ncolor" "('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "timer7_active" SID "204" Ports [1, 1] Position [515, 588, 575, 602] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, double, o" "r fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarded, depen" "ding on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" UseAsDAC off DACChannel "'1'" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "9.1.01" sg_icon_stat "60,14,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 14 14 0 ],[0.95 0.93 0.65" " ]);\nplot([0 60 60 0 0 ],[0 0 14 14 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[9.22 9.22 11." "22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[7.22 7.22 9.22 9.22 7.22 ],[0." "985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([27.55 34" ".44 32.44 30.44 28.44 25.55 27.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.985 0.979 0.895 ]);\nfprintf('','COMME" "NT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ');\ncolor" "('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end icon text');" } Line { SrcBlock "T7" SrcPort 1 Points [35, 0] Branch { DstBlock "Concat13" DstPort 1 } Branch { Points [0, 450] DstBlock "LSB+8" DstPort 1 } } Line { SrcBlock "T6" SrcPort 1 Points [40, 0] Branch { DstBlock "Concat13" DstPort 2 } Branch { Points [0, 395] DstBlock "LSB+7" DstPort 1 } } Line { SrcBlock "T5" SrcPort 1 Points [45, 0] Branch { DstBlock "Concat13" DstPort 3 } Branch { Points [0, 340] DstBlock "LSB+6" DstPort 1 } } Line { SrcBlock "T4" SrcPort 1 Points [50, 0] Branch { DstBlock "Concat13" DstPort 4 } Branch { Points [0, 285] DstBlock "LSB+4" DstPort 1 } } Line { SrcBlock "T3" SrcPort 1 Points [55, 0] Branch { DstBlock "Concat13" DstPort 5 } Branch { Points [0, 230] DstBlock "LSB+5" DstPort 1 } } Line { SrcBlock "T2" SrcPort 1 Points [60, 0] Branch { DstBlock "Concat13" DstPort 6 } Branch { Points [0, 175] DstBlock "LSB+3" DstPort 1 } } Line { SrcBlock "T1" SrcPort 1 Points [65, 0] Branch { DstBlock "Concat13" DstPort 7 } Branch { Points [0, 120] DstBlock "LSB+1" DstPort 1 } } Line { SrcBlock "T0" SrcPort 1 Points [70, 0] Branch { DstBlock "Concat13" DstPort 8 } Branch { Points [0, 65] DstBlock "LSB+2" DstPort 1 } } Line { SrcBlock "LSB+2" SrcPort 1 Points [40, 0] Branch { DstBlock "timer0_active" DstPort 1 } Branch { DstBlock "Logical" DstPort 1 } } Line { SrcBlock "LSB+1" SrcPort 1 Points [35, 0] Branch { DstBlock "timer1_active" DstPort 1 } Branch { Points [0, 230] DstBlock "Logical" DstPort 2 } } Line { SrcBlock "LSB+3" SrcPort 1 Points [30, 0] Branch { DstBlock "timer2_active" DstPort 1 } Branch { Points [0, 210] DstBlock "Logical" DstPort 3 } } Line { SrcBlock "LSB+5" SrcPort 1 Points [25, 0] Branch { DstBlock "timer3_active" DstPort 1 } Branch { Points [0, 190] DstBlock "Logical" DstPort 4 } } Line { SrcBlock "LSB+4" SrcPort 1 Points [20, 0] Branch { DstBlock "timer4_active" DstPort 1 } Branch { Points [0, 170] DstBlock "Logical" DstPort 5 } } Line { SrcBlock "LSB+6" SrcPort 1 Points [15, 0] Branch { DstBlock "timer5_active" DstPort 1 } Branch { Points [0, 150] DstBlock "Logical" DstPort 6 } } Line { SrcBlock "LSB+7" SrcPort 1 Points [10, 0] Branch { DstBlock "timer6_active" DstPort 1 } Branch { Points [0, 130] DstBlock "Logical" DstPort 7 } } Line { SrcBlock "LSB+8" SrcPort 1 Points [5, 0] Branch { DstBlock "timer7_active" DstPort 1 } Branch { Points [0, 110] DstBlock "Logical" DstPort 8 } } Line { SrcBlock "Logical" SrcPort 1 DstBlock "TIMEREXPIRE" DstPort 1 } Line { SrcBlock "Concat13" SrcPort 1 DstBlock "Goto" DstPort 1 } } } Block { BlockType SubSystem Name "Timer 0" SID "205" Ports [7, 4] Position [335, 80, 440, 200] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "Timer 0" Location [202, 70, 1438, 850] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "start" SID "206" Position [310, 283, 340, 297] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "pause" SID "207" Position [310, 323, 340, 337] Port "2" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "mode" SID "208" Position [255, 648, 285, 662] NamePlacement "alternate" Port "3" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "done_reset" SID "209" Position [1175, 283, 1205, 297] Port "4" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "slotCount" SID "210" Position [980, 238, 1010, 252] NamePlacement "alternate" Port "5" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "slotTime" SID "211" Position [930, 658, 960, 672] Port "6" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "Medium Idle" SID "212" Position [250, 698, 280, 712] Port "7" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "AddSub" SID "213" Ports [2, 1] Position [1210, 339, 1255, 386] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Subtraction" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Unsigned" n_bits "32" bin_pt "0" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL off hw_selection "Fabric" pipelined off xl_use_area off xl_area "[16 0 0 32 0 0 0]" use_rpm "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" block_version "8.2" sg_icon_stat "45,47,2,1,white,blue,0,32e1f85f,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 47 47 0 ],[0.77 0.82 0.91" " ]);\nplot([0 45 45 0 0 ],[0 0 47 47 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[29.66 29.66 35." "66 29.66 35.66 35.66 35.66 29.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[23.66 23.66 29.66 29.66 23.66" " ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[17.66 17.66 23.66 23.66 17.66 ],[1 1 1 ]);\npatch(" "[14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[11.66 11.66 17.66 11.66 17.66 17.66 11.66 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'" ",1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bf{a - b}','texmode','" "on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant" SID "214" Ports [0, 1] Position [940, 454, 970, 466] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "50,50,400,346" block_type "constant" block_version "10.1.2" sg_icon_stat "30,12,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 12 12 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 12 12 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ],[7.11 7.11 " "8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[6.11 6.11 7.11 7.11 6.11 ],[" "0.931 0.946 0.973 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch([13." "775 17.22 16.22 15.22 14.22 12.775 13.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.931 0.946 0.973 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'0'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant1" SID "215" Ports [0, 1] Position [255, 672, 290, 688] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "8.2" sg_icon_stat "35,16,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 16 16 0 ],[0.77 0.82 0.91" " ]);\nplot([0 35 35 0 0 ],[0 0 16 16 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[10.22 10.22 1" "2.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[8.22 8.22 10.22 10.22 8.22" " ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatch([14" ".55 21.44 19.44 17.44 15.44 12.55 14.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprintf(''," "'COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Constant Name "Constant2" SID "216" Position [260, 261, 275, 279] ShowName off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Constant Name "Constant4" SID "217" Position [315, 576, 330, 594] ShowName off Value "0" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Convert1" SID "218" Ports [1, 1] Position [380, 670, 415, 690] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "16" bin_pt "14" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,461,375" block_type "convert" block_version "8.2" sg_icon_stat "35,20,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.91" " ]);\nplot([0 35 35 0 0 ],[0 0 20 20 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output'," "1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Counter" SID "219" Ports [2, 1] Position [905, 224, 965, 326] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited counter is" " implemented by combining a counter with a comparator." cnt_type "Free Running" cnt_to "Inf" operation "Up" start_count "0" cnt_by_val "1" arith_type "Unsigned" n_bits "32" bin_pt "0" load_pin off rst on en on explicit_period "on" period "1" dbl_ovrd off use_behavioral_HDL off implementation "Fabric" xl_use_area off xl_area "[17 32 0 32 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,356,630" block_type "counter" block_version "8.2" sg_icon_stat "60,102,2,1,white,blue,0,ae3608d6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 102 102 0 ],[0.77 0.82 0." "91 ]);\nplot([0 60 60 0 0 ],[0 0 102 102 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[59.88 59.88 " "67.88 59.88 67.88 67.88 67.88 59.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[51.88 51.88 59.88 59.88 51.8" "8 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[43.88 43.88 51.88 51.88 43.88 ],[1 1 1 ]);\npatch(" "[20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[35.88 35.88 43.88 35.88 43.88 43.88 35.88 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'rst');\ncolor('black');port_label('input',2,'en');\n\ncolor('black');disp('{\\fontsize{14}\\bf++}','texmode','on'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Counter1" SID "220" Ports [2, 1] Position [835, 644, 895, 746] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited counter is" " implemented by combining a counter with a comparator." cnt_type "Free Running" cnt_to "Inf" operation "Up" start_count "0" cnt_by_val "1" arith_type "Unsigned" n_bits "16" bin_pt "0" load_pin off rst on en on explicit_period "on" period "1" dbl_ovrd off use_behavioral_HDL off implementation "Fabric" xl_use_area off xl_area "[17 32 0 32 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,356,630" block_type "counter" block_version "8.2" sg_icon_stat "60,102,2,1,white,blue,0,ae3608d6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 102 102 0 ],[0.77 0.82 0." "91 ]);\nplot([0 60 60 0 0 ],[0 0 102 102 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[59.88 59.88 " "67.88 59.88 67.88 67.88 67.88 59.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[51.88 51.88 59.88 59.88 51.8" "8 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[43.88 43.88 51.88 51.88 43.88 ],[1 1 1 ]);\npatch(" "[20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[35.88 35.88 43.88 35.88 43.88 43.88 35.88 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'rst');\ncolor('black');port_label('input',2,'en');\n\ncolor('black');disp('{\\fontsize{14}\\bf++}','texmode','on'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay" SID "221" Ports [1, 1] Position [925, 331, 950, 359] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "10.1.3" sg_icon_stat "25,28,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 28 28 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 28 28 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 17.33 20" ".33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33 17.33 14.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-1}','t" "exmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out" SID "870" Ports [1, 1] Position [1465, 314, 1495, 326] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" UseAsDAC off DACChannel "'1'" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "30,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.88" " ]);\nplot([0 30 30 0 0 ],[0 0 12 12 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ],[7.11 7.11 " "8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[6.11 6.11 7.11 7.11 6.11 ],[" "0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch([13." "775 17.22 16.22 15.22 14.22 12.775 13.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ')" ";\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" } Block { BlockType Reference Name "Gateway Out1" SID "871" Ports [1, 1] Position [1465, 349, 1495, 361] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" UseAsDAC off DACChannel "'1'" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "30,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.88" " ]);\nplot([0 30 30 0 0 ],[0 0 12 12 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ],[7.11 7.11 " "8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[6.11 6.11 7.11 7.11 6.11 ],[" "0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch([13." "775 17.22 16.22 15.22 14.22 12.775 13.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ')" ";\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" } Block { BlockType Reference Name "Gateway Out2" SID "872" Ports [1, 1] Position [1465, 384, 1495, 396] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" UseAsDAC off DACChannel "'1'" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "30,12,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 12 12 0 ],[0.88 0.88 0.88" " ]);\nplot([0 30 30 0 0 ],[0 0 12 12 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ],[7.11 7.11 " "8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[6.11 6.11 7.11 7.11 6.11 ],[" "0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch([13." "775 17.22 16.22 15.22 14.22 12.775 13.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.964 0.964 0.964 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ')" ";\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" } Block { BlockType Reference Name "Inverter" SID "222" Ports [1, 1] Position [1080, 476, 1125, 494] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "10.1.2" sg_icon_stat "45,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.91" " ]);\nplot([0 45 45 0 0 ],[0 0 18 18 0 ]);\npatch([17.55 20.44 22.44 24.44 26.44 22.44 19.55 17.55 ],[11.22 11.22 1" "3.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([19.55 22.44 20.44 17.55 19.55 ],[9.22 9.22 11.22 11.22 9.22" " ],[0.931 0.946 0.973 ]);\npatch([17.55 20.44 22.44 19.55 17.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([19" ".55 26.44 24.44 22.44 20.44 17.55 19.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf(''," "'COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nfprintf('" "','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter1" SID "223" Ports [1, 1] Position [590, 661, 635, 679] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "10.1.2" sg_icon_stat "45,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.91" " ]);\nplot([0 45 45 0 0 ],[0 0 18 18 0 ]);\npatch([17.55 20.44 22.44 24.44 26.44 22.44 19.55 17.55 ],[11.22 11.22 1" "3.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([19.55 22.44 20.44 17.55 19.55 ],[9.22 9.22 11.22 11.22 9.22" " ],[0.931 0.946 0.973 ]);\npatch([17.55 20.44 22.44 19.55 17.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([19" ".55 26.44 24.44 22.44 20.44 17.55 19.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf(''," "'COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nfprintf('" "','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "224" Ports [2, 1] Position [855, 231, 885, 264] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "9.1.01" sg_icon_stat "30,33,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 33 33 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 33 33 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[20.44 20.44 24.44 " "20.44 24.44 24.44 24.44 20.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[16.44 16.44 20.44 20.44 16.44 ],[0." "931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[12.44 12.44 16.44 16.44 12.44 ],[1 1 1 ]);\npatch([10.1 23." "88 19.88 15.88 11.88 6.1 10.1 ],[8.44 8.44 12.44 8.44 12.44 12.44 8.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('or');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "Logical2" SID "225" Ports [2, 1] Position [590, 306, 620, 339] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "9.1.01" sg_icon_stat "30,33,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 33 33 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 33 33 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[20.44 20.44 24.44 " "20.44 24.44 24.44 24.44 20.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[16.44 16.44 20.44 20.44 16.44 ],[0." "931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[12.44 12.44 16.44 16.44 12.44 ],[1 1 1 ]);\npatch([10.1 23." "88 19.88 15.88 11.88 6.1 10.1 ],[8.44 8.44 12.44 8.44 12.44 12.44 8.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('or');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "Logical3" SID "226" Ports [2, 1] Position [590, 271, 620, 304] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "9.1.01" sg_icon_stat "30,33,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 33 33 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 33 33 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[20.44 20.44 24.44 " "20.44 24.44 24.44 24.44 20.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[16.44 16.44 20.44 20.44 16.44 ],[0." "931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[12.44 12.44 16.44 16.44 12.44 ],[1 1 1 ]);\npatch([10.1 23." "88 19.88 15.88 11.88 6.1 10.1 ],[8.44 8.44 12.44 8.44 12.44 12.44 8.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('or');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "Logical4" SID "227" Ports [2, 1] Position [1155, 433, 1200, 502] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "10.1.2" sg_icon_stat "45,69,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 69 69 0 ],[0.77 0.82 0.91" " ]);\nplot([0 45 45 0 0 ],[0 0 69 69 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[40.66 40.66 46." "66 40.66 46.66 46.66 46.66 40.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[34.66 34.66 40.66 40.66 34.66" " ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[28.66 28.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch(" "[14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 22.66 28.66 28.66 22.66 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('and');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical5" SID "228" Ports [3, 1] Position [770, 652, 805, 688] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "3" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,261" block_type "logical" block_version "8.2" sg_icon_stat "35,36,3,1,white,blue,0,a2abe52d,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 36 36 0 ],[0.77 0.82 0.91" " ]);\nplot([0 35 35 0 0 ],[0 0 36 36 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[23.55 23.55 28.55" " 23.55 28.55 28.55 28.55 23.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[18.55 18.55 23.55 23.55 18.55 " "],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[13.55 13.55 18.55 18.55 13.55 ],[1 1 1 ]);\npatch(" "[10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[8.55 8.55 13.55 8.55 13.55 13.55 8.55 ],[0.931 0.946 0.973 ]);\nfprintf" "('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n\ncolor('black');disp('or');\nfp" "rintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical6" SID "229" Ports [3, 1] Position [850, 282, 885, 318] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "3" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,261" block_type "logical" block_version "8.2" sg_icon_stat "35,36,3,1,white,blue,0,98d76266,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 36 36 0 ],[0.77 0.82 0.91" " ]);\nplot([0 35 35 0 0 ],[0 0 36 36 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[23.55 23.55 28.55" " 23.55 28.55 28.55 28.55 23.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[18.55 18.55 23.55 23.55 18.55 " "],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[13.55 13.55 18.55 18.55 13.55 ],[1 1 1 ]);\npatch(" "[10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[8.55 8.55 13.55 8.55 13.55 13.55 8.55 ],[0.931 0.946 0.973 ]);\nfprintf" "('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n\ncolor('black');disp('and');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical7" SID "230" Ports [3, 1] Position [1175, 243, 1205, 277] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "3" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,261" block_type "logical" block_version "9.1.01" sg_icon_stat "30,34,3,1,white,blue,0,98d76266,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 34 34 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 34 34 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[21.44 21.44 25.44 " "21.44 25.44 25.44 25.44 21.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[17.44 17.44 21.44 21.44 17.44 ],[0." "931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[13.44 13.44 17.44 17.44 13.44 ],[1 1 1 ]);\npatch([10.1 23." "88 19.88 15.88 11.88 6.1 10.1 ],[9.44 9.44 13.44 9.44 13.44 13.44 9.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n\ncolor('black');disp('and');\nfprintf('','" "COMMENT: end icon text');\n" } Block { BlockType Reference Name "Mux" SID "231" Ports [3, 1] Position [320, 643, 345, 717] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" block_version "8.2" sg_icon_stat "25,74,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 10.5714 63.4286 74 0 ],[0.7" "7 0.82 0.91 ]);\nplot([0 25 25 0 0 ],[0 10.5714 63.4286 74 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5" ".325 ],[40.33 40.33 43.33 40.33 43.33 43.33 43.33 40.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[37.33 " "37.33 40.33 40.33 37.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[34.33 34.33 37.33 37.33 34" ".33 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[31.33 31.33 34.33 31.33 34.33 34.33 31.33 ],[0" ".931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('input',3" ",'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational" SID "232" Ports [2, 1] Position [1060, 231, 1100, 289] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a<=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[8 0 0 16 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "relational" block_version "8.2" sg_icon_stat "40,58,2,1,white,blue,0,52e4b236,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 58 58 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 58 58 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[34.55 34.55 39.55" " 34.55 39.55 39.55 39.55 34.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[29.55 29.55 34.55 34.55 29.55 " "],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[24.55 24.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch(" "[13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[19.55 19.55 24.55 19.55 24.55 24.55 19.55 ],[0.931 0.946 0.973 ]);\nfpr" "intf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa \\leq b','texmode'," "'on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational1" SID "233" Ports [2, 1] Position [1005, 431, 1050, 469] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a>b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[16 1 0 32 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "relational" block_version "10.1.2" sg_icon_stat "45,38,2,1,white,blue,0,b5131c97,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 38 38 0 ],[0.77 0.82 0.91" " ]);\nplot([0 45 45 0 0 ],[0 0 38 38 0 ]);\npatch([10.875 18.1 23.1 28.1 33.1 23.1 15.875 10.875 ],[24.55 24.55 29." "55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([15.875 23.1 18.1 10.875 15.875 ],[19.55 19.55 24.55 24.55 19." "55 ],[0.931 0.946 0.973 ]);\npatch([10.875 18.1 23.1 15.875 10.875 ],[14.55 14.55 19.55 19.55 14.55 ],[1 1 1 ]);\np" "atch([15.875 33.1 28.1 23.1 18.1 10.875 15.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input" "',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa > b','texmode','o" "n');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational2" SID "234" Ports [2, 1] Position [985, 651, 1025, 709] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a<=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[8 0 0 16 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "relational" block_version "8.2" sg_icon_stat "40,58,2,1,white,blue,0,52e4b236,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 58 58 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 58 58 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[34.55 34.55 39.55" " 34.55 39.55 39.55 39.55 34.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[29.55 29.55 34.55 34.55 29.55 " "],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[24.55 24.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch(" "[13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[19.55 19.55 24.55 19.55 24.55 24.55 19.55 ],[0.931 0.946 0.973 ]);\nfpr" "intf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa \\leq b','texmode'," "'on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "S-R_Latch1" SID "235" Ports [2, 1] Position [665, 272, 705, 343] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "S-R_Latch1" Location [202, 70, 1438, 850] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "S" SID "236" Position [95, 58, 125, 72] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "R" SID "237" Position [95, 88, 125, 102] Port "2" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Inverter" SID "238" Ports [1, 1] Position [220, 82, 250, 108] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "30,26,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[" "16.33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 1" "3.33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13." "33 10.33 ],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7" ".33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text')" ";\n\n\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register" SID "239" Ports [3, 1] Position [150, 70, 195, 120] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,50,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 50 50 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 50 50 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[31." "66 31.66 37.66 31.66 37.66 37.66 37.66 31.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[25.66 25.66 3" "1.66 31.66 25.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[19.66 19.66 25.66 25.66 19.66 " "],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[13.66 13.66 19.66 13.66 19.66 19.66 13.66 ],[0" ".931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor" "('black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('i" "nput',3,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfpri" "ntf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "240" Position [285, 63, 315, 77] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "R" SrcPort 1 DstBlock "Register" DstPort 2 } Line { SrcBlock "S" SrcPort 1 DstBlock "Register" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 Points [10, 0; 0, 55; -130, 0] DstBlock "Register" DstPort 3 } Line { SrcBlock "Register" SrcPort 1 Points [0, 0; 5, 0] Branch { Points [0, -25] DstBlock "Q" DstPort 1 } Branch { DstBlock "Inverter" DstPort 1 } } } } Block { BlockType SubSystem Name "S-R_Latch2" SID "241" Ports [2, 1] Position [1285, 245, 1325, 305] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "S-R_Latch2" Location [521, 318, 918, 591] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "S" SID "242" Position [95, 58, 125, 72] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "R" SID "243" Position [95, 88, 125, 102] Port "2" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Inverter" SID "244" Ports [1, 1] Position [220, 82, 250, 108] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "30,26,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[" "16.33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 1" "3.33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13." "33 10.33 ],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7" ".33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text')" ";\n\n\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register" SID "245" Ports [3, 1] Position [150, 70, 195, 120] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,50,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 50 50 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 50 50 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[31." "66 31.66 37.66 31.66 37.66 37.66 37.66 31.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[25.66 25.66 3" "1.66 31.66 25.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[19.66 19.66 25.66 25.66 19.66 " "],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[13.66 13.66 19.66 13.66 19.66 19.66 13.66 ],[0" ".931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor" "('black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('i" "nput',3,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfpri" "ntf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "246" Position [285, 63, 315, 77] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "Register" SrcPort 1 Points [0, 0; 5, 0] Branch { DstBlock "Inverter" DstPort 1 } Branch { Points [0, -25] DstBlock "Q" DstPort 1 } } Line { SrcBlock "Inverter" SrcPort 1 Points [10, 0; 0, 55; -130, 0] DstBlock "Register" DstPort 3 } Line { SrcBlock "S" SrcPort 1 DstBlock "Register" DstPort 1 } Line { SrcBlock "R" SrcPort 1 DstBlock "Register" DstPort 2 } } } Block { BlockType SubSystem Name "S-R_Latch3" SID "247" Ports [2, 1] Position [665, 167, 705, 238] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "S-R_Latch3" Location [202, 70, 1438, 850] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "S" SID "248" Position [95, 58, 125, 72] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "R" SID "249" Position [95, 88, 125, 102] Port "2" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Inverter" SID "250" Ports [1, 1] Position [220, 82, 250, 108] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "30,26,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[" "16.33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 1" "3.33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13." "33 10.33 ],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7" ".33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text')" ";\n\n\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register" SID "251" Ports [3, 1] Position [150, 70, 195, 120] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,50,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 50 50 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 50 50 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[31." "66 31.66 37.66 31.66 37.66 37.66 37.66 31.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[25.66 25.66 3" "1.66 31.66 25.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[19.66 19.66 25.66 25.66 19.66 " "],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[13.66 13.66 19.66 13.66 19.66 19.66 13.66 ],[0" ".931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor" "('black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('i" "nput',3,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfpri" "ntf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "252" Position [285, 63, 315, 77] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "Register" SrcPort 1 Points [0, 0; 5, 0] Branch { DstBlock "Inverter" DstPort 1 } Branch { Points [0, -25] DstBlock "Q" DstPort 1 } } Line { SrcBlock "Inverter" SrcPort 1 Points [10, 0; 0, 55; -130, 0] DstBlock "Register" DstPort 3 } Line { SrcBlock "S" SrcPort 1 DstBlock "Register" DstPort 1 } Line { SrcBlock "R" SrcPort 1 DstBlock "Register" DstPort 2 } } } Block { BlockType Scope Name "Scope" SID "253" Ports [3] Position [1530, 305, 1560, 405] Floating off Location [1, 45, 1441, 869] Open off NumInputPorts "3" ZoomMode "xonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" } YMin "-5~-5~-5" YMax "5~5~5" DataFormat "StructureWithTime" SampleTime "0" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Sim Mux" SID "254" Ports [2, 1] Position [405, 261, 445, 299] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Simulation Multiplexer" SourceType "Xilinx Simulation Multiplexer Block" infoedit "Distinguish input subsystems as \"simulation only\" and \"generation only\". The input specified For " "Simulation will be used during Simulink simulation. The input specified For Generation will be used during code ge" "neration. This block will typically be used on the output of a HW Co-Simulation, Black Box, or ModelSim subsystem." "

Hardware Notes: This block costs nothing." sim_sel "1" hw_sel "2" has_advanced_control "0" sggui_pos "20,20,336,197" block_type "simmux" block_version "10.1.3" sg_icon_stat "40,38,2,1,white,blue,0,4170dd71,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 38 38 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 38 38 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[24.55 24.55 29.55" " 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[19.55 19.55 24.55 24.55 19.55 " "],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[14.55 14.55 19.55 19.55 14.55 ],[1 1 1 ]);\npatch(" "[13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 0.946 0.973 ]);\nfprintf" "('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\nfprintf('','COMMENT: end icon te" "xt');color('red');\nplot(swLineX,simSwLineY);\ncolor('black');\nplot(swLineX,hwSwLineY);\n" } Block { BlockType Reference Name "Sim Mux1" SID "255" Ports [2, 1] Position [470, 576, 510, 614] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Simulation Multiplexer" SourceType "Xilinx Simulation Multiplexer Block" infoedit "Distinguish input subsystems as \"simulation only\" and \"generation only\". The input specified For " "Simulation will be used during Simulink simulation. The input specified For Generation will be used during code ge" "neration. This block will typically be used on the output of a HW Co-Simulation, Black Box, or ModelSim subsystem." "

Hardware Notes: This block costs nothing." sim_sel "1" hw_sel "2" has_advanced_control "0" sggui_pos "20,20,336,197" block_type "simmux" block_version "10.1.3" sg_icon_stat "40,38,2,1,white,blue,0,4170dd71,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 38 38 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 38 38 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[24.55 24.55 29.55" " 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[19.55 19.55 24.55 24.55 19.55 " "],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[14.55 14.55 19.55 19.55 14.55 ],[1 1 1 ]);\npatch(" "[13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 0.946 0.973 ]);\nfprintf" "('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\nfprintf('','COMMENT: end icon te" "xt');color('red');\nplot(swLineX,simSwLineY);\ncolor('black');\nplot(swLineX,hwSwLineY);\n" } Block { BlockType SubSystem Name "Sim-only\nGateway In" SID "256" Ports [1, 1] Position [305, 260, 350, 280] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "Sim-only\nGateway In" Location [269, 280, 494, 362] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" SID "257" Position [20, 33, 50, 47] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Disregard Subsystem" SID "258" Tag "discardX" Ports [] Position [86, 85, 144, 143] ShowName off AttributesFormatString "Disregard Subsystem\\nFor Generation" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Disregard Subsystem" SourceType "Xilinx Disregard Subsystem For Generation Block" infoedit "Place this block into a subsystem to have System Generator ignore the subsystem during code ge" "neration. This block can be used in combination with the Simulation Multiplexer block to provide an alternative" " simulation model for another subsystem (e.g., to provide a simulation model for a black box)." has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "disregard" block_version "10.1.3" sg_icon_stat "58,58,-1,-1,darkgray,black,0,0,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 58 58 0 ],[0 0 58 58 ],[0.1 0.1 0." "1]);\npatch([14 4 18 4 14 29 33 37 53 40 28 19 33 19 28 40 53 37 33 29 14 ],[6 16 30 44 54 54 50 54 54 41 53 44" " 30 16 7 19 6 6 10 6 6 ],[0.33 0.33 0.33]);\nplot([0 58 58 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end ico" "n graphics');\nfprintf('','COMMENT: begin icon text');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Gateway In" SID "259" Ports [1, 1] Position [80, 30, 145, 50] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, double and fixed point to Xilinx" " fixed point type.

Hardware notes: In hardware these blocks become top level input ports." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0 0 0 0 1 0 0]" inherit_from_input off UseAsADC off ADCChannel "'1'" hdl_port "on" has_advanced_control "0" sggui_pos "20,20,348,406" block_type "gatewayin" block_version "10.1.3" sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0" ".93 0.65 ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[1" "2.22 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.2" "2 12.22 12.22 10.22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.2" "2 ],[1 1 1 ]);\npatch([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985" " 0.979 0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' " "');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "260" Position [170, 33, 200, 47] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "D" SrcPort 1 DstBlock "Gateway In" DstPort 1 } Line { SrcBlock "Gateway In" SrcPort 1 DstBlock "Q" DstPort 1 } } } Block { BlockType SubSystem Name "Sim-only\nGateway In2" SID "261" Ports [1, 1] Position [360, 575, 405, 595] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "Sim-only\nGateway In2" Location [214, 70, 1918, 1152] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" SID "262" Position [20, 33, 50, 47] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Disregard Subsystem" SID "263" Tag "discardX" Ports [] Position [71, 110, 129, 168] ShowName off AttributesFormatString "Disregard Subsystem\\nFor Generation" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Disregard Subsystem" SourceType "Xilinx Disregard Subsystem For Generation Block" infoedit "Place this block into a subsystem to have System Generator ignore the subsystem during code ge" "neration. This block can be used in combination with the Simulation Multiplexer block to provide an alternative" " simulation model for another subsystem (e.g., to provide a simulation model for a black box)." has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "disregard" block_version "10.1.3" sg_icon_stat "58,58,-1,-1,darkgray,black,0,0,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 58 58 0 ],[0 0 58 58 ],[0.1 0.1 0." "1]);\npatch([14 4 18 4 14 29 33 37 53 40 28 19 33 19 28 40 53 37 33 29 14 ],[6 16 30 44 54 54 50 54 54 41 53 44" " 30 16 7 19 6 6 10 6 6 ],[0.33 0.33 0.33]);\nplot([0 58 58 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end ico" "n graphics');\nfprintf('','COMMENT: begin icon text');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Gateway In" SID "264" Ports [1, 1] Position [80, 30, 145, 50] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, double and fixed point to Xilinx" " fixed point type.

Hardware notes: In hardware these blocks become top level input ports." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0 0 0 0 1 0 0]" inherit_from_input off UseAsADC off ADCChannel "'1'" hdl_port "on" has_advanced_control "0" sggui_pos "20,20,348,406" block_type "gatewayin" block_version "10.1.3" sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0" ".93 0.65 ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[1" "2.22 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.2" "2 12.22 12.22 10.22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.2" "2 ],[1 1 1 ]);\npatch([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985" " 0.979 0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' " "');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "265" Position [170, 33, 200, 47] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "Gateway In" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "D" SrcPort 1 DstBlock "Gateway In" DstPort 1 } } } Block { BlockType SubSystem Name "negedge" SID "266" Ports [1, 1] Position [495, 288, 525, 302] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "negedge" Location [459, 339, 854, 490] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "In" SID "267" Position [170, 213, 200, 227] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Delay" SID "268" Ports [1, 1] Position [230, 247, 290, 303] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p. If register retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "8.2" sg_icon_stat "60,56,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.8" "8 36.88 44.88 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.8" "8 36.88 28.88 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1" " 1 1 ]);\npatch([20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0" ".946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('" "black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "269" Ports [1, 1] Position [290, 191, 345, 249] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "8.2" sg_icon_stat "55,58,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 58 58 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ]" ",[36.77 36.77 43.77 36.77 43.77 43.77 43.77 36.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[29.7" "7 29.77 36.77 36.77 29.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[22.77 22.77 29.7" "7 29.77 22.77 ],[1 1 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[15.77 15.77 22.77 15.77 22.7" "7 22.77 15.77 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin i" "con text');\n\n\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical" SID "270" Ports [2, 1] Position [410, 205, 465, 265] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "8.2" sg_icon_stat "55,60,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 60 60 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ]" ",[37.77 37.77 44.77 37.77 44.77 44.77 44.77 37.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[30.7" "7 30.77 37.77 37.77 30.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[23.77 23.77 30.7" "7 30.77 23.77 ],[1 1 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[16.77 16.77 23.77 16.77 23.7" "7 23.77 16.77 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin i" "con text');\n\n\n\ncolor('black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Out" SID "271" Position [490, 228, 520, 242] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "Logical" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "In" SrcPort 1 Points [5, 0] Branch { Points [0, 55] DstBlock "Delay" DstPort 1 } Branch { DstBlock "Inverter" DstPort 1 } } Line { SrcBlock "Delay" SrcPort 1 Points [90, 0; 0, -25] DstBlock "Logical" DstPort 2 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical" DstPort 1 } } } Block { BlockType SubSystem Name "posedge" SID "272" Ports [1, 1] Position [495, 273, 525, 287] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "posedge" Location [459, 339, 854, 490] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "In" SID "273" Position [20, 33, 50, 47] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Delay" SID "274" Ports [1, 1] Position [80, 67, 140, 123] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p. If register retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "8.2" sg_icon_stat "60,56,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.8" "8 36.88 44.88 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.8" "8 36.88 28.88 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1" " 1 1 ]);\npatch([20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0" ".946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('" "black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "275" Ports [1, 1] Position [170, 66, 225, 124] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "8.2" sg_icon_stat "55,58,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 58 58 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ]" ",[36.77 36.77 43.77 36.77 43.77 43.77 43.77 36.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[29.7" "7 29.77 36.77 36.77 29.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[22.77 22.77 29.7" "7 29.77 22.77 ],[1 1 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[15.77 15.77 22.77 15.77 22.7" "7 22.77 15.77 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin i" "con text');\n\n\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical" SID "276" Ports [2, 1] Position [260, 25, 315, 85] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "8.2" sg_icon_stat "55,60,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 60 60 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ]" ",[37.77 37.77 44.77 37.77 44.77 44.77 44.77 37.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[30.7" "7 30.77 37.77 37.77 30.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[23.77 23.77 30.7" "7 30.77 23.77 ],[1 1 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[16.77 16.77 23.77 16.77 23.7" "7 23.77 16.77 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin i" "con text');\n\n\n\ncolor('black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Out" SID "277" Position [340, 48, 370, 62] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "Delay" SrcPort 1 Points [0, 0] DstBlock "Inverter" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 Points [5, 0; 0, -25] DstBlock "Logical" DstPort 2 } Line { SrcBlock "In" SrcPort 1 Points [0, 0; 5, 0] Branch { DstBlock "Logical" DstPort 1 } Branch { Points [0, 55] DstBlock "Delay" DstPort 1 } } Line { SrcBlock "Logical" SrcPort 1 Points [0, 0] DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "posedge2" SID "278" Ports [1, 1] Position [495, 323, 525, 337] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "posedge2" Location [459, 339, 854, 490] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "In" SID "279" Position [20, 33, 50, 47] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Delay" SID "280" Ports [1, 1] Position [80, 67, 140, 123] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p. If register retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "8.2" sg_icon_stat "60,56,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.8" "8 36.88 44.88 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.8" "8 36.88 28.88 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1" " 1 1 ]);\npatch([20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0" ".946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('" "black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "281" Ports [1, 1] Position [170, 66, 225, 124] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "8.2" sg_icon_stat "55,58,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 58 58 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ]" ",[36.77 36.77 43.77 36.77 43.77 43.77 43.77 36.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[29.7" "7 29.77 36.77 36.77 29.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[22.77 22.77 29.7" "7 29.77 22.77 ],[1 1 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[15.77 15.77 22.77 15.77 22.7" "7 22.77 15.77 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin i" "con text');\n\n\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical" SID "282" Ports [2, 1] Position [260, 25, 315, 85] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "8.2" sg_icon_stat "55,60,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 60 60 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ]" ",[37.77 37.77 44.77 37.77 44.77 44.77 44.77 37.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[30.7" "7 30.77 37.77 37.77 30.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[23.77 23.77 30.7" "7 30.77 23.77 ],[1 1 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[16.77 16.77 23.77 16.77 23.7" "7 23.77 16.77 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin i" "con text');\n\n\n\ncolor('black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Out" SID "283" Position [340, 48, 370, 62] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "Delay" SrcPort 1 Points [0, 0] DstBlock "Inverter" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 Points [5, 0; 0, -25] DstBlock "Logical" DstPort 2 } Line { SrcBlock "In" SrcPort 1 Points [0, 0; 5, 0] Branch { DstBlock "Logical" DstPort 1 } Branch { Points [0, 55] DstBlock "Delay" DstPort 1 } } Line { SrcBlock "Logical" SrcPort 1 Points [0, 0] DstBlock "Out" DstPort 1 } } } Block { BlockType Outport Name "done" SID "284" Position [1350, 268, 1380, 282] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Outport Name "running" SID "285" Position [1245, 518, 1275, 532] Port "2" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Outport Name "paused" SID "286" Position [1240, 463, 1270, 477] Port "3" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Outport Name "timeLeft" SID "287" Position [1285, 358, 1315, 372] Port "4" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "mode" SrcPort 1 DstBlock "Mux" DstPort 1 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Mux" DstPort 2 } Line { SrcBlock "Medium Idle" SrcPort 1 DstBlock "Mux" DstPort 3 } Line { SrcBlock "Mux" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Logical4" SrcPort 1 DstBlock "paused" DstPort 1 } Line { SrcBlock "start" SrcPort 1 DstBlock "Sim Mux" DstPort 2 } Line { SrcBlock "Sim Mux" SrcPort 1 DstBlock "posedge" DstPort 1 } Line { SrcBlock "AddSub" SrcPort 1 DstBlock "timeLeft" DstPort 1 } Line { SrcBlock "Constant" SrcPort 1 DstBlock "Relational1" DstPort 2 } Line { SrcBlock "Relational1" SrcPort 1 DstBlock "Logical4" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical4" DstPort 2 } Line { SrcBlock "S-R_Latch1" SrcPort 1 Points [25, 0] Branch { Points [0, 175] Branch { Points [0, 235] DstBlock "Counter1" DstPort 2 } Branch { Points [290, 0] Branch { DstBlock "Inverter" DstPort 1 } Branch { Points [0, 40] DstBlock "running" DstPort 1 } } } Branch { Points [0, -20] DstBlock "Logical6" DstPort 1 } } Line { SrcBlock "slotCount" SrcPort 1 Points [10, 0] Branch { Points [0, 105] DstBlock "AddSub" DstPort 1 } Branch { DstBlock "Relational" DstPort 1 } } Line { SrcBlock "Counter" SrcPort 1 Points [0, 0] Branch { Labels [1, 0] DstBlock "Relational" DstPort 2 } Branch { Points [0, 100] Branch { DstBlock "AddSub" DstPort 2 } Branch { Points [0, 30] Branch { Points [0, 35] DstBlock "Relational1" DstPort 1 } Branch { Points [445, 0; 0, -85] DstBlock "Gateway Out" DstPort 1 } } } } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Counter" DstPort 1 } Line { SrcBlock "S-R_Latch2" SrcPort 1 DstBlock "done" DstPort 1 } Line { SrcBlock "Relational" SrcPort 1 Points [10, 0] Branch { Points [0, 110; -550, 0; 0, -40] DstBlock "Logical2" DstPort 2 } Branch { Points [0, -80; -290, 0; 0, 60] DstBlock "Logical1" DstPort 1 } Branch { DstBlock "Logical7" DstPort 2 } } Line { SrcBlock "done_reset" SrcPort 1 Points [15, 0] Branch { DstBlock "S-R_Latch2" DstPort 2 } Branch { Points [0, -145; -625, 0; 0, 75] DstBlock "S-R_Latch3" DstPort 2 } } Line { SrcBlock "posedge" SrcPort 1 Points [15, 0] Branch { DstBlock "Logical3" DstPort 1 } Branch { Points [0, 400] DstBlock "Logical5" DstPort 3 } Branch { Points [0, -25] Branch { DstBlock "Logical1" DstPort 2 } Branch { Points [0, -70] DstBlock "S-R_Latch3" DstPort 1 } } } Line { SrcBlock "Logical3" SrcPort 1 DstBlock "S-R_Latch1" DstPort 1 } Line { SrcBlock "negedge" SrcPort 1 DstBlock "Logical3" DstPort 2 } Line { SrcBlock "pause" SrcPort 1 Points [115, 0] Branch { DstBlock "posedge2" DstPort 1 } Branch { Points [0, -35] DstBlock "negedge" DstPort 1 } } Line { SrcBlock "Sim-only\nGateway In" SrcPort 1 DstBlock "Sim Mux" DstPort 1 } Line { SrcBlock "slotTime" SrcPort 1 DstBlock "Relational2" DstPort 1 } Line { SrcBlock "Counter1" SrcPort 1 Points [35, 0] Branch { DstBlock "Relational2" DstPort 2 } Branch { Points [0, 35; 505, 0; 0, -340] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "Logical5" SrcPort 1 DstBlock "Counter1" DstPort 1 } Line { SrcBlock "Relational2" SrcPort 1 Points [20, 0; 0, -60] Branch { Points [-295, 0] Branch { DstBlock "Logical5" DstPort 1 } Branch { Points [0, -320] DstBlock "Logical6" DstPort 2 } } Branch { Points [380, 0; 0, -265] DstBlock "Gateway Out1" DstPort 1 } } Line { SrcBlock "Inverter1" SrcPort 1 DstBlock "Logical5" DstPort 2 } Line { SrcBlock "Logical6" SrcPort 1 DstBlock "Counter" DstPort 2 } Line { SrcBlock "Convert1" SrcPort 1 Points [25, 0; 0, -75] DstBlock "Sim Mux1" DstPort 2 } Line { SrcBlock "Sim Mux1" SrcPort 1 Points [60, 0] Branch { DstBlock "Inverter1" DstPort 1 } Branch { Points [260, 0; 0, -250] Branch { DstBlock "Logical6" DstPort 3 } Branch { DstBlock "Delay" DstPort 1 } } } Line { SrcBlock "Constant2" SrcPort 1 DstBlock "Sim-only\nGateway In" DstPort 1 } Line { SrcBlock "posedge2" SrcPort 1 Points [25, 0; 0, -15] DstBlock "Logical2" DstPort 1 } Line { SrcBlock "Logical2" SrcPort 1 DstBlock "S-R_Latch1" DstPort 2 } Line { SrcBlock "Constant4" SrcPort 1 DstBlock "Sim-only\nGateway In2" DstPort 1 } Line { SrcBlock "Sim-only\nGateway In2" SrcPort 1 DstBlock "Sim Mux1" DstPort 1 } Line { SrcBlock "Logical7" SrcPort 1 DstBlock "S-R_Latch2" DstPort 1 } Line { SrcBlock "S-R_Latch3" SrcPort 1 Points [70, 0; 0, -50; 350, 0; 0, 95] DstBlock "Logical7" DstPort 1 } Line { SrcBlock "Delay" SrcPort 1 Points [195, 0; 0, -75] DstBlock "Logical7" DstPort 3 } Line { SrcBlock "Gateway Out" SrcPort 1 DstBlock "Scope" DstPort 1 } Line { SrcBlock "Gateway Out1" SrcPort 1 DstBlock "Scope" DstPort 2 } Line { SrcBlock "Gateway Out2" SrcPort 1 DstBlock "Scope" DstPort 3 } Annotation { Name "This SR latch handles the case of a zero-slot-count\ntimer event. When the user code sets the slotCount t" "o 0,\nthe comparison is immedilatey true. The timer done\nsignal then asserts when:\nif(carrier sensing) after IDLE" " AND\nafter user asserts start\nDone de-assets when the user clears the done bit\n*but does not re-assert* until th" "e next user-initiated start." Position [697, 92] } } } Block { BlockType SubSystem Name "Timer 1" SID "288" Ports [7, 4] Position [335, 215, 440, 335] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "Timer 1" Location [214, 74, 1910, 1156] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "start" SID "289" Position [310, 283, 340, 297] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "pause" SID "290" Position [310, 323, 340, 337] Port "2" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "mode" SID "291" Position [255, 648, 285, 662] NamePlacement "alternate" Port "3" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "done_reset" SID "292" Position [1175, 283, 1205, 297] Port "4" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "slotCount" SID "293" Position [980, 238, 1010, 252] NamePlacement "alternate" Port "5" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "slotTime" SID "294" Position [930, 658, 960, 672] Port "6" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "Medium Idle" SID "295" Position [250, 698, 280, 712] Port "7" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "AddSub" SID "296" Ports [2, 1] Position [1210, 339, 1255, 386] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Subtraction" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Unsigned" n_bits "32" bin_pt "0" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL off hw_selection "Fabric" pipelined off xl_use_area off xl_area "[16 0 0 32 0 0 0]" use_rpm "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" block_version "8.2" sg_icon_stat "45,47,2,1,white,blue,0,32e1f85f,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 47 47 0 ],[0.77 0.82 0.91" " ]);\nplot([0 45 45 0 0 ],[0 0 47 47 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[29.66 29.66 35." "66 29.66 35.66 35.66 35.66 29.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[23.66 23.66 29.66 29.66 23.66" " ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[17.66 17.66 23.66 23.66 17.66 ],[1 1 1 ]);\npatch(" "[14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[11.66 11.66 17.66 11.66 17.66 17.66 11.66 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'" ",1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bf{a - b}','texmode','" "on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant" SID "297" Ports [0, 1] Position [940, 454, 970, 466] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "50,50,400,346" block_type "constant" block_version "10.1.2" sg_icon_stat "30,12,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 12 12 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 12 12 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ],[7.11 7.11 " "8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[6.11 6.11 7.11 7.11 6.11 ],[" "0.931 0.946 0.973 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch([13." "775 17.22 16.22 15.22 14.22 12.775 13.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.931 0.946 0.973 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'0'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant1" SID "298" Ports [0, 1] Position [255, 672, 290, 688] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "8.2" sg_icon_stat "35,16,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 16 16 0 ],[0.77 0.82 0.91" " ]);\nplot([0 35 35 0 0 ],[0 0 16 16 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[10.22 10.22 1" "2.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[8.22 8.22 10.22 10.22 8.22" " ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatch([14" ".55 21.44 19.44 17.44 15.44 12.55 14.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprintf(''," "'COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Constant Name "Constant2" SID "299" Position [260, 261, 275, 279] ShowName off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Constant Name "Constant4" SID "300" Position [315, 576, 330, 594] ShowName off Value "0" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Convert1" SID "301" Ports [1, 1] Position [380, 670, 415, 690] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "16" bin_pt "14" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,461,375" block_type "convert" block_version "8.2" sg_icon_stat "35,20,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.91" " ]);\nplot([0 35 35 0 0 ],[0 0 20 20 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output'," "1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Counter" SID "302" Ports [2, 1] Position [905, 224, 965, 326] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited counter is" " implemented by combining a counter with a comparator." cnt_type "Free Running" cnt_to "Inf" operation "Up" start_count "0" cnt_by_val "1" arith_type "Unsigned" n_bits "32" bin_pt "0" load_pin off rst on en on explicit_period "on" period "1" dbl_ovrd off use_behavioral_HDL off implementation "Fabric" xl_use_area off xl_area "[17 32 0 32 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,356,630" block_type "counter" block_version "8.2" sg_icon_stat "60,102,2,1,white,blue,0,ae3608d6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 102 102 0 ],[0.77 0.82 0." "91 ]);\nplot([0 60 60 0 0 ],[0 0 102 102 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[59.88 59.88 " "67.88 59.88 67.88 67.88 67.88 59.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[51.88 51.88 59.88 59.88 51.8" "8 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[43.88 43.88 51.88 51.88 43.88 ],[1 1 1 ]);\npatch(" "[20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[35.88 35.88 43.88 35.88 43.88 43.88 35.88 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'rst');\ncolor('black');port_label('input',2,'en');\n\ncolor('black');disp('{\\fontsize{14}\\bf++}','texmode','on'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Counter1" SID "303" Ports [2, 1] Position [835, 644, 895, 746] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited counter is" " implemented by combining a counter with a comparator." cnt_type "Free Running" cnt_to "Inf" operation "Up" start_count "0" cnt_by_val "1" arith_type "Unsigned" n_bits "16" bin_pt "0" load_pin off rst on en on explicit_period "on" period "1" dbl_ovrd off use_behavioral_HDL off implementation "Fabric" xl_use_area off xl_area "[17 32 0 32 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,356,630" block_type "counter" block_version "8.2" sg_icon_stat "60,102,2,1,white,blue,0,ae3608d6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 102 102 0 ],[0.77 0.82 0." "91 ]);\nplot([0 60 60 0 0 ],[0 0 102 102 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[59.88 59.88 " "67.88 59.88 67.88 67.88 67.88 59.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[51.88 51.88 59.88 59.88 51.8" "8 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[43.88 43.88 51.88 51.88 43.88 ],[1 1 1 ]);\npatch(" "[20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[35.88 35.88 43.88 35.88 43.88 43.88 35.88 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'rst');\ncolor('black');port_label('input',2,'en');\n\ncolor('black');disp('{\\fontsize{14}\\bf++}','texmode','on'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay" SID "304" Ports [1, 1] Position [925, 331, 950, 359] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "10.1.3" sg_icon_stat "25,28,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 28 28 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 28 28 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 17.33 20" ".33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33 17.33 14.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-1}','t" "exmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "305" Ports [1, 1] Position [1080, 476, 1125, 494] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "10.1.2" sg_icon_stat "45,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.91" " ]);\nplot([0 45 45 0 0 ],[0 0 18 18 0 ]);\npatch([17.55 20.44 22.44 24.44 26.44 22.44 19.55 17.55 ],[11.22 11.22 1" "3.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([19.55 22.44 20.44 17.55 19.55 ],[9.22 9.22 11.22 11.22 9.22" " ],[0.931 0.946 0.973 ]);\npatch([17.55 20.44 22.44 19.55 17.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([19" ".55 26.44 24.44 22.44 20.44 17.55 19.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf(''," "'COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nfprintf('" "','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter1" SID "306" Ports [1, 1] Position [590, 661, 635, 679] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "10.1.2" sg_icon_stat "45,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.91" " ]);\nplot([0 45 45 0 0 ],[0 0 18 18 0 ]);\npatch([17.55 20.44 22.44 24.44 26.44 22.44 19.55 17.55 ],[11.22 11.22 1" "3.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([19.55 22.44 20.44 17.55 19.55 ],[9.22 9.22 11.22 11.22 9.22" " ],[0.931 0.946 0.973 ]);\npatch([17.55 20.44 22.44 19.55 17.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([19" ".55 26.44 24.44 22.44 20.44 17.55 19.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf(''," "'COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nfprintf('" "','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "307" Ports [2, 1] Position [855, 231, 885, 264] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "9.1.01" sg_icon_stat "30,33,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 33 33 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 33 33 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[20.44 20.44 24.44 " "20.44 24.44 24.44 24.44 20.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[16.44 16.44 20.44 20.44 16.44 ],[0." "931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[12.44 12.44 16.44 16.44 12.44 ],[1 1 1 ]);\npatch([10.1 23." "88 19.88 15.88 11.88 6.1 10.1 ],[8.44 8.44 12.44 8.44 12.44 12.44 8.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('or');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "Logical2" SID "308" Ports [2, 1] Position [590, 306, 620, 339] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "9.1.01" sg_icon_stat "30,33,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 33 33 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 33 33 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[20.44 20.44 24.44 " "20.44 24.44 24.44 24.44 20.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[16.44 16.44 20.44 20.44 16.44 ],[0." "931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[12.44 12.44 16.44 16.44 12.44 ],[1 1 1 ]);\npatch([10.1 23." "88 19.88 15.88 11.88 6.1 10.1 ],[8.44 8.44 12.44 8.44 12.44 12.44 8.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('or');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "Logical3" SID "309" Ports [2, 1] Position [590, 271, 620, 304] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "9.1.01" sg_icon_stat "30,33,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 33 33 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 33 33 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[20.44 20.44 24.44 " "20.44 24.44 24.44 24.44 20.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[16.44 16.44 20.44 20.44 16.44 ],[0." "931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[12.44 12.44 16.44 16.44 12.44 ],[1 1 1 ]);\npatch([10.1 23." "88 19.88 15.88 11.88 6.1 10.1 ],[8.44 8.44 12.44 8.44 12.44 12.44 8.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('or');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "Logical4" SID "310" Ports [2, 1] Position [1155, 433, 1200, 502] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "10.1.2" sg_icon_stat "45,69,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 69 69 0 ],[0.77 0.82 0.91" " ]);\nplot([0 45 45 0 0 ],[0 0 69 69 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[40.66 40.66 46." "66 40.66 46.66 46.66 46.66 40.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[34.66 34.66 40.66 40.66 34.66" " ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[28.66 28.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch(" "[14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 22.66 28.66 28.66 22.66 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('and');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical5" SID "311" Ports [3, 1] Position [770, 652, 805, 688] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "3" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,261" block_type "logical" block_version "8.2" sg_icon_stat "35,36,3,1,white,blue,0,a2abe52d,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 36 36 0 ],[0.77 0.82 0.91" " ]);\nplot([0 35 35 0 0 ],[0 0 36 36 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[23.55 23.55 28.55" " 23.55 28.55 28.55 28.55 23.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[18.55 18.55 23.55 23.55 18.55 " "],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[13.55 13.55 18.55 18.55 13.55 ],[1 1 1 ]);\npatch(" "[10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[8.55 8.55 13.55 8.55 13.55 13.55 8.55 ],[0.931 0.946 0.973 ]);\nfprintf" "('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n\ncolor('black');disp('or');\nfp" "rintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical6" SID "312" Ports [3, 1] Position [850, 282, 885, 318] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "3" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,261" block_type "logical" block_version "8.2" sg_icon_stat "35,36,3,1,white,blue,0,98d76266,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 36 36 0 ],[0.77 0.82 0.91" " ]);\nplot([0 35 35 0 0 ],[0 0 36 36 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[23.55 23.55 28.55" " 23.55 28.55 28.55 28.55 23.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[18.55 18.55 23.55 23.55 18.55 " "],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[13.55 13.55 18.55 18.55 13.55 ],[1 1 1 ]);\npatch(" "[10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[8.55 8.55 13.55 8.55 13.55 13.55 8.55 ],[0.931 0.946 0.973 ]);\nfprintf" "('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n\ncolor('black');disp('and');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical7" SID "313" Ports [3, 1] Position [1175, 243, 1205, 277] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "3" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,261" block_type "logical" block_version "9.1.01" sg_icon_stat "30,34,3,1,white,blue,0,98d76266,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 34 34 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 34 34 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[21.44 21.44 25.44 " "21.44 25.44 25.44 25.44 21.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[17.44 17.44 21.44 21.44 17.44 ],[0." "931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[13.44 13.44 17.44 17.44 13.44 ],[1 1 1 ]);\npatch([10.1 23." "88 19.88 15.88 11.88 6.1 10.1 ],[9.44 9.44 13.44 9.44 13.44 13.44 9.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n\ncolor('black');disp('and');\nfprintf('','" "COMMENT: end icon text');\n" } Block { BlockType Reference Name "Mux" SID "314" Ports [3, 1] Position [320, 643, 345, 717] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" block_version "8.2" sg_icon_stat "25,74,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 10.5714 63.4286 74 0 ],[0.7" "7 0.82 0.91 ]);\nplot([0 25 25 0 0 ],[0 10.5714 63.4286 74 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5" ".325 ],[40.33 40.33 43.33 40.33 43.33 43.33 43.33 40.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[37.33 " "37.33 40.33 40.33 37.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[34.33 34.33 37.33 37.33 34" ".33 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[31.33 31.33 34.33 31.33 34.33 34.33 31.33 ],[0" ".931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('input',3" ",'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational" SID "315" Ports [2, 1] Position [1060, 231, 1100, 289] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a<=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[8 0 0 16 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "relational" block_version "8.2" sg_icon_stat "40,58,2,1,white,blue,0,52e4b236,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 58 58 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 58 58 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[34.55 34.55 39.55" " 34.55 39.55 39.55 39.55 34.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[29.55 29.55 34.55 34.55 29.55 " "],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[24.55 24.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch(" "[13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[19.55 19.55 24.55 19.55 24.55 24.55 19.55 ],[0.931 0.946 0.973 ]);\nfpr" "intf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa \\leq b','texmode'," "'on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational1" SID "316" Ports [2, 1] Position [1005, 431, 1050, 469] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a>b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[16 1 0 32 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "relational" block_version "10.1.2" sg_icon_stat "45,38,2,1,white,blue,0,b5131c97,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 38 38 0 ],[0.77 0.82 0.91" " ]);\nplot([0 45 45 0 0 ],[0 0 38 38 0 ]);\npatch([10.875 18.1 23.1 28.1 33.1 23.1 15.875 10.875 ],[24.55 24.55 29." "55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([15.875 23.1 18.1 10.875 15.875 ],[19.55 19.55 24.55 24.55 19." "55 ],[0.931 0.946 0.973 ]);\npatch([10.875 18.1 23.1 15.875 10.875 ],[14.55 14.55 19.55 19.55 14.55 ],[1 1 1 ]);\np" "atch([15.875 33.1 28.1 23.1 18.1 10.875 15.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input" "',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa > b','texmode','o" "n');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational2" SID "317" Ports [2, 1] Position [985, 651, 1025, 709] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a<=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[8 0 0 16 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "relational" block_version "8.2" sg_icon_stat "40,58,2,1,white,blue,0,52e4b236,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 58 58 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 58 58 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[34.55 34.55 39.55" " 34.55 39.55 39.55 39.55 34.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[29.55 29.55 34.55 34.55 29.55 " "],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[24.55 24.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch(" "[13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[19.55 19.55 24.55 19.55 24.55 24.55 19.55 ],[0.931 0.946 0.973 ]);\nfpr" "intf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa \\leq b','texmode'," "'on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "S-R_Latch1" SID "318" Ports [2, 1] Position [665, 272, 705, 343] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "S-R_Latch1" Location [202, 70, 1438, 850] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "S" SID "319" Position [95, 58, 125, 72] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "R" SID "320" Position [95, 88, 125, 102] Port "2" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Inverter" SID "321" Ports [1, 1] Position [220, 82, 250, 108] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "30,26,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[" "16.33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 1" "3.33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13." "33 10.33 ],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7" ".33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text')" ";\n\n\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register" SID "322" Ports [3, 1] Position [150, 70, 195, 120] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,50,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 50 50 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 50 50 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[31." "66 31.66 37.66 31.66 37.66 37.66 37.66 31.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[25.66 25.66 3" "1.66 31.66 25.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[19.66 19.66 25.66 25.66 19.66 " "],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[13.66 13.66 19.66 13.66 19.66 19.66 13.66 ],[0" ".931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor" "('black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('i" "nput',3,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfpri" "ntf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "323" Position [285, 63, 315, 77] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "Register" SrcPort 1 Points [0, 0; 5, 0] Branch { DstBlock "Inverter" DstPort 1 } Branch { Points [0, -25] DstBlock "Q" DstPort 1 } } Line { SrcBlock "Inverter" SrcPort 1 Points [10, 0; 0, 55; -130, 0] DstBlock "Register" DstPort 3 } Line { SrcBlock "S" SrcPort 1 DstBlock "Register" DstPort 1 } Line { SrcBlock "R" SrcPort 1 DstBlock "Register" DstPort 2 } } } Block { BlockType SubSystem Name "S-R_Latch2" SID "324" Ports [2, 1] Position [1285, 245, 1325, 305] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "S-R_Latch2" Location [521, 318, 918, 591] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "S" SID "325" Position [95, 58, 125, 72] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "R" SID "326" Position [95, 88, 125, 102] Port "2" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Inverter" SID "327" Ports [1, 1] Position [220, 82, 250, 108] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "30,26,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[" "16.33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 1" "3.33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13." "33 10.33 ],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7" ".33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text')" ";\n\n\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register" SID "328" Ports [3, 1] Position [150, 70, 195, 120] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,50,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 50 50 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 50 50 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[31." "66 31.66 37.66 31.66 37.66 37.66 37.66 31.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[25.66 25.66 3" "1.66 31.66 25.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[19.66 19.66 25.66 25.66 19.66 " "],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[13.66 13.66 19.66 13.66 19.66 19.66 13.66 ],[0" ".931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor" "('black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('i" "nput',3,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfpri" "ntf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "329" Position [285, 63, 315, 77] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "R" SrcPort 1 DstBlock "Register" DstPort 2 } Line { SrcBlock "S" SrcPort 1 DstBlock "Register" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 Points [10, 0; 0, 55; -130, 0] DstBlock "Register" DstPort 3 } Line { SrcBlock "Register" SrcPort 1 Points [0, 0; 5, 0] Branch { Points [0, -25] DstBlock "Q" DstPort 1 } Branch { DstBlock "Inverter" DstPort 1 } } } } Block { BlockType SubSystem Name "S-R_Latch3" SID "330" Ports [2, 1] Position [665, 167, 705, 238] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "S-R_Latch3" Location [202, 70, 1438, 850] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "S" SID "331" Position [95, 58, 125, 72] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "R" SID "332" Position [95, 88, 125, 102] Port "2" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Inverter" SID "333" Ports [1, 1] Position [220, 82, 250, 108] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "30,26,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[" "16.33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 1" "3.33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13." "33 10.33 ],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7" ".33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text')" ";\n\n\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register" SID "334" Ports [3, 1] Position [150, 70, 195, 120] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,50,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 50 50 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 50 50 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[31." "66 31.66 37.66 31.66 37.66 37.66 37.66 31.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[25.66 25.66 3" "1.66 31.66 25.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[19.66 19.66 25.66 25.66 19.66 " "],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[13.66 13.66 19.66 13.66 19.66 19.66 13.66 ],[0" ".931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor" "('black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('i" "nput',3,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfpri" "ntf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "335" Position [285, 63, 315, 77] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "R" SrcPort 1 DstBlock "Register" DstPort 2 } Line { SrcBlock "S" SrcPort 1 DstBlock "Register" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 Points [10, 0; 0, 55; -130, 0] DstBlock "Register" DstPort 3 } Line { SrcBlock "Register" SrcPort 1 Points [0, 0; 5, 0] Branch { Points [0, -25] DstBlock "Q" DstPort 1 } Branch { DstBlock "Inverter" DstPort 1 } } } } Block { BlockType Reference Name "Sim Mux" SID "337" Ports [2, 1] Position [405, 261, 445, 299] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Simulation Multiplexer" SourceType "Xilinx Simulation Multiplexer Block" infoedit "Distinguish input subsystems as \"simulation only\" and \"generation only\". The input specified For " "Simulation will be used during Simulink simulation. The input specified For Generation will be used during code ge" "neration. This block will typically be used on the output of a HW Co-Simulation, Black Box, or ModelSim subsystem." "

Hardware Notes: This block costs nothing." sim_sel "1" hw_sel "2" has_advanced_control "0" sggui_pos "20,20,336,197" block_type "simmux" block_version "10.1.3" sg_icon_stat "40,38,2,1,white,blue,0,4170dd71,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 38 38 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 38 38 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[24.55 24.55 29.55" " 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[19.55 19.55 24.55 24.55 19.55 " "],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[14.55 14.55 19.55 19.55 14.55 ],[1 1 1 ]);\npatch(" "[13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 0.946 0.973 ]);\nfprintf" "('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\nfprintf('','COMMENT: end icon te" "xt');color('red');\nplot(swLineX,simSwLineY);\ncolor('black');\nplot(swLineX,hwSwLineY);\n" } Block { BlockType Reference Name "Sim Mux1" SID "338" Ports [2, 1] Position [470, 576, 510, 614] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Simulation Multiplexer" SourceType "Xilinx Simulation Multiplexer Block" infoedit "Distinguish input subsystems as \"simulation only\" and \"generation only\". The input specified For " "Simulation will be used during Simulink simulation. The input specified For Generation will be used during code ge" "neration. This block will typically be used on the output of a HW Co-Simulation, Black Box, or ModelSim subsystem." "

Hardware Notes: This block costs nothing." sim_sel "1" hw_sel "2" has_advanced_control "0" sggui_pos "20,20,336,197" block_type "simmux" block_version "10.1.3" sg_icon_stat "40,38,2,1,white,blue,0,4170dd71,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 38 38 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 38 38 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[24.55 24.55 29.55" " 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[19.55 19.55 24.55 24.55 19.55 " "],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[14.55 14.55 19.55 19.55 14.55 ],[1 1 1 ]);\npatch(" "[13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 0.946 0.973 ]);\nfprintf" "('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\nfprintf('','COMMENT: end icon te" "xt');color('red');\nplot(swLineX,simSwLineY);\ncolor('black');\nplot(swLineX,hwSwLineY);\n" } Block { BlockType SubSystem Name "Sim-only\nGateway In" SID "339" Ports [1, 1] Position [305, 260, 350, 280] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "Sim-only\nGateway In" Location [269, 280, 494, 362] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" SID "340" Position [20, 33, 50, 47] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Disregard Subsystem" SID "341" Tag "discardX" Ports [] Position [86, 85, 144, 143] ShowName off AttributesFormatString "Disregard Subsystem\\nFor Generation" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Disregard Subsystem" SourceType "Xilinx Disregard Subsystem For Generation Block" infoedit "Place this block into a subsystem to have System Generator ignore the subsystem during code ge" "neration. This block can be used in combination with the Simulation Multiplexer block to provide an alternative" " simulation model for another subsystem (e.g., to provide a simulation model for a black box)." has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "disregard" block_version "10.1.3" sg_icon_stat "58,58,-1,-1,darkgray,black,0,0,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 58 58 0 ],[0 0 58 58 ],[0.1 0.1 0." "1]);\npatch([14 4 18 4 14 29 33 37 53 40 28 19 33 19 28 40 53 37 33 29 14 ],[6 16 30 44 54 54 50 54 54 41 53 44" " 30 16 7 19 6 6 10 6 6 ],[0.33 0.33 0.33]);\nplot([0 58 58 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end ico" "n graphics');\nfprintf('','COMMENT: begin icon text');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Gateway In" SID "342" Ports [1, 1] Position [80, 30, 145, 50] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, double and fixed point to Xilinx" " fixed point type.

Hardware notes: In hardware these blocks become top level input ports." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0 0 0 0 1 0 0]" inherit_from_input off UseAsADC off ADCChannel "'1'" hdl_port "on" has_advanced_control "0" sggui_pos "20,20,348,406" block_type "gatewayin" block_version "10.1.3" sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0" ".93 0.65 ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[1" "2.22 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.2" "2 12.22 12.22 10.22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.2" "2 ],[1 1 1 ]);\npatch([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985" " 0.979 0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' " "');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "343" Position [170, 33, 200, 47] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "Gateway In" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "D" SrcPort 1 DstBlock "Gateway In" DstPort 1 } } } Block { BlockType SubSystem Name "Sim-only\nGateway In2" SID "344" Ports [1, 1] Position [360, 575, 405, 595] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "Sim-only\nGateway In2" Location [214, 70, 1918, 1152] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" SID "345" Position [20, 33, 50, 47] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Disregard Subsystem" SID "346" Tag "discardX" Ports [] Position [71, 110, 129, 168] ShowName off AttributesFormatString "Disregard Subsystem\\nFor Generation" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Disregard Subsystem" SourceType "Xilinx Disregard Subsystem For Generation Block" infoedit "Place this block into a subsystem to have System Generator ignore the subsystem during code ge" "neration. This block can be used in combination with the Simulation Multiplexer block to provide an alternative" " simulation model for another subsystem (e.g., to provide a simulation model for a black box)." has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "disregard" block_version "10.1.3" sg_icon_stat "58,58,-1,-1,darkgray,black,0,0,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 58 58 0 ],[0 0 58 58 ],[0.1 0.1 0." "1]);\npatch([14 4 18 4 14 29 33 37 53 40 28 19 33 19 28 40 53 37 33 29 14 ],[6 16 30 44 54 54 50 54 54 41 53 44" " 30 16 7 19 6 6 10 6 6 ],[0.33 0.33 0.33]);\nplot([0 58 58 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end ico" "n graphics');\nfprintf('','COMMENT: begin icon text');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Gateway In" SID "347" Ports [1, 1] Position [80, 30, 145, 50] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, double and fixed point to Xilinx" " fixed point type.

Hardware notes: In hardware these blocks become top level input ports." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0 0 0 0 1 0 0]" inherit_from_input off UseAsADC off ADCChannel "'1'" hdl_port "on" has_advanced_control "0" sggui_pos "20,20,348,406" block_type "gatewayin" block_version "10.1.3" sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0" ".93 0.65 ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[1" "2.22 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.2" "2 12.22 12.22 10.22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.2" "2 ],[1 1 1 ]);\npatch([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985" " 0.979 0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' " "');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "348" Position [170, 33, 200, 47] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "D" SrcPort 1 DstBlock "Gateway In" DstPort 1 } Line { SrcBlock "Gateway In" SrcPort 1 DstBlock "Q" DstPort 1 } } } Block { BlockType SubSystem Name "negedge" SID "349" Ports [1, 1] Position [495, 288, 525, 302] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "negedge" Location [459, 339, 854, 490] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "In" SID "350" Position [170, 213, 200, 227] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Delay" SID "351" Ports [1, 1] Position [230, 247, 290, 303] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p. If register retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "8.2" sg_icon_stat "60,56,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.8" "8 36.88 44.88 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.8" "8 36.88 28.88 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1" " 1 1 ]);\npatch([20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0" ".946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('" "black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "352" Ports [1, 1] Position [290, 191, 345, 249] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "8.2" sg_icon_stat "55,58,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 58 58 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ]" ",[36.77 36.77 43.77 36.77 43.77 43.77 43.77 36.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[29.7" "7 29.77 36.77 36.77 29.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[22.77 22.77 29.7" "7 29.77 22.77 ],[1 1 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[15.77 15.77 22.77 15.77 22.7" "7 22.77 15.77 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin i" "con text');\n\n\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical" SID "353" Ports [2, 1] Position [410, 205, 465, 265] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "8.2" sg_icon_stat "55,60,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 60 60 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ]" ",[37.77 37.77 44.77 37.77 44.77 44.77 44.77 37.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[30.7" "7 30.77 37.77 37.77 30.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[23.77 23.77 30.7" "7 30.77 23.77 ],[1 1 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[16.77 16.77 23.77 16.77 23.7" "7 23.77 16.77 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin i" "con text');\n\n\n\ncolor('black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Out" SID "354" Position [490, 228, 520, 242] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical" DstPort 1 } Line { SrcBlock "Delay" SrcPort 1 Points [90, 0; 0, -25] DstBlock "Logical" DstPort 2 } Line { SrcBlock "In" SrcPort 1 Points [5, 0] Branch { DstBlock "Inverter" DstPort 1 } Branch { Points [0, 55] DstBlock "Delay" DstPort 1 } } Line { SrcBlock "Logical" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "posedge" SID "355" Ports [1, 1] Position [495, 273, 525, 287] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "posedge" Location [459, 339, 854, 490] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "In" SID "356" Position [20, 33, 50, 47] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Delay" SID "357" Ports [1, 1] Position [80, 67, 140, 123] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p. If register retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "8.2" sg_icon_stat "60,56,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.8" "8 36.88 44.88 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.8" "8 36.88 28.88 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1" " 1 1 ]);\npatch([20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0" ".946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('" "black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "358" Ports [1, 1] Position [170, 66, 225, 124] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "8.2" sg_icon_stat "55,58,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 58 58 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ]" ",[36.77 36.77 43.77 36.77 43.77 43.77 43.77 36.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[29.7" "7 29.77 36.77 36.77 29.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[22.77 22.77 29.7" "7 29.77 22.77 ],[1 1 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[15.77 15.77 22.77 15.77 22.7" "7 22.77 15.77 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin i" "con text');\n\n\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical" SID "359" Ports [2, 1] Position [260, 25, 315, 85] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "8.2" sg_icon_stat "55,60,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 60 60 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ]" ",[37.77 37.77 44.77 37.77 44.77 44.77 44.77 37.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[30.7" "7 30.77 37.77 37.77 30.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[23.77 23.77 30.7" "7 30.77 23.77 ],[1 1 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[16.77 16.77 23.77 16.77 23.7" "7 23.77 16.77 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin i" "con text');\n\n\n\ncolor('black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Out" SID "360" Position [340, 48, 370, 62] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "Logical" SrcPort 1 Points [0, 0] DstBlock "Out" DstPort 1 } Line { SrcBlock "In" SrcPort 1 Points [0, 0; 5, 0] Branch { Points [0, 55] DstBlock "Delay" DstPort 1 } Branch { DstBlock "Logical" DstPort 1 } } Line { SrcBlock "Inverter" SrcPort 1 Points [5, 0; 0, -25] DstBlock "Logical" DstPort 2 } Line { SrcBlock "Delay" SrcPort 1 Points [0, 0] DstBlock "Inverter" DstPort 1 } } } Block { BlockType SubSystem Name "posedge2" SID "361" Ports [1, 1] Position [495, 323, 525, 337] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "posedge2" Location [459, 339, 854, 490] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "In" SID "362" Position [20, 33, 50, 47] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Delay" SID "363" Ports [1, 1] Position [80, 67, 140, 123] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p. If register retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "8.2" sg_icon_stat "60,56,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.8" "8 36.88 44.88 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.8" "8 36.88 28.88 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1" " 1 1 ]);\npatch([20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0" ".946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('" "black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "364" Ports [1, 1] Position [170, 66, 225, 124] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "8.2" sg_icon_stat "55,58,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 58 58 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ]" ",[36.77 36.77 43.77 36.77 43.77 43.77 43.77 36.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[29.7" "7 29.77 36.77 36.77 29.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[22.77 22.77 29.7" "7 29.77 22.77 ],[1 1 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[15.77 15.77 22.77 15.77 22.7" "7 22.77 15.77 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin i" "con text');\n\n\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical" SID "365" Ports [2, 1] Position [260, 25, 315, 85] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "8.2" sg_icon_stat "55,60,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 60 60 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ]" ",[37.77 37.77 44.77 37.77 44.77 44.77 44.77 37.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[30.7" "7 30.77 37.77 37.77 30.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[23.77 23.77 30.7" "7 30.77 23.77 ],[1 1 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[16.77 16.77 23.77 16.77 23.7" "7 23.77 16.77 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin i" "con text');\n\n\n\ncolor('black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Out" SID "366" Position [340, 48, 370, 62] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "Logical" SrcPort 1 Points [0, 0] DstBlock "Out" DstPort 1 } Line { SrcBlock "In" SrcPort 1 Points [0, 0; 5, 0] Branch { Points [0, 55] DstBlock "Delay" DstPort 1 } Branch { DstBlock "Logical" DstPort 1 } } Line { SrcBlock "Inverter" SrcPort 1 Points [5, 0; 0, -25] DstBlock "Logical" DstPort 2 } Line { SrcBlock "Delay" SrcPort 1 Points [0, 0] DstBlock "Inverter" DstPort 1 } } } Block { BlockType Outport Name "done" SID "367" Position [1350, 268, 1380, 282] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Outport Name "running" SID "368" Position [1245, 518, 1275, 532] Port "2" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Outport Name "paused" SID "369" Position [1240, 463, 1270, 477] Port "3" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Outport Name "timeLeft" SID "370" Position [1285, 358, 1315, 372] Port "4" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "Delay" SrcPort 1 Points [195, 0; 0, -75] DstBlock "Logical7" DstPort 3 } Line { SrcBlock "S-R_Latch3" SrcPort 1 Points [70, 0; 0, -50; 350, 0; 0, 95] DstBlock "Logical7" DstPort 1 } Line { SrcBlock "Logical7" SrcPort 1 DstBlock "S-R_Latch2" DstPort 1 } Line { SrcBlock "Sim-only\nGateway In2" SrcPort 1 DstBlock "Sim Mux1" DstPort 1 } Line { SrcBlock "Constant4" SrcPort 1 DstBlock "Sim-only\nGateway In2" DstPort 1 } Line { SrcBlock "Logical2" SrcPort 1 DstBlock "S-R_Latch1" DstPort 2 } Line { SrcBlock "posedge2" SrcPort 1 Points [25, 0; 0, -15] DstBlock "Logical2" DstPort 1 } Line { SrcBlock "Constant2" SrcPort 1 DstBlock "Sim-only\nGateway In" DstPort 1 } Line { SrcBlock "Sim Mux1" SrcPort 1 Points [60, 0] Branch { Points [260, 0; 0, -250] Branch { DstBlock "Delay" DstPort 1 } Branch { DstBlock "Logical6" DstPort 3 } } Branch { DstBlock "Inverter1" DstPort 1 } } Line { SrcBlock "Convert1" SrcPort 1 Points [25, 0; 0, -75] DstBlock "Sim Mux1" DstPort 2 } Line { SrcBlock "Logical6" SrcPort 1 DstBlock "Counter" DstPort 2 } Line { SrcBlock "Inverter1" SrcPort 1 DstBlock "Logical5" DstPort 2 } Line { SrcBlock "Relational2" SrcPort 1 Points [20, 0; 0, -60; -295, 0] Branch { Points [0, -320] DstBlock "Logical6" DstPort 2 } Branch { DstBlock "Logical5" DstPort 1 } } Line { SrcBlock "Logical5" SrcPort 1 DstBlock "Counter1" DstPort 1 } Line { SrcBlock "Counter1" SrcPort 1 DstBlock "Relational2" DstPort 2 } Line { SrcBlock "slotTime" SrcPort 1 DstBlock "Relational2" DstPort 1 } Line { SrcBlock "Sim-only\nGateway In" SrcPort 1 DstBlock "Sim Mux" DstPort 1 } Line { SrcBlock "pause" SrcPort 1 Points [115, 0] Branch { Points [0, -35] DstBlock "negedge" DstPort 1 } Branch { DstBlock "posedge2" DstPort 1 } } Line { SrcBlock "negedge" SrcPort 1 DstBlock "Logical3" DstPort 2 } Line { SrcBlock "Logical3" SrcPort 1 DstBlock "S-R_Latch1" DstPort 1 } Line { SrcBlock "posedge" SrcPort 1 Points [15, 0] Branch { Points [0, -25] Branch { Points [0, -70] DstBlock "S-R_Latch3" DstPort 1 } Branch { DstBlock "Logical1" DstPort 2 } } Branch { Points [0, 400] DstBlock "Logical5" DstPort 3 } Branch { DstBlock "Logical3" DstPort 1 } } Line { SrcBlock "done_reset" SrcPort 1 Points [15, 0] Branch { Points [0, -145; -625, 0; 0, 75] DstBlock "S-R_Latch3" DstPort 2 } Branch { DstBlock "S-R_Latch2" DstPort 2 } } Line { SrcBlock "Relational" SrcPort 1 Points [10, 0] Branch { DstBlock "Logical7" DstPort 2 } Branch { Points [0, -80; -290, 0; 0, 60] DstBlock "Logical1" DstPort 1 } Branch { Points [0, 110; -550, 0; 0, -40] DstBlock "Logical2" DstPort 2 } } Line { SrcBlock "S-R_Latch2" SrcPort 1 DstBlock "done" DstPort 1 } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Counter" DstPort 1 } Line { SrcBlock "Counter" SrcPort 1 Points [0, 0] Branch { Points [0, 100] Branch { DstBlock "AddSub" DstPort 2 } Branch { Points [0, 65] DstBlock "Relational1" DstPort 1 } } Branch { Labels [1, 0] DstBlock "Relational" DstPort 2 } } Line { SrcBlock "slotCount" SrcPort 1 Points [10, 0] Branch { DstBlock "Relational" DstPort 1 } Branch { Points [0, 105] DstBlock "AddSub" DstPort 1 } } Line { SrcBlock "S-R_Latch1" SrcPort 1 Points [25, 0] Branch { Points [0, -20] DstBlock "Logical6" DstPort 1 } Branch { Points [0, 175] Branch { Points [290, 0] Branch { Points [0, 40] DstBlock "running" DstPort 1 } Branch { DstBlock "Inverter" DstPort 1 } } Branch { Points [0, 235] DstBlock "Counter1" DstPort 2 } } } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical4" DstPort 2 } Line { SrcBlock "Relational1" SrcPort 1 DstBlock "Logical4" DstPort 1 } Line { SrcBlock "Constant" SrcPort 1 DstBlock "Relational1" DstPort 2 } Line { SrcBlock "AddSub" SrcPort 1 DstBlock "timeLeft" DstPort 1 } Line { SrcBlock "Sim Mux" SrcPort 1 DstBlock "posedge" DstPort 1 } Line { SrcBlock "start" SrcPort 1 DstBlock "Sim Mux" DstPort 2 } Line { SrcBlock "Logical4" SrcPort 1 DstBlock "paused" DstPort 1 } Line { SrcBlock "Mux" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Medium Idle" SrcPort 1 DstBlock "Mux" DstPort 3 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Mux" DstPort 2 } Line { SrcBlock "mode" SrcPort 1 DstBlock "Mux" DstPort 1 } Annotation { Name "This SR latch handles the case of a zero-slot-count\ntimer event. When the user code sets the slotCount t" "o 0,\nthe comparison is immedilatey true. The timer done\nsignal then asserts when:\nif(carrier sensing) after IDLE" " AND\nafter user asserts start\nDone de-assets when the user clears the done bit\n*but does not re-assert* until th" "e next user-initiated start." Position [697, 92] } } } Block { BlockType SubSystem Name "Timer 2" SID "371" Ports [7, 4] Position [335, 350, 440, 470] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "Timer 2" Location [214, 74, 1910, 1156] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "start" SID "372" Position [310, 283, 340, 297] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "pause" SID "373" Position [310, 323, 340, 337] Port "2" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "mode" SID "374" Position [255, 648, 285, 662] NamePlacement "alternate" Port "3" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "done_reset" SID "375" Position [1175, 283, 1205, 297] Port "4" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "slotCount" SID "376" Position [980, 238, 1010, 252] NamePlacement "alternate" Port "5" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "slotTime" SID "377" Position [930, 658, 960, 672] Port "6" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "Medium Idle" SID "378" Position [250, 698, 280, 712] Port "7" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "AddSub" SID "379" Ports [2, 1] Position [1210, 339, 1255, 386] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Subtraction" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Unsigned" n_bits "32" bin_pt "0" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL off hw_selection "Fabric" pipelined off xl_use_area off xl_area "[16 0 0 32 0 0 0]" use_rpm "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" block_version "8.2" sg_icon_stat "45,47,2,1,white,blue,0,32e1f85f,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 47 47 0 ],[0.77 0.82 0.91" " ]);\nplot([0 45 45 0 0 ],[0 0 47 47 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[29.66 29.66 35." "66 29.66 35.66 35.66 35.66 29.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[23.66 23.66 29.66 29.66 23.66" " ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[17.66 17.66 23.66 23.66 17.66 ],[1 1 1 ]);\npatch(" "[14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[11.66 11.66 17.66 11.66 17.66 17.66 11.66 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'" ",1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bf{a - b}','texmode','" "on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant" SID "380" Ports [0, 1] Position [940, 454, 970, 466] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "50,50,400,346" block_type "constant" block_version "10.1.2" sg_icon_stat "30,12,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 12 12 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 12 12 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ],[7.11 7.11 " "8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[6.11 6.11 7.11 7.11 6.11 ],[" "0.931 0.946 0.973 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch([13." "775 17.22 16.22 15.22 14.22 12.775 13.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.931 0.946 0.973 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'0'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant1" SID "381" Ports [0, 1] Position [255, 672, 290, 688] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "8.2" sg_icon_stat "35,16,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 16 16 0 ],[0.77 0.82 0.91" " ]);\nplot([0 35 35 0 0 ],[0 0 16 16 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[10.22 10.22 1" "2.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[8.22 8.22 10.22 10.22 8.22" " ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatch([14" ".55 21.44 19.44 17.44 15.44 12.55 14.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprintf(''," "'COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Constant Name "Constant2" SID "382" Position [260, 261, 275, 279] ShowName off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Constant Name "Constant4" SID "383" Position [315, 576, 330, 594] ShowName off Value "0" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Convert1" SID "384" Ports [1, 1] Position [380, 670, 415, 690] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "16" bin_pt "14" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,461,375" block_type "convert" block_version "8.2" sg_icon_stat "35,20,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.91" " ]);\nplot([0 35 35 0 0 ],[0 0 20 20 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output'," "1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Counter" SID "385" Ports [2, 1] Position [905, 224, 965, 326] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited counter is" " implemented by combining a counter with a comparator." cnt_type "Free Running" cnt_to "Inf" operation "Up" start_count "0" cnt_by_val "1" arith_type "Unsigned" n_bits "32" bin_pt "0" load_pin off rst on en on explicit_period "on" period "1" dbl_ovrd off use_behavioral_HDL off implementation "Fabric" xl_use_area off xl_area "[17 32 0 32 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,356,630" block_type "counter" block_version "8.2" sg_icon_stat "60,102,2,1,white,blue,0,ae3608d6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 102 102 0 ],[0.77 0.82 0." "91 ]);\nplot([0 60 60 0 0 ],[0 0 102 102 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[59.88 59.88 " "67.88 59.88 67.88 67.88 67.88 59.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[51.88 51.88 59.88 59.88 51.8" "8 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[43.88 43.88 51.88 51.88 43.88 ],[1 1 1 ]);\npatch(" "[20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[35.88 35.88 43.88 35.88 43.88 43.88 35.88 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'rst');\ncolor('black');port_label('input',2,'en');\n\ncolor('black');disp('{\\fontsize{14}\\bf++}','texmode','on'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Counter1" SID "386" Ports [2, 1] Position [835, 644, 895, 746] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited counter is" " implemented by combining a counter with a comparator." cnt_type "Free Running" cnt_to "Inf" operation "Up" start_count "0" cnt_by_val "1" arith_type "Unsigned" n_bits "16" bin_pt "0" load_pin off rst on en on explicit_period "on" period "1" dbl_ovrd off use_behavioral_HDL off implementation "Fabric" xl_use_area off xl_area "[17 32 0 32 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,356,630" block_type "counter" block_version "8.2" sg_icon_stat "60,102,2,1,white,blue,0,ae3608d6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 102 102 0 ],[0.77 0.82 0." "91 ]);\nplot([0 60 60 0 0 ],[0 0 102 102 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[59.88 59.88 " "67.88 59.88 67.88 67.88 67.88 59.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[51.88 51.88 59.88 59.88 51.8" "8 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[43.88 43.88 51.88 51.88 43.88 ],[1 1 1 ]);\npatch(" "[20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[35.88 35.88 43.88 35.88 43.88 43.88 35.88 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'rst');\ncolor('black');port_label('input',2,'en');\n\ncolor('black');disp('{\\fontsize{14}\\bf++}','texmode','on'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay" SID "387" Ports [1, 1] Position [925, 331, 950, 359] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "10.1.3" sg_icon_stat "25,28,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 28 28 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 28 28 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 17.33 20" ".33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33 17.33 14.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-1}','t" "exmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "388" Ports [1, 1] Position [1080, 476, 1125, 494] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "10.1.2" sg_icon_stat "45,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.91" " ]);\nplot([0 45 45 0 0 ],[0 0 18 18 0 ]);\npatch([17.55 20.44 22.44 24.44 26.44 22.44 19.55 17.55 ],[11.22 11.22 1" "3.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([19.55 22.44 20.44 17.55 19.55 ],[9.22 9.22 11.22 11.22 9.22" " ],[0.931 0.946 0.973 ]);\npatch([17.55 20.44 22.44 19.55 17.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([19" ".55 26.44 24.44 22.44 20.44 17.55 19.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf(''," "'COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nfprintf('" "','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter1" SID "389" Ports [1, 1] Position [590, 661, 635, 679] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "10.1.2" sg_icon_stat "45,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.91" " ]);\nplot([0 45 45 0 0 ],[0 0 18 18 0 ]);\npatch([17.55 20.44 22.44 24.44 26.44 22.44 19.55 17.55 ],[11.22 11.22 1" "3.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([19.55 22.44 20.44 17.55 19.55 ],[9.22 9.22 11.22 11.22 9.22" " ],[0.931 0.946 0.973 ]);\npatch([17.55 20.44 22.44 19.55 17.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([19" ".55 26.44 24.44 22.44 20.44 17.55 19.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf(''," "'COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nfprintf('" "','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "390" Ports [2, 1] Position [855, 231, 885, 264] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "9.1.01" sg_icon_stat "30,33,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 33 33 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 33 33 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[20.44 20.44 24.44 " "20.44 24.44 24.44 24.44 20.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[16.44 16.44 20.44 20.44 16.44 ],[0." "931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[12.44 12.44 16.44 16.44 12.44 ],[1 1 1 ]);\npatch([10.1 23." "88 19.88 15.88 11.88 6.1 10.1 ],[8.44 8.44 12.44 8.44 12.44 12.44 8.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('or');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "Logical2" SID "391" Ports [2, 1] Position [590, 306, 620, 339] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "9.1.01" sg_icon_stat "30,33,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 33 33 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 33 33 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[20.44 20.44 24.44 " "20.44 24.44 24.44 24.44 20.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[16.44 16.44 20.44 20.44 16.44 ],[0." "931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[12.44 12.44 16.44 16.44 12.44 ],[1 1 1 ]);\npatch([10.1 23." "88 19.88 15.88 11.88 6.1 10.1 ],[8.44 8.44 12.44 8.44 12.44 12.44 8.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('or');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "Logical3" SID "392" Ports [2, 1] Position [590, 271, 620, 304] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "9.1.01" sg_icon_stat "30,33,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 33 33 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 33 33 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[20.44 20.44 24.44 " "20.44 24.44 24.44 24.44 20.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[16.44 16.44 20.44 20.44 16.44 ],[0." "931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[12.44 12.44 16.44 16.44 12.44 ],[1 1 1 ]);\npatch([10.1 23." "88 19.88 15.88 11.88 6.1 10.1 ],[8.44 8.44 12.44 8.44 12.44 12.44 8.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('or');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "Logical4" SID "393" Ports [2, 1] Position [1155, 433, 1200, 502] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "10.1.2" sg_icon_stat "45,69,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 69 69 0 ],[0.77 0.82 0.91" " ]);\nplot([0 45 45 0 0 ],[0 0 69 69 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[40.66 40.66 46." "66 40.66 46.66 46.66 46.66 40.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[34.66 34.66 40.66 40.66 34.66" " ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[28.66 28.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch(" "[14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 22.66 28.66 28.66 22.66 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('and');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical5" SID "394" Ports [3, 1] Position [770, 652, 805, 688] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "3" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,261" block_type "logical" block_version "8.2" sg_icon_stat "35,36,3,1,white,blue,0,a2abe52d,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 36 36 0 ],[0.77 0.82 0.91" " ]);\nplot([0 35 35 0 0 ],[0 0 36 36 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[23.55 23.55 28.55" " 23.55 28.55 28.55 28.55 23.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[18.55 18.55 23.55 23.55 18.55 " "],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[13.55 13.55 18.55 18.55 13.55 ],[1 1 1 ]);\npatch(" "[10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[8.55 8.55 13.55 8.55 13.55 13.55 8.55 ],[0.931 0.946 0.973 ]);\nfprintf" "('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n\ncolor('black');disp('or');\nfp" "rintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical6" SID "395" Ports [3, 1] Position [850, 282, 885, 318] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "3" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,261" block_type "logical" block_version "8.2" sg_icon_stat "35,36,3,1,white,blue,0,98d76266,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 36 36 0 ],[0.77 0.82 0.91" " ]);\nplot([0 35 35 0 0 ],[0 0 36 36 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[23.55 23.55 28.55" " 23.55 28.55 28.55 28.55 23.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[18.55 18.55 23.55 23.55 18.55 " "],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[13.55 13.55 18.55 18.55 13.55 ],[1 1 1 ]);\npatch(" "[10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[8.55 8.55 13.55 8.55 13.55 13.55 8.55 ],[0.931 0.946 0.973 ]);\nfprintf" "('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n\ncolor('black');disp('and');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical7" SID "396" Ports [3, 1] Position [1175, 243, 1205, 277] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "3" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,261" block_type "logical" block_version "9.1.01" sg_icon_stat "30,34,3,1,white,blue,0,98d76266,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 34 34 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 34 34 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[21.44 21.44 25.44 " "21.44 25.44 25.44 25.44 21.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[17.44 17.44 21.44 21.44 17.44 ],[0." "931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[13.44 13.44 17.44 17.44 13.44 ],[1 1 1 ]);\npatch([10.1 23." "88 19.88 15.88 11.88 6.1 10.1 ],[9.44 9.44 13.44 9.44 13.44 13.44 9.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n\ncolor('black');disp('and');\nfprintf('','" "COMMENT: end icon text');\n" } Block { BlockType Reference Name "Mux" SID "397" Ports [3, 1] Position [320, 643, 345, 717] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" block_version "8.2" sg_icon_stat "25,74,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 10.5714 63.4286 74 0 ],[0.7" "7 0.82 0.91 ]);\nplot([0 25 25 0 0 ],[0 10.5714 63.4286 74 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5" ".325 ],[40.33 40.33 43.33 40.33 43.33 43.33 43.33 40.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[37.33 " "37.33 40.33 40.33 37.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[34.33 34.33 37.33 37.33 34" ".33 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[31.33 31.33 34.33 31.33 34.33 34.33 31.33 ],[0" ".931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('input',3" ",'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational" SID "398" Ports [2, 1] Position [1060, 231, 1100, 289] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a<=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[8 0 0 16 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "relational" block_version "8.2" sg_icon_stat "40,58,2,1,white,blue,0,52e4b236,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 58 58 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 58 58 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[34.55 34.55 39.55" " 34.55 39.55 39.55 39.55 34.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[29.55 29.55 34.55 34.55 29.55 " "],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[24.55 24.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch(" "[13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[19.55 19.55 24.55 19.55 24.55 24.55 19.55 ],[0.931 0.946 0.973 ]);\nfpr" "intf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa \\leq b','texmode'," "'on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational1" SID "399" Ports [2, 1] Position [1005, 431, 1050, 469] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a>b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[16 1 0 32 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "relational" block_version "10.1.2" sg_icon_stat "45,38,2,1,white,blue,0,b5131c97,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 38 38 0 ],[0.77 0.82 0.91" " ]);\nplot([0 45 45 0 0 ],[0 0 38 38 0 ]);\npatch([10.875 18.1 23.1 28.1 33.1 23.1 15.875 10.875 ],[24.55 24.55 29." "55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([15.875 23.1 18.1 10.875 15.875 ],[19.55 19.55 24.55 24.55 19." "55 ],[0.931 0.946 0.973 ]);\npatch([10.875 18.1 23.1 15.875 10.875 ],[14.55 14.55 19.55 19.55 14.55 ],[1 1 1 ]);\np" "atch([15.875 33.1 28.1 23.1 18.1 10.875 15.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input" "',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa > b','texmode','o" "n');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational2" SID "400" Ports [2, 1] Position [985, 651, 1025, 709] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a<=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[8 0 0 16 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "relational" block_version "8.2" sg_icon_stat "40,58,2,1,white,blue,0,52e4b236,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 58 58 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 58 58 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[34.55 34.55 39.55" " 34.55 39.55 39.55 39.55 34.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[29.55 29.55 34.55 34.55 29.55 " "],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[24.55 24.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch(" "[13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[19.55 19.55 24.55 19.55 24.55 24.55 19.55 ],[0.931 0.946 0.973 ]);\nfpr" "intf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa \\leq b','texmode'," "'on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "S-R_Latch1" SID "401" Ports [2, 1] Position [665, 272, 705, 343] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "S-R_Latch1" Location [202, 70, 1438, 850] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "S" SID "402" Position [95, 58, 125, 72] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "R" SID "403" Position [95, 88, 125, 102] Port "2" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Inverter" SID "404" Ports [1, 1] Position [220, 82, 250, 108] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "30,26,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[" "16.33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 1" "3.33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13." "33 10.33 ],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7" ".33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text')" ";\n\n\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register" SID "405" Ports [3, 1] Position [150, 70, 195, 120] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,50,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 50 50 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 50 50 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[31." "66 31.66 37.66 31.66 37.66 37.66 37.66 31.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[25.66 25.66 3" "1.66 31.66 25.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[19.66 19.66 25.66 25.66 19.66 " "],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[13.66 13.66 19.66 13.66 19.66 19.66 13.66 ],[0" ".931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor" "('black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('i" "nput',3,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfpri" "ntf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "406" Position [285, 63, 315, 77] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "R" SrcPort 1 DstBlock "Register" DstPort 2 } Line { SrcBlock "S" SrcPort 1 DstBlock "Register" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 Points [10, 0; 0, 55; -130, 0] DstBlock "Register" DstPort 3 } Line { SrcBlock "Register" SrcPort 1 Points [0, 0; 5, 0] Branch { Points [0, -25] DstBlock "Q" DstPort 1 } Branch { DstBlock "Inverter" DstPort 1 } } } } Block { BlockType SubSystem Name "S-R_Latch2" SID "407" Ports [2, 1] Position [1285, 245, 1325, 305] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "S-R_Latch2" Location [521, 318, 918, 591] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "S" SID "408" Position [95, 58, 125, 72] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "R" SID "409" Position [95, 88, 125, 102] Port "2" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Inverter" SID "410" Ports [1, 1] Position [220, 82, 250, 108] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "30,26,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[" "16.33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 1" "3.33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13." "33 10.33 ],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7" ".33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text')" ";\n\n\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register" SID "411" Ports [3, 1] Position [150, 70, 195, 120] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,50,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 50 50 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 50 50 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[31." "66 31.66 37.66 31.66 37.66 37.66 37.66 31.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[25.66 25.66 3" "1.66 31.66 25.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[19.66 19.66 25.66 25.66 19.66 " "],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[13.66 13.66 19.66 13.66 19.66 19.66 13.66 ],[0" ".931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor" "('black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('i" "nput',3,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfpri" "ntf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "412" Position [285, 63, 315, 77] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "Register" SrcPort 1 Points [0, 0; 5, 0] Branch { DstBlock "Inverter" DstPort 1 } Branch { Points [0, -25] DstBlock "Q" DstPort 1 } } Line { SrcBlock "Inverter" SrcPort 1 Points [10, 0; 0, 55; -130, 0] DstBlock "Register" DstPort 3 } Line { SrcBlock "S" SrcPort 1 DstBlock "Register" DstPort 1 } Line { SrcBlock "R" SrcPort 1 DstBlock "Register" DstPort 2 } } } Block { BlockType SubSystem Name "S-R_Latch3" SID "413" Ports [2, 1] Position [665, 167, 705, 238] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "S-R_Latch3" Location [202, 70, 1438, 850] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "S" SID "414" Position [95, 58, 125, 72] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "R" SID "415" Position [95, 88, 125, 102] Port "2" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Inverter" SID "416" Ports [1, 1] Position [220, 82, 250, 108] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "30,26,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[" "16.33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 1" "3.33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13." "33 10.33 ],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7" ".33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text')" ";\n\n\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register" SID "417" Ports [3, 1] Position [150, 70, 195, 120] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,50,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 50 50 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 50 50 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[31." "66 31.66 37.66 31.66 37.66 37.66 37.66 31.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[25.66 25.66 3" "1.66 31.66 25.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[19.66 19.66 25.66 25.66 19.66 " "],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[13.66 13.66 19.66 13.66 19.66 19.66 13.66 ],[0" ".931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor" "('black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('i" "nput',3,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfpri" "ntf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "418" Position [285, 63, 315, 77] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "Register" SrcPort 1 Points [0, 0; 5, 0] Branch { DstBlock "Inverter" DstPort 1 } Branch { Points [0, -25] DstBlock "Q" DstPort 1 } } Line { SrcBlock "Inverter" SrcPort 1 Points [10, 0; 0, 55; -130, 0] DstBlock "Register" DstPort 3 } Line { SrcBlock "S" SrcPort 1 DstBlock "Register" DstPort 1 } Line { SrcBlock "R" SrcPort 1 DstBlock "Register" DstPort 2 } } } Block { BlockType Reference Name "Sim Mux" SID "420" Ports [2, 1] Position [405, 261, 445, 299] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Simulation Multiplexer" SourceType "Xilinx Simulation Multiplexer Block" infoedit "Distinguish input subsystems as \"simulation only\" and \"generation only\". The input specified For " "Simulation will be used during Simulink simulation. The input specified For Generation will be used during code ge" "neration. This block will typically be used on the output of a HW Co-Simulation, Black Box, or ModelSim subsystem." "

Hardware Notes: This block costs nothing." sim_sel "1" hw_sel "2" has_advanced_control "0" sggui_pos "20,20,336,197" block_type "simmux" block_version "10.1.3" sg_icon_stat "40,38,2,1,white,blue,0,4170dd71,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 38 38 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 38 38 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[24.55 24.55 29.55" " 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[19.55 19.55 24.55 24.55 19.55 " "],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[14.55 14.55 19.55 19.55 14.55 ],[1 1 1 ]);\npatch(" "[13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 0.946 0.973 ]);\nfprintf" "('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\nfprintf('','COMMENT: end icon te" "xt');color('red');\nplot(swLineX,simSwLineY);\ncolor('black');\nplot(swLineX,hwSwLineY);\n" } Block { BlockType Reference Name "Sim Mux1" SID "421" Ports [2, 1] Position [470, 576, 510, 614] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Simulation Multiplexer" SourceType "Xilinx Simulation Multiplexer Block" infoedit "Distinguish input subsystems as \"simulation only\" and \"generation only\". The input specified For " "Simulation will be used during Simulink simulation. The input specified For Generation will be used during code ge" "neration. This block will typically be used on the output of a HW Co-Simulation, Black Box, or ModelSim subsystem." "

Hardware Notes: This block costs nothing." sim_sel "1" hw_sel "2" has_advanced_control "0" sggui_pos "20,20,336,197" block_type "simmux" block_version "10.1.3" sg_icon_stat "40,38,2,1,white,blue,0,4170dd71,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 38 38 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 38 38 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[24.55 24.55 29.55" " 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[19.55 19.55 24.55 24.55 19.55 " "],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[14.55 14.55 19.55 19.55 14.55 ],[1 1 1 ]);\npatch(" "[13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 0.946 0.973 ]);\nfprintf" "('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\nfprintf('','COMMENT: end icon te" "xt');color('red');\nplot(swLineX,simSwLineY);\ncolor('black');\nplot(swLineX,hwSwLineY);\n" } Block { BlockType SubSystem Name "Sim-only\nGateway In" SID "422" Ports [1, 1] Position [305, 260, 350, 280] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "Sim-only\nGateway In" Location [269, 280, 494, 362] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" SID "423" Position [20, 33, 50, 47] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Disregard Subsystem" SID "424" Tag "discardX" Ports [] Position [86, 85, 144, 143] ShowName off AttributesFormatString "Disregard Subsystem\\nFor Generation" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Disregard Subsystem" SourceType "Xilinx Disregard Subsystem For Generation Block" infoedit "Place this block into a subsystem to have System Generator ignore the subsystem during code ge" "neration. This block can be used in combination with the Simulation Multiplexer block to provide an alternative" " simulation model for another subsystem (e.g., to provide a simulation model for a black box)." has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "disregard" block_version "10.1.3" sg_icon_stat "58,58,-1,-1,darkgray,black,0,0,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 58 58 0 ],[0 0 58 58 ],[0.1 0.1 0." "1]);\npatch([14 4 18 4 14 29 33 37 53 40 28 19 33 19 28 40 53 37 33 29 14 ],[6 16 30 44 54 54 50 54 54 41 53 44" " 30 16 7 19 6 6 10 6 6 ],[0.33 0.33 0.33]);\nplot([0 58 58 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end ico" "n graphics');\nfprintf('','COMMENT: begin icon text');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Gateway In" SID "425" Ports [1, 1] Position [80, 30, 145, 50] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, double and fixed point to Xilinx" " fixed point type.

Hardware notes: In hardware these blocks become top level input ports." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0 0 0 0 1 0 0]" inherit_from_input off UseAsADC off ADCChannel "'1'" hdl_port "on" has_advanced_control "0" sggui_pos "20,20,348,406" block_type "gatewayin" block_version "10.1.3" sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0" ".93 0.65 ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[1" "2.22 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.2" "2 12.22 12.22 10.22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.2" "2 ],[1 1 1 ]);\npatch([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985" " 0.979 0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' " "');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "426" Position [170, 33, 200, 47] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "D" SrcPort 1 DstBlock "Gateway In" DstPort 1 } Line { SrcBlock "Gateway In" SrcPort 1 DstBlock "Q" DstPort 1 } } } Block { BlockType SubSystem Name "Sim-only\nGateway In2" SID "427" Ports [1, 1] Position [360, 575, 405, 595] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "Sim-only\nGateway In2" Location [214, 70, 1918, 1152] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" SID "428" Position [20, 33, 50, 47] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Disregard Subsystem" SID "429" Tag "discardX" Ports [] Position [71, 110, 129, 168] ShowName off AttributesFormatString "Disregard Subsystem\\nFor Generation" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Disregard Subsystem" SourceType "Xilinx Disregard Subsystem For Generation Block" infoedit "Place this block into a subsystem to have System Generator ignore the subsystem during code ge" "neration. This block can be used in combination with the Simulation Multiplexer block to provide an alternative" " simulation model for another subsystem (e.g., to provide a simulation model for a black box)." has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "disregard" block_version "10.1.3" sg_icon_stat "58,58,-1,-1,darkgray,black,0,0,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 58 58 0 ],[0 0 58 58 ],[0.1 0.1 0." "1]);\npatch([14 4 18 4 14 29 33 37 53 40 28 19 33 19 28 40 53 37 33 29 14 ],[6 16 30 44 54 54 50 54 54 41 53 44" " 30 16 7 19 6 6 10 6 6 ],[0.33 0.33 0.33]);\nplot([0 58 58 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end ico" "n graphics');\nfprintf('','COMMENT: begin icon text');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Gateway In" SID "430" Ports [1, 1] Position [80, 30, 145, 50] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, double and fixed point to Xilinx" " fixed point type.

Hardware notes: In hardware these blocks become top level input ports." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0 0 0 0 1 0 0]" inherit_from_input off UseAsADC off ADCChannel "'1'" hdl_port "on" has_advanced_control "0" sggui_pos "20,20,348,406" block_type "gatewayin" block_version "10.1.3" sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0" ".93 0.65 ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[1" "2.22 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.2" "2 12.22 12.22 10.22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.2" "2 ],[1 1 1 ]);\npatch([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985" " 0.979 0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' " "');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "431" Position [170, 33, 200, 47] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "Gateway In" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "D" SrcPort 1 DstBlock "Gateway In" DstPort 1 } } } Block { BlockType SubSystem Name "negedge" SID "432" Ports [1, 1] Position [495, 288, 525, 302] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "negedge" Location [459, 339, 854, 490] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "In" SID "433" Position [170, 213, 200, 227] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Delay" SID "434" Ports [1, 1] Position [230, 247, 290, 303] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p. If register retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "8.2" sg_icon_stat "60,56,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.8" "8 36.88 44.88 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.8" "8 36.88 28.88 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1" " 1 1 ]);\npatch([20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0" ".946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('" "black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "435" Ports [1, 1] Position [290, 191, 345, 249] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "8.2" sg_icon_stat "55,58,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 58 58 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ]" ",[36.77 36.77 43.77 36.77 43.77 43.77 43.77 36.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[29.7" "7 29.77 36.77 36.77 29.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[22.77 22.77 29.7" "7 29.77 22.77 ],[1 1 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[15.77 15.77 22.77 15.77 22.7" "7 22.77 15.77 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin i" "con text');\n\n\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical" SID "436" Ports [2, 1] Position [410, 205, 465, 265] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "8.2" sg_icon_stat "55,60,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 60 60 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ]" ",[37.77 37.77 44.77 37.77 44.77 44.77 44.77 37.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[30.7" "7 30.77 37.77 37.77 30.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[23.77 23.77 30.7" "7 30.77 23.77 ],[1 1 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[16.77 16.77 23.77 16.77 23.7" "7 23.77 16.77 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin i" "con text');\n\n\n\ncolor('black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Out" SID "437" Position [490, 228, 520, 242] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "Logical" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "In" SrcPort 1 Points [5, 0] Branch { Points [0, 55] DstBlock "Delay" DstPort 1 } Branch { DstBlock "Inverter" DstPort 1 } } Line { SrcBlock "Delay" SrcPort 1 Points [90, 0; 0, -25] DstBlock "Logical" DstPort 2 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical" DstPort 1 } } } Block { BlockType SubSystem Name "posedge" SID "438" Ports [1, 1] Position [495, 273, 525, 287] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "posedge" Location [459, 339, 854, 490] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "In" SID "439" Position [20, 33, 50, 47] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Delay" SID "440" Ports [1, 1] Position [80, 67, 140, 123] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p. If register retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "8.2" sg_icon_stat "60,56,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.8" "8 36.88 44.88 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.8" "8 36.88 28.88 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1" " 1 1 ]);\npatch([20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0" ".946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('" "black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "441" Ports [1, 1] Position [170, 66, 225, 124] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "8.2" sg_icon_stat "55,58,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 58 58 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ]" ",[36.77 36.77 43.77 36.77 43.77 43.77 43.77 36.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[29.7" "7 29.77 36.77 36.77 29.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[22.77 22.77 29.7" "7 29.77 22.77 ],[1 1 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[15.77 15.77 22.77 15.77 22.7" "7 22.77 15.77 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin i" "con text');\n\n\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical" SID "442" Ports [2, 1] Position [260, 25, 315, 85] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "8.2" sg_icon_stat "55,60,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 60 60 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ]" ",[37.77 37.77 44.77 37.77 44.77 44.77 44.77 37.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[30.7" "7 30.77 37.77 37.77 30.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[23.77 23.77 30.7" "7 30.77 23.77 ],[1 1 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[16.77 16.77 23.77 16.77 23.7" "7 23.77 16.77 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin i" "con text');\n\n\n\ncolor('black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Out" SID "443" Position [340, 48, 370, 62] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "Delay" SrcPort 1 Points [0, 0] DstBlock "Inverter" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 Points [5, 0; 0, -25] DstBlock "Logical" DstPort 2 } Line { SrcBlock "In" SrcPort 1 Points [0, 0; 5, 0] Branch { DstBlock "Logical" DstPort 1 } Branch { Points [0, 55] DstBlock "Delay" DstPort 1 } } Line { SrcBlock "Logical" SrcPort 1 Points [0, 0] DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "posedge2" SID "444" Ports [1, 1] Position [495, 323, 525, 337] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "posedge2" Location [459, 339, 854, 490] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "In" SID "445" Position [20, 33, 50, 47] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Delay" SID "446" Ports [1, 1] Position [80, 67, 140, 123] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p. If register retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "8.2" sg_icon_stat "60,56,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.8" "8 36.88 44.88 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.8" "8 36.88 28.88 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1" " 1 1 ]);\npatch([20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0" ".946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('" "black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "447" Ports [1, 1] Position [170, 66, 225, 124] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "8.2" sg_icon_stat "55,58,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 58 58 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ]" ",[36.77 36.77 43.77 36.77 43.77 43.77 43.77 36.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[29.7" "7 29.77 36.77 36.77 29.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[22.77 22.77 29.7" "7 29.77 22.77 ],[1 1 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[15.77 15.77 22.77 15.77 22.7" "7 22.77 15.77 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin i" "con text');\n\n\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical" SID "448" Ports [2, 1] Position [260, 25, 315, 85] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "8.2" sg_icon_stat "55,60,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 60 60 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ]" ",[37.77 37.77 44.77 37.77 44.77 44.77 44.77 37.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[30.7" "7 30.77 37.77 37.77 30.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[23.77 23.77 30.7" "7 30.77 23.77 ],[1 1 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[16.77 16.77 23.77 16.77 23.7" "7 23.77 16.77 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin i" "con text');\n\n\n\ncolor('black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Out" SID "449" Position [340, 48, 370, 62] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "Delay" SrcPort 1 Points [0, 0] DstBlock "Inverter" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 Points [5, 0; 0, -25] DstBlock "Logical" DstPort 2 } Line { SrcBlock "In" SrcPort 1 Points [0, 0; 5, 0] Branch { DstBlock "Logical" DstPort 1 } Branch { Points [0, 55] DstBlock "Delay" DstPort 1 } } Line { SrcBlock "Logical" SrcPort 1 Points [0, 0] DstBlock "Out" DstPort 1 } } } Block { BlockType Outport Name "done" SID "450" Position [1350, 268, 1380, 282] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Outport Name "running" SID "451" Position [1245, 518, 1275, 532] Port "2" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Outport Name "paused" SID "452" Position [1240, 463, 1270, 477] Port "3" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Outport Name "timeLeft" SID "453" Position [1285, 358, 1315, 372] Port "4" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "mode" SrcPort 1 DstBlock "Mux" DstPort 1 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Mux" DstPort 2 } Line { SrcBlock "Medium Idle" SrcPort 1 DstBlock "Mux" DstPort 3 } Line { SrcBlock "Mux" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Logical4" SrcPort 1 DstBlock "paused" DstPort 1 } Line { SrcBlock "start" SrcPort 1 DstBlock "Sim Mux" DstPort 2 } Line { SrcBlock "Sim Mux" SrcPort 1 DstBlock "posedge" DstPort 1 } Line { SrcBlock "AddSub" SrcPort 1 DstBlock "timeLeft" DstPort 1 } Line { SrcBlock "Constant" SrcPort 1 DstBlock "Relational1" DstPort 2 } Line { SrcBlock "Relational1" SrcPort 1 DstBlock "Logical4" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical4" DstPort 2 } Line { SrcBlock "S-R_Latch1" SrcPort 1 Points [25, 0] Branch { Points [0, 175] Branch { Points [0, 235] DstBlock "Counter1" DstPort 2 } Branch { Points [290, 0] Branch { DstBlock "Inverter" DstPort 1 } Branch { Points [0, 40] DstBlock "running" DstPort 1 } } } Branch { Points [0, -20] DstBlock "Logical6" DstPort 1 } } Line { SrcBlock "slotCount" SrcPort 1 Points [10, 0] Branch { Points [0, 105] DstBlock "AddSub" DstPort 1 } Branch { DstBlock "Relational" DstPort 1 } } Line { SrcBlock "Counter" SrcPort 1 Points [0, 0] Branch { Labels [1, 0] DstBlock "Relational" DstPort 2 } Branch { Points [0, 100] Branch { DstBlock "AddSub" DstPort 2 } Branch { Points [0, 65] DstBlock "Relational1" DstPort 1 } } } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Counter" DstPort 1 } Line { SrcBlock "S-R_Latch2" SrcPort 1 DstBlock "done" DstPort 1 } Line { SrcBlock "Relational" SrcPort 1 Points [10, 0] Branch { Points [0, 110; -550, 0; 0, -40] DstBlock "Logical2" DstPort 2 } Branch { Points [0, -80; -290, 0; 0, 60] DstBlock "Logical1" DstPort 1 } Branch { DstBlock "Logical7" DstPort 2 } } Line { SrcBlock "done_reset" SrcPort 1 Points [15, 0] Branch { DstBlock "S-R_Latch2" DstPort 2 } Branch { Points [0, -145; -625, 0; 0, 75] DstBlock "S-R_Latch3" DstPort 2 } } Line { SrcBlock "posedge" SrcPort 1 Points [15, 0] Branch { DstBlock "Logical3" DstPort 1 } Branch { Points [0, 400] DstBlock "Logical5" DstPort 3 } Branch { Points [0, -25] Branch { DstBlock "Logical1" DstPort 2 } Branch { Points [0, -70] DstBlock "S-R_Latch3" DstPort 1 } } } Line { SrcBlock "Logical3" SrcPort 1 DstBlock "S-R_Latch1" DstPort 1 } Line { SrcBlock "negedge" SrcPort 1 DstBlock "Logical3" DstPort 2 } Line { SrcBlock "pause" SrcPort 1 Points [115, 0] Branch { DstBlock "posedge2" DstPort 1 } Branch { Points [0, -35] DstBlock "negedge" DstPort 1 } } Line { SrcBlock "Sim-only\nGateway In" SrcPort 1 DstBlock "Sim Mux" DstPort 1 } Line { SrcBlock "slotTime" SrcPort 1 DstBlock "Relational2" DstPort 1 } Line { SrcBlock "Counter1" SrcPort 1 DstBlock "Relational2" DstPort 2 } Line { SrcBlock "Logical5" SrcPort 1 DstBlock "Counter1" DstPort 1 } Line { SrcBlock "Relational2" SrcPort 1 Points [20, 0; 0, -60; -295, 0] Branch { DstBlock "Logical5" DstPort 1 } Branch { Points [0, -320] DstBlock "Logical6" DstPort 2 } } Line { SrcBlock "Inverter1" SrcPort 1 DstBlock "Logical5" DstPort 2 } Line { SrcBlock "Logical6" SrcPort 1 DstBlock "Counter" DstPort 2 } Line { SrcBlock "Convert1" SrcPort 1 Points [25, 0; 0, -75] DstBlock "Sim Mux1" DstPort 2 } Line { SrcBlock "Sim Mux1" SrcPort 1 Points [60, 0] Branch { DstBlock "Inverter1" DstPort 1 } Branch { Points [260, 0; 0, -250] Branch { DstBlock "Logical6" DstPort 3 } Branch { DstBlock "Delay" DstPort 1 } } } Line { SrcBlock "Constant2" SrcPort 1 DstBlock "Sim-only\nGateway In" DstPort 1 } Line { SrcBlock "posedge2" SrcPort 1 Points [25, 0; 0, -15] DstBlock "Logical2" DstPort 1 } Line { SrcBlock "Logical2" SrcPort 1 DstBlock "S-R_Latch1" DstPort 2 } Line { SrcBlock "Constant4" SrcPort 1 DstBlock "Sim-only\nGateway In2" DstPort 1 } Line { SrcBlock "Sim-only\nGateway In2" SrcPort 1 DstBlock "Sim Mux1" DstPort 1 } Line { SrcBlock "Logical7" SrcPort 1 DstBlock "S-R_Latch2" DstPort 1 } Line { SrcBlock "S-R_Latch3" SrcPort 1 Points [70, 0; 0, -50; 350, 0; 0, 95] DstBlock "Logical7" DstPort 1 } Line { SrcBlock "Delay" SrcPort 1 Points [195, 0; 0, -75] DstBlock "Logical7" DstPort 3 } Annotation { Name "This SR latch handles the case of a zero-slot-count\ntimer event. When the user code sets the slotCount t" "o 0,\nthe comparison is immedilatey true. The timer done\nsignal then asserts when:\nif(carrier sensing) after IDLE" " AND\nafter user asserts start\nDone de-assets when the user clears the done bit\n*but does not re-assert* until th" "e next user-initiated start." Position [697, 92] } } } Block { BlockType SubSystem Name "Timer 3" SID "454" Ports [7, 4] Position [335, 490, 440, 610] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "Timer 3" Location [214, 74, 1910, 1156] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "start" SID "455" Position [310, 283, 340, 297] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "pause" SID "456" Position [310, 323, 340, 337] Port "2" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "mode" SID "457" Position [255, 648, 285, 662] NamePlacement "alternate" Port "3" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "done_reset" SID "458" Position [1175, 283, 1205, 297] Port "4" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "slotCount" SID "459" Position [980, 238, 1010, 252] NamePlacement "alternate" Port "5" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "slotTime" SID "460" Position [930, 658, 960, 672] Port "6" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "Medium Idle" SID "461" Position [250, 698, 280, 712] Port "7" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "AddSub" SID "462" Ports [2, 1] Position [1210, 339, 1255, 386] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Subtraction" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Unsigned" n_bits "32" bin_pt "0" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL off hw_selection "Fabric" pipelined off xl_use_area off xl_area "[16 0 0 32 0 0 0]" use_rpm "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" block_version "8.2" sg_icon_stat "45,47,2,1,white,blue,0,32e1f85f,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 47 47 0 ],[0.77 0.82 0.91" " ]);\nplot([0 45 45 0 0 ],[0 0 47 47 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[29.66 29.66 35." "66 29.66 35.66 35.66 35.66 29.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[23.66 23.66 29.66 29.66 23.66" " ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[17.66 17.66 23.66 23.66 17.66 ],[1 1 1 ]);\npatch(" "[14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[11.66 11.66 17.66 11.66 17.66 17.66 11.66 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'" ",1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bf{a - b}','texmode','" "on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant" SID "463" Ports [0, 1] Position [940, 454, 970, 466] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "50,50,400,346" block_type "constant" block_version "10.1.2" sg_icon_stat "30,12,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 12 12 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 12 12 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ],[7.11 7.11 " "8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[6.11 6.11 7.11 7.11 6.11 ],[" "0.931 0.946 0.973 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch([13." "775 17.22 16.22 15.22 14.22 12.775 13.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.931 0.946 0.973 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'0'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant1" SID "464" Ports [0, 1] Position [255, 672, 290, 688] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "8.2" sg_icon_stat "35,16,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 16 16 0 ],[0.77 0.82 0.91" " ]);\nplot([0 35 35 0 0 ],[0 0 16 16 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[10.22 10.22 1" "2.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[8.22 8.22 10.22 10.22 8.22" " ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatch([14" ".55 21.44 19.44 17.44 15.44 12.55 14.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprintf(''," "'COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Constant Name "Constant2" SID "465" Position [260, 261, 275, 279] ShowName off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Constant Name "Constant4" SID "466" Position [315, 576, 330, 594] ShowName off Value "0" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Convert1" SID "467" Ports [1, 1] Position [380, 670, 415, 690] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "16" bin_pt "14" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,461,375" block_type "convert" block_version "8.2" sg_icon_stat "35,20,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.91" " ]);\nplot([0 35 35 0 0 ],[0 0 20 20 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output'," "1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Counter" SID "468" Ports [2, 1] Position [905, 224, 965, 326] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited counter is" " implemented by combining a counter with a comparator." cnt_type "Free Running" cnt_to "Inf" operation "Up" start_count "0" cnt_by_val "1" arith_type "Unsigned" n_bits "32" bin_pt "0" load_pin off rst on en on explicit_period "on" period "1" dbl_ovrd off use_behavioral_HDL off implementation "Fabric" xl_use_area off xl_area "[17 32 0 32 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,356,630" block_type "counter" block_version "8.2" sg_icon_stat "60,102,2,1,white,blue,0,ae3608d6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 102 102 0 ],[0.77 0.82 0." "91 ]);\nplot([0 60 60 0 0 ],[0 0 102 102 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[59.88 59.88 " "67.88 59.88 67.88 67.88 67.88 59.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[51.88 51.88 59.88 59.88 51.8" "8 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[43.88 43.88 51.88 51.88 43.88 ],[1 1 1 ]);\npatch(" "[20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[35.88 35.88 43.88 35.88 43.88 43.88 35.88 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'rst');\ncolor('black');port_label('input',2,'en');\n\ncolor('black');disp('{\\fontsize{14}\\bf++}','texmode','on'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Counter1" SID "469" Ports [2, 1] Position [835, 644, 895, 746] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited counter is" " implemented by combining a counter with a comparator." cnt_type "Free Running" cnt_to "Inf" operation "Up" start_count "0" cnt_by_val "1" arith_type "Unsigned" n_bits "16" bin_pt "0" load_pin off rst on en on explicit_period "on" period "1" dbl_ovrd off use_behavioral_HDL off implementation "Fabric" xl_use_area off xl_area "[17 32 0 32 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,356,630" block_type "counter" block_version "8.2" sg_icon_stat "60,102,2,1,white,blue,0,ae3608d6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 102 102 0 ],[0.77 0.82 0." "91 ]);\nplot([0 60 60 0 0 ],[0 0 102 102 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[59.88 59.88 " "67.88 59.88 67.88 67.88 67.88 59.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[51.88 51.88 59.88 59.88 51.8" "8 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[43.88 43.88 51.88 51.88 43.88 ],[1 1 1 ]);\npatch(" "[20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[35.88 35.88 43.88 35.88 43.88 43.88 35.88 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'rst');\ncolor('black');port_label('input',2,'en');\n\ncolor('black');disp('{\\fontsize{14}\\bf++}','texmode','on'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay" SID "470" Ports [1, 1] Position [925, 331, 950, 359] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "10.1.3" sg_icon_stat "25,28,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 28 28 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 28 28 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 17.33 20" ".33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33 17.33 14.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-1}','t" "exmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "471" Ports [1, 1] Position [1080, 476, 1125, 494] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "10.1.2" sg_icon_stat "45,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.91" " ]);\nplot([0 45 45 0 0 ],[0 0 18 18 0 ]);\npatch([17.55 20.44 22.44 24.44 26.44 22.44 19.55 17.55 ],[11.22 11.22 1" "3.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([19.55 22.44 20.44 17.55 19.55 ],[9.22 9.22 11.22 11.22 9.22" " ],[0.931 0.946 0.973 ]);\npatch([17.55 20.44 22.44 19.55 17.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([19" ".55 26.44 24.44 22.44 20.44 17.55 19.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf(''," "'COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nfprintf('" "','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter1" SID "472" Ports [1, 1] Position [590, 661, 635, 679] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "10.1.2" sg_icon_stat "45,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.91" " ]);\nplot([0 45 45 0 0 ],[0 0 18 18 0 ]);\npatch([17.55 20.44 22.44 24.44 26.44 22.44 19.55 17.55 ],[11.22 11.22 1" "3.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([19.55 22.44 20.44 17.55 19.55 ],[9.22 9.22 11.22 11.22 9.22" " ],[0.931 0.946 0.973 ]);\npatch([17.55 20.44 22.44 19.55 17.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([19" ".55 26.44 24.44 22.44 20.44 17.55 19.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf(''," "'COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nfprintf('" "','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "473" Ports [2, 1] Position [855, 231, 885, 264] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "9.1.01" sg_icon_stat "30,33,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 33 33 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 33 33 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[20.44 20.44 24.44 " "20.44 24.44 24.44 24.44 20.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[16.44 16.44 20.44 20.44 16.44 ],[0." "931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[12.44 12.44 16.44 16.44 12.44 ],[1 1 1 ]);\npatch([10.1 23." "88 19.88 15.88 11.88 6.1 10.1 ],[8.44 8.44 12.44 8.44 12.44 12.44 8.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('or');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "Logical2" SID "474" Ports [2, 1] Position [590, 306, 620, 339] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "9.1.01" sg_icon_stat "30,33,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 33 33 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 33 33 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[20.44 20.44 24.44 " "20.44 24.44 24.44 24.44 20.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[16.44 16.44 20.44 20.44 16.44 ],[0." "931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[12.44 12.44 16.44 16.44 12.44 ],[1 1 1 ]);\npatch([10.1 23." "88 19.88 15.88 11.88 6.1 10.1 ],[8.44 8.44 12.44 8.44 12.44 12.44 8.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('or');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "Logical3" SID "475" Ports [2, 1] Position [590, 271, 620, 304] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "9.1.01" sg_icon_stat "30,33,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 33 33 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 33 33 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[20.44 20.44 24.44 " "20.44 24.44 24.44 24.44 20.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[16.44 16.44 20.44 20.44 16.44 ],[0." "931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[12.44 12.44 16.44 16.44 12.44 ],[1 1 1 ]);\npatch([10.1 23." "88 19.88 15.88 11.88 6.1 10.1 ],[8.44 8.44 12.44 8.44 12.44 12.44 8.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('or');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "Logical4" SID "476" Ports [2, 1] Position [1155, 433, 1200, 502] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "10.1.2" sg_icon_stat "45,69,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 69 69 0 ],[0.77 0.82 0.91" " ]);\nplot([0 45 45 0 0 ],[0 0 69 69 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[40.66 40.66 46." "66 40.66 46.66 46.66 46.66 40.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[34.66 34.66 40.66 40.66 34.66" " ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[28.66 28.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch(" "[14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 22.66 28.66 28.66 22.66 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('and');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical5" SID "477" Ports [3, 1] Position [770, 652, 805, 688] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "3" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,261" block_type "logical" block_version "8.2" sg_icon_stat "35,36,3,1,white,blue,0,a2abe52d,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 36 36 0 ],[0.77 0.82 0.91" " ]);\nplot([0 35 35 0 0 ],[0 0 36 36 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[23.55 23.55 28.55" " 23.55 28.55 28.55 28.55 23.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[18.55 18.55 23.55 23.55 18.55 " "],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[13.55 13.55 18.55 18.55 13.55 ],[1 1 1 ]);\npatch(" "[10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[8.55 8.55 13.55 8.55 13.55 13.55 8.55 ],[0.931 0.946 0.973 ]);\nfprintf" "('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n\ncolor('black');disp('or');\nfp" "rintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical6" SID "478" Ports [3, 1] Position [850, 282, 885, 318] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "3" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,261" block_type "logical" block_version "8.2" sg_icon_stat "35,36,3,1,white,blue,0,98d76266,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 36 36 0 ],[0.77 0.82 0.91" " ]);\nplot([0 35 35 0 0 ],[0 0 36 36 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[23.55 23.55 28.55" " 23.55 28.55 28.55 28.55 23.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[18.55 18.55 23.55 23.55 18.55 " "],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[13.55 13.55 18.55 18.55 13.55 ],[1 1 1 ]);\npatch(" "[10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[8.55 8.55 13.55 8.55 13.55 13.55 8.55 ],[0.931 0.946 0.973 ]);\nfprintf" "('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n\ncolor('black');disp('and');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical7" SID "479" Ports [3, 1] Position [1175, 243, 1205, 277] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "3" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,261" block_type "logical" block_version "9.1.01" sg_icon_stat "30,34,3,1,white,blue,0,98d76266,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 34 34 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 34 34 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[21.44 21.44 25.44 " "21.44 25.44 25.44 25.44 21.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[17.44 17.44 21.44 21.44 17.44 ],[0." "931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[13.44 13.44 17.44 17.44 13.44 ],[1 1 1 ]);\npatch([10.1 23." "88 19.88 15.88 11.88 6.1 10.1 ],[9.44 9.44 13.44 9.44 13.44 13.44 9.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n\ncolor('black');disp('and');\nfprintf('','" "COMMENT: end icon text');\n" } Block { BlockType Reference Name "Mux" SID "480" Ports [3, 1] Position [320, 643, 345, 717] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" block_version "8.2" sg_icon_stat "25,74,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 10.5714 63.4286 74 0 ],[0.7" "7 0.82 0.91 ]);\nplot([0 25 25 0 0 ],[0 10.5714 63.4286 74 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5" ".325 ],[40.33 40.33 43.33 40.33 43.33 43.33 43.33 40.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[37.33 " "37.33 40.33 40.33 37.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[34.33 34.33 37.33 37.33 34" ".33 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[31.33 31.33 34.33 31.33 34.33 34.33 31.33 ],[0" ".931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('input',3" ",'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational" SID "481" Ports [2, 1] Position [1060, 231, 1100, 289] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a<=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[8 0 0 16 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "relational" block_version "8.2" sg_icon_stat "40,58,2,1,white,blue,0,52e4b236,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 58 58 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 58 58 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[34.55 34.55 39.55" " 34.55 39.55 39.55 39.55 34.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[29.55 29.55 34.55 34.55 29.55 " "],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[24.55 24.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch(" "[13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[19.55 19.55 24.55 19.55 24.55 24.55 19.55 ],[0.931 0.946 0.973 ]);\nfpr" "intf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa \\leq b','texmode'," "'on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational1" SID "482" Ports [2, 1] Position [1005, 431, 1050, 469] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a>b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[16 1 0 32 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "relational" block_version "10.1.2" sg_icon_stat "45,38,2,1,white,blue,0,b5131c97,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 38 38 0 ],[0.77 0.82 0.91" " ]);\nplot([0 45 45 0 0 ],[0 0 38 38 0 ]);\npatch([10.875 18.1 23.1 28.1 33.1 23.1 15.875 10.875 ],[24.55 24.55 29." "55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([15.875 23.1 18.1 10.875 15.875 ],[19.55 19.55 24.55 24.55 19." "55 ],[0.931 0.946 0.973 ]);\npatch([10.875 18.1 23.1 15.875 10.875 ],[14.55 14.55 19.55 19.55 14.55 ],[1 1 1 ]);\np" "atch([15.875 33.1 28.1 23.1 18.1 10.875 15.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input" "',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa > b','texmode','o" "n');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational2" SID "483" Ports [2, 1] Position [985, 651, 1025, 709] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a<=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[8 0 0 16 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "relational" block_version "8.2" sg_icon_stat "40,58,2,1,white,blue,0,52e4b236,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 58 58 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 58 58 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[34.55 34.55 39.55" " 34.55 39.55 39.55 39.55 34.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[29.55 29.55 34.55 34.55 29.55 " "],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[24.55 24.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch(" "[13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[19.55 19.55 24.55 19.55 24.55 24.55 19.55 ],[0.931 0.946 0.973 ]);\nfpr" "intf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa \\leq b','texmode'," "'on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "S-R_Latch1" SID "484" Ports [2, 1] Position [665, 272, 705, 343] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "S-R_Latch1" Location [202, 70, 1438, 850] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "S" SID "485" Position [95, 58, 125, 72] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "R" SID "486" Position [95, 88, 125, 102] Port "2" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Inverter" SID "487" Ports [1, 1] Position [220, 82, 250, 108] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "30,26,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[" "16.33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 1" "3.33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13." "33 10.33 ],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7" ".33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text')" ";\n\n\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register" SID "488" Ports [3, 1] Position [150, 70, 195, 120] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,50,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 50 50 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 50 50 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[31." "66 31.66 37.66 31.66 37.66 37.66 37.66 31.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[25.66 25.66 3" "1.66 31.66 25.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[19.66 19.66 25.66 25.66 19.66 " "],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[13.66 13.66 19.66 13.66 19.66 19.66 13.66 ],[0" ".931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor" "('black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('i" "nput',3,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfpri" "ntf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "489" Position [285, 63, 315, 77] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "Register" SrcPort 1 Points [0, 0; 5, 0] Branch { DstBlock "Inverter" DstPort 1 } Branch { Points [0, -25] DstBlock "Q" DstPort 1 } } Line { SrcBlock "Inverter" SrcPort 1 Points [10, 0; 0, 55; -130, 0] DstBlock "Register" DstPort 3 } Line { SrcBlock "S" SrcPort 1 DstBlock "Register" DstPort 1 } Line { SrcBlock "R" SrcPort 1 DstBlock "Register" DstPort 2 } } } Block { BlockType SubSystem Name "S-R_Latch2" SID "490" Ports [2, 1] Position [1285, 245, 1325, 305] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "S-R_Latch2" Location [521, 318, 918, 591] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "S" SID "491" Position [95, 58, 125, 72] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "R" SID "492" Position [95, 88, 125, 102] Port "2" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Inverter" SID "493" Ports [1, 1] Position [220, 82, 250, 108] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "30,26,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[" "16.33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 1" "3.33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13." "33 10.33 ],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7" ".33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text')" ";\n\n\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register" SID "494" Ports [3, 1] Position [150, 70, 195, 120] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,50,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 50 50 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 50 50 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[31." "66 31.66 37.66 31.66 37.66 37.66 37.66 31.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[25.66 25.66 3" "1.66 31.66 25.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[19.66 19.66 25.66 25.66 19.66 " "],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[13.66 13.66 19.66 13.66 19.66 19.66 13.66 ],[0" ".931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor" "('black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('i" "nput',3,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfpri" "ntf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "495" Position [285, 63, 315, 77] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "R" SrcPort 1 DstBlock "Register" DstPort 2 } Line { SrcBlock "S" SrcPort 1 DstBlock "Register" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 Points [10, 0; 0, 55; -130, 0] DstBlock "Register" DstPort 3 } Line { SrcBlock "Register" SrcPort 1 Points [0, 0; 5, 0] Branch { Points [0, -25] DstBlock "Q" DstPort 1 } Branch { DstBlock "Inverter" DstPort 1 } } } } Block { BlockType SubSystem Name "S-R_Latch3" SID "496" Ports [2, 1] Position [665, 167, 705, 238] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "S-R_Latch3" Location [202, 70, 1438, 850] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "S" SID "497" Position [95, 58, 125, 72] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "R" SID "498" Position [95, 88, 125, 102] Port "2" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Inverter" SID "499" Ports [1, 1] Position [220, 82, 250, 108] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "30,26,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[" "16.33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 1" "3.33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13." "33 10.33 ],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7" ".33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text')" ";\n\n\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register" SID "500" Ports [3, 1] Position [150, 70, 195, 120] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,50,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 50 50 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 50 50 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[31." "66 31.66 37.66 31.66 37.66 37.66 37.66 31.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[25.66 25.66 3" "1.66 31.66 25.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[19.66 19.66 25.66 25.66 19.66 " "],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[13.66 13.66 19.66 13.66 19.66 19.66 13.66 ],[0" ".931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor" "('black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('i" "nput',3,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfpri" "ntf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "501" Position [285, 63, 315, 77] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "R" SrcPort 1 DstBlock "Register" DstPort 2 } Line { SrcBlock "S" SrcPort 1 DstBlock "Register" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 Points [10, 0; 0, 55; -130, 0] DstBlock "Register" DstPort 3 } Line { SrcBlock "Register" SrcPort 1 Points [0, 0; 5, 0] Branch { Points [0, -25] DstBlock "Q" DstPort 1 } Branch { DstBlock "Inverter" DstPort 1 } } } } Block { BlockType Reference Name "Sim Mux" SID "503" Ports [2, 1] Position [405, 261, 445, 299] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Simulation Multiplexer" SourceType "Xilinx Simulation Multiplexer Block" infoedit "Distinguish input subsystems as \"simulation only\" and \"generation only\". The input specified For " "Simulation will be used during Simulink simulation. The input specified For Generation will be used during code ge" "neration. This block will typically be used on the output of a HW Co-Simulation, Black Box, or ModelSim subsystem." "

Hardware Notes: This block costs nothing." sim_sel "1" hw_sel "2" has_advanced_control "0" sggui_pos "20,20,336,197" block_type "simmux" block_version "10.1.3" sg_icon_stat "40,38,2,1,white,blue,0,4170dd71,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 38 38 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 38 38 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[24.55 24.55 29.55" " 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[19.55 19.55 24.55 24.55 19.55 " "],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[14.55 14.55 19.55 19.55 14.55 ],[1 1 1 ]);\npatch(" "[13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 0.946 0.973 ]);\nfprintf" "('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\nfprintf('','COMMENT: end icon te" "xt');color('red');\nplot(swLineX,simSwLineY);\ncolor('black');\nplot(swLineX,hwSwLineY);\n" } Block { BlockType Reference Name "Sim Mux1" SID "504" Ports [2, 1] Position [470, 576, 510, 614] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Simulation Multiplexer" SourceType "Xilinx Simulation Multiplexer Block" infoedit "Distinguish input subsystems as \"simulation only\" and \"generation only\". The input specified For " "Simulation will be used during Simulink simulation. The input specified For Generation will be used during code ge" "neration. This block will typically be used on the output of a HW Co-Simulation, Black Box, or ModelSim subsystem." "

Hardware Notes: This block costs nothing." sim_sel "1" hw_sel "2" has_advanced_control "0" sggui_pos "20,20,336,197" block_type "simmux" block_version "10.1.3" sg_icon_stat "40,38,2,1,white,blue,0,4170dd71,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 38 38 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 38 38 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[24.55 24.55 29.55" " 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[19.55 19.55 24.55 24.55 19.55 " "],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[14.55 14.55 19.55 19.55 14.55 ],[1 1 1 ]);\npatch(" "[13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 0.946 0.973 ]);\nfprintf" "('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\nfprintf('','COMMENT: end icon te" "xt');color('red');\nplot(swLineX,simSwLineY);\ncolor('black');\nplot(swLineX,hwSwLineY);\n" } Block { BlockType SubSystem Name "Sim-only\nGateway In" SID "505" Ports [1, 1] Position [305, 260, 350, 280] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "Sim-only\nGateway In" Location [269, 280, 494, 362] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" SID "506" Position [20, 33, 50, 47] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Disregard Subsystem" SID "507" Tag "discardX" Ports [] Position [86, 85, 144, 143] ShowName off AttributesFormatString "Disregard Subsystem\\nFor Generation" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Disregard Subsystem" SourceType "Xilinx Disregard Subsystem For Generation Block" infoedit "Place this block into a subsystem to have System Generator ignore the subsystem during code ge" "neration. This block can be used in combination with the Simulation Multiplexer block to provide an alternative" " simulation model for another subsystem (e.g., to provide a simulation model for a black box)." has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "disregard" block_version "10.1.3" sg_icon_stat "58,58,-1,-1,darkgray,black,0,0,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 58 58 0 ],[0 0 58 58 ],[0.1 0.1 0." "1]);\npatch([14 4 18 4 14 29 33 37 53 40 28 19 33 19 28 40 53 37 33 29 14 ],[6 16 30 44 54 54 50 54 54 41 53 44" " 30 16 7 19 6 6 10 6 6 ],[0.33 0.33 0.33]);\nplot([0 58 58 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end ico" "n graphics');\nfprintf('','COMMENT: begin icon text');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Gateway In" SID "508" Ports [1, 1] Position [80, 30, 145, 50] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, double and fixed point to Xilinx" " fixed point type.

Hardware notes: In hardware these blocks become top level input ports." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0 0 0 0 1 0 0]" inherit_from_input off UseAsADC off ADCChannel "'1'" hdl_port "on" has_advanced_control "0" sggui_pos "20,20,348,406" block_type "gatewayin" block_version "10.1.3" sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0" ".93 0.65 ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[1" "2.22 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.2" "2 12.22 12.22 10.22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.2" "2 ],[1 1 1 ]);\npatch([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985" " 0.979 0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' " "');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "509" Position [170, 33, 200, 47] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "Gateway In" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "D" SrcPort 1 DstBlock "Gateway In" DstPort 1 } } } Block { BlockType SubSystem Name "Sim-only\nGateway In2" SID "510" Ports [1, 1] Position [360, 575, 405, 595] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "Sim-only\nGateway In2" Location [214, 70, 1918, 1152] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" SID "511" Position [20, 33, 50, 47] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Disregard Subsystem" SID "512" Tag "discardX" Ports [] Position [71, 110, 129, 168] ShowName off AttributesFormatString "Disregard Subsystem\\nFor Generation" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Disregard Subsystem" SourceType "Xilinx Disregard Subsystem For Generation Block" infoedit "Place this block into a subsystem to have System Generator ignore the subsystem during code ge" "neration. This block can be used in combination with the Simulation Multiplexer block to provide an alternative" " simulation model for another subsystem (e.g., to provide a simulation model for a black box)." has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "disregard" block_version "10.1.3" sg_icon_stat "58,58,-1,-1,darkgray,black,0,0,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 58 58 0 ],[0 0 58 58 ],[0.1 0.1 0." "1]);\npatch([14 4 18 4 14 29 33 37 53 40 28 19 33 19 28 40 53 37 33 29 14 ],[6 16 30 44 54 54 50 54 54 41 53 44" " 30 16 7 19 6 6 10 6 6 ],[0.33 0.33 0.33]);\nplot([0 58 58 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end ico" "n graphics');\nfprintf('','COMMENT: begin icon text');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Gateway In" SID "513" Ports [1, 1] Position [80, 30, 145, 50] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, double and fixed point to Xilinx" " fixed point type.

Hardware notes: In hardware these blocks become top level input ports." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0 0 0 0 1 0 0]" inherit_from_input off UseAsADC off ADCChannel "'1'" hdl_port "on" has_advanced_control "0" sggui_pos "20,20,348,406" block_type "gatewayin" block_version "10.1.3" sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0" ".93 0.65 ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[1" "2.22 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.2" "2 12.22 12.22 10.22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.2" "2 ],[1 1 1 ]);\npatch([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985" " 0.979 0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' " "');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "514" Position [170, 33, 200, 47] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "D" SrcPort 1 DstBlock "Gateway In" DstPort 1 } Line { SrcBlock "Gateway In" SrcPort 1 DstBlock "Q" DstPort 1 } } } Block { BlockType SubSystem Name "negedge" SID "515" Ports [1, 1] Position [495, 288, 525, 302] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "negedge" Location [459, 339, 854, 490] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "In" SID "516" Position [170, 213, 200, 227] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Delay" SID "517" Ports [1, 1] Position [230, 247, 290, 303] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p. If register retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "8.2" sg_icon_stat "60,56,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.8" "8 36.88 44.88 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.8" "8 36.88 28.88 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1" " 1 1 ]);\npatch([20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0" ".946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('" "black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "518" Ports [1, 1] Position [290, 191, 345, 249] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "8.2" sg_icon_stat "55,58,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 58 58 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ]" ",[36.77 36.77 43.77 36.77 43.77 43.77 43.77 36.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[29.7" "7 29.77 36.77 36.77 29.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[22.77 22.77 29.7" "7 29.77 22.77 ],[1 1 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[15.77 15.77 22.77 15.77 22.7" "7 22.77 15.77 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin i" "con text');\n\n\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical" SID "519" Ports [2, 1] Position [410, 205, 465, 265] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "8.2" sg_icon_stat "55,60,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 60 60 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ]" ",[37.77 37.77 44.77 37.77 44.77 44.77 44.77 37.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[30.7" "7 30.77 37.77 37.77 30.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[23.77 23.77 30.7" "7 30.77 23.77 ],[1 1 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[16.77 16.77 23.77 16.77 23.7" "7 23.77 16.77 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin i" "con text');\n\n\n\ncolor('black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Out" SID "520" Position [490, 228, 520, 242] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical" DstPort 1 } Line { SrcBlock "Delay" SrcPort 1 Points [90, 0; 0, -25] DstBlock "Logical" DstPort 2 } Line { SrcBlock "In" SrcPort 1 Points [5, 0] Branch { DstBlock "Inverter" DstPort 1 } Branch { Points [0, 55] DstBlock "Delay" DstPort 1 } } Line { SrcBlock "Logical" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "posedge" SID "521" Ports [1, 1] Position [495, 273, 525, 287] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "posedge" Location [459, 339, 854, 490] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "In" SID "522" Position [20, 33, 50, 47] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Delay" SID "523" Ports [1, 1] Position [80, 67, 140, 123] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p. If register retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "8.2" sg_icon_stat "60,56,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.8" "8 36.88 44.88 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.8" "8 36.88 28.88 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1" " 1 1 ]);\npatch([20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0" ".946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('" "black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "524" Ports [1, 1] Position [170, 66, 225, 124] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "8.2" sg_icon_stat "55,58,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 58 58 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ]" ",[36.77 36.77 43.77 36.77 43.77 43.77 43.77 36.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[29.7" "7 29.77 36.77 36.77 29.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[22.77 22.77 29.7" "7 29.77 22.77 ],[1 1 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[15.77 15.77 22.77 15.77 22.7" "7 22.77 15.77 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin i" "con text');\n\n\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical" SID "525" Ports [2, 1] Position [260, 25, 315, 85] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "8.2" sg_icon_stat "55,60,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 60 60 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ]" ",[37.77 37.77 44.77 37.77 44.77 44.77 44.77 37.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[30.7" "7 30.77 37.77 37.77 30.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[23.77 23.77 30.7" "7 30.77 23.77 ],[1 1 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[16.77 16.77 23.77 16.77 23.7" "7 23.77 16.77 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin i" "con text');\n\n\n\ncolor('black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Out" SID "526" Position [340, 48, 370, 62] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "Logical" SrcPort 1 Points [0, 0] DstBlock "Out" DstPort 1 } Line { SrcBlock "In" SrcPort 1 Points [0, 0; 5, 0] Branch { Points [0, 55] DstBlock "Delay" DstPort 1 } Branch { DstBlock "Logical" DstPort 1 } } Line { SrcBlock "Inverter" SrcPort 1 Points [5, 0; 0, -25] DstBlock "Logical" DstPort 2 } Line { SrcBlock "Delay" SrcPort 1 Points [0, 0] DstBlock "Inverter" DstPort 1 } } } Block { BlockType SubSystem Name "posedge2" SID "527" Ports [1, 1] Position [495, 323, 525, 337] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "posedge2" Location [459, 339, 854, 490] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "In" SID "528" Position [20, 33, 50, 47] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Delay" SID "529" Ports [1, 1] Position [80, 67, 140, 123] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p. If register retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "8.2" sg_icon_stat "60,56,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.8" "8 36.88 44.88 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.8" "8 36.88 28.88 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1" " 1 1 ]);\npatch([20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0" ".946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('" "black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "530" Ports [1, 1] Position [170, 66, 225, 124] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "8.2" sg_icon_stat "55,58,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 58 58 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ]" ",[36.77 36.77 43.77 36.77 43.77 43.77 43.77 36.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[29.7" "7 29.77 36.77 36.77 29.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[22.77 22.77 29.7" "7 29.77 22.77 ],[1 1 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[15.77 15.77 22.77 15.77 22.7" "7 22.77 15.77 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin i" "con text');\n\n\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical" SID "531" Ports [2, 1] Position [260, 25, 315, 85] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "8.2" sg_icon_stat "55,60,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 60 60 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ]" ",[37.77 37.77 44.77 37.77 44.77 44.77 44.77 37.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[30.7" "7 30.77 37.77 37.77 30.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[23.77 23.77 30.7" "7 30.77 23.77 ],[1 1 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[16.77 16.77 23.77 16.77 23.7" "7 23.77 16.77 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin i" "con text');\n\n\n\ncolor('black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Out" SID "532" Position [340, 48, 370, 62] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "Logical" SrcPort 1 Points [0, 0] DstBlock "Out" DstPort 1 } Line { SrcBlock "In" SrcPort 1 Points [0, 0; 5, 0] Branch { Points [0, 55] DstBlock "Delay" DstPort 1 } Branch { DstBlock "Logical" DstPort 1 } } Line { SrcBlock "Inverter" SrcPort 1 Points [5, 0; 0, -25] DstBlock "Logical" DstPort 2 } Line { SrcBlock "Delay" SrcPort 1 Points [0, 0] DstBlock "Inverter" DstPort 1 } } } Block { BlockType Outport Name "done" SID "533" Position [1350, 268, 1380, 282] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Outport Name "running" SID "534" Position [1245, 518, 1275, 532] Port "2" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Outport Name "paused" SID "535" Position [1240, 463, 1270, 477] Port "3" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Outport Name "timeLeft" SID "536" Position [1285, 358, 1315, 372] Port "4" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "Delay" SrcPort 1 Points [195, 0; 0, -75] DstBlock "Logical7" DstPort 3 } Line { SrcBlock "S-R_Latch3" SrcPort 1 Points [70, 0; 0, -50; 350, 0; 0, 95] DstBlock "Logical7" DstPort 1 } Line { SrcBlock "Logical7" SrcPort 1 DstBlock "S-R_Latch2" DstPort 1 } Line { SrcBlock "Sim-only\nGateway In2" SrcPort 1 DstBlock "Sim Mux1" DstPort 1 } Line { SrcBlock "Constant4" SrcPort 1 DstBlock "Sim-only\nGateway In2" DstPort 1 } Line { SrcBlock "Logical2" SrcPort 1 DstBlock "S-R_Latch1" DstPort 2 } Line { SrcBlock "posedge2" SrcPort 1 Points [25, 0; 0, -15] DstBlock "Logical2" DstPort 1 } Line { SrcBlock "Constant2" SrcPort 1 DstBlock "Sim-only\nGateway In" DstPort 1 } Line { SrcBlock "Sim Mux1" SrcPort 1 Points [60, 0] Branch { Points [260, 0; 0, -250] Branch { DstBlock "Delay" DstPort 1 } Branch { DstBlock "Logical6" DstPort 3 } } Branch { DstBlock "Inverter1" DstPort 1 } } Line { SrcBlock "Convert1" SrcPort 1 Points [25, 0; 0, -75] DstBlock "Sim Mux1" DstPort 2 } Line { SrcBlock "Logical6" SrcPort 1 DstBlock "Counter" DstPort 2 } Line { SrcBlock "Inverter1" SrcPort 1 DstBlock "Logical5" DstPort 2 } Line { SrcBlock "Relational2" SrcPort 1 Points [20, 0; 0, -60; -295, 0] Branch { Points [0, -320] DstBlock "Logical6" DstPort 2 } Branch { DstBlock "Logical5" DstPort 1 } } Line { SrcBlock "Logical5" SrcPort 1 DstBlock "Counter1" DstPort 1 } Line { SrcBlock "Counter1" SrcPort 1 DstBlock "Relational2" DstPort 2 } Line { SrcBlock "slotTime" SrcPort 1 DstBlock "Relational2" DstPort 1 } Line { SrcBlock "Sim-only\nGateway In" SrcPort 1 DstBlock "Sim Mux" DstPort 1 } Line { SrcBlock "pause" SrcPort 1 Points [115, 0] Branch { Points [0, -35] DstBlock "negedge" DstPort 1 } Branch { DstBlock "posedge2" DstPort 1 } } Line { SrcBlock "negedge" SrcPort 1 DstBlock "Logical3" DstPort 2 } Line { SrcBlock "Logical3" SrcPort 1 DstBlock "S-R_Latch1" DstPort 1 } Line { SrcBlock "posedge" SrcPort 1 Points [15, 0] Branch { Points [0, -25] Branch { Points [0, -70] DstBlock "S-R_Latch3" DstPort 1 } Branch { DstBlock "Logical1" DstPort 2 } } Branch { Points [0, 400] DstBlock "Logical5" DstPort 3 } Branch { DstBlock "Logical3" DstPort 1 } } Line { SrcBlock "done_reset" SrcPort 1 Points [15, 0] Branch { Points [0, -145; -625, 0; 0, 75] DstBlock "S-R_Latch3" DstPort 2 } Branch { DstBlock "S-R_Latch2" DstPort 2 } } Line { SrcBlock "Relational" SrcPort 1 Points [10, 0] Branch { DstBlock "Logical7" DstPort 2 } Branch { Points [0, -80; -290, 0; 0, 60] DstBlock "Logical1" DstPort 1 } Branch { Points [0, 110; -550, 0; 0, -40] DstBlock "Logical2" DstPort 2 } } Line { SrcBlock "S-R_Latch2" SrcPort 1 DstBlock "done" DstPort 1 } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Counter" DstPort 1 } Line { SrcBlock "Counter" SrcPort 1 Points [0, 0] Branch { Points [0, 100] Branch { DstBlock "AddSub" DstPort 2 } Branch { Points [0, 65] DstBlock "Relational1" DstPort 1 } } Branch { Labels [1, 0] DstBlock "Relational" DstPort 2 } } Line { SrcBlock "slotCount" SrcPort 1 Points [10, 0] Branch { DstBlock "Relational" DstPort 1 } Branch { Points [0, 105] DstBlock "AddSub" DstPort 1 } } Line { SrcBlock "S-R_Latch1" SrcPort 1 Points [25, 0] Branch { Points [0, -20] DstBlock "Logical6" DstPort 1 } Branch { Points [0, 175] Branch { Points [290, 0] Branch { Points [0, 40] DstBlock "running" DstPort 1 } Branch { DstBlock "Inverter" DstPort 1 } } Branch { Points [0, 235] DstBlock "Counter1" DstPort 2 } } } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical4" DstPort 2 } Line { SrcBlock "Relational1" SrcPort 1 DstBlock "Logical4" DstPort 1 } Line { SrcBlock "Constant" SrcPort 1 DstBlock "Relational1" DstPort 2 } Line { SrcBlock "AddSub" SrcPort 1 DstBlock "timeLeft" DstPort 1 } Line { SrcBlock "Sim Mux" SrcPort 1 DstBlock "posedge" DstPort 1 } Line { SrcBlock "start" SrcPort 1 DstBlock "Sim Mux" DstPort 2 } Line { SrcBlock "Logical4" SrcPort 1 DstBlock "paused" DstPort 1 } Line { SrcBlock "Mux" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Medium Idle" SrcPort 1 DstBlock "Mux" DstPort 3 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Mux" DstPort 2 } Line { SrcBlock "mode" SrcPort 1 DstBlock "Mux" DstPort 1 } Annotation { Name "This SR latch handles the case of a zero-slot-count\ntimer event. When the user code sets the slotCount t" "o 0,\nthe comparison is immedilatey true. The timer done\nsignal then asserts when:\nif(carrier sensing) after IDLE" " AND\nafter user asserts start\nDone de-assets when the user clears the done bit\n*but does not re-assert* until th" "e next user-initiated start." Position [697, 92] } } } Block { BlockType SubSystem Name "Timer 4" SID "537" Ports [7, 4] Position [855, 70, 960, 190] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "Timer 4" Location [214, 74, 1910, 1156] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "start" SID "538" Position [310, 283, 340, 297] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "pause" SID "539" Position [310, 323, 340, 337] Port "2" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "mode" SID "540" Position [255, 648, 285, 662] NamePlacement "alternate" Port "3" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "done_reset" SID "541" Position [1175, 283, 1205, 297] Port "4" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "slotCount" SID "542" Position [980, 238, 1010, 252] NamePlacement "alternate" Port "5" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "slotTime" SID "543" Position [930, 658, 960, 672] Port "6" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "Medium Idle" SID "544" Position [250, 698, 280, 712] Port "7" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "AddSub" SID "545" Ports [2, 1] Position [1210, 339, 1255, 386] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Subtraction" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Unsigned" n_bits "32" bin_pt "0" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL off hw_selection "Fabric" pipelined off xl_use_area off xl_area "[16 0 0 32 0 0 0]" use_rpm "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" block_version "8.2" sg_icon_stat "45,47,2,1,white,blue,0,32e1f85f,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 47 47 0 ],[0.77 0.82 0.91" " ]);\nplot([0 45 45 0 0 ],[0 0 47 47 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[29.66 29.66 35." "66 29.66 35.66 35.66 35.66 29.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[23.66 23.66 29.66 29.66 23.66" " ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[17.66 17.66 23.66 23.66 17.66 ],[1 1 1 ]);\npatch(" "[14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[11.66 11.66 17.66 11.66 17.66 17.66 11.66 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'" ",1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bf{a - b}','texmode','" "on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant" SID "546" Ports [0, 1] Position [940, 454, 970, 466] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "50,50,400,346" block_type "constant" block_version "10.1.2" sg_icon_stat "30,12,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 12 12 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 12 12 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ],[7.11 7.11 " "8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[6.11 6.11 7.11 7.11 6.11 ],[" "0.931 0.946 0.973 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch([13." "775 17.22 16.22 15.22 14.22 12.775 13.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.931 0.946 0.973 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'0'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant1" SID "547" Ports [0, 1] Position [255, 672, 290, 688] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "8.2" sg_icon_stat "35,16,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 16 16 0 ],[0.77 0.82 0.91" " ]);\nplot([0 35 35 0 0 ],[0 0 16 16 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[10.22 10.22 1" "2.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[8.22 8.22 10.22 10.22 8.22" " ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatch([14" ".55 21.44 19.44 17.44 15.44 12.55 14.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprintf(''," "'COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Constant Name "Constant2" SID "548" Position [260, 261, 275, 279] ShowName off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Constant Name "Constant4" SID "549" Position [315, 576, 330, 594] ShowName off Value "0" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Convert1" SID "550" Ports [1, 1] Position [380, 670, 415, 690] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "16" bin_pt "14" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,461,375" block_type "convert" block_version "8.2" sg_icon_stat "35,20,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.91" " ]);\nplot([0 35 35 0 0 ],[0 0 20 20 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output'," "1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Counter" SID "551" Ports [2, 1] Position [905, 224, 965, 326] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited counter is" " implemented by combining a counter with a comparator." cnt_type "Free Running" cnt_to "Inf" operation "Up" start_count "0" cnt_by_val "1" arith_type "Unsigned" n_bits "32" bin_pt "0" load_pin off rst on en on explicit_period "on" period "1" dbl_ovrd off use_behavioral_HDL off implementation "Fabric" xl_use_area off xl_area "[17 32 0 32 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,356,630" block_type "counter" block_version "8.2" sg_icon_stat "60,102,2,1,white,blue,0,ae3608d6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 102 102 0 ],[0.77 0.82 0." "91 ]);\nplot([0 60 60 0 0 ],[0 0 102 102 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[59.88 59.88 " "67.88 59.88 67.88 67.88 67.88 59.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[51.88 51.88 59.88 59.88 51.8" "8 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[43.88 43.88 51.88 51.88 43.88 ],[1 1 1 ]);\npatch(" "[20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[35.88 35.88 43.88 35.88 43.88 43.88 35.88 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'rst');\ncolor('black');port_label('input',2,'en');\n\ncolor('black');disp('{\\fontsize{14}\\bf++}','texmode','on'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Counter1" SID "552" Ports [2, 1] Position [835, 644, 895, 746] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited counter is" " implemented by combining a counter with a comparator." cnt_type "Free Running" cnt_to "Inf" operation "Up" start_count "0" cnt_by_val "1" arith_type "Unsigned" n_bits "16" bin_pt "0" load_pin off rst on en on explicit_period "on" period "1" dbl_ovrd off use_behavioral_HDL off implementation "Fabric" xl_use_area off xl_area "[17 32 0 32 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,356,630" block_type "counter" block_version "8.2" sg_icon_stat "60,102,2,1,white,blue,0,ae3608d6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 102 102 0 ],[0.77 0.82 0." "91 ]);\nplot([0 60 60 0 0 ],[0 0 102 102 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[59.88 59.88 " "67.88 59.88 67.88 67.88 67.88 59.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[51.88 51.88 59.88 59.88 51.8" "8 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[43.88 43.88 51.88 51.88 43.88 ],[1 1 1 ]);\npatch(" "[20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[35.88 35.88 43.88 35.88 43.88 43.88 35.88 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'rst');\ncolor('black');port_label('input',2,'en');\n\ncolor('black');disp('{\\fontsize{14}\\bf++}','texmode','on'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay" SID "553" Ports [1, 1] Position [925, 331, 950, 359] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "10.1.3" sg_icon_stat "25,28,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 28 28 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 28 28 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 17.33 20" ".33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33 17.33 14.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-1}','t" "exmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "554" Ports [1, 1] Position [1080, 476, 1125, 494] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "10.1.2" sg_icon_stat "45,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.91" " ]);\nplot([0 45 45 0 0 ],[0 0 18 18 0 ]);\npatch([17.55 20.44 22.44 24.44 26.44 22.44 19.55 17.55 ],[11.22 11.22 1" "3.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([19.55 22.44 20.44 17.55 19.55 ],[9.22 9.22 11.22 11.22 9.22" " ],[0.931 0.946 0.973 ]);\npatch([17.55 20.44 22.44 19.55 17.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([19" ".55 26.44 24.44 22.44 20.44 17.55 19.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf(''," "'COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nfprintf('" "','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter1" SID "555" Ports [1, 1] Position [590, 661, 635, 679] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "10.1.2" sg_icon_stat "45,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.91" " ]);\nplot([0 45 45 0 0 ],[0 0 18 18 0 ]);\npatch([17.55 20.44 22.44 24.44 26.44 22.44 19.55 17.55 ],[11.22 11.22 1" "3.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([19.55 22.44 20.44 17.55 19.55 ],[9.22 9.22 11.22 11.22 9.22" " ],[0.931 0.946 0.973 ]);\npatch([17.55 20.44 22.44 19.55 17.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([19" ".55 26.44 24.44 22.44 20.44 17.55 19.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf(''," "'COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nfprintf('" "','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "556" Ports [2, 1] Position [855, 231, 885, 264] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "9.1.01" sg_icon_stat "30,33,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 33 33 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 33 33 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[20.44 20.44 24.44 " "20.44 24.44 24.44 24.44 20.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[16.44 16.44 20.44 20.44 16.44 ],[0." "931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[12.44 12.44 16.44 16.44 12.44 ],[1 1 1 ]);\npatch([10.1 23." "88 19.88 15.88 11.88 6.1 10.1 ],[8.44 8.44 12.44 8.44 12.44 12.44 8.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('or');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "Logical2" SID "557" Ports [2, 1] Position [590, 306, 620, 339] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "9.1.01" sg_icon_stat "30,33,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 33 33 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 33 33 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[20.44 20.44 24.44 " "20.44 24.44 24.44 24.44 20.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[16.44 16.44 20.44 20.44 16.44 ],[0." "931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[12.44 12.44 16.44 16.44 12.44 ],[1 1 1 ]);\npatch([10.1 23." "88 19.88 15.88 11.88 6.1 10.1 ],[8.44 8.44 12.44 8.44 12.44 12.44 8.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('or');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "Logical3" SID "558" Ports [2, 1] Position [590, 271, 620, 304] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "9.1.01" sg_icon_stat "30,33,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 33 33 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 33 33 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[20.44 20.44 24.44 " "20.44 24.44 24.44 24.44 20.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[16.44 16.44 20.44 20.44 16.44 ],[0." "931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[12.44 12.44 16.44 16.44 12.44 ],[1 1 1 ]);\npatch([10.1 23." "88 19.88 15.88 11.88 6.1 10.1 ],[8.44 8.44 12.44 8.44 12.44 12.44 8.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('or');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "Logical4" SID "559" Ports [2, 1] Position [1155, 433, 1200, 502] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "10.1.2" sg_icon_stat "45,69,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 69 69 0 ],[0.77 0.82 0.91" " ]);\nplot([0 45 45 0 0 ],[0 0 69 69 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[40.66 40.66 46." "66 40.66 46.66 46.66 46.66 40.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[34.66 34.66 40.66 40.66 34.66" " ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[28.66 28.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch(" "[14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 22.66 28.66 28.66 22.66 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('and');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical5" SID "560" Ports [3, 1] Position [770, 652, 805, 688] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "3" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,261" block_type "logical" block_version "8.2" sg_icon_stat "35,36,3,1,white,blue,0,a2abe52d,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 36 36 0 ],[0.77 0.82 0.91" " ]);\nplot([0 35 35 0 0 ],[0 0 36 36 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[23.55 23.55 28.55" " 23.55 28.55 28.55 28.55 23.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[18.55 18.55 23.55 23.55 18.55 " "],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[13.55 13.55 18.55 18.55 13.55 ],[1 1 1 ]);\npatch(" "[10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[8.55 8.55 13.55 8.55 13.55 13.55 8.55 ],[0.931 0.946 0.973 ]);\nfprintf" "('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n\ncolor('black');disp('or');\nfp" "rintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical6" SID "561" Ports [3, 1] Position [850, 282, 885, 318] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "3" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,261" block_type "logical" block_version "8.2" sg_icon_stat "35,36,3,1,white,blue,0,98d76266,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 36 36 0 ],[0.77 0.82 0.91" " ]);\nplot([0 35 35 0 0 ],[0 0 36 36 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[23.55 23.55 28.55" " 23.55 28.55 28.55 28.55 23.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[18.55 18.55 23.55 23.55 18.55 " "],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[13.55 13.55 18.55 18.55 13.55 ],[1 1 1 ]);\npatch(" "[10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[8.55 8.55 13.55 8.55 13.55 13.55 8.55 ],[0.931 0.946 0.973 ]);\nfprintf" "('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n\ncolor('black');disp('and');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical7" SID "562" Ports [3, 1] Position [1175, 243, 1205, 277] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "3" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,261" block_type "logical" block_version "9.1.01" sg_icon_stat "30,34,3,1,white,blue,0,98d76266,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 34 34 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 34 34 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[21.44 21.44 25.44 " "21.44 25.44 25.44 25.44 21.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[17.44 17.44 21.44 21.44 17.44 ],[0." "931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[13.44 13.44 17.44 17.44 13.44 ],[1 1 1 ]);\npatch([10.1 23." "88 19.88 15.88 11.88 6.1 10.1 ],[9.44 9.44 13.44 9.44 13.44 13.44 9.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n\ncolor('black');disp('and');\nfprintf('','" "COMMENT: end icon text');\n" } Block { BlockType Reference Name "Mux" SID "563" Ports [3, 1] Position [320, 643, 345, 717] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" block_version "8.2" sg_icon_stat "25,74,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 10.5714 63.4286 74 0 ],[0.7" "7 0.82 0.91 ]);\nplot([0 25 25 0 0 ],[0 10.5714 63.4286 74 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5" ".325 ],[40.33 40.33 43.33 40.33 43.33 43.33 43.33 40.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[37.33 " "37.33 40.33 40.33 37.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[34.33 34.33 37.33 37.33 34" ".33 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[31.33 31.33 34.33 31.33 34.33 34.33 31.33 ],[0" ".931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('input',3" ",'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational" SID "564" Ports [2, 1] Position [1060, 231, 1100, 289] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a<=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[8 0 0 16 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "relational" block_version "8.2" sg_icon_stat "40,58,2,1,white,blue,0,52e4b236,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 58 58 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 58 58 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[34.55 34.55 39.55" " 34.55 39.55 39.55 39.55 34.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[29.55 29.55 34.55 34.55 29.55 " "],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[24.55 24.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch(" "[13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[19.55 19.55 24.55 19.55 24.55 24.55 19.55 ],[0.931 0.946 0.973 ]);\nfpr" "intf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa \\leq b','texmode'," "'on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational1" SID "565" Ports [2, 1] Position [1005, 431, 1050, 469] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a>b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[16 1 0 32 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "relational" block_version "10.1.2" sg_icon_stat "45,38,2,1,white,blue,0,b5131c97,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 38 38 0 ],[0.77 0.82 0.91" " ]);\nplot([0 45 45 0 0 ],[0 0 38 38 0 ]);\npatch([10.875 18.1 23.1 28.1 33.1 23.1 15.875 10.875 ],[24.55 24.55 29." "55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([15.875 23.1 18.1 10.875 15.875 ],[19.55 19.55 24.55 24.55 19." "55 ],[0.931 0.946 0.973 ]);\npatch([10.875 18.1 23.1 15.875 10.875 ],[14.55 14.55 19.55 19.55 14.55 ],[1 1 1 ]);\np" "atch([15.875 33.1 28.1 23.1 18.1 10.875 15.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input" "',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa > b','texmode','o" "n');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational2" SID "566" Ports [2, 1] Position [985, 651, 1025, 709] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a<=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[8 0 0 16 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "relational" block_version "8.2" sg_icon_stat "40,58,2,1,white,blue,0,52e4b236,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 58 58 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 58 58 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[34.55 34.55 39.55" " 34.55 39.55 39.55 39.55 34.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[29.55 29.55 34.55 34.55 29.55 " "],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[24.55 24.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch(" "[13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[19.55 19.55 24.55 19.55 24.55 24.55 19.55 ],[0.931 0.946 0.973 ]);\nfpr" "intf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa \\leq b','texmode'," "'on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "S-R_Latch1" SID "567" Ports [2, 1] Position [665, 272, 705, 343] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "S-R_Latch1" Location [202, 70, 1438, 850] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "S" SID "568" Position [95, 58, 125, 72] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "R" SID "569" Position [95, 88, 125, 102] Port "2" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Inverter" SID "570" Ports [1, 1] Position [220, 82, 250, 108] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "30,26,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[" "16.33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 1" "3.33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13." "33 10.33 ],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7" ".33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text')" ";\n\n\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register" SID "571" Ports [3, 1] Position [150, 70, 195, 120] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,50,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 50 50 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 50 50 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[31." "66 31.66 37.66 31.66 37.66 37.66 37.66 31.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[25.66 25.66 3" "1.66 31.66 25.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[19.66 19.66 25.66 25.66 19.66 " "],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[13.66 13.66 19.66 13.66 19.66 19.66 13.66 ],[0" ".931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor" "('black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('i" "nput',3,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfpri" "ntf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "572" Position [285, 63, 315, 77] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "R" SrcPort 1 DstBlock "Register" DstPort 2 } Line { SrcBlock "S" SrcPort 1 DstBlock "Register" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 Points [10, 0; 0, 55; -130, 0] DstBlock "Register" DstPort 3 } Line { SrcBlock "Register" SrcPort 1 Points [0, 0; 5, 0] Branch { Points [0, -25] DstBlock "Q" DstPort 1 } Branch { DstBlock "Inverter" DstPort 1 } } } } Block { BlockType SubSystem Name "S-R_Latch2" SID "573" Ports [2, 1] Position [1285, 245, 1325, 305] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "S-R_Latch2" Location [521, 318, 918, 591] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "S" SID "574" Position [95, 58, 125, 72] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "R" SID "575" Position [95, 88, 125, 102] Port "2" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Inverter" SID "576" Ports [1, 1] Position [220, 82, 250, 108] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "30,26,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[" "16.33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 1" "3.33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13." "33 10.33 ],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7" ".33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text')" ";\n\n\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register" SID "577" Ports [3, 1] Position [150, 70, 195, 120] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,50,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 50 50 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 50 50 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[31." "66 31.66 37.66 31.66 37.66 37.66 37.66 31.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[25.66 25.66 3" "1.66 31.66 25.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[19.66 19.66 25.66 25.66 19.66 " "],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[13.66 13.66 19.66 13.66 19.66 19.66 13.66 ],[0" ".931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor" "('black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('i" "nput',3,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfpri" "ntf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "578" Position [285, 63, 315, 77] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "Register" SrcPort 1 Points [0, 0; 5, 0] Branch { DstBlock "Inverter" DstPort 1 } Branch { Points [0, -25] DstBlock "Q" DstPort 1 } } Line { SrcBlock "Inverter" SrcPort 1 Points [10, 0; 0, 55; -130, 0] DstBlock "Register" DstPort 3 } Line { SrcBlock "S" SrcPort 1 DstBlock "Register" DstPort 1 } Line { SrcBlock "R" SrcPort 1 DstBlock "Register" DstPort 2 } } } Block { BlockType SubSystem Name "S-R_Latch3" SID "579" Ports [2, 1] Position [665, 167, 705, 238] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "S-R_Latch3" Location [202, 70, 1438, 850] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "S" SID "580" Position [95, 58, 125, 72] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "R" SID "581" Position [95, 88, 125, 102] Port "2" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Inverter" SID "582" Ports [1, 1] Position [220, 82, 250, 108] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "30,26,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[" "16.33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 1" "3.33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13." "33 10.33 ],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7" ".33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text')" ";\n\n\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register" SID "583" Ports [3, 1] Position [150, 70, 195, 120] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,50,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 50 50 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 50 50 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[31." "66 31.66 37.66 31.66 37.66 37.66 37.66 31.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[25.66 25.66 3" "1.66 31.66 25.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[19.66 19.66 25.66 25.66 19.66 " "],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[13.66 13.66 19.66 13.66 19.66 19.66 13.66 ],[0" ".931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor" "('black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('i" "nput',3,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfpri" "ntf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "584" Position [285, 63, 315, 77] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "Register" SrcPort 1 Points [0, 0; 5, 0] Branch { DstBlock "Inverter" DstPort 1 } Branch { Points [0, -25] DstBlock "Q" DstPort 1 } } Line { SrcBlock "Inverter" SrcPort 1 Points [10, 0; 0, 55; -130, 0] DstBlock "Register" DstPort 3 } Line { SrcBlock "S" SrcPort 1 DstBlock "Register" DstPort 1 } Line { SrcBlock "R" SrcPort 1 DstBlock "Register" DstPort 2 } } } Block { BlockType Reference Name "Sim Mux" SID "586" Ports [2, 1] Position [405, 261, 445, 299] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Simulation Multiplexer" SourceType "Xilinx Simulation Multiplexer Block" infoedit "Distinguish input subsystems as \"simulation only\" and \"generation only\". The input specified For " "Simulation will be used during Simulink simulation. The input specified For Generation will be used during code ge" "neration. This block will typically be used on the output of a HW Co-Simulation, Black Box, or ModelSim subsystem." "

Hardware Notes: This block costs nothing." sim_sel "1" hw_sel "2" has_advanced_control "0" sggui_pos "20,20,336,197" block_type "simmux" block_version "10.1.3" sg_icon_stat "40,38,2,1,white,blue,0,4170dd71,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 38 38 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 38 38 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[24.55 24.55 29.55" " 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[19.55 19.55 24.55 24.55 19.55 " "],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[14.55 14.55 19.55 19.55 14.55 ],[1 1 1 ]);\npatch(" "[13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 0.946 0.973 ]);\nfprintf" "('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\nfprintf('','COMMENT: end icon te" "xt');color('red');\nplot(swLineX,simSwLineY);\ncolor('black');\nplot(swLineX,hwSwLineY);\n" } Block { BlockType Reference Name "Sim Mux1" SID "587" Ports [2, 1] Position [470, 576, 510, 614] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Simulation Multiplexer" SourceType "Xilinx Simulation Multiplexer Block" infoedit "Distinguish input subsystems as \"simulation only\" and \"generation only\". The input specified For " "Simulation will be used during Simulink simulation. The input specified For Generation will be used during code ge" "neration. This block will typically be used on the output of a HW Co-Simulation, Black Box, or ModelSim subsystem." "

Hardware Notes: This block costs nothing." sim_sel "1" hw_sel "2" has_advanced_control "0" sggui_pos "20,20,336,197" block_type "simmux" block_version "10.1.3" sg_icon_stat "40,38,2,1,white,blue,0,4170dd71,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 38 38 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 38 38 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[24.55 24.55 29.55" " 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[19.55 19.55 24.55 24.55 19.55 " "],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[14.55 14.55 19.55 19.55 14.55 ],[1 1 1 ]);\npatch(" "[13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 0.946 0.973 ]);\nfprintf" "('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\nfprintf('','COMMENT: end icon te" "xt');color('red');\nplot(swLineX,simSwLineY);\ncolor('black');\nplot(swLineX,hwSwLineY);\n" } Block { BlockType SubSystem Name "Sim-only\nGateway In" SID "588" Ports [1, 1] Position [305, 260, 350, 280] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "Sim-only\nGateway In" Location [269, 280, 494, 362] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" SID "589" Position [20, 33, 50, 47] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Disregard Subsystem" SID "590" Tag "discardX" Ports [] Position [86, 85, 144, 143] ShowName off AttributesFormatString "Disregard Subsystem\\nFor Generation" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Disregard Subsystem" SourceType "Xilinx Disregard Subsystem For Generation Block" infoedit "Place this block into a subsystem to have System Generator ignore the subsystem during code ge" "neration. This block can be used in combination with the Simulation Multiplexer block to provide an alternative" " simulation model for another subsystem (e.g., to provide a simulation model for a black box)." has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "disregard" block_version "10.1.3" sg_icon_stat "58,58,-1,-1,darkgray,black,0,0,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 58 58 0 ],[0 0 58 58 ],[0.1 0.1 0." "1]);\npatch([14 4 18 4 14 29 33 37 53 40 28 19 33 19 28 40 53 37 33 29 14 ],[6 16 30 44 54 54 50 54 54 41 53 44" " 30 16 7 19 6 6 10 6 6 ],[0.33 0.33 0.33]);\nplot([0 58 58 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end ico" "n graphics');\nfprintf('','COMMENT: begin icon text');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Gateway In" SID "591" Ports [1, 1] Position [80, 30, 145, 50] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, double and fixed point to Xilinx" " fixed point type.

Hardware notes: In hardware these blocks become top level input ports." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0 0 0 0 1 0 0]" inherit_from_input off UseAsADC off ADCChannel "'1'" hdl_port "on" has_advanced_control "0" sggui_pos "20,20,348,406" block_type "gatewayin" block_version "10.1.3" sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0" ".93 0.65 ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[1" "2.22 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.2" "2 12.22 12.22 10.22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.2" "2 ],[1 1 1 ]);\npatch([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985" " 0.979 0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' " "');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "592" Position [170, 33, 200, 47] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "D" SrcPort 1 DstBlock "Gateway In" DstPort 1 } Line { SrcBlock "Gateway In" SrcPort 1 DstBlock "Q" DstPort 1 } } } Block { BlockType SubSystem Name "Sim-only\nGateway In2" SID "593" Ports [1, 1] Position [360, 575, 405, 595] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "Sim-only\nGateway In2" Location [214, 70, 1918, 1152] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" SID "594" Position [20, 33, 50, 47] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Disregard Subsystem" SID "595" Tag "discardX" Ports [] Position [71, 110, 129, 168] ShowName off AttributesFormatString "Disregard Subsystem\\nFor Generation" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Disregard Subsystem" SourceType "Xilinx Disregard Subsystem For Generation Block" infoedit "Place this block into a subsystem to have System Generator ignore the subsystem during code ge" "neration. This block can be used in combination with the Simulation Multiplexer block to provide an alternative" " simulation model for another subsystem (e.g., to provide a simulation model for a black box)." has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "disregard" block_version "10.1.3" sg_icon_stat "58,58,-1,-1,darkgray,black,0,0,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 58 58 0 ],[0 0 58 58 ],[0.1 0.1 0." "1]);\npatch([14 4 18 4 14 29 33 37 53 40 28 19 33 19 28 40 53 37 33 29 14 ],[6 16 30 44 54 54 50 54 54 41 53 44" " 30 16 7 19 6 6 10 6 6 ],[0.33 0.33 0.33]);\nplot([0 58 58 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end ico" "n graphics');\nfprintf('','COMMENT: begin icon text');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Gateway In" SID "596" Ports [1, 1] Position [80, 30, 145, 50] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, double and fixed point to Xilinx" " fixed point type.

Hardware notes: In hardware these blocks become top level input ports." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0 0 0 0 1 0 0]" inherit_from_input off UseAsADC off ADCChannel "'1'" hdl_port "on" has_advanced_control "0" sggui_pos "20,20,348,406" block_type "gatewayin" block_version "10.1.3" sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0" ".93 0.65 ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[1" "2.22 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.2" "2 12.22 12.22 10.22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.2" "2 ],[1 1 1 ]);\npatch([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985" " 0.979 0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' " "');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "597" Position [170, 33, 200, 47] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "Gateway In" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "D" SrcPort 1 DstBlock "Gateway In" DstPort 1 } } } Block { BlockType SubSystem Name "negedge" SID "598" Ports [1, 1] Position [495, 288, 525, 302] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "negedge" Location [459, 339, 854, 490] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "In" SID "599" Position [170, 213, 200, 227] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Delay" SID "600" Ports [1, 1] Position [230, 247, 290, 303] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p. If register retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "8.2" sg_icon_stat "60,56,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.8" "8 36.88 44.88 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.8" "8 36.88 28.88 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1" " 1 1 ]);\npatch([20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0" ".946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('" "black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "601" Ports [1, 1] Position [290, 191, 345, 249] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "8.2" sg_icon_stat "55,58,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 58 58 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ]" ",[36.77 36.77 43.77 36.77 43.77 43.77 43.77 36.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[29.7" "7 29.77 36.77 36.77 29.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[22.77 22.77 29.7" "7 29.77 22.77 ],[1 1 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[15.77 15.77 22.77 15.77 22.7" "7 22.77 15.77 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin i" "con text');\n\n\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical" SID "602" Ports [2, 1] Position [410, 205, 465, 265] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "8.2" sg_icon_stat "55,60,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 60 60 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ]" ",[37.77 37.77 44.77 37.77 44.77 44.77 44.77 37.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[30.7" "7 30.77 37.77 37.77 30.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[23.77 23.77 30.7" "7 30.77 23.77 ],[1 1 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[16.77 16.77 23.77 16.77 23.7" "7 23.77 16.77 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin i" "con text');\n\n\n\ncolor('black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Out" SID "603" Position [490, 228, 520, 242] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "Logical" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "In" SrcPort 1 Points [5, 0] Branch { Points [0, 55] DstBlock "Delay" DstPort 1 } Branch { DstBlock "Inverter" DstPort 1 } } Line { SrcBlock "Delay" SrcPort 1 Points [90, 0; 0, -25] DstBlock "Logical" DstPort 2 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical" DstPort 1 } } } Block { BlockType SubSystem Name "posedge" SID "604" Ports [1, 1] Position [495, 273, 525, 287] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "posedge" Location [459, 339, 854, 490] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "In" SID "605" Position [20, 33, 50, 47] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Delay" SID "606" Ports [1, 1] Position [80, 67, 140, 123] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p. If register retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "8.2" sg_icon_stat "60,56,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.8" "8 36.88 44.88 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.8" "8 36.88 28.88 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1" " 1 1 ]);\npatch([20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0" ".946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('" "black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "607" Ports [1, 1] Position [170, 66, 225, 124] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "8.2" sg_icon_stat "55,58,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 58 58 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ]" ",[36.77 36.77 43.77 36.77 43.77 43.77 43.77 36.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[29.7" "7 29.77 36.77 36.77 29.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[22.77 22.77 29.7" "7 29.77 22.77 ],[1 1 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[15.77 15.77 22.77 15.77 22.7" "7 22.77 15.77 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin i" "con text');\n\n\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical" SID "608" Ports [2, 1] Position [260, 25, 315, 85] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "8.2" sg_icon_stat "55,60,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 60 60 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ]" ",[37.77 37.77 44.77 37.77 44.77 44.77 44.77 37.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[30.7" "7 30.77 37.77 37.77 30.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[23.77 23.77 30.7" "7 30.77 23.77 ],[1 1 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[16.77 16.77 23.77 16.77 23.7" "7 23.77 16.77 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin i" "con text');\n\n\n\ncolor('black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Out" SID "609" Position [340, 48, 370, 62] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "Delay" SrcPort 1 Points [0, 0] DstBlock "Inverter" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 Points [5, 0; 0, -25] DstBlock "Logical" DstPort 2 } Line { SrcBlock "In" SrcPort 1 Points [0, 0; 5, 0] Branch { DstBlock "Logical" DstPort 1 } Branch { Points [0, 55] DstBlock "Delay" DstPort 1 } } Line { SrcBlock "Logical" SrcPort 1 Points [0, 0] DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "posedge2" SID "610" Ports [1, 1] Position [495, 323, 525, 337] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "posedge2" Location [459, 339, 854, 490] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "In" SID "611" Position [20, 33, 50, 47] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Delay" SID "612" Ports [1, 1] Position [80, 67, 140, 123] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p. If register retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "8.2" sg_icon_stat "60,56,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.8" "8 36.88 44.88 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.8" "8 36.88 28.88 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1" " 1 1 ]);\npatch([20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0" ".946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('" "black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "613" Ports [1, 1] Position [170, 66, 225, 124] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "8.2" sg_icon_stat "55,58,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 58 58 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ]" ",[36.77 36.77 43.77 36.77 43.77 43.77 43.77 36.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[29.7" "7 29.77 36.77 36.77 29.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[22.77 22.77 29.7" "7 29.77 22.77 ],[1 1 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[15.77 15.77 22.77 15.77 22.7" "7 22.77 15.77 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin i" "con text');\n\n\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical" SID "614" Ports [2, 1] Position [260, 25, 315, 85] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "8.2" sg_icon_stat "55,60,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 60 60 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ]" ",[37.77 37.77 44.77 37.77 44.77 44.77 44.77 37.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[30.7" "7 30.77 37.77 37.77 30.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[23.77 23.77 30.7" "7 30.77 23.77 ],[1 1 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[16.77 16.77 23.77 16.77 23.7" "7 23.77 16.77 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin i" "con text');\n\n\n\ncolor('black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Out" SID "615" Position [340, 48, 370, 62] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "Delay" SrcPort 1 Points [0, 0] DstBlock "Inverter" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 Points [5, 0; 0, -25] DstBlock "Logical" DstPort 2 } Line { SrcBlock "In" SrcPort 1 Points [0, 0; 5, 0] Branch { DstBlock "Logical" DstPort 1 } Branch { Points [0, 55] DstBlock "Delay" DstPort 1 } } Line { SrcBlock "Logical" SrcPort 1 Points [0, 0] DstBlock "Out" DstPort 1 } } } Block { BlockType Outport Name "done" SID "616" Position [1350, 268, 1380, 282] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Outport Name "running" SID "617" Position [1245, 518, 1275, 532] Port "2" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Outport Name "paused" SID "618" Position [1240, 463, 1270, 477] Port "3" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Outport Name "timeLeft" SID "619" Position [1285, 358, 1315, 372] Port "4" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "mode" SrcPort 1 DstBlock "Mux" DstPort 1 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Mux" DstPort 2 } Line { SrcBlock "Medium Idle" SrcPort 1 DstBlock "Mux" DstPort 3 } Line { SrcBlock "Mux" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Logical4" SrcPort 1 DstBlock "paused" DstPort 1 } Line { SrcBlock "start" SrcPort 1 DstBlock "Sim Mux" DstPort 2 } Line { SrcBlock "Sim Mux" SrcPort 1 DstBlock "posedge" DstPort 1 } Line { SrcBlock "AddSub" SrcPort 1 DstBlock "timeLeft" DstPort 1 } Line { SrcBlock "Constant" SrcPort 1 DstBlock "Relational1" DstPort 2 } Line { SrcBlock "Relational1" SrcPort 1 DstBlock "Logical4" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical4" DstPort 2 } Line { SrcBlock "S-R_Latch1" SrcPort 1 Points [25, 0] Branch { Points [0, 175] Branch { Points [0, 235] DstBlock "Counter1" DstPort 2 } Branch { Points [290, 0] Branch { DstBlock "Inverter" DstPort 1 } Branch { Points [0, 40] DstBlock "running" DstPort 1 } } } Branch { Points [0, -20] DstBlock "Logical6" DstPort 1 } } Line { SrcBlock "slotCount" SrcPort 1 Points [10, 0] Branch { Points [0, 105] DstBlock "AddSub" DstPort 1 } Branch { DstBlock "Relational" DstPort 1 } } Line { SrcBlock "Counter" SrcPort 1 Points [0, 0] Branch { Labels [1, 0] DstBlock "Relational" DstPort 2 } Branch { Points [0, 100] Branch { DstBlock "AddSub" DstPort 2 } Branch { Points [0, 65] DstBlock "Relational1" DstPort 1 } } } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Counter" DstPort 1 } Line { SrcBlock "S-R_Latch2" SrcPort 1 DstBlock "done" DstPort 1 } Line { SrcBlock "Relational" SrcPort 1 Points [10, 0] Branch { Points [0, 110; -550, 0; 0, -40] DstBlock "Logical2" DstPort 2 } Branch { Points [0, -80; -290, 0; 0, 60] DstBlock "Logical1" DstPort 1 } Branch { DstBlock "Logical7" DstPort 2 } } Line { SrcBlock "done_reset" SrcPort 1 Points [15, 0] Branch { DstBlock "S-R_Latch2" DstPort 2 } Branch { Points [0, -145; -625, 0; 0, 75] DstBlock "S-R_Latch3" DstPort 2 } } Line { SrcBlock "posedge" SrcPort 1 Points [15, 0] Branch { DstBlock "Logical3" DstPort 1 } Branch { Points [0, 400] DstBlock "Logical5" DstPort 3 } Branch { Points [0, -25] Branch { DstBlock "Logical1" DstPort 2 } Branch { Points [0, -70] DstBlock "S-R_Latch3" DstPort 1 } } } Line { SrcBlock "Logical3" SrcPort 1 DstBlock "S-R_Latch1" DstPort 1 } Line { SrcBlock "negedge" SrcPort 1 DstBlock "Logical3" DstPort 2 } Line { SrcBlock "pause" SrcPort 1 Points [115, 0] Branch { DstBlock "posedge2" DstPort 1 } Branch { Points [0, -35] DstBlock "negedge" DstPort 1 } } Line { SrcBlock "Sim-only\nGateway In" SrcPort 1 DstBlock "Sim Mux" DstPort 1 } Line { SrcBlock "slotTime" SrcPort 1 DstBlock "Relational2" DstPort 1 } Line { SrcBlock "Counter1" SrcPort 1 DstBlock "Relational2" DstPort 2 } Line { SrcBlock "Logical5" SrcPort 1 DstBlock "Counter1" DstPort 1 } Line { SrcBlock "Relational2" SrcPort 1 Points [20, 0; 0, -60; -295, 0] Branch { DstBlock "Logical5" DstPort 1 } Branch { Points [0, -320] DstBlock "Logical6" DstPort 2 } } Line { SrcBlock "Inverter1" SrcPort 1 DstBlock "Logical5" DstPort 2 } Line { SrcBlock "Logical6" SrcPort 1 DstBlock "Counter" DstPort 2 } Line { SrcBlock "Convert1" SrcPort 1 Points [25, 0; 0, -75] DstBlock "Sim Mux1" DstPort 2 } Line { SrcBlock "Sim Mux1" SrcPort 1 Points [60, 0] Branch { DstBlock "Inverter1" DstPort 1 } Branch { Points [260, 0; 0, -250] Branch { DstBlock "Logical6" DstPort 3 } Branch { DstBlock "Delay" DstPort 1 } } } Line { SrcBlock "Constant2" SrcPort 1 DstBlock "Sim-only\nGateway In" DstPort 1 } Line { SrcBlock "posedge2" SrcPort 1 Points [25, 0; 0, -15] DstBlock "Logical2" DstPort 1 } Line { SrcBlock "Logical2" SrcPort 1 DstBlock "S-R_Latch1" DstPort 2 } Line { SrcBlock "Constant4" SrcPort 1 DstBlock "Sim-only\nGateway In2" DstPort 1 } Line { SrcBlock "Sim-only\nGateway In2" SrcPort 1 DstBlock "Sim Mux1" DstPort 1 } Line { SrcBlock "Logical7" SrcPort 1 DstBlock "S-R_Latch2" DstPort 1 } Line { SrcBlock "S-R_Latch3" SrcPort 1 Points [70, 0; 0, -50; 350, 0; 0, 95] DstBlock "Logical7" DstPort 1 } Line { SrcBlock "Delay" SrcPort 1 Points [195, 0; 0, -75] DstBlock "Logical7" DstPort 3 } Annotation { Name "This SR latch handles the case of a zero-slot-count\ntimer event. When the user code sets the slotCount t" "o 0,\nthe comparison is immedilatey true. The timer done\nsignal then asserts when:\nif(carrier sensing) after IDLE" " AND\nafter user asserts start\nDone de-assets when the user clears the done bit\n*but does not re-assert* until th" "e next user-initiated start." Position [697, 92] } } } Block { BlockType SubSystem Name "Timer 5" SID "620" Ports [7, 4] Position [855, 205, 960, 325] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "Timer 5" Location [214, 74, 1910, 1156] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "start" SID "621" Position [310, 283, 340, 297] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "pause" SID "622" Position [310, 323, 340, 337] Port "2" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "mode" SID "623" Position [255, 648, 285, 662] NamePlacement "alternate" Port "3" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "done_reset" SID "624" Position [1175, 283, 1205, 297] Port "4" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "slotCount" SID "625" Position [980, 238, 1010, 252] NamePlacement "alternate" Port "5" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "slotTime" SID "626" Position [930, 658, 960, 672] Port "6" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "Medium Idle" SID "627" Position [250, 698, 280, 712] Port "7" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "AddSub" SID "628" Ports [2, 1] Position [1210, 339, 1255, 386] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Subtraction" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Unsigned" n_bits "32" bin_pt "0" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL off hw_selection "Fabric" pipelined off xl_use_area off xl_area "[16 0 0 32 0 0 0]" use_rpm "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" block_version "8.2" sg_icon_stat "45,47,2,1,white,blue,0,32e1f85f,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 47 47 0 ],[0.77 0.82 0.91" " ]);\nplot([0 45 45 0 0 ],[0 0 47 47 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[29.66 29.66 35." "66 29.66 35.66 35.66 35.66 29.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[23.66 23.66 29.66 29.66 23.66" " ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[17.66 17.66 23.66 23.66 17.66 ],[1 1 1 ]);\npatch(" "[14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[11.66 11.66 17.66 11.66 17.66 17.66 11.66 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'" ",1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bf{a - b}','texmode','" "on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant" SID "629" Ports [0, 1] Position [940, 454, 970, 466] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "50,50,400,346" block_type "constant" block_version "10.1.2" sg_icon_stat "30,12,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 12 12 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 12 12 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ],[7.11 7.11 " "8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[6.11 6.11 7.11 7.11 6.11 ],[" "0.931 0.946 0.973 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch([13." "775 17.22 16.22 15.22 14.22 12.775 13.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.931 0.946 0.973 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'0'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant1" SID "630" Ports [0, 1] Position [255, 672, 290, 688] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "8.2" sg_icon_stat "35,16,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 16 16 0 ],[0.77 0.82 0.91" " ]);\nplot([0 35 35 0 0 ],[0 0 16 16 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[10.22 10.22 1" "2.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[8.22 8.22 10.22 10.22 8.22" " ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatch([14" ".55 21.44 19.44 17.44 15.44 12.55 14.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprintf(''," "'COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Constant Name "Constant2" SID "631" Position [260, 261, 275, 279] ShowName off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Constant Name "Constant4" SID "632" Position [315, 576, 330, 594] ShowName off Value "0" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Convert1" SID "633" Ports [1, 1] Position [380, 670, 415, 690] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "16" bin_pt "14" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,461,375" block_type "convert" block_version "8.2" sg_icon_stat "35,20,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.91" " ]);\nplot([0 35 35 0 0 ],[0 0 20 20 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output'," "1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Counter" SID "634" Ports [2, 1] Position [905, 224, 965, 326] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited counter is" " implemented by combining a counter with a comparator." cnt_type "Free Running" cnt_to "Inf" operation "Up" start_count "0" cnt_by_val "1" arith_type "Unsigned" n_bits "32" bin_pt "0" load_pin off rst on en on explicit_period "on" period "1" dbl_ovrd off use_behavioral_HDL off implementation "Fabric" xl_use_area off xl_area "[17 32 0 32 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,356,630" block_type "counter" block_version "8.2" sg_icon_stat "60,102,2,1,white,blue,0,ae3608d6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 102 102 0 ],[0.77 0.82 0." "91 ]);\nplot([0 60 60 0 0 ],[0 0 102 102 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[59.88 59.88 " "67.88 59.88 67.88 67.88 67.88 59.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[51.88 51.88 59.88 59.88 51.8" "8 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[43.88 43.88 51.88 51.88 43.88 ],[1 1 1 ]);\npatch(" "[20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[35.88 35.88 43.88 35.88 43.88 43.88 35.88 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'rst');\ncolor('black');port_label('input',2,'en');\n\ncolor('black');disp('{\\fontsize{14}\\bf++}','texmode','on'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Counter1" SID "635" Ports [2, 1] Position [835, 644, 895, 746] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited counter is" " implemented by combining a counter with a comparator." cnt_type "Free Running" cnt_to "Inf" operation "Up" start_count "0" cnt_by_val "1" arith_type "Unsigned" n_bits "16" bin_pt "0" load_pin off rst on en on explicit_period "on" period "1" dbl_ovrd off use_behavioral_HDL off implementation "Fabric" xl_use_area off xl_area "[17 32 0 32 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,356,630" block_type "counter" block_version "8.2" sg_icon_stat "60,102,2,1,white,blue,0,ae3608d6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 102 102 0 ],[0.77 0.82 0." "91 ]);\nplot([0 60 60 0 0 ],[0 0 102 102 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[59.88 59.88 " "67.88 59.88 67.88 67.88 67.88 59.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[51.88 51.88 59.88 59.88 51.8" "8 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[43.88 43.88 51.88 51.88 43.88 ],[1 1 1 ]);\npatch(" "[20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[35.88 35.88 43.88 35.88 43.88 43.88 35.88 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'rst');\ncolor('black');port_label('input',2,'en');\n\ncolor('black');disp('{\\fontsize{14}\\bf++}','texmode','on'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay" SID "636" Ports [1, 1] Position [925, 331, 950, 359] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "10.1.3" sg_icon_stat "25,28,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 28 28 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 28 28 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 17.33 20" ".33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33 17.33 14.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-1}','t" "exmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "637" Ports [1, 1] Position [1080, 476, 1125, 494] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "10.1.2" sg_icon_stat "45,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.91" " ]);\nplot([0 45 45 0 0 ],[0 0 18 18 0 ]);\npatch([17.55 20.44 22.44 24.44 26.44 22.44 19.55 17.55 ],[11.22 11.22 1" "3.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([19.55 22.44 20.44 17.55 19.55 ],[9.22 9.22 11.22 11.22 9.22" " ],[0.931 0.946 0.973 ]);\npatch([17.55 20.44 22.44 19.55 17.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([19" ".55 26.44 24.44 22.44 20.44 17.55 19.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf(''," "'COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nfprintf('" "','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter1" SID "638" Ports [1, 1] Position [590, 661, 635, 679] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "10.1.2" sg_icon_stat "45,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.91" " ]);\nplot([0 45 45 0 0 ],[0 0 18 18 0 ]);\npatch([17.55 20.44 22.44 24.44 26.44 22.44 19.55 17.55 ],[11.22 11.22 1" "3.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([19.55 22.44 20.44 17.55 19.55 ],[9.22 9.22 11.22 11.22 9.22" " ],[0.931 0.946 0.973 ]);\npatch([17.55 20.44 22.44 19.55 17.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([19" ".55 26.44 24.44 22.44 20.44 17.55 19.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf(''," "'COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nfprintf('" "','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "639" Ports [2, 1] Position [855, 231, 885, 264] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "9.1.01" sg_icon_stat "30,33,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 33 33 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 33 33 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[20.44 20.44 24.44 " "20.44 24.44 24.44 24.44 20.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[16.44 16.44 20.44 20.44 16.44 ],[0." "931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[12.44 12.44 16.44 16.44 12.44 ],[1 1 1 ]);\npatch([10.1 23." "88 19.88 15.88 11.88 6.1 10.1 ],[8.44 8.44 12.44 8.44 12.44 12.44 8.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('or');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "Logical2" SID "640" Ports [2, 1] Position [590, 306, 620, 339] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "9.1.01" sg_icon_stat "30,33,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 33 33 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 33 33 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[20.44 20.44 24.44 " "20.44 24.44 24.44 24.44 20.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[16.44 16.44 20.44 20.44 16.44 ],[0." "931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[12.44 12.44 16.44 16.44 12.44 ],[1 1 1 ]);\npatch([10.1 23." "88 19.88 15.88 11.88 6.1 10.1 ],[8.44 8.44 12.44 8.44 12.44 12.44 8.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('or');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "Logical3" SID "641" Ports [2, 1] Position [590, 271, 620, 304] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "9.1.01" sg_icon_stat "30,33,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 33 33 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 33 33 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[20.44 20.44 24.44 " "20.44 24.44 24.44 24.44 20.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[16.44 16.44 20.44 20.44 16.44 ],[0." "931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[12.44 12.44 16.44 16.44 12.44 ],[1 1 1 ]);\npatch([10.1 23." "88 19.88 15.88 11.88 6.1 10.1 ],[8.44 8.44 12.44 8.44 12.44 12.44 8.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('or');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "Logical4" SID "642" Ports [2, 1] Position [1155, 433, 1200, 502] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "10.1.2" sg_icon_stat "45,69,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 69 69 0 ],[0.77 0.82 0.91" " ]);\nplot([0 45 45 0 0 ],[0 0 69 69 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[40.66 40.66 46." "66 40.66 46.66 46.66 46.66 40.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[34.66 34.66 40.66 40.66 34.66" " ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[28.66 28.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch(" "[14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 22.66 28.66 28.66 22.66 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('and');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical5" SID "643" Ports [3, 1] Position [770, 652, 805, 688] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "3" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,261" block_type "logical" block_version "8.2" sg_icon_stat "35,36,3,1,white,blue,0,a2abe52d,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 36 36 0 ],[0.77 0.82 0.91" " ]);\nplot([0 35 35 0 0 ],[0 0 36 36 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[23.55 23.55 28.55" " 23.55 28.55 28.55 28.55 23.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[18.55 18.55 23.55 23.55 18.55 " "],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[13.55 13.55 18.55 18.55 13.55 ],[1 1 1 ]);\npatch(" "[10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[8.55 8.55 13.55 8.55 13.55 13.55 8.55 ],[0.931 0.946 0.973 ]);\nfprintf" "('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n\ncolor('black');disp('or');\nfp" "rintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical6" SID "644" Ports [3, 1] Position [850, 282, 885, 318] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "3" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,261" block_type "logical" block_version "8.2" sg_icon_stat "35,36,3,1,white,blue,0,98d76266,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 36 36 0 ],[0.77 0.82 0.91" " ]);\nplot([0 35 35 0 0 ],[0 0 36 36 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[23.55 23.55 28.55" " 23.55 28.55 28.55 28.55 23.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[18.55 18.55 23.55 23.55 18.55 " "],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[13.55 13.55 18.55 18.55 13.55 ],[1 1 1 ]);\npatch(" "[10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[8.55 8.55 13.55 8.55 13.55 13.55 8.55 ],[0.931 0.946 0.973 ]);\nfprintf" "('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n\ncolor('black');disp('and');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical7" SID "645" Ports [3, 1] Position [1175, 243, 1205, 277] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "3" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,261" block_type "logical" block_version "9.1.01" sg_icon_stat "30,34,3,1,white,blue,0,98d76266,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 34 34 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 34 34 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[21.44 21.44 25.44 " "21.44 25.44 25.44 25.44 21.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[17.44 17.44 21.44 21.44 17.44 ],[0." "931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[13.44 13.44 17.44 17.44 13.44 ],[1 1 1 ]);\npatch([10.1 23." "88 19.88 15.88 11.88 6.1 10.1 ],[9.44 9.44 13.44 9.44 13.44 13.44 9.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n\ncolor('black');disp('and');\nfprintf('','" "COMMENT: end icon text');\n" } Block { BlockType Reference Name "Mux" SID "646" Ports [3, 1] Position [320, 643, 345, 717] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" block_version "8.2" sg_icon_stat "25,74,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 10.5714 63.4286 74 0 ],[0.7" "7 0.82 0.91 ]);\nplot([0 25 25 0 0 ],[0 10.5714 63.4286 74 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5" ".325 ],[40.33 40.33 43.33 40.33 43.33 43.33 43.33 40.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[37.33 " "37.33 40.33 40.33 37.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[34.33 34.33 37.33 37.33 34" ".33 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[31.33 31.33 34.33 31.33 34.33 34.33 31.33 ],[0" ".931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('input',3" ",'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational" SID "647" Ports [2, 1] Position [1060, 231, 1100, 289] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a<=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[8 0 0 16 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "relational" block_version "8.2" sg_icon_stat "40,58,2,1,white,blue,0,52e4b236,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 58 58 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 58 58 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[34.55 34.55 39.55" " 34.55 39.55 39.55 39.55 34.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[29.55 29.55 34.55 34.55 29.55 " "],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[24.55 24.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch(" "[13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[19.55 19.55 24.55 19.55 24.55 24.55 19.55 ],[0.931 0.946 0.973 ]);\nfpr" "intf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa \\leq b','texmode'," "'on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational1" SID "648" Ports [2, 1] Position [1005, 431, 1050, 469] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a>b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[16 1 0 32 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "relational" block_version "10.1.2" sg_icon_stat "45,38,2,1,white,blue,0,b5131c97,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 38 38 0 ],[0.77 0.82 0.91" " ]);\nplot([0 45 45 0 0 ],[0 0 38 38 0 ]);\npatch([10.875 18.1 23.1 28.1 33.1 23.1 15.875 10.875 ],[24.55 24.55 29." "55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([15.875 23.1 18.1 10.875 15.875 ],[19.55 19.55 24.55 24.55 19." "55 ],[0.931 0.946 0.973 ]);\npatch([10.875 18.1 23.1 15.875 10.875 ],[14.55 14.55 19.55 19.55 14.55 ],[1 1 1 ]);\np" "atch([15.875 33.1 28.1 23.1 18.1 10.875 15.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input" "',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa > b','texmode','o" "n');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational2" SID "649" Ports [2, 1] Position [985, 651, 1025, 709] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a<=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[8 0 0 16 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "relational" block_version "8.2" sg_icon_stat "40,58,2,1,white,blue,0,52e4b236,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 58 58 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 58 58 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[34.55 34.55 39.55" " 34.55 39.55 39.55 39.55 34.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[29.55 29.55 34.55 34.55 29.55 " "],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[24.55 24.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch(" "[13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[19.55 19.55 24.55 19.55 24.55 24.55 19.55 ],[0.931 0.946 0.973 ]);\nfpr" "intf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa \\leq b','texmode'," "'on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "S-R_Latch1" SID "650" Ports [2, 1] Position [665, 272, 705, 343] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "S-R_Latch1" Location [202, 70, 1438, 850] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "S" SID "651" Position [95, 58, 125, 72] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "R" SID "652" Position [95, 88, 125, 102] Port "2" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Inverter" SID "653" Ports [1, 1] Position [220, 82, 250, 108] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "30,26,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[" "16.33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 1" "3.33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13." "33 10.33 ],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7" ".33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text')" ";\n\n\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register" SID "654" Ports [3, 1] Position [150, 70, 195, 120] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,50,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 50 50 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 50 50 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[31." "66 31.66 37.66 31.66 37.66 37.66 37.66 31.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[25.66 25.66 3" "1.66 31.66 25.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[19.66 19.66 25.66 25.66 19.66 " "],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[13.66 13.66 19.66 13.66 19.66 19.66 13.66 ],[0" ".931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor" "('black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('i" "nput',3,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfpri" "ntf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "655" Position [285, 63, 315, 77] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "Register" SrcPort 1 Points [0, 0; 5, 0] Branch { DstBlock "Inverter" DstPort 1 } Branch { Points [0, -25] DstBlock "Q" DstPort 1 } } Line { SrcBlock "Inverter" SrcPort 1 Points [10, 0; 0, 55; -130, 0] DstBlock "Register" DstPort 3 } Line { SrcBlock "S" SrcPort 1 DstBlock "Register" DstPort 1 } Line { SrcBlock "R" SrcPort 1 DstBlock "Register" DstPort 2 } } } Block { BlockType SubSystem Name "S-R_Latch2" SID "656" Ports [2, 1] Position [1285, 245, 1325, 305] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "S-R_Latch2" Location [521, 318, 918, 591] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "S" SID "657" Position [95, 58, 125, 72] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "R" SID "658" Position [95, 88, 125, 102] Port "2" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Inverter" SID "659" Ports [1, 1] Position [220, 82, 250, 108] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "30,26,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[" "16.33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 1" "3.33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13." "33 10.33 ],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7" ".33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text')" ";\n\n\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register" SID "660" Ports [3, 1] Position [150, 70, 195, 120] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,50,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 50 50 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 50 50 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[31." "66 31.66 37.66 31.66 37.66 37.66 37.66 31.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[25.66 25.66 3" "1.66 31.66 25.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[19.66 19.66 25.66 25.66 19.66 " "],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[13.66 13.66 19.66 13.66 19.66 19.66 13.66 ],[0" ".931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor" "('black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('i" "nput',3,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfpri" "ntf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "661" Position [285, 63, 315, 77] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "R" SrcPort 1 DstBlock "Register" DstPort 2 } Line { SrcBlock "S" SrcPort 1 DstBlock "Register" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 Points [10, 0; 0, 55; -130, 0] DstBlock "Register" DstPort 3 } Line { SrcBlock "Register" SrcPort 1 Points [0, 0; 5, 0] Branch { Points [0, -25] DstBlock "Q" DstPort 1 } Branch { DstBlock "Inverter" DstPort 1 } } } } Block { BlockType SubSystem Name "S-R_Latch3" SID "662" Ports [2, 1] Position [665, 167, 705, 238] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "S-R_Latch3" Location [202, 70, 1438, 850] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "S" SID "663" Position [95, 58, 125, 72] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "R" SID "664" Position [95, 88, 125, 102] Port "2" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Inverter" SID "665" Ports [1, 1] Position [220, 82, 250, 108] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "30,26,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[" "16.33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 1" "3.33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13." "33 10.33 ],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7" ".33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text')" ";\n\n\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register" SID "666" Ports [3, 1] Position [150, 70, 195, 120] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,50,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 50 50 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 50 50 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[31." "66 31.66 37.66 31.66 37.66 37.66 37.66 31.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[25.66 25.66 3" "1.66 31.66 25.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[19.66 19.66 25.66 25.66 19.66 " "],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[13.66 13.66 19.66 13.66 19.66 19.66 13.66 ],[0" ".931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor" "('black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('i" "nput',3,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfpri" "ntf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "667" Position [285, 63, 315, 77] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "R" SrcPort 1 DstBlock "Register" DstPort 2 } Line { SrcBlock "S" SrcPort 1 DstBlock "Register" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 Points [10, 0; 0, 55; -130, 0] DstBlock "Register" DstPort 3 } Line { SrcBlock "Register" SrcPort 1 Points [0, 0; 5, 0] Branch { Points [0, -25] DstBlock "Q" DstPort 1 } Branch { DstBlock "Inverter" DstPort 1 } } } } Block { BlockType Reference Name "Sim Mux" SID "669" Ports [2, 1] Position [405, 261, 445, 299] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Simulation Multiplexer" SourceType "Xilinx Simulation Multiplexer Block" infoedit "Distinguish input subsystems as \"simulation only\" and \"generation only\". The input specified For " "Simulation will be used during Simulink simulation. The input specified For Generation will be used during code ge" "neration. This block will typically be used on the output of a HW Co-Simulation, Black Box, or ModelSim subsystem." "

Hardware Notes: This block costs nothing." sim_sel "1" hw_sel "2" has_advanced_control "0" sggui_pos "20,20,336,197" block_type "simmux" block_version "10.1.3" sg_icon_stat "40,38,2,1,white,blue,0,4170dd71,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 38 38 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 38 38 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[24.55 24.55 29.55" " 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[19.55 19.55 24.55 24.55 19.55 " "],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[14.55 14.55 19.55 19.55 14.55 ],[1 1 1 ]);\npatch(" "[13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 0.946 0.973 ]);\nfprintf" "('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\nfprintf('','COMMENT: end icon te" "xt');color('red');\nplot(swLineX,simSwLineY);\ncolor('black');\nplot(swLineX,hwSwLineY);\n" } Block { BlockType Reference Name "Sim Mux1" SID "670" Ports [2, 1] Position [470, 576, 510, 614] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Simulation Multiplexer" SourceType "Xilinx Simulation Multiplexer Block" infoedit "Distinguish input subsystems as \"simulation only\" and \"generation only\". The input specified For " "Simulation will be used during Simulink simulation. The input specified For Generation will be used during code ge" "neration. This block will typically be used on the output of a HW Co-Simulation, Black Box, or ModelSim subsystem." "

Hardware Notes: This block costs nothing." sim_sel "1" hw_sel "2" has_advanced_control "0" sggui_pos "20,20,336,197" block_type "simmux" block_version "10.1.3" sg_icon_stat "40,38,2,1,white,blue,0,4170dd71,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 38 38 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 38 38 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[24.55 24.55 29.55" " 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[19.55 19.55 24.55 24.55 19.55 " "],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[14.55 14.55 19.55 19.55 14.55 ],[1 1 1 ]);\npatch(" "[13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 0.946 0.973 ]);\nfprintf" "('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\nfprintf('','COMMENT: end icon te" "xt');color('red');\nplot(swLineX,simSwLineY);\ncolor('black');\nplot(swLineX,hwSwLineY);\n" } Block { BlockType SubSystem Name "Sim-only\nGateway In" SID "671" Ports [1, 1] Position [305, 260, 350, 280] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "Sim-only\nGateway In" Location [269, 280, 494, 362] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" SID "672" Position [20, 33, 50, 47] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Disregard Subsystem" SID "673" Tag "discardX" Ports [] Position [86, 85, 144, 143] ShowName off AttributesFormatString "Disregard Subsystem\\nFor Generation" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Disregard Subsystem" SourceType "Xilinx Disregard Subsystem For Generation Block" infoedit "Place this block into a subsystem to have System Generator ignore the subsystem during code ge" "neration. This block can be used in combination with the Simulation Multiplexer block to provide an alternative" " simulation model for another subsystem (e.g., to provide a simulation model for a black box)." has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "disregard" block_version "10.1.3" sg_icon_stat "58,58,-1,-1,darkgray,black,0,0,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 58 58 0 ],[0 0 58 58 ],[0.1 0.1 0." "1]);\npatch([14 4 18 4 14 29 33 37 53 40 28 19 33 19 28 40 53 37 33 29 14 ],[6 16 30 44 54 54 50 54 54 41 53 44" " 30 16 7 19 6 6 10 6 6 ],[0.33 0.33 0.33]);\nplot([0 58 58 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end ico" "n graphics');\nfprintf('','COMMENT: begin icon text');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Gateway In" SID "674" Ports [1, 1] Position [80, 30, 145, 50] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, double and fixed point to Xilinx" " fixed point type.

Hardware notes: In hardware these blocks become top level input ports." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0 0 0 0 1 0 0]" inherit_from_input off UseAsADC off ADCChannel "'1'" hdl_port "on" has_advanced_control "0" sggui_pos "20,20,348,406" block_type "gatewayin" block_version "10.1.3" sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0" ".93 0.65 ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[1" "2.22 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.2" "2 12.22 12.22 10.22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.2" "2 ],[1 1 1 ]);\npatch([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985" " 0.979 0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' " "');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "675" Position [170, 33, 200, 47] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "Gateway In" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "D" SrcPort 1 DstBlock "Gateway In" DstPort 1 } } } Block { BlockType SubSystem Name "Sim-only\nGateway In2" SID "676" Ports [1, 1] Position [360, 575, 405, 595] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "Sim-only\nGateway In2" Location [214, 70, 1918, 1152] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" SID "677" Position [20, 33, 50, 47] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Disregard Subsystem" SID "678" Tag "discardX" Ports [] Position [71, 110, 129, 168] ShowName off AttributesFormatString "Disregard Subsystem\\nFor Generation" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Disregard Subsystem" SourceType "Xilinx Disregard Subsystem For Generation Block" infoedit "Place this block into a subsystem to have System Generator ignore the subsystem during code ge" "neration. This block can be used in combination with the Simulation Multiplexer block to provide an alternative" " simulation model for another subsystem (e.g., to provide a simulation model for a black box)." has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "disregard" block_version "10.1.3" sg_icon_stat "58,58,-1,-1,darkgray,black,0,0,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 58 58 0 ],[0 0 58 58 ],[0.1 0.1 0." "1]);\npatch([14 4 18 4 14 29 33 37 53 40 28 19 33 19 28 40 53 37 33 29 14 ],[6 16 30 44 54 54 50 54 54 41 53 44" " 30 16 7 19 6 6 10 6 6 ],[0.33 0.33 0.33]);\nplot([0 58 58 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end ico" "n graphics');\nfprintf('','COMMENT: begin icon text');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Gateway In" SID "679" Ports [1, 1] Position [80, 30, 145, 50] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, double and fixed point to Xilinx" " fixed point type.

Hardware notes: In hardware these blocks become top level input ports." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0 0 0 0 1 0 0]" inherit_from_input off UseAsADC off ADCChannel "'1'" hdl_port "on" has_advanced_control "0" sggui_pos "20,20,348,406" block_type "gatewayin" block_version "10.1.3" sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0" ".93 0.65 ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[1" "2.22 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.2" "2 12.22 12.22 10.22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.2" "2 ],[1 1 1 ]);\npatch([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985" " 0.979 0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' " "');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "680" Position [170, 33, 200, 47] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "D" SrcPort 1 DstBlock "Gateway In" DstPort 1 } Line { SrcBlock "Gateway In" SrcPort 1 DstBlock "Q" DstPort 1 } } } Block { BlockType SubSystem Name "negedge" SID "681" Ports [1, 1] Position [495, 288, 525, 302] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "negedge" Location [459, 339, 854, 490] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "In" SID "682" Position [170, 213, 200, 227] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Delay" SID "683" Ports [1, 1] Position [230, 247, 290, 303] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p. If register retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "8.2" sg_icon_stat "60,56,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.8" "8 36.88 44.88 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.8" "8 36.88 28.88 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1" " 1 1 ]);\npatch([20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0" ".946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('" "black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "684" Ports [1, 1] Position [290, 191, 345, 249] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "8.2" sg_icon_stat "55,58,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 58 58 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ]" ",[36.77 36.77 43.77 36.77 43.77 43.77 43.77 36.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[29.7" "7 29.77 36.77 36.77 29.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[22.77 22.77 29.7" "7 29.77 22.77 ],[1 1 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[15.77 15.77 22.77 15.77 22.7" "7 22.77 15.77 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin i" "con text');\n\n\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical" SID "685" Ports [2, 1] Position [410, 205, 465, 265] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "8.2" sg_icon_stat "55,60,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 60 60 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ]" ",[37.77 37.77 44.77 37.77 44.77 44.77 44.77 37.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[30.7" "7 30.77 37.77 37.77 30.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[23.77 23.77 30.7" "7 30.77 23.77 ],[1 1 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[16.77 16.77 23.77 16.77 23.7" "7 23.77 16.77 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin i" "con text');\n\n\n\ncolor('black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Out" SID "686" Position [490, 228, 520, 242] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical" DstPort 1 } Line { SrcBlock "Delay" SrcPort 1 Points [90, 0; 0, -25] DstBlock "Logical" DstPort 2 } Line { SrcBlock "In" SrcPort 1 Points [5, 0] Branch { DstBlock "Inverter" DstPort 1 } Branch { Points [0, 55] DstBlock "Delay" DstPort 1 } } Line { SrcBlock "Logical" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "posedge" SID "687" Ports [1, 1] Position [495, 273, 525, 287] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "posedge" Location [459, 339, 854, 490] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "In" SID "688" Position [20, 33, 50, 47] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Delay" SID "689" Ports [1, 1] Position [80, 67, 140, 123] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p. If register retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "8.2" sg_icon_stat "60,56,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.8" "8 36.88 44.88 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.8" "8 36.88 28.88 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1" " 1 1 ]);\npatch([20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0" ".946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('" "black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "690" Ports [1, 1] Position [170, 66, 225, 124] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "8.2" sg_icon_stat "55,58,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 58 58 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ]" ",[36.77 36.77 43.77 36.77 43.77 43.77 43.77 36.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[29.7" "7 29.77 36.77 36.77 29.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[22.77 22.77 29.7" "7 29.77 22.77 ],[1 1 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[15.77 15.77 22.77 15.77 22.7" "7 22.77 15.77 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin i" "con text');\n\n\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical" SID "691" Ports [2, 1] Position [260, 25, 315, 85] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "8.2" sg_icon_stat "55,60,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 60 60 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ]" ",[37.77 37.77 44.77 37.77 44.77 44.77 44.77 37.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[30.7" "7 30.77 37.77 37.77 30.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[23.77 23.77 30.7" "7 30.77 23.77 ],[1 1 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[16.77 16.77 23.77 16.77 23.7" "7 23.77 16.77 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin i" "con text');\n\n\n\ncolor('black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Out" SID "692" Position [340, 48, 370, 62] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "Logical" SrcPort 1 Points [0, 0] DstBlock "Out" DstPort 1 } Line { SrcBlock "In" SrcPort 1 Points [0, 0; 5, 0] Branch { Points [0, 55] DstBlock "Delay" DstPort 1 } Branch { DstBlock "Logical" DstPort 1 } } Line { SrcBlock "Inverter" SrcPort 1 Points [5, 0; 0, -25] DstBlock "Logical" DstPort 2 } Line { SrcBlock "Delay" SrcPort 1 Points [0, 0] DstBlock "Inverter" DstPort 1 } } } Block { BlockType SubSystem Name "posedge2" SID "693" Ports [1, 1] Position [495, 323, 525, 337] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "posedge2" Location [459, 339, 854, 490] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "In" SID "694" Position [20, 33, 50, 47] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Delay" SID "695" Ports [1, 1] Position [80, 67, 140, 123] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p. If register retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "8.2" sg_icon_stat "60,56,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.8" "8 36.88 44.88 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.8" "8 36.88 28.88 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1" " 1 1 ]);\npatch([20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0" ".946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('" "black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "696" Ports [1, 1] Position [170, 66, 225, 124] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "8.2" sg_icon_stat "55,58,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 58 58 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ]" ",[36.77 36.77 43.77 36.77 43.77 43.77 43.77 36.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[29.7" "7 29.77 36.77 36.77 29.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[22.77 22.77 29.7" "7 29.77 22.77 ],[1 1 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[15.77 15.77 22.77 15.77 22.7" "7 22.77 15.77 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin i" "con text');\n\n\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical" SID "697" Ports [2, 1] Position [260, 25, 315, 85] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "8.2" sg_icon_stat "55,60,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 60 60 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ]" ",[37.77 37.77 44.77 37.77 44.77 44.77 44.77 37.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[30.7" "7 30.77 37.77 37.77 30.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[23.77 23.77 30.7" "7 30.77 23.77 ],[1 1 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[16.77 16.77 23.77 16.77 23.7" "7 23.77 16.77 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin i" "con text');\n\n\n\ncolor('black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Out" SID "698" Position [340, 48, 370, 62] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "Logical" SrcPort 1 Points [0, 0] DstBlock "Out" DstPort 1 } Line { SrcBlock "In" SrcPort 1 Points [0, 0; 5, 0] Branch { Points [0, 55] DstBlock "Delay" DstPort 1 } Branch { DstBlock "Logical" DstPort 1 } } Line { SrcBlock "Inverter" SrcPort 1 Points [5, 0; 0, -25] DstBlock "Logical" DstPort 2 } Line { SrcBlock "Delay" SrcPort 1 Points [0, 0] DstBlock "Inverter" DstPort 1 } } } Block { BlockType Outport Name "done" SID "699" Position [1350, 268, 1380, 282] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Outport Name "running" SID "700" Position [1245, 518, 1275, 532] Port "2" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Outport Name "paused" SID "701" Position [1240, 463, 1270, 477] Port "3" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Outport Name "timeLeft" SID "702" Position [1285, 358, 1315, 372] Port "4" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "Delay" SrcPort 1 Points [195, 0; 0, -75] DstBlock "Logical7" DstPort 3 } Line { SrcBlock "S-R_Latch3" SrcPort 1 Points [70, 0; 0, -50; 350, 0; 0, 95] DstBlock "Logical7" DstPort 1 } Line { SrcBlock "Logical7" SrcPort 1 DstBlock "S-R_Latch2" DstPort 1 } Line { SrcBlock "Sim-only\nGateway In2" SrcPort 1 DstBlock "Sim Mux1" DstPort 1 } Line { SrcBlock "Constant4" SrcPort 1 DstBlock "Sim-only\nGateway In2" DstPort 1 } Line { SrcBlock "Logical2" SrcPort 1 DstBlock "S-R_Latch1" DstPort 2 } Line { SrcBlock "posedge2" SrcPort 1 Points [25, 0; 0, -15] DstBlock "Logical2" DstPort 1 } Line { SrcBlock "Constant2" SrcPort 1 DstBlock "Sim-only\nGateway In" DstPort 1 } Line { SrcBlock "Sim Mux1" SrcPort 1 Points [60, 0] Branch { Points [260, 0; 0, -250] Branch { DstBlock "Delay" DstPort 1 } Branch { DstBlock "Logical6" DstPort 3 } } Branch { DstBlock "Inverter1" DstPort 1 } } Line { SrcBlock "Convert1" SrcPort 1 Points [25, 0; 0, -75] DstBlock "Sim Mux1" DstPort 2 } Line { SrcBlock "Logical6" SrcPort 1 DstBlock "Counter" DstPort 2 } Line { SrcBlock "Inverter1" SrcPort 1 DstBlock "Logical5" DstPort 2 } Line { SrcBlock "Relational2" SrcPort 1 Points [20, 0; 0, -60; -295, 0] Branch { Points [0, -320] DstBlock "Logical6" DstPort 2 } Branch { DstBlock "Logical5" DstPort 1 } } Line { SrcBlock "Logical5" SrcPort 1 DstBlock "Counter1" DstPort 1 } Line { SrcBlock "Counter1" SrcPort 1 DstBlock "Relational2" DstPort 2 } Line { SrcBlock "slotTime" SrcPort 1 DstBlock "Relational2" DstPort 1 } Line { SrcBlock "Sim-only\nGateway In" SrcPort 1 DstBlock "Sim Mux" DstPort 1 } Line { SrcBlock "pause" SrcPort 1 Points [115, 0] Branch { Points [0, -35] DstBlock "negedge" DstPort 1 } Branch { DstBlock "posedge2" DstPort 1 } } Line { SrcBlock "negedge" SrcPort 1 DstBlock "Logical3" DstPort 2 } Line { SrcBlock "Logical3" SrcPort 1 DstBlock "S-R_Latch1" DstPort 1 } Line { SrcBlock "posedge" SrcPort 1 Points [15, 0] Branch { Points [0, -25] Branch { Points [0, -70] DstBlock "S-R_Latch3" DstPort 1 } Branch { DstBlock "Logical1" DstPort 2 } } Branch { Points [0, 400] DstBlock "Logical5" DstPort 3 } Branch { DstBlock "Logical3" DstPort 1 } } Line { SrcBlock "done_reset" SrcPort 1 Points [15, 0] Branch { Points [0, -145; -625, 0; 0, 75] DstBlock "S-R_Latch3" DstPort 2 } Branch { DstBlock "S-R_Latch2" DstPort 2 } } Line { SrcBlock "Relational" SrcPort 1 Points [10, 0] Branch { DstBlock "Logical7" DstPort 2 } Branch { Points [0, -80; -290, 0; 0, 60] DstBlock "Logical1" DstPort 1 } Branch { Points [0, 110; -550, 0; 0, -40] DstBlock "Logical2" DstPort 2 } } Line { SrcBlock "S-R_Latch2" SrcPort 1 DstBlock "done" DstPort 1 } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Counter" DstPort 1 } Line { SrcBlock "Counter" SrcPort 1 Points [0, 0] Branch { Points [0, 100] Branch { DstBlock "AddSub" DstPort 2 } Branch { Points [0, 65] DstBlock "Relational1" DstPort 1 } } Branch { Labels [1, 0] DstBlock "Relational" DstPort 2 } } Line { SrcBlock "slotCount" SrcPort 1 Points [10, 0] Branch { DstBlock "Relational" DstPort 1 } Branch { Points [0, 105] DstBlock "AddSub" DstPort 1 } } Line { SrcBlock "S-R_Latch1" SrcPort 1 Points [25, 0] Branch { Points [0, -20] DstBlock "Logical6" DstPort 1 } Branch { Points [0, 175] Branch { Points [290, 0] Branch { Points [0, 40] DstBlock "running" DstPort 1 } Branch { DstBlock "Inverter" DstPort 1 } } Branch { Points [0, 235] DstBlock "Counter1" DstPort 2 } } } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical4" DstPort 2 } Line { SrcBlock "Relational1" SrcPort 1 DstBlock "Logical4" DstPort 1 } Line { SrcBlock "Constant" SrcPort 1 DstBlock "Relational1" DstPort 2 } Line { SrcBlock "AddSub" SrcPort 1 DstBlock "timeLeft" DstPort 1 } Line { SrcBlock "Sim Mux" SrcPort 1 DstBlock "posedge" DstPort 1 } Line { SrcBlock "start" SrcPort 1 DstBlock "Sim Mux" DstPort 2 } Line { SrcBlock "Logical4" SrcPort 1 DstBlock "paused" DstPort 1 } Line { SrcBlock "Mux" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Medium Idle" SrcPort 1 DstBlock "Mux" DstPort 3 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Mux" DstPort 2 } Line { SrcBlock "mode" SrcPort 1 DstBlock "Mux" DstPort 1 } Annotation { Name "This SR latch handles the case of a zero-slot-count\ntimer event. When the user code sets the slotCount t" "o 0,\nthe comparison is immedilatey true. The timer done\nsignal then asserts when:\nif(carrier sensing) after IDLE" " AND\nafter user asserts start\nDone de-assets when the user clears the done bit\n*but does not re-assert* until th" "e next user-initiated start." Position [697, 92] } } } Block { BlockType SubSystem Name "Timer 6" SID "703" Ports [7, 4] Position [860, 340, 965, 460] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "Timer 6" Location [214, 74, 1910, 1156] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "start" SID "704" Position [310, 283, 340, 297] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "pause" SID "705" Position [310, 323, 340, 337] Port "2" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "mode" SID "706" Position [255, 648, 285, 662] NamePlacement "alternate" Port "3" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "done_reset" SID "707" Position [1175, 283, 1205, 297] Port "4" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "slotCount" SID "708" Position [980, 238, 1010, 252] NamePlacement "alternate" Port "5" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "slotTime" SID "709" Position [930, 658, 960, 672] Port "6" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "Medium Idle" SID "710" Position [250, 698, 280, 712] Port "7" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "AddSub" SID "711" Ports [2, 1] Position [1210, 339, 1255, 386] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Subtraction" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Unsigned" n_bits "32" bin_pt "0" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL off hw_selection "Fabric" pipelined off xl_use_area off xl_area "[16 0 0 32 0 0 0]" use_rpm "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" block_version "8.2" sg_icon_stat "45,47,2,1,white,blue,0,32e1f85f,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 47 47 0 ],[0.77 0.82 0.91" " ]);\nplot([0 45 45 0 0 ],[0 0 47 47 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[29.66 29.66 35." "66 29.66 35.66 35.66 35.66 29.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[23.66 23.66 29.66 29.66 23.66" " ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[17.66 17.66 23.66 23.66 17.66 ],[1 1 1 ]);\npatch(" "[14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[11.66 11.66 17.66 11.66 17.66 17.66 11.66 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'" ",1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bf{a - b}','texmode','" "on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant" SID "712" Ports [0, 1] Position [940, 454, 970, 466] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "50,50,400,346" block_type "constant" block_version "10.1.2" sg_icon_stat "30,12,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 12 12 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 12 12 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ],[7.11 7.11 " "8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[6.11 6.11 7.11 7.11 6.11 ],[" "0.931 0.946 0.973 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch([13." "775 17.22 16.22 15.22 14.22 12.775 13.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.931 0.946 0.973 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'0'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant1" SID "713" Ports [0, 1] Position [255, 672, 290, 688] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "8.2" sg_icon_stat "35,16,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 16 16 0 ],[0.77 0.82 0.91" " ]);\nplot([0 35 35 0 0 ],[0 0 16 16 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[10.22 10.22 1" "2.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[8.22 8.22 10.22 10.22 8.22" " ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatch([14" ".55 21.44 19.44 17.44 15.44 12.55 14.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprintf(''," "'COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Constant Name "Constant2" SID "714" Position [260, 261, 275, 279] ShowName off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Constant Name "Constant4" SID "715" Position [315, 576, 330, 594] ShowName off Value "0" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Convert1" SID "716" Ports [1, 1] Position [380, 670, 415, 690] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "16" bin_pt "14" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,461,375" block_type "convert" block_version "8.2" sg_icon_stat "35,20,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.91" " ]);\nplot([0 35 35 0 0 ],[0 0 20 20 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output'," "1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Counter" SID "717" Ports [2, 1] Position [905, 224, 965, 326] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited counter is" " implemented by combining a counter with a comparator." cnt_type "Free Running" cnt_to "Inf" operation "Up" start_count "0" cnt_by_val "1" arith_type "Unsigned" n_bits "32" bin_pt "0" load_pin off rst on en on explicit_period "on" period "1" dbl_ovrd off use_behavioral_HDL off implementation "Fabric" xl_use_area off xl_area "[17 32 0 32 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,356,630" block_type "counter" block_version "8.2" sg_icon_stat "60,102,2,1,white,blue,0,ae3608d6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 102 102 0 ],[0.77 0.82 0." "91 ]);\nplot([0 60 60 0 0 ],[0 0 102 102 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[59.88 59.88 " "67.88 59.88 67.88 67.88 67.88 59.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[51.88 51.88 59.88 59.88 51.8" "8 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[43.88 43.88 51.88 51.88 43.88 ],[1 1 1 ]);\npatch(" "[20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[35.88 35.88 43.88 35.88 43.88 43.88 35.88 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'rst');\ncolor('black');port_label('input',2,'en');\n\ncolor('black');disp('{\\fontsize{14}\\bf++}','texmode','on'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Counter1" SID "718" Ports [2, 1] Position [835, 644, 895, 746] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited counter is" " implemented by combining a counter with a comparator." cnt_type "Free Running" cnt_to "Inf" operation "Up" start_count "0" cnt_by_val "1" arith_type "Unsigned" n_bits "16" bin_pt "0" load_pin off rst on en on explicit_period "on" period "1" dbl_ovrd off use_behavioral_HDL off implementation "Fabric" xl_use_area off xl_area "[17 32 0 32 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,356,630" block_type "counter" block_version "8.2" sg_icon_stat "60,102,2,1,white,blue,0,ae3608d6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 102 102 0 ],[0.77 0.82 0." "91 ]);\nplot([0 60 60 0 0 ],[0 0 102 102 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[59.88 59.88 " "67.88 59.88 67.88 67.88 67.88 59.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[51.88 51.88 59.88 59.88 51.8" "8 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[43.88 43.88 51.88 51.88 43.88 ],[1 1 1 ]);\npatch(" "[20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[35.88 35.88 43.88 35.88 43.88 43.88 35.88 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'rst');\ncolor('black');port_label('input',2,'en');\n\ncolor('black');disp('{\\fontsize{14}\\bf++}','texmode','on'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay" SID "719" Ports [1, 1] Position [925, 331, 950, 359] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "10.1.3" sg_icon_stat "25,28,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 28 28 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 28 28 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 17.33 20" ".33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33 17.33 14.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-1}','t" "exmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "720" Ports [1, 1] Position [1080, 476, 1125, 494] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "10.1.2" sg_icon_stat "45,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.91" " ]);\nplot([0 45 45 0 0 ],[0 0 18 18 0 ]);\npatch([17.55 20.44 22.44 24.44 26.44 22.44 19.55 17.55 ],[11.22 11.22 1" "3.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([19.55 22.44 20.44 17.55 19.55 ],[9.22 9.22 11.22 11.22 9.22" " ],[0.931 0.946 0.973 ]);\npatch([17.55 20.44 22.44 19.55 17.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([19" ".55 26.44 24.44 22.44 20.44 17.55 19.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf(''," "'COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nfprintf('" "','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter1" SID "721" Ports [1, 1] Position [590, 661, 635, 679] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "10.1.2" sg_icon_stat "45,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.91" " ]);\nplot([0 45 45 0 0 ],[0 0 18 18 0 ]);\npatch([17.55 20.44 22.44 24.44 26.44 22.44 19.55 17.55 ],[11.22 11.22 1" "3.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([19.55 22.44 20.44 17.55 19.55 ],[9.22 9.22 11.22 11.22 9.22" " ],[0.931 0.946 0.973 ]);\npatch([17.55 20.44 22.44 19.55 17.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([19" ".55 26.44 24.44 22.44 20.44 17.55 19.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf(''," "'COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nfprintf('" "','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "722" Ports [2, 1] Position [855, 231, 885, 264] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "9.1.01" sg_icon_stat "30,33,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 33 33 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 33 33 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[20.44 20.44 24.44 " "20.44 24.44 24.44 24.44 20.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[16.44 16.44 20.44 20.44 16.44 ],[0." "931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[12.44 12.44 16.44 16.44 12.44 ],[1 1 1 ]);\npatch([10.1 23." "88 19.88 15.88 11.88 6.1 10.1 ],[8.44 8.44 12.44 8.44 12.44 12.44 8.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('or');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "Logical2" SID "723" Ports [2, 1] Position [590, 306, 620, 339] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "9.1.01" sg_icon_stat "30,33,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 33 33 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 33 33 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[20.44 20.44 24.44 " "20.44 24.44 24.44 24.44 20.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[16.44 16.44 20.44 20.44 16.44 ],[0." "931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[12.44 12.44 16.44 16.44 12.44 ],[1 1 1 ]);\npatch([10.1 23." "88 19.88 15.88 11.88 6.1 10.1 ],[8.44 8.44 12.44 8.44 12.44 12.44 8.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('or');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "Logical3" SID "724" Ports [2, 1] Position [590, 271, 620, 304] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "9.1.01" sg_icon_stat "30,33,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 33 33 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 33 33 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[20.44 20.44 24.44 " "20.44 24.44 24.44 24.44 20.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[16.44 16.44 20.44 20.44 16.44 ],[0." "931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[12.44 12.44 16.44 16.44 12.44 ],[1 1 1 ]);\npatch([10.1 23." "88 19.88 15.88 11.88 6.1 10.1 ],[8.44 8.44 12.44 8.44 12.44 12.44 8.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('or');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "Logical4" SID "725" Ports [2, 1] Position [1155, 433, 1200, 502] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "10.1.2" sg_icon_stat "45,69,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 69 69 0 ],[0.77 0.82 0.91" " ]);\nplot([0 45 45 0 0 ],[0 0 69 69 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[40.66 40.66 46." "66 40.66 46.66 46.66 46.66 40.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[34.66 34.66 40.66 40.66 34.66" " ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[28.66 28.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch(" "[14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 22.66 28.66 28.66 22.66 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('and');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical5" SID "726" Ports [3, 1] Position [770, 652, 805, 688] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "3" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,261" block_type "logical" block_version "8.2" sg_icon_stat "35,36,3,1,white,blue,0,a2abe52d,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 36 36 0 ],[0.77 0.82 0.91" " ]);\nplot([0 35 35 0 0 ],[0 0 36 36 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[23.55 23.55 28.55" " 23.55 28.55 28.55 28.55 23.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[18.55 18.55 23.55 23.55 18.55 " "],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[13.55 13.55 18.55 18.55 13.55 ],[1 1 1 ]);\npatch(" "[10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[8.55 8.55 13.55 8.55 13.55 13.55 8.55 ],[0.931 0.946 0.973 ]);\nfprintf" "('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n\ncolor('black');disp('or');\nfp" "rintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical6" SID "727" Ports [3, 1] Position [850, 282, 885, 318] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "3" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,261" block_type "logical" block_version "8.2" sg_icon_stat "35,36,3,1,white,blue,0,98d76266,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 36 36 0 ],[0.77 0.82 0.91" " ]);\nplot([0 35 35 0 0 ],[0 0 36 36 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[23.55 23.55 28.55" " 23.55 28.55 28.55 28.55 23.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[18.55 18.55 23.55 23.55 18.55 " "],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[13.55 13.55 18.55 18.55 13.55 ],[1 1 1 ]);\npatch(" "[10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[8.55 8.55 13.55 8.55 13.55 13.55 8.55 ],[0.931 0.946 0.973 ]);\nfprintf" "('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n\ncolor('black');disp('and');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical7" SID "728" Ports [3, 1] Position [1175, 243, 1205, 277] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "3" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,261" block_type "logical" block_version "9.1.01" sg_icon_stat "30,34,3,1,white,blue,0,98d76266,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 34 34 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 34 34 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[21.44 21.44 25.44 " "21.44 25.44 25.44 25.44 21.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[17.44 17.44 21.44 21.44 17.44 ],[0." "931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[13.44 13.44 17.44 17.44 13.44 ],[1 1 1 ]);\npatch([10.1 23." "88 19.88 15.88 11.88 6.1 10.1 ],[9.44 9.44 13.44 9.44 13.44 13.44 9.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n\ncolor('black');disp('and');\nfprintf('','" "COMMENT: end icon text');\n" } Block { BlockType Reference Name "Mux" SID "729" Ports [3, 1] Position [320, 643, 345, 717] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" block_version "8.2" sg_icon_stat "25,74,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 10.5714 63.4286 74 0 ],[0.7" "7 0.82 0.91 ]);\nplot([0 25 25 0 0 ],[0 10.5714 63.4286 74 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5" ".325 ],[40.33 40.33 43.33 40.33 43.33 43.33 43.33 40.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[37.33 " "37.33 40.33 40.33 37.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[34.33 34.33 37.33 37.33 34" ".33 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[31.33 31.33 34.33 31.33 34.33 34.33 31.33 ],[0" ".931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('input',3" ",'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational" SID "730" Ports [2, 1] Position [1060, 231, 1100, 289] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a<=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[8 0 0 16 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "relational" block_version "8.2" sg_icon_stat "40,58,2,1,white,blue,0,52e4b236,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 58 58 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 58 58 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[34.55 34.55 39.55" " 34.55 39.55 39.55 39.55 34.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[29.55 29.55 34.55 34.55 29.55 " "],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[24.55 24.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch(" "[13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[19.55 19.55 24.55 19.55 24.55 24.55 19.55 ],[0.931 0.946 0.973 ]);\nfpr" "intf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa \\leq b','texmode'," "'on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational1" SID "731" Ports [2, 1] Position [1005, 431, 1050, 469] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a>b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[16 1 0 32 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "relational" block_version "10.1.2" sg_icon_stat "45,38,2,1,white,blue,0,b5131c97,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 38 38 0 ],[0.77 0.82 0.91" " ]);\nplot([0 45 45 0 0 ],[0 0 38 38 0 ]);\npatch([10.875 18.1 23.1 28.1 33.1 23.1 15.875 10.875 ],[24.55 24.55 29." "55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([15.875 23.1 18.1 10.875 15.875 ],[19.55 19.55 24.55 24.55 19." "55 ],[0.931 0.946 0.973 ]);\npatch([10.875 18.1 23.1 15.875 10.875 ],[14.55 14.55 19.55 19.55 14.55 ],[1 1 1 ]);\np" "atch([15.875 33.1 28.1 23.1 18.1 10.875 15.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input" "',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa > b','texmode','o" "n');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational2" SID "732" Ports [2, 1] Position [985, 651, 1025, 709] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a<=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[8 0 0 16 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "relational" block_version "8.2" sg_icon_stat "40,58,2,1,white,blue,0,52e4b236,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 58 58 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 58 58 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[34.55 34.55 39.55" " 34.55 39.55 39.55 39.55 34.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[29.55 29.55 34.55 34.55 29.55 " "],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[24.55 24.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch(" "[13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[19.55 19.55 24.55 19.55 24.55 24.55 19.55 ],[0.931 0.946 0.973 ]);\nfpr" "intf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa \\leq b','texmode'," "'on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "S-R_Latch1" SID "733" Ports [2, 1] Position [665, 272, 705, 343] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "S-R_Latch1" Location [202, 70, 1438, 850] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "S" SID "734" Position [95, 58, 125, 72] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "R" SID "735" Position [95, 88, 125, 102] Port "2" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Inverter" SID "736" Ports [1, 1] Position [220, 82, 250, 108] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "30,26,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[" "16.33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 1" "3.33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13." "33 10.33 ],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7" ".33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text')" ";\n\n\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register" SID "737" Ports [3, 1] Position [150, 70, 195, 120] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,50,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 50 50 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 50 50 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[31." "66 31.66 37.66 31.66 37.66 37.66 37.66 31.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[25.66 25.66 3" "1.66 31.66 25.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[19.66 19.66 25.66 25.66 19.66 " "],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[13.66 13.66 19.66 13.66 19.66 19.66 13.66 ],[0" ".931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor" "('black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('i" "nput',3,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfpri" "ntf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "738" Position [285, 63, 315, 77] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "R" SrcPort 1 DstBlock "Register" DstPort 2 } Line { SrcBlock "S" SrcPort 1 DstBlock "Register" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 Points [10, 0; 0, 55; -130, 0] DstBlock "Register" DstPort 3 } Line { SrcBlock "Register" SrcPort 1 Points [0, 0; 5, 0] Branch { Points [0, -25] DstBlock "Q" DstPort 1 } Branch { DstBlock "Inverter" DstPort 1 } } } } Block { BlockType SubSystem Name "S-R_Latch2" SID "739" Ports [2, 1] Position [1285, 245, 1325, 305] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "S-R_Latch2" Location [521, 318, 918, 591] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "S" SID "740" Position [95, 58, 125, 72] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "R" SID "741" Position [95, 88, 125, 102] Port "2" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Inverter" SID "742" Ports [1, 1] Position [220, 82, 250, 108] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "30,26,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[" "16.33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 1" "3.33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13." "33 10.33 ],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7" ".33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text')" ";\n\n\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register" SID "743" Ports [3, 1] Position [150, 70, 195, 120] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,50,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 50 50 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 50 50 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[31." "66 31.66 37.66 31.66 37.66 37.66 37.66 31.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[25.66 25.66 3" "1.66 31.66 25.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[19.66 19.66 25.66 25.66 19.66 " "],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[13.66 13.66 19.66 13.66 19.66 19.66 13.66 ],[0" ".931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor" "('black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('i" "nput',3,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfpri" "ntf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "744" Position [285, 63, 315, 77] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "Register" SrcPort 1 Points [0, 0; 5, 0] Branch { DstBlock "Inverter" DstPort 1 } Branch { Points [0, -25] DstBlock "Q" DstPort 1 } } Line { SrcBlock "Inverter" SrcPort 1 Points [10, 0; 0, 55; -130, 0] DstBlock "Register" DstPort 3 } Line { SrcBlock "S" SrcPort 1 DstBlock "Register" DstPort 1 } Line { SrcBlock "R" SrcPort 1 DstBlock "Register" DstPort 2 } } } Block { BlockType SubSystem Name "S-R_Latch3" SID "745" Ports [2, 1] Position [665, 167, 705, 238] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "S-R_Latch3" Location [202, 70, 1438, 850] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "S" SID "746" Position [95, 58, 125, 72] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "R" SID "747" Position [95, 88, 125, 102] Port "2" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Inverter" SID "748" Ports [1, 1] Position [220, 82, 250, 108] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "30,26,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[" "16.33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 1" "3.33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13." "33 10.33 ],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7" ".33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text')" ";\n\n\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register" SID "749" Ports [3, 1] Position [150, 70, 195, 120] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,50,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 50 50 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 50 50 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[31." "66 31.66 37.66 31.66 37.66 37.66 37.66 31.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[25.66 25.66 3" "1.66 31.66 25.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[19.66 19.66 25.66 25.66 19.66 " "],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[13.66 13.66 19.66 13.66 19.66 19.66 13.66 ],[0" ".931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor" "('black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('i" "nput',3,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfpri" "ntf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "750" Position [285, 63, 315, 77] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "Register" SrcPort 1 Points [0, 0; 5, 0] Branch { DstBlock "Inverter" DstPort 1 } Branch { Points [0, -25] DstBlock "Q" DstPort 1 } } Line { SrcBlock "Inverter" SrcPort 1 Points [10, 0; 0, 55; -130, 0] DstBlock "Register" DstPort 3 } Line { SrcBlock "S" SrcPort 1 DstBlock "Register" DstPort 1 } Line { SrcBlock "R" SrcPort 1 DstBlock "Register" DstPort 2 } } } Block { BlockType Reference Name "Sim Mux" SID "752" Ports [2, 1] Position [405, 261, 445, 299] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Simulation Multiplexer" SourceType "Xilinx Simulation Multiplexer Block" infoedit "Distinguish input subsystems as \"simulation only\" and \"generation only\". The input specified For " "Simulation will be used during Simulink simulation. The input specified For Generation will be used during code ge" "neration. This block will typically be used on the output of a HW Co-Simulation, Black Box, or ModelSim subsystem." "

Hardware Notes: This block costs nothing." sim_sel "1" hw_sel "2" has_advanced_control "0" sggui_pos "20,20,336,197" block_type "simmux" block_version "10.1.3" sg_icon_stat "40,38,2,1,white,blue,0,4170dd71,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 38 38 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 38 38 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[24.55 24.55 29.55" " 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[19.55 19.55 24.55 24.55 19.55 " "],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[14.55 14.55 19.55 19.55 14.55 ],[1 1 1 ]);\npatch(" "[13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 0.946 0.973 ]);\nfprintf" "('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\nfprintf('','COMMENT: end icon te" "xt');color('red');\nplot(swLineX,simSwLineY);\ncolor('black');\nplot(swLineX,hwSwLineY);\n" } Block { BlockType Reference Name "Sim Mux1" SID "753" Ports [2, 1] Position [470, 576, 510, 614] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Simulation Multiplexer" SourceType "Xilinx Simulation Multiplexer Block" infoedit "Distinguish input subsystems as \"simulation only\" and \"generation only\". The input specified For " "Simulation will be used during Simulink simulation. The input specified For Generation will be used during code ge" "neration. This block will typically be used on the output of a HW Co-Simulation, Black Box, or ModelSim subsystem." "

Hardware Notes: This block costs nothing." sim_sel "1" hw_sel "2" has_advanced_control "0" sggui_pos "20,20,336,197" block_type "simmux" block_version "10.1.3" sg_icon_stat "40,38,2,1,white,blue,0,4170dd71,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 38 38 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 38 38 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[24.55 24.55 29.55" " 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[19.55 19.55 24.55 24.55 19.55 " "],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[14.55 14.55 19.55 19.55 14.55 ],[1 1 1 ]);\npatch(" "[13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 0.946 0.973 ]);\nfprintf" "('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\nfprintf('','COMMENT: end icon te" "xt');color('red');\nplot(swLineX,simSwLineY);\ncolor('black');\nplot(swLineX,hwSwLineY);\n" } Block { BlockType SubSystem Name "Sim-only\nGateway In" SID "754" Ports [1, 1] Position [305, 260, 350, 280] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "Sim-only\nGateway In" Location [269, 280, 494, 362] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" SID "755" Position [20, 33, 50, 47] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Disregard Subsystem" SID "756" Tag "discardX" Ports [] Position [86, 85, 144, 143] ShowName off AttributesFormatString "Disregard Subsystem\\nFor Generation" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Disregard Subsystem" SourceType "Xilinx Disregard Subsystem For Generation Block" infoedit "Place this block into a subsystem to have System Generator ignore the subsystem during code ge" "neration. This block can be used in combination with the Simulation Multiplexer block to provide an alternative" " simulation model for another subsystem (e.g., to provide a simulation model for a black box)." has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "disregard" block_version "10.1.3" sg_icon_stat "58,58,-1,-1,darkgray,black,0,0,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 58 58 0 ],[0 0 58 58 ],[0.1 0.1 0." "1]);\npatch([14 4 18 4 14 29 33 37 53 40 28 19 33 19 28 40 53 37 33 29 14 ],[6 16 30 44 54 54 50 54 54 41 53 44" " 30 16 7 19 6 6 10 6 6 ],[0.33 0.33 0.33]);\nplot([0 58 58 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end ico" "n graphics');\nfprintf('','COMMENT: begin icon text');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Gateway In" SID "757" Ports [1, 1] Position [80, 30, 145, 50] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, double and fixed point to Xilinx" " fixed point type.

Hardware notes: In hardware these blocks become top level input ports." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0 0 0 0 1 0 0]" inherit_from_input off UseAsADC off ADCChannel "'1'" hdl_port "on" has_advanced_control "0" sggui_pos "20,20,348,406" block_type "gatewayin" block_version "10.1.3" sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0" ".93 0.65 ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[1" "2.22 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.2" "2 12.22 12.22 10.22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.2" "2 ],[1 1 1 ]);\npatch([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985" " 0.979 0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' " "');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "758" Position [170, 33, 200, 47] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "D" SrcPort 1 DstBlock "Gateway In" DstPort 1 } Line { SrcBlock "Gateway In" SrcPort 1 DstBlock "Q" DstPort 1 } } } Block { BlockType SubSystem Name "Sim-only\nGateway In2" SID "759" Ports [1, 1] Position [360, 575, 405, 595] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "Sim-only\nGateway In2" Location [214, 70, 1918, 1152] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" SID "760" Position [20, 33, 50, 47] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Disregard Subsystem" SID "761" Tag "discardX" Ports [] Position [71, 110, 129, 168] ShowName off AttributesFormatString "Disregard Subsystem\\nFor Generation" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Disregard Subsystem" SourceType "Xilinx Disregard Subsystem For Generation Block" infoedit "Place this block into a subsystem to have System Generator ignore the subsystem during code ge" "neration. This block can be used in combination with the Simulation Multiplexer block to provide an alternative" " simulation model for another subsystem (e.g., to provide a simulation model for a black box)." has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "disregard" block_version "10.1.3" sg_icon_stat "58,58,-1,-1,darkgray,black,0,0,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 58 58 0 ],[0 0 58 58 ],[0.1 0.1 0." "1]);\npatch([14 4 18 4 14 29 33 37 53 40 28 19 33 19 28 40 53 37 33 29 14 ],[6 16 30 44 54 54 50 54 54 41 53 44" " 30 16 7 19 6 6 10 6 6 ],[0.33 0.33 0.33]);\nplot([0 58 58 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end ico" "n graphics');\nfprintf('','COMMENT: begin icon text');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Gateway In" SID "762" Ports [1, 1] Position [80, 30, 145, 50] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, double and fixed point to Xilinx" " fixed point type.

Hardware notes: In hardware these blocks become top level input ports." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0 0 0 0 1 0 0]" inherit_from_input off UseAsADC off ADCChannel "'1'" hdl_port "on" has_advanced_control "0" sggui_pos "20,20,348,406" block_type "gatewayin" block_version "10.1.3" sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0" ".93 0.65 ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[1" "2.22 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.2" "2 12.22 12.22 10.22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.2" "2 ],[1 1 1 ]);\npatch([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985" " 0.979 0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' " "');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "763" Position [170, 33, 200, 47] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "Gateway In" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "D" SrcPort 1 DstBlock "Gateway In" DstPort 1 } } } Block { BlockType SubSystem Name "negedge" SID "764" Ports [1, 1] Position [495, 288, 525, 302] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "negedge" Location [459, 339, 854, 490] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "In" SID "765" Position [170, 213, 200, 227] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Delay" SID "766" Ports [1, 1] Position [230, 247, 290, 303] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p. If register retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "8.2" sg_icon_stat "60,56,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.8" "8 36.88 44.88 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.8" "8 36.88 28.88 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1" " 1 1 ]);\npatch([20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0" ".946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('" "black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "767" Ports [1, 1] Position [290, 191, 345, 249] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "8.2" sg_icon_stat "55,58,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 58 58 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ]" ",[36.77 36.77 43.77 36.77 43.77 43.77 43.77 36.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[29.7" "7 29.77 36.77 36.77 29.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[22.77 22.77 29.7" "7 29.77 22.77 ],[1 1 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[15.77 15.77 22.77 15.77 22.7" "7 22.77 15.77 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin i" "con text');\n\n\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical" SID "768" Ports [2, 1] Position [410, 205, 465, 265] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "8.2" sg_icon_stat "55,60,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 60 60 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ]" ",[37.77 37.77 44.77 37.77 44.77 44.77 44.77 37.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[30.7" "7 30.77 37.77 37.77 30.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[23.77 23.77 30.7" "7 30.77 23.77 ],[1 1 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[16.77 16.77 23.77 16.77 23.7" "7 23.77 16.77 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin i" "con text');\n\n\n\ncolor('black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Out" SID "769" Position [490, 228, 520, 242] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "Logical" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "In" SrcPort 1 Points [5, 0] Branch { Points [0, 55] DstBlock "Delay" DstPort 1 } Branch { DstBlock "Inverter" DstPort 1 } } Line { SrcBlock "Delay" SrcPort 1 Points [90, 0; 0, -25] DstBlock "Logical" DstPort 2 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical" DstPort 1 } } } Block { BlockType SubSystem Name "posedge" SID "770" Ports [1, 1] Position [495, 273, 525, 287] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "posedge" Location [459, 339, 854, 490] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "In" SID "771" Position [20, 33, 50, 47] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Delay" SID "772" Ports [1, 1] Position [80, 67, 140, 123] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p. If register retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "8.2" sg_icon_stat "60,56,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.8" "8 36.88 44.88 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.8" "8 36.88 28.88 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1" " 1 1 ]);\npatch([20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0" ".946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('" "black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "773" Ports [1, 1] Position [170, 66, 225, 124] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "8.2" sg_icon_stat "55,58,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 58 58 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ]" ",[36.77 36.77 43.77 36.77 43.77 43.77 43.77 36.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[29.7" "7 29.77 36.77 36.77 29.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[22.77 22.77 29.7" "7 29.77 22.77 ],[1 1 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[15.77 15.77 22.77 15.77 22.7" "7 22.77 15.77 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin i" "con text');\n\n\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical" SID "774" Ports [2, 1] Position [260, 25, 315, 85] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "8.2" sg_icon_stat "55,60,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 60 60 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ]" ",[37.77 37.77 44.77 37.77 44.77 44.77 44.77 37.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[30.7" "7 30.77 37.77 37.77 30.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[23.77 23.77 30.7" "7 30.77 23.77 ],[1 1 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[16.77 16.77 23.77 16.77 23.7" "7 23.77 16.77 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin i" "con text');\n\n\n\ncolor('black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Out" SID "775" Position [340, 48, 370, 62] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "Delay" SrcPort 1 Points [0, 0] DstBlock "Inverter" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 Points [5, 0; 0, -25] DstBlock "Logical" DstPort 2 } Line { SrcBlock "In" SrcPort 1 Points [0, 0; 5, 0] Branch { DstBlock "Logical" DstPort 1 } Branch { Points [0, 55] DstBlock "Delay" DstPort 1 } } Line { SrcBlock "Logical" SrcPort 1 Points [0, 0] DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "posedge2" SID "776" Ports [1, 1] Position [495, 323, 525, 337] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "posedge2" Location [459, 339, 854, 490] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "In" SID "777" Position [20, 33, 50, 47] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Delay" SID "778" Ports [1, 1] Position [80, 67, 140, 123] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p. If register retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "8.2" sg_icon_stat "60,56,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.8" "8 36.88 44.88 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.8" "8 36.88 28.88 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1" " 1 1 ]);\npatch([20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0" ".946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('" "black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "779" Ports [1, 1] Position [170, 66, 225, 124] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "8.2" sg_icon_stat "55,58,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 58 58 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ]" ",[36.77 36.77 43.77 36.77 43.77 43.77 43.77 36.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[29.7" "7 29.77 36.77 36.77 29.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[22.77 22.77 29.7" "7 29.77 22.77 ],[1 1 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[15.77 15.77 22.77 15.77 22.7" "7 22.77 15.77 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin i" "con text');\n\n\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical" SID "780" Ports [2, 1] Position [260, 25, 315, 85] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "8.2" sg_icon_stat "55,60,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 60 60 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ]" ",[37.77 37.77 44.77 37.77 44.77 44.77 44.77 37.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[30.7" "7 30.77 37.77 37.77 30.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[23.77 23.77 30.7" "7 30.77 23.77 ],[1 1 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[16.77 16.77 23.77 16.77 23.7" "7 23.77 16.77 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin i" "con text');\n\n\n\ncolor('black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Out" SID "781" Position [340, 48, 370, 62] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "Delay" SrcPort 1 Points [0, 0] DstBlock "Inverter" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 Points [5, 0; 0, -25] DstBlock "Logical" DstPort 2 } Line { SrcBlock "In" SrcPort 1 Points [0, 0; 5, 0] Branch { DstBlock "Logical" DstPort 1 } Branch { Points [0, 55] DstBlock "Delay" DstPort 1 } } Line { SrcBlock "Logical" SrcPort 1 Points [0, 0] DstBlock "Out" DstPort 1 } } } Block { BlockType Outport Name "done" SID "782" Position [1350, 268, 1380, 282] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Outport Name "running" SID "783" Position [1245, 518, 1275, 532] Port "2" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Outport Name "paused" SID "784" Position [1240, 463, 1270, 477] Port "3" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Outport Name "timeLeft" SID "785" Position [1285, 358, 1315, 372] Port "4" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "mode" SrcPort 1 DstBlock "Mux" DstPort 1 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Mux" DstPort 2 } Line { SrcBlock "Medium Idle" SrcPort 1 DstBlock "Mux" DstPort 3 } Line { SrcBlock "Mux" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Logical4" SrcPort 1 DstBlock "paused" DstPort 1 } Line { SrcBlock "start" SrcPort 1 DstBlock "Sim Mux" DstPort 2 } Line { SrcBlock "Sim Mux" SrcPort 1 DstBlock "posedge" DstPort 1 } Line { SrcBlock "AddSub" SrcPort 1 DstBlock "timeLeft" DstPort 1 } Line { SrcBlock "Constant" SrcPort 1 DstBlock "Relational1" DstPort 2 } Line { SrcBlock "Relational1" SrcPort 1 DstBlock "Logical4" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical4" DstPort 2 } Line { SrcBlock "S-R_Latch1" SrcPort 1 Points [25, 0] Branch { Points [0, 175] Branch { Points [0, 235] DstBlock "Counter1" DstPort 2 } Branch { Points [290, 0] Branch { DstBlock "Inverter" DstPort 1 } Branch { Points [0, 40] DstBlock "running" DstPort 1 } } } Branch { Points [0, -20] DstBlock "Logical6" DstPort 1 } } Line { SrcBlock "slotCount" SrcPort 1 Points [10, 0] Branch { Points [0, 105] DstBlock "AddSub" DstPort 1 } Branch { DstBlock "Relational" DstPort 1 } } Line { SrcBlock "Counter" SrcPort 1 Points [0, 0] Branch { Labels [1, 0] DstBlock "Relational" DstPort 2 } Branch { Points [0, 100] Branch { DstBlock "AddSub" DstPort 2 } Branch { Points [0, 65] DstBlock "Relational1" DstPort 1 } } } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Counter" DstPort 1 } Line { SrcBlock "S-R_Latch2" SrcPort 1 DstBlock "done" DstPort 1 } Line { SrcBlock "Relational" SrcPort 1 Points [10, 0] Branch { Points [0, 110; -550, 0; 0, -40] DstBlock "Logical2" DstPort 2 } Branch { Points [0, -80; -290, 0; 0, 60] DstBlock "Logical1" DstPort 1 } Branch { DstBlock "Logical7" DstPort 2 } } Line { SrcBlock "done_reset" SrcPort 1 Points [15, 0] Branch { DstBlock "S-R_Latch2" DstPort 2 } Branch { Points [0, -145; -625, 0; 0, 75] DstBlock "S-R_Latch3" DstPort 2 } } Line { SrcBlock "posedge" SrcPort 1 Points [15, 0] Branch { DstBlock "Logical3" DstPort 1 } Branch { Points [0, 400] DstBlock "Logical5" DstPort 3 } Branch { Points [0, -25] Branch { DstBlock "Logical1" DstPort 2 } Branch { Points [0, -70] DstBlock "S-R_Latch3" DstPort 1 } } } Line { SrcBlock "Logical3" SrcPort 1 DstBlock "S-R_Latch1" DstPort 1 } Line { SrcBlock "negedge" SrcPort 1 DstBlock "Logical3" DstPort 2 } Line { SrcBlock "pause" SrcPort 1 Points [115, 0] Branch { DstBlock "posedge2" DstPort 1 } Branch { Points [0, -35] DstBlock "negedge" DstPort 1 } } Line { SrcBlock "Sim-only\nGateway In" SrcPort 1 DstBlock "Sim Mux" DstPort 1 } Line { SrcBlock "slotTime" SrcPort 1 DstBlock "Relational2" DstPort 1 } Line { SrcBlock "Counter1" SrcPort 1 DstBlock "Relational2" DstPort 2 } Line { SrcBlock "Logical5" SrcPort 1 DstBlock "Counter1" DstPort 1 } Line { SrcBlock "Relational2" SrcPort 1 Points [20, 0; 0, -60; -295, 0] Branch { DstBlock "Logical5" DstPort 1 } Branch { Points [0, -320] DstBlock "Logical6" DstPort 2 } } Line { SrcBlock "Inverter1" SrcPort 1 DstBlock "Logical5" DstPort 2 } Line { SrcBlock "Logical6" SrcPort 1 DstBlock "Counter" DstPort 2 } Line { SrcBlock "Convert1" SrcPort 1 Points [25, 0; 0, -75] DstBlock "Sim Mux1" DstPort 2 } Line { SrcBlock "Sim Mux1" SrcPort 1 Points [60, 0] Branch { DstBlock "Inverter1" DstPort 1 } Branch { Points [260, 0; 0, -250] Branch { DstBlock "Logical6" DstPort 3 } Branch { DstBlock "Delay" DstPort 1 } } } Line { SrcBlock "Constant2" SrcPort 1 DstBlock "Sim-only\nGateway In" DstPort 1 } Line { SrcBlock "posedge2" SrcPort 1 Points [25, 0; 0, -15] DstBlock "Logical2" DstPort 1 } Line { SrcBlock "Logical2" SrcPort 1 DstBlock "S-R_Latch1" DstPort 2 } Line { SrcBlock "Constant4" SrcPort 1 DstBlock "Sim-only\nGateway In2" DstPort 1 } Line { SrcBlock "Sim-only\nGateway In2" SrcPort 1 DstBlock "Sim Mux1" DstPort 1 } Line { SrcBlock "Logical7" SrcPort 1 DstBlock "S-R_Latch2" DstPort 1 } Line { SrcBlock "S-R_Latch3" SrcPort 1 Points [70, 0; 0, -50; 350, 0; 0, 95] DstBlock "Logical7" DstPort 1 } Line { SrcBlock "Delay" SrcPort 1 Points [195, 0; 0, -75] DstBlock "Logical7" DstPort 3 } Annotation { Name "This SR latch handles the case of a zero-slot-count\ntimer event. When the user code sets the slotCount t" "o 0,\nthe comparison is immedilatey true. The timer done\nsignal then asserts when:\nif(carrier sensing) after IDLE" " AND\nafter user asserts start\nDone de-assets when the user clears the done bit\n*but does not re-assert* until th" "e next user-initiated start." Position [697, 92] } } } Block { BlockType SubSystem Name "Timer 7" SID "786" Ports [7, 4] Position [860, 480, 965, 600] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "Timer 7" Location [214, 74, 1910, 1156] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "start" SID "787" Position [310, 283, 340, 297] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "pause" SID "788" Position [310, 323, 340, 337] Port "2" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "mode" SID "789" Position [255, 648, 285, 662] NamePlacement "alternate" Port "3" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "done_reset" SID "790" Position [1175, 283, 1205, 297] Port "4" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "slotCount" SID "791" Position [980, 238, 1010, 252] NamePlacement "alternate" Port "5" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "slotTime" SID "792" Position [930, 658, 960, 672] Port "6" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "Medium Idle" SID "793" Position [250, 698, 280, 712] Port "7" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "AddSub" SID "794" Ports [2, 1] Position [1210, 339, 1255, 386] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/AddSub" SourceType "Xilinx Adder/Subtracter Block" mode "Subtraction" use_carryin off use_carryout off en off latency "0" precision "User Defined" arith_type "Unsigned" n_bits "32" bin_pt "0" quantization "Truncate" overflow "Wrap" dbl_ovrd off use_behavioral_HDL off hw_selection "Fabric" pipelined off xl_use_area off xl_area "[16 0 0 32 0 0 0]" use_rpm "on" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "addsub" block_version "8.2" sg_icon_stat "45,47,2,1,white,blue,0,32e1f85f,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 47 47 0 ],[0.77 0.82 0.91" " ]);\nplot([0 45 45 0 0 ],[0 0 47 47 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[29.66 29.66 35." "66 29.66 35.66 35.66 35.66 29.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[23.66 23.66 29.66 29.66 23.66" " ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[17.66 17.66 23.66 23.66 17.66 ],[1 1 1 ]);\npatch(" "[14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[11.66 11.66 17.66 11.66 17.66 17.66 11.66 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'" ",1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bf{a - b}','texmode','" "on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant" SID "795" Ports [0, 1] Position [940, 454, 970, 466] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "50,50,400,346" block_type "constant" block_version "10.1.2" sg_icon_stat "30,12,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 12 12 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 12 12 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ],[7.11 7.11 " "8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[6.11 6.11 7.11 7.11 6.11 ],[" "0.931 0.946 0.973 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1 ]);\npatch([13." "775 17.22 16.22 15.22 14.22 12.775 13.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.931 0.946 0.973 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'0'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant1" SID "796" Ports [0, 1] Position [255, 672, 290, 688] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "8.2" sg_icon_stat "35,16,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 16 16 0 ],[0.77 0.82 0.91" " ]);\nplot([0 35 35 0 0 ],[0 0 16 16 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[10.22 10.22 1" "2.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[8.22 8.22 10.22 10.22 8.22" " ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatch([14" ".55 21.44 19.44 17.44 15.44 12.55 14.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprintf(''," "'COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Constant Name "Constant2" SID "797" Position [260, 261, 275, 279] ShowName off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Constant Name "Constant4" SID "798" Position [315, 576, 330, 594] ShowName off Value "0" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Convert1" SID "799" Ports [1, 1] Position [380, 670, 415, 690] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "16" bin_pt "14" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,461,375" block_type "convert" block_version "8.2" sg_icon_stat "35,20,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.91" " ]);\nplot([0 35 35 0 0 ],[0 0 20 20 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output'," "1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Counter" SID "800" Ports [2, 1] Position [905, 224, 965, 326] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited counter is" " implemented by combining a counter with a comparator." cnt_type "Free Running" cnt_to "Inf" operation "Up" start_count "0" cnt_by_val "1" arith_type "Unsigned" n_bits "32" bin_pt "0" load_pin off rst on en on explicit_period "on" period "1" dbl_ovrd off use_behavioral_HDL off implementation "Fabric" xl_use_area off xl_area "[17 32 0 32 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,356,630" block_type "counter" block_version "8.2" sg_icon_stat "60,102,2,1,white,blue,0,ae3608d6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 102 102 0 ],[0.77 0.82 0." "91 ]);\nplot([0 60 60 0 0 ],[0 0 102 102 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[59.88 59.88 " "67.88 59.88 67.88 67.88 67.88 59.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[51.88 51.88 59.88 59.88 51.8" "8 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[43.88 43.88 51.88 51.88 43.88 ],[1 1 1 ]);\npatch(" "[20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[35.88 35.88 43.88 35.88 43.88 43.88 35.88 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'rst');\ncolor('black');port_label('input',2,'en');\n\ncolor('black');disp('{\\fontsize{14}\\bf++}','texmode','on'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Counter1" SID "801" Ports [2, 1] Position [835, 644, 895, 746] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited counter is" " implemented by combining a counter with a comparator." cnt_type "Free Running" cnt_to "Inf" operation "Up" start_count "0" cnt_by_val "1" arith_type "Unsigned" n_bits "16" bin_pt "0" load_pin off rst on en on explicit_period "on" period "1" dbl_ovrd off use_behavioral_HDL off implementation "Fabric" xl_use_area off xl_area "[17 32 0 32 0 0 0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,356,630" block_type "counter" block_version "8.2" sg_icon_stat "60,102,2,1,white,blue,0,ae3608d6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 102 102 0 ],[0.77 0.82 0." "91 ]);\nplot([0 60 60 0 0 ],[0 0 102 102 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[59.88 59.88 " "67.88 59.88 67.88 67.88 67.88 59.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[51.88 51.88 59.88 59.88 51.8" "8 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[43.88 43.88 51.88 51.88 43.88 ],[1 1 1 ]);\npatch(" "[20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[35.88 35.88 43.88 35.88 43.88 43.88 35.88 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1" ",'rst');\ncolor('black');port_label('input',2,'en');\n\ncolor('black');disp('{\\fontsize{14}\\bf++}','texmode','on'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Delay" SID "802" Ports [1, 1] Position [925, 331, 950, 359] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "10.1.3" sg_icon_stat "25,28,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 28 28 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 28 28 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[17.33 17.33 20" ".33 17.33 20.33 20.33 20.33 17.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[14.33 14.33 17.33 17.33 14.3" "3 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[11.33 11.33 14.33 14.33 11.33 ],[1 1 1 ]);\npatc" "h([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[8.33 8.33 11.33 8.33 11.33 11.33 8.33 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-1}','t" "exmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "803" Ports [1, 1] Position [1080, 476, 1125, 494] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "10.1.2" sg_icon_stat "45,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.91" " ]);\nplot([0 45 45 0 0 ],[0 0 18 18 0 ]);\npatch([17.55 20.44 22.44 24.44 26.44 22.44 19.55 17.55 ],[11.22 11.22 1" "3.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([19.55 22.44 20.44 17.55 19.55 ],[9.22 9.22 11.22 11.22 9.22" " ],[0.931 0.946 0.973 ]);\npatch([17.55 20.44 22.44 19.55 17.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([19" ".55 26.44 24.44 22.44 20.44 17.55 19.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf(''," "'COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nfprintf('" "','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter1" SID "804" Ports [1, 1] Position [590, 661, 635, 679] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "10.1.2" sg_icon_stat "45,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.91" " ]);\nplot([0 45 45 0 0 ],[0 0 18 18 0 ]);\npatch([17.55 20.44 22.44 24.44 26.44 22.44 19.55 17.55 ],[11.22 11.22 1" "3.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([19.55 22.44 20.44 17.55 19.55 ],[9.22 9.22 11.22 11.22 9.22" " ],[0.931 0.946 0.973 ]);\npatch([17.55 20.44 22.44 19.55 17.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([19" ".55 26.44 24.44 22.44 20.44 17.55 19.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf(''," "'COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nfprintf('" "','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "805" Ports [2, 1] Position [855, 231, 885, 264] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "9.1.01" sg_icon_stat "30,33,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 33 33 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 33 33 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[20.44 20.44 24.44 " "20.44 24.44 24.44 24.44 20.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[16.44 16.44 20.44 20.44 16.44 ],[0." "931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[12.44 12.44 16.44 16.44 12.44 ],[1 1 1 ]);\npatch([10.1 23." "88 19.88 15.88 11.88 6.1 10.1 ],[8.44 8.44 12.44 8.44 12.44 12.44 8.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('or');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "Logical2" SID "806" Ports [2, 1] Position [590, 306, 620, 339] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "9.1.01" sg_icon_stat "30,33,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 33 33 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 33 33 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[20.44 20.44 24.44 " "20.44 24.44 24.44 24.44 20.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[16.44 16.44 20.44 20.44 16.44 ],[0." "931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[12.44 12.44 16.44 16.44 12.44 ],[1 1 1 ]);\npatch([10.1 23." "88 19.88 15.88 11.88 6.1 10.1 ],[8.44 8.44 12.44 8.44 12.44 12.44 8.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('or');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "Logical3" SID "807" Ports [2, 1] Position [590, 271, 620, 304] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "9.1.01" sg_icon_stat "30,33,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 33 33 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 33 33 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[20.44 20.44 24.44 " "20.44 24.44 24.44 24.44 20.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[16.44 16.44 20.44 20.44 16.44 ],[0." "931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[12.44 12.44 16.44 16.44 12.44 ],[1 1 1 ]);\npatch([10.1 23." "88 19.88 15.88 11.88 6.1 10.1 ],[8.44 8.44 12.44 8.44 12.44 12.44 8.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('or');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "Logical4" SID "808" Ports [2, 1] Position [1155, 433, 1200, 502] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "10.1.2" sg_icon_stat "45,69,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 69 69 0 ],[0.77 0.82 0.91" " ]);\nplot([0 45 45 0 0 ],[0 0 69 69 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[40.66 40.66 46." "66 40.66 46.66 46.66 46.66 40.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[34.66 34.66 40.66 40.66 34.66" " ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[28.66 28.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch(" "[14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[22.66 22.66 28.66 22.66 28.66 28.66 22.66 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('and');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical5" SID "809" Ports [3, 1] Position [770, 652, 805, 688] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "3" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,261" block_type "logical" block_version "8.2" sg_icon_stat "35,36,3,1,white,blue,0,a2abe52d,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 36 36 0 ],[0.77 0.82 0.91" " ]);\nplot([0 35 35 0 0 ],[0 0 36 36 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[23.55 23.55 28.55" " 23.55 28.55 28.55 28.55 23.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[18.55 18.55 23.55 23.55 18.55 " "],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[13.55 13.55 18.55 18.55 13.55 ],[1 1 1 ]);\npatch(" "[10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[8.55 8.55 13.55 8.55 13.55 13.55 8.55 ],[0.931 0.946 0.973 ]);\nfprintf" "('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n\ncolor('black');disp('or');\nfp" "rintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical6" SID "810" Ports [3, 1] Position [850, 282, 885, 318] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "3" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,261" block_type "logical" block_version "8.2" sg_icon_stat "35,36,3,1,white,blue,0,98d76266,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 36 36 0 ],[0.77 0.82 0.91" " ]);\nplot([0 35 35 0 0 ],[0 0 36 36 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[23.55 23.55 28.55" " 23.55 28.55 28.55 28.55 23.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[18.55 18.55 23.55 23.55 18.55 " "],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[13.55 13.55 18.55 18.55 13.55 ],[1 1 1 ]);\npatch(" "[10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[8.55 8.55 13.55 8.55 13.55 13.55 8.55 ],[0.931 0.946 0.973 ]);\nfprintf" "('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n\ncolor('black');disp('and');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical7" SID "811" Ports [3, 1] Position [1175, 243, 1205, 277] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "3" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,261" block_type "logical" block_version "9.1.01" sg_icon_stat "30,34,3,1,white,blue,0,98d76266,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 34 34 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 34 34 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[21.44 21.44 25.44 " "21.44 25.44 25.44 25.44 21.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[17.44 17.44 21.44 21.44 17.44 ],[0." "931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[13.44 13.44 17.44 17.44 13.44 ],[1 1 1 ]);\npatch([10.1 23." "88 19.88 15.88 11.88 6.1 10.1 ],[9.44 9.44 13.44 9.44 13.44 13.44 9.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n\ncolor('black');disp('and');\nfprintf('','" "COMMENT: end icon text');\n" } Block { BlockType Reference Name "Mux" SID "812" Ports [3, 1] Position [320, 643, 345, 717] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" block_version "8.2" sg_icon_stat "25,74,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 10.5714 63.4286 74 0 ],[0.7" "7 0.82 0.91 ]);\nplot([0 25 25 0 0 ],[0 10.5714 63.4286 74 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5" ".325 ],[40.33 40.33 43.33 40.33 43.33 43.33 43.33 40.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[37.33 " "37.33 40.33 40.33 37.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[34.33 34.33 37.33 37.33 34" ".33 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[31.33 31.33 34.33 31.33 34.33 34.33 31.33 ],[0" ".931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('input',3" ",'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational" SID "813" Ports [2, 1] Position [1060, 231, 1100, 289] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a<=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[8 0 0 16 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "relational" block_version "8.2" sg_icon_stat "40,58,2,1,white,blue,0,52e4b236,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 58 58 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 58 58 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[34.55 34.55 39.55" " 34.55 39.55 39.55 39.55 34.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[29.55 29.55 34.55 34.55 29.55 " "],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[24.55 24.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch(" "[13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[19.55 19.55 24.55 19.55 24.55 24.55 19.55 ],[0.931 0.946 0.973 ]);\nfpr" "intf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa \\leq b','texmode'," "'on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational1" SID "814" Ports [2, 1] Position [1005, 431, 1050, 469] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a>b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[16 1 0 32 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "relational" block_version "10.1.2" sg_icon_stat "45,38,2,1,white,blue,0,b5131c97,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 38 38 0 ],[0.77 0.82 0.91" " ]);\nplot([0 45 45 0 0 ],[0 0 38 38 0 ]);\npatch([10.875 18.1 23.1 28.1 33.1 23.1 15.875 10.875 ],[24.55 24.55 29." "55 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([15.875 23.1 18.1 10.875 15.875 ],[19.55 19.55 24.55 24.55 19." "55 ],[0.931 0.946 0.973 ]);\npatch([10.875 18.1 23.1 15.875 10.875 ],[14.55 14.55 19.55 19.55 14.55 ],[1 1 1 ]);\np" "atch([15.875 33.1 28.1 23.1 18.1 10.875 15.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 0.946 0.973 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input" "',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa > b','texmode','o" "n');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational2" SID "815" Ports [2, 1] Position [985, 651, 1025, 709] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a<=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[8 0 0 16 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "relational" block_version "8.2" sg_icon_stat "40,58,2,1,white,blue,0,52e4b236,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 58 58 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 58 58 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[34.55 34.55 39.55" " 34.55 39.55 39.55 39.55 34.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[29.55 29.55 34.55 34.55 29.55 " "],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[24.55 24.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch(" "[13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[19.55 19.55 24.55 19.55 24.55 24.55 19.55 ],[0.931 0.946 0.973 ]);\nfpr" "intf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa \\leq b','texmode'," "'on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "S-R_Latch1" SID "816" Ports [2, 1] Position [665, 272, 705, 343] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "S-R_Latch1" Location [202, 70, 1438, 850] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "S" SID "817" Position [95, 58, 125, 72] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "R" SID "818" Position [95, 88, 125, 102] Port "2" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Inverter" SID "819" Ports [1, 1] Position [220, 82, 250, 108] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "30,26,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[" "16.33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 1" "3.33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13." "33 10.33 ],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7" ".33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text')" ";\n\n\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register" SID "820" Ports [3, 1] Position [150, 70, 195, 120] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,50,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 50 50 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 50 50 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[31." "66 31.66 37.66 31.66 37.66 37.66 37.66 31.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[25.66 25.66 3" "1.66 31.66 25.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[19.66 19.66 25.66 25.66 19.66 " "],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[13.66 13.66 19.66 13.66 19.66 19.66 13.66 ],[0" ".931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor" "('black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('i" "nput',3,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfpri" "ntf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "821" Position [285, 63, 315, 77] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "Register" SrcPort 1 Points [0, 0; 5, 0] Branch { DstBlock "Inverter" DstPort 1 } Branch { Points [0, -25] DstBlock "Q" DstPort 1 } } Line { SrcBlock "Inverter" SrcPort 1 Points [10, 0; 0, 55; -130, 0] DstBlock "Register" DstPort 3 } Line { SrcBlock "S" SrcPort 1 DstBlock "Register" DstPort 1 } Line { SrcBlock "R" SrcPort 1 DstBlock "Register" DstPort 2 } } } Block { BlockType SubSystem Name "S-R_Latch2" SID "822" Ports [2, 1] Position [1285, 245, 1325, 305] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "S-R_Latch2" Location [521, 318, 918, 591] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "S" SID "823" Position [95, 58, 125, 72] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "R" SID "824" Position [95, 88, 125, 102] Port "2" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Inverter" SID "825" Ports [1, 1] Position [220, 82, 250, 108] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "30,26,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[" "16.33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 1" "3.33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13." "33 10.33 ],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7" ".33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text')" ";\n\n\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register" SID "826" Ports [3, 1] Position [150, 70, 195, 120] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,50,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 50 50 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 50 50 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[31." "66 31.66 37.66 31.66 37.66 37.66 37.66 31.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[25.66 25.66 3" "1.66 31.66 25.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[19.66 19.66 25.66 25.66 19.66 " "],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[13.66 13.66 19.66 13.66 19.66 19.66 13.66 ],[0" ".931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor" "('black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('i" "nput',3,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfpri" "ntf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "827" Position [285, 63, 315, 77] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "R" SrcPort 1 DstBlock "Register" DstPort 2 } Line { SrcBlock "S" SrcPort 1 DstBlock "Register" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 Points [10, 0; 0, 55; -130, 0] DstBlock "Register" DstPort 3 } Line { SrcBlock "Register" SrcPort 1 Points [0, 0; 5, 0] Branch { Points [0, -25] DstBlock "Q" DstPort 1 } Branch { DstBlock "Inverter" DstPort 1 } } } } Block { BlockType SubSystem Name "S-R_Latch3" SID "828" Ports [2, 1] Position [665, 167, 705, 238] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "S-R_Latch3" Location [202, 70, 1438, 850] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "S" SID "829" Position [95, 58, 125, 72] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "R" SID "830" Position [95, 88, 125, 102] Port "2" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Inverter" SID "831" Ports [1, 1] Position [220, 82, 250, 108] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "VER_STRING_GOES_HERE" sg_icon_stat "30,26,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[" "16.33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 1" "3.33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13." "33 10.33 ],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7" ".33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text')" ";\n\n\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register" SID "832" Ports [3, 1] Position [150, 70, 195, 120] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,50,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 50 50 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 50 50 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[31." "66 31.66 37.66 31.66 37.66 37.66 37.66 31.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[25.66 25.66 3" "1.66 31.66 25.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[19.66 19.66 25.66 25.66 19.66 " "],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[13.66 13.66 19.66 13.66 19.66 19.66 13.66 ],[0" ".931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor" "('black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('i" "nput',3,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfpri" "ntf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "833" Position [285, 63, 315, 77] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "R" SrcPort 1 DstBlock "Register" DstPort 2 } Line { SrcBlock "S" SrcPort 1 DstBlock "Register" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 Points [10, 0; 0, 55; -130, 0] DstBlock "Register" DstPort 3 } Line { SrcBlock "Register" SrcPort 1 Points [0, 0; 5, 0] Branch { Points [0, -25] DstBlock "Q" DstPort 1 } Branch { DstBlock "Inverter" DstPort 1 } } } } Block { BlockType Reference Name "Sim Mux" SID "835" Ports [2, 1] Position [405, 261, 445, 299] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Simulation Multiplexer" SourceType "Xilinx Simulation Multiplexer Block" infoedit "Distinguish input subsystems as \"simulation only\" and \"generation only\". The input specified For " "Simulation will be used during Simulink simulation. The input specified For Generation will be used during code ge" "neration. This block will typically be used on the output of a HW Co-Simulation, Black Box, or ModelSim subsystem." "

Hardware Notes: This block costs nothing." sim_sel "1" hw_sel "2" has_advanced_control "0" sggui_pos "20,20,336,197" block_type "simmux" block_version "10.1.3" sg_icon_stat "40,38,2,1,white,blue,0,4170dd71,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 38 38 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 38 38 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[24.55 24.55 29.55" " 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[19.55 19.55 24.55 24.55 19.55 " "],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[14.55 14.55 19.55 19.55 14.55 ],[1 1 1 ]);\npatch(" "[13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 0.946 0.973 ]);\nfprintf" "('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\nfprintf('','COMMENT: end icon te" "xt');color('red');\nplot(swLineX,simSwLineY);\ncolor('black');\nplot(swLineX,hwSwLineY);\n" } Block { BlockType Reference Name "Sim Mux1" SID "836" Ports [2, 1] Position [470, 576, 510, 614] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Simulation Multiplexer" SourceType "Xilinx Simulation Multiplexer Block" infoedit "Distinguish input subsystems as \"simulation only\" and \"generation only\". The input specified For " "Simulation will be used during Simulink simulation. The input specified For Generation will be used during code ge" "neration. This block will typically be used on the output of a HW Co-Simulation, Black Box, or ModelSim subsystem." "

Hardware Notes: This block costs nothing." sim_sel "1" hw_sel "2" has_advanced_control "0" sggui_pos "20,20,336,197" block_type "simmux" block_version "10.1.3" sg_icon_stat "40,38,2,1,white,blue,0,4170dd71,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 38 38 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 38 38 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[24.55 24.55 29.55" " 24.55 29.55 29.55 29.55 24.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[19.55 19.55 24.55 24.55 19.55 " "],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[14.55 14.55 19.55 19.55 14.55 ],[1 1 1 ]);\npatch(" "[13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[9.55 9.55 14.55 9.55 14.55 14.55 9.55 ],[0.931 0.946 0.973 ]);\nfprintf" "('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\nfprintf('','COMMENT: end icon te" "xt');color('red');\nplot(swLineX,simSwLineY);\ncolor('black');\nplot(swLineX,hwSwLineY);\n" } Block { BlockType SubSystem Name "Sim-only\nGateway In" SID "837" Ports [1, 1] Position [305, 260, 350, 280] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "Sim-only\nGateway In" Location [269, 280, 494, 362] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" SID "838" Position [20, 33, 50, 47] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Disregard Subsystem" SID "839" Tag "discardX" Ports [] Position [86, 85, 144, 143] ShowName off AttributesFormatString "Disregard Subsystem\\nFor Generation" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Disregard Subsystem" SourceType "Xilinx Disregard Subsystem For Generation Block" infoedit "Place this block into a subsystem to have System Generator ignore the subsystem during code ge" "neration. This block can be used in combination with the Simulation Multiplexer block to provide an alternative" " simulation model for another subsystem (e.g., to provide a simulation model for a black box)." has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "disregard" block_version "10.1.3" sg_icon_stat "58,58,-1,-1,darkgray,black,0,0,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 58 58 0 ],[0 0 58 58 ],[0.1 0.1 0." "1]);\npatch([14 4 18 4 14 29 33 37 53 40 28 19 33 19 28 40 53 37 33 29 14 ],[6 16 30 44 54 54 50 54 54 41 53 44" " 30 16 7 19 6 6 10 6 6 ],[0.33 0.33 0.33]);\nplot([0 58 58 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end ico" "n graphics');\nfprintf('','COMMENT: begin icon text');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Gateway In" SID "840" Ports [1, 1] Position [80, 30, 145, 50] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, double and fixed point to Xilinx" " fixed point type.

Hardware notes: In hardware these blocks become top level input ports." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0 0 0 0 1 0 0]" inherit_from_input off UseAsADC off ADCChannel "'1'" hdl_port "on" has_advanced_control "0" sggui_pos "20,20,348,406" block_type "gatewayin" block_version "10.1.3" sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0" ".93 0.65 ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[1" "2.22 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.2" "2 12.22 12.22 10.22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.2" "2 ],[1 1 1 ]);\npatch([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985" " 0.979 0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' " "');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "841" Position [170, 33, 200, 47] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "Gateway In" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "D" SrcPort 1 DstBlock "Gateway In" DstPort 1 } } } Block { BlockType SubSystem Name "Sim-only\nGateway In2" SID "842" Ports [1, 1] Position [360, 575, 405, 595] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "Sim-only\nGateway In2" Location [214, 70, 1918, 1152] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" SID "843" Position [20, 33, 50, 47] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Disregard Subsystem" SID "844" Tag "discardX" Ports [] Position [71, 110, 129, 168] ShowName off AttributesFormatString "Disregard Subsystem\\nFor Generation" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Disregard Subsystem" SourceType "Xilinx Disregard Subsystem For Generation Block" infoedit "Place this block into a subsystem to have System Generator ignore the subsystem during code ge" "neration. This block can be used in combination with the Simulation Multiplexer block to provide an alternative" " simulation model for another subsystem (e.g., to provide a simulation model for a black box)." has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "disregard" block_version "10.1.3" sg_icon_stat "58,58,-1,-1,darkgray,black,0,0,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 58 58 0 ],[0 0 58 58 ],[0.1 0.1 0." "1]);\npatch([14 4 18 4 14 29 33 37 53 40 28 19 33 19 28 40 53 37 33 29 14 ],[6 16 30 44 54 54 50 54 54 41 53 44" " 30 16 7 19 6 6 10 6 6 ],[0.33 0.33 0.33]);\nplot([0 58 58 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end ico" "n graphics');\nfprintf('','COMMENT: begin icon text');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Gateway In" SID "845" Ports [1, 1] Position [80, 30, 145, 50] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, double and fixed point to Xilinx" " fixed point type.

Hardware notes: In hardware these blocks become top level input ports." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0 0 0 0 1 0 0]" inherit_from_input off UseAsADC off ADCChannel "'1'" hdl_port "on" has_advanced_control "0" sggui_pos "20,20,348,406" block_type "gatewayin" block_version "10.1.3" sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0" ".93 0.65 ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[1" "2.22 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.2" "2 12.22 12.22 10.22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.2" "2 ],[1 1 1 ]);\npatch([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985" " 0.979 0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' " "');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "846" Position [170, 33, 200, 47] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "D" SrcPort 1 DstBlock "Gateway In" DstPort 1 } Line { SrcBlock "Gateway In" SrcPort 1 DstBlock "Q" DstPort 1 } } } Block { BlockType SubSystem Name "negedge" SID "847" Ports [1, 1] Position [495, 288, 525, 302] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "negedge" Location [459, 339, 854, 490] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "In" SID "848" Position [170, 213, 200, 227] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Delay" SID "849" Ports [1, 1] Position [230, 247, 290, 303] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p. If register retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "8.2" sg_icon_stat "60,56,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.8" "8 36.88 44.88 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.8" "8 36.88 28.88 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1" " 1 1 ]);\npatch([20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0" ".946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('" "black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "850" Ports [1, 1] Position [290, 191, 345, 249] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "8.2" sg_icon_stat "55,58,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 58 58 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ]" ",[36.77 36.77 43.77 36.77 43.77 43.77 43.77 36.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[29.7" "7 29.77 36.77 36.77 29.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[22.77 22.77 29.7" "7 29.77 22.77 ],[1 1 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[15.77 15.77 22.77 15.77 22.7" "7 22.77 15.77 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin i" "con text');\n\n\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical" SID "851" Ports [2, 1] Position [410, 205, 465, 265] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "8.2" sg_icon_stat "55,60,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 60 60 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ]" ",[37.77 37.77 44.77 37.77 44.77 44.77 44.77 37.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[30.7" "7 30.77 37.77 37.77 30.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[23.77 23.77 30.7" "7 30.77 23.77 ],[1 1 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[16.77 16.77 23.77 16.77 23.7" "7 23.77 16.77 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin i" "con text');\n\n\n\ncolor('black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Out" SID "852" Position [490, 228, 520, 242] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical" DstPort 1 } Line { SrcBlock "Delay" SrcPort 1 Points [90, 0; 0, -25] DstBlock "Logical" DstPort 2 } Line { SrcBlock "In" SrcPort 1 Points [5, 0] Branch { DstBlock "Inverter" DstPort 1 } Branch { Points [0, 55] DstBlock "Delay" DstPort 1 } } Line { SrcBlock "Logical" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "posedge" SID "853" Ports [1, 1] Position [495, 273, 525, 287] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "posedge" Location [459, 339, 854, 490] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "In" SID "854" Position [20, 33, 50, 47] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Delay" SID "855" Ports [1, 1] Position [80, 67, 140, 123] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p. If register retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "8.2" sg_icon_stat "60,56,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.8" "8 36.88 44.88 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.8" "8 36.88 28.88 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1" " 1 1 ]);\npatch([20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0" ".946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('" "black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "856" Ports [1, 1] Position [170, 66, 225, 124] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "8.2" sg_icon_stat "55,58,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 58 58 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ]" ",[36.77 36.77 43.77 36.77 43.77 43.77 43.77 36.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[29.7" "7 29.77 36.77 36.77 29.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[22.77 22.77 29.7" "7 29.77 22.77 ],[1 1 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[15.77 15.77 22.77 15.77 22.7" "7 22.77 15.77 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin i" "con text');\n\n\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical" SID "857" Ports [2, 1] Position [260, 25, 315, 85] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "8.2" sg_icon_stat "55,60,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 60 60 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ]" ",[37.77 37.77 44.77 37.77 44.77 44.77 44.77 37.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[30.7" "7 30.77 37.77 37.77 30.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[23.77 23.77 30.7" "7 30.77 23.77 ],[1 1 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[16.77 16.77 23.77 16.77 23.7" "7 23.77 16.77 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin i" "con text');\n\n\n\ncolor('black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Out" SID "858" Position [340, 48, 370, 62] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "Logical" SrcPort 1 Points [0, 0] DstBlock "Out" DstPort 1 } Line { SrcBlock "In" SrcPort 1 Points [0, 0; 5, 0] Branch { Points [0, 55] DstBlock "Delay" DstPort 1 } Branch { DstBlock "Logical" DstPort 1 } } Line { SrcBlock "Inverter" SrcPort 1 Points [5, 0; 0, -25] DstBlock "Logical" DstPort 2 } Line { SrcBlock "Delay" SrcPort 1 Points [0, 0] DstBlock "Inverter" DstPort 1 } } } Block { BlockType SubSystem Name "posedge2" SID "859" Ports [1, 1] Position [495, 323, 525, 337] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "posedge2" Location [459, 339, 854, 490] Open off ModelBrowserVisibility on ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "In" SID "860" Position [20, 33, 50, 47] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Delay" SID "861" Ports [1, 1] Position [80, 67, 140, 123] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p. If register retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[1 1 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "8.2" sg_icon_stat "60,56,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.8" "8 36.88 44.88 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.8" "8 36.88 28.88 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1" " 1 1 ]);\npatch([20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0" ".946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('" "black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "862" Ports [1, 1] Position [170, 66, 225, 124] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0 0 0 0 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "8.2" sg_icon_stat "55,58,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 58 58 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ]" ",[36.77 36.77 43.77 36.77 43.77 43.77 43.77 36.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[29.7" "7 29.77 36.77 36.77 29.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[22.77 22.77 29.7" "7 29.77 22.77 ],[1 1 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[15.77 15.77 22.77 15.77 22.7" "7 22.77 15.77 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin i" "con text');\n\n\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical" SID "863" Ports [2, 1] Position [260, 25, 315, 85] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[1 0 0 1 0 0 0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "8.2" sg_icon_stat "55,60,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 60 60 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ]" ",[37.77 37.77 44.77 37.77 44.77 44.77 44.77 37.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[30.7" "7 30.77 37.77 37.77 30.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[23.77 23.77 30.7" "7 30.77 23.77 ],[1 1 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[16.77 16.77 23.77 16.77 23.7" "7 23.77 16.77 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin i" "con text');\n\n\n\ncolor('black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Out" SID "864" Position [340, 48, 370, 62] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "Logical" SrcPort 1 Points [0, 0] DstBlock "Out" DstPort 1 } Line { SrcBlock "In" SrcPort 1 Points [0, 0; 5, 0] Branch { Points [0, 55] DstBlock "Delay" DstPort 1 } Branch { DstBlock "Logical" DstPort 1 } } Line { SrcBlock "Inverter" SrcPort 1 Points [5, 0; 0, -25] DstBlock "Logical" DstPort 2 } Line { SrcBlock "Delay" SrcPort 1 Points [0, 0] DstBlock "Inverter" DstPort 1 } } } Block { BlockType Outport Name "done" SID "865" Position [1350, 268, 1380, 282] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Outport Name "running" SID "866" Position [1245, 518, 1275, 532] Port "2" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Outport Name "paused" SID "867" Position [1240, 463, 1270, 477] Port "3" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Outport Name "timeLeft" SID "868" Position [1285, 358, 1315, 372] Port "4" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "Delay" SrcPort 1 Points [195, 0; 0, -75] DstBlock "Logical7" DstPort 3 } Line { SrcBlock "S-R_Latch3" SrcPort 1 Points [70, 0; 0, -50; 350, 0; 0, 95] DstBlock "Logical7" DstPort 1 } Line { SrcBlock "Logical7" SrcPort 1 DstBlock "S-R_Latch2" DstPort 1 } Line { SrcBlock "Sim-only\nGateway In2" SrcPort 1 DstBlock "Sim Mux1" DstPort 1 } Line { SrcBlock "Constant4" SrcPort 1 DstBlock "Sim-only\nGateway In2" DstPort 1 } Line { SrcBlock "Logical2" SrcPort 1 DstBlock "S-R_Latch1" DstPort 2 } Line { SrcBlock "posedge2" SrcPort 1 Points [25, 0; 0, -15] DstBlock "Logical2" DstPort 1 } Line { SrcBlock "Constant2" SrcPort 1 DstBlock "Sim-only\nGateway In" DstPort 1 } Line { SrcBlock "Sim Mux1" SrcPort 1 Points [60, 0] Branch { Points [260, 0; 0, -250] Branch { DstBlock "Delay" DstPort 1 } Branch { DstBlock "Logical6" DstPort 3 } } Branch { DstBlock "Inverter1" DstPort 1 } } Line { SrcBlock "Convert1" SrcPort 1 Points [25, 0; 0, -75] DstBlock "Sim Mux1" DstPort 2 } Line { SrcBlock "Logical6" SrcPort 1 DstBlock "Counter" DstPort 2 } Line { SrcBlock "Inverter1" SrcPort 1 DstBlock "Logical5" DstPort 2 } Line { SrcBlock "Relational2" SrcPort 1 Points [20, 0; 0, -60; -295, 0] Branch { Points [0, -320] DstBlock "Logical6" DstPort 2 } Branch { DstBlock "Logical5" DstPort 1 } } Line { SrcBlock "Logical5" SrcPort 1 DstBlock "Counter1" DstPort 1 } Line { SrcBlock "Counter1" SrcPort 1 DstBlock "Relational2" DstPort 2 } Line { SrcBlock "slotTime" SrcPort 1 DstBlock "Relational2" DstPort 1 } Line { SrcBlock "Sim-only\nGateway In" SrcPort 1 DstBlock "Sim Mux" DstPort 1 } Line { SrcBlock "pause" SrcPort 1 Points [115, 0] Branch { Points [0, -35] DstBlock "negedge" DstPort 1 } Branch { DstBlock "posedge2" DstPort 1 } } Line { SrcBlock "negedge" SrcPort 1 DstBlock "Logical3" DstPort 2 } Line { SrcBlock "Logical3" SrcPort 1 DstBlock "S-R_Latch1" DstPort 1 } Line { SrcBlock "posedge" SrcPort 1 Points [15, 0] Branch { Points [0, -25] Branch { Points [0, -70] DstBlock "S-R_Latch3" DstPort 1 } Branch { DstBlock "Logical1" DstPort 2 } } Branch { Points [0, 400] DstBlock "Logical5" DstPort 3 } Branch { DstBlock "Logical3" DstPort 1 } } Line { SrcBlock "done_reset" SrcPort 1 Points [15, 0] Branch { Points [0, -145; -625, 0; 0, 75] DstBlock "S-R_Latch3" DstPort 2 } Branch { DstBlock "S-R_Latch2" DstPort 2 } } Line { SrcBlock "Relational" SrcPort 1 Points [10, 0] Branch { DstBlock "Logical7" DstPort 2 } Branch { Points [0, -80; -290, 0; 0, 60] DstBlock "Logical1" DstPort 1 } Branch { Points [0, 110; -550, 0; 0, -40] DstBlock "Logical2" DstPort 2 } } Line { SrcBlock "S-R_Latch2" SrcPort 1 DstBlock "done" DstPort 1 } Line { SrcBlock "Logical1" SrcPort 1 DstBlock "Counter" DstPort 1 } Line { SrcBlock "Counter" SrcPort 1 Points [0, 0] Branch { Points [0, 100] Branch { DstBlock "AddSub" DstPort 2 } Branch { Points [0, 65] DstBlock "Relational1" DstPort 1 } } Branch { Labels [1, 0] DstBlock "Relational" DstPort 2 } } Line { SrcBlock "slotCount" SrcPort 1 Points [10, 0] Branch { DstBlock "Relational" DstPort 1 } Branch { Points [0, 105] DstBlock "AddSub" DstPort 1 } } Line { SrcBlock "S-R_Latch1" SrcPort 1 Points [25, 0] Branch { Points [0, -20] DstBlock "Logical6" DstPort 1 } Branch { Points [0, 175] Branch { Points [290, 0] Branch { Points [0, 40] DstBlock "running" DstPort 1 } Branch { DstBlock "Inverter" DstPort 1 } } Branch { Points [0, 235] DstBlock "Counter1" DstPort 2 } } } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical4" DstPort 2 } Line { SrcBlock "Relational1" SrcPort 1 DstBlock "Logical4" DstPort 1 } Line { SrcBlock "Constant" SrcPort 1 DstBlock "Relational1" DstPort 2 } Line { SrcBlock "AddSub" SrcPort 1 DstBlock "timeLeft" DstPort 1 } Line { SrcBlock "Sim Mux" SrcPort 1 DstBlock "posedge" DstPort 1 } Line { SrcBlock "start" SrcPort 1 DstBlock "Sim Mux" DstPort 2 } Line { SrcBlock "Logical4" SrcPort 1 DstBlock "paused" DstPort 1 } Line { SrcBlock "Mux" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Medium Idle" SrcPort 1 DstBlock "Mux" DstPort 3 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Mux" DstPort 2 } Line { SrcBlock "mode" SrcPort 1 DstBlock "Mux" DstPort 1 } Annotation { Name "This SR latch handles the case of a zero-slot-count\ntimer event. When the user code sets the slotCount t" "o 0,\nthe comparison is immedilatey true. The timer done\nsignal then asserts when:\nif(carrier sensing) after IDLE" " AND\nafter user asserts start\nDone de-assets when the user clears the done bit\n*but does not re-assert* until th" "e next user-initiated start." Position [697, 92] } } } Line { SrcBlock "Constant" SrcPort 1 DstBlock "IDLEFORDIFS" DstPort 1 } Line { SrcBlock "From" SrcPort 1 DstBlock "Timer 0" DstPort 4 } Line { SrcBlock "From1" SrcPort 1 DstBlock "Timer 0" DstPort 3 } Line { SrcBlock "From2" SrcPort 1 DstBlock "Timer 0" DstPort 2 } Line { SrcBlock "From3" SrcPort 1 DstBlock "Timer 0" DstPort 1 } Line { SrcBlock "From4" SrcPort 1 DstBlock "Timer 0" DstPort 5 } Line { SrcBlock "From5" SrcPort 1 DstBlock "Timer 0" DstPort 6 } Line { SrcBlock "From6" SrcPort 1 DstBlock "Timer 1" DstPort 4 } Line { SrcBlock "From7" SrcPort 1 DstBlock "Timer 1" DstPort 3 } Line { SrcBlock "From8" SrcPort 1 DstBlock "Timer 1" DstPort 2 } Line { SrcBlock "From9" SrcPort 1 DstBlock "Timer 1" DstPort 1 } Line { SrcBlock "From10" SrcPort 1 DstBlock "Timer 1" DstPort 5 } Line { SrcBlock "From11" SrcPort 1 DstBlock "Timer 1" DstPort 6 } Line { SrcBlock "From14" SrcPort 1 DstBlock "Timer 2" DstPort 4 } Line { SrcBlock "From15" SrcPort 1 DstBlock "Timer 2" DstPort 3 } Line { SrcBlock "From16" SrcPort 1 DstBlock "Timer 2" DstPort 2 } Line { SrcBlock "From17" SrcPort 1 DstBlock "Timer 2" DstPort 1 } Line { SrcBlock "From12" SrcPort 1 DstBlock "Timer 2" DstPort 5 } Line { SrcBlock "From13" SrcPort 1 DstBlock "Timer 2" DstPort 6 } Line { SrcBlock "From20" SrcPort 1 DstBlock "Timer 3" DstPort 4 } Line { SrcBlock "From21" SrcPort 1 DstBlock "Timer 3" DstPort 3 } Line { SrcBlock "From22" SrcPort 1 DstBlock "Timer 3" DstPort 2 } Line { SrcBlock "From23" SrcPort 1 DstBlock "Timer 3" DstPort 1 } Line { SrcBlock "From18" SrcPort 1 DstBlock "Timer 3" DstPort 5 } Line { SrcBlock "From19" SrcPort 1 DstBlock "Timer 3" DstPort 6 } Line { SrcBlock "From24" SrcPort 1 DstBlock "Timer 4" DstPort 4 } Line { SrcBlock "From25" SrcPort 1 DstBlock "Timer 4" DstPort 3 } Line { SrcBlock "From36" SrcPort 1 DstBlock "Timer 4" DstPort 2 } Line { SrcBlock "From41" SrcPort 1 DstBlock "Timer 4" DstPort 1 } Line { SrcBlock "From42" SrcPort 1 DstBlock "Timer 4" DstPort 5 } Line { SrcBlock "From43" SrcPort 1 DstBlock "Timer 4" DstPort 6 } Line { SrcBlock "From44" SrcPort 1 DstBlock "Timer 5" DstPort 4 } Line { SrcBlock "From45" SrcPort 1 DstBlock "Timer 5" DstPort 3 } Line { SrcBlock "From46" SrcPort 1 DstBlock "Timer 5" DstPort 2 } Line { SrcBlock "From47" SrcPort 1 DstBlock "Timer 5" DstPort 1 } Line { SrcBlock "From26" SrcPort 1 DstBlock "Timer 5" DstPort 5 } Line { SrcBlock "From27" SrcPort 1 DstBlock "Timer 5" DstPort 6 } Line { SrcBlock "From30" SrcPort 1 DstBlock "Timer 6" DstPort 4 } Line { SrcBlock "From31" SrcPort 1 DstBlock "Timer 6" DstPort 3 } Line { SrcBlock "From32" SrcPort 1 DstBlock "Timer 6" DstPort 2 } Line { SrcBlock "From33" SrcPort 1 DstBlock "Timer 6" DstPort 1 } Line { SrcBlock "From28" SrcPort 1 DstBlock "Timer 6" DstPort 5 } Line { SrcBlock "From29" SrcPort 1 DstBlock "Timer 6" DstPort 6 } Line { SrcBlock "From37" SrcPort 1 DstBlock "Timer 7" DstPort 4 } Line { SrcBlock "From38" SrcPort 1 DstBlock "Timer 7" DstPort 3 } Line { SrcBlock "From39" SrcPort 1 DstBlock "Timer 7" DstPort 2 } Line { SrcBlock "From40" SrcPort 1 DstBlock "Timer 7" DstPort 1 } Line { SrcBlock "From34" SrcPort 1 DstBlock "Timer 7" DstPort 5 } Line { SrcBlock "From35" SrcPort 1 DstBlock "Timer 7" DstPort 6 } Line { SrcBlock "Timer 0" SrcPort 1 DstBlock "BitBasher" DstPort 1 } Line { SrcBlock "Timer 0" SrcPort 2 DstBlock "BitBasher" DstPort 2 } Line { SrcBlock "Timer 0" SrcPort 3 DstBlock "BitBasher" DstPort 3 } Line { SrcBlock "IDLEFORDIFS" SrcPort 1 Points [155, 0] Branch { DstBlock "Timer 0" DstPort 7 } Branch { Points [0, 135] Branch { Points [0, 135] Branch { Points [0, 140] Branch { Points [0, 30; 520, 0; 0, -40] Branch { Points [0, -140] Branch { Points [0, -135] Branch { Points [0, -135] DstBlock "Timer 4" DstPort 7 } Branch { DstBlock "Timer 5" DstPort 7 } } Branch { DstBlock "Timer 6" DstPort 7 } } Branch { DstBlock "Timer 7" DstPort 7 } } Branch { DstBlock "Timer 3" DstPort 7 } } Branch { DstBlock "Timer 2" DstPort 7 } } Branch { DstBlock "Timer 1" DstPort 7 } } } Line { SrcBlock "Timer 1" SrcPort 1 DstBlock "BitBasher1" DstPort 1 } Line { SrcBlock "Timer 1" SrcPort 2 DstBlock "BitBasher1" DstPort 2 } Line { SrcBlock "Timer 1" SrcPort 3 DstBlock "BitBasher1" DstPort 3 } Line { SrcBlock "Timer 2" SrcPort 1 DstBlock "BitBasher2" DstPort 1 } Line { SrcBlock "Timer 2" SrcPort 2 DstBlock "BitBasher2" DstPort 2 } Line { SrcBlock "Timer 2" SrcPort 3 DstBlock "BitBasher2" DstPort 3 } Line { SrcBlock "Timer 3" SrcPort 1 DstBlock "BitBasher3" DstPort 1 } Line { SrcBlock "Timer 3" SrcPort 2 DstBlock "BitBasher3" DstPort 2 } Line { SrcBlock "Timer 3" SrcPort 3 DstBlock "BitBasher3" DstPort 3 } Line { SrcBlock "Timer 4" SrcPort 1 DstBlock "BitBasher4" DstPort 1 } Line { SrcBlock "Timer 4" SrcPort 2 DstBlock "BitBasher4" DstPort 2 } Line { SrcBlock "Timer 4" SrcPort 3 DstBlock "BitBasher4" DstPort 3 } Line { SrcBlock "Timer 5" SrcPort 1 DstBlock "BitBasher5" DstPort 1 } Line { SrcBlock "Timer 5" SrcPort 2 DstBlock "BitBasher5" DstPort 2 } Line { SrcBlock "Timer 5" SrcPort 3 DstBlock "BitBasher5" DstPort 3 } Line { SrcBlock "Timer 6" SrcPort 1 DstBlock "BitBasher6" DstPort 1 } Line { SrcBlock "Timer 6" SrcPort 2 DstBlock "BitBasher6" DstPort 2 } Line { SrcBlock "Timer 6" SrcPort 3 DstBlock "BitBasher6" DstPort 3 } Line { SrcBlock "Timer 7" SrcPort 1 DstBlock "BitBasher7" DstPort 1 } Line { SrcBlock "Timer 7" SrcPort 2 DstBlock "BitBasher7" DstPort 2 } Line { SrcBlock "Timer 7" SrcPort 3 DstBlock "BitBasher7" DstPort 3 } Line { SrcBlock "BitBasher" SrcPort 1 Points [5, 0; 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