Model { Name "warplab_mimo_4x4" Version 7.1 MdlSubVersion 0 GraphicalInterface { NumRootInports 0 NumRootOutports 0 ParameterArgumentNames "" ComputedModelVersion "1.176" NumModelReferences 0 NumTestPointedSignals 0 } SavedCharacterEncoding "windows-1252" SaveDefaultBlockParams on SampleTimeColors off LibraryLinkDisplay "none" WideLines off ShowLineDimensions off ShowPortDataTypes off ShowLoopsOnError on IgnoreBidirectionalLines off ShowStorageClass off ShowTestPointIcons on ShowSignalResolutionIcons on ShowViewerIcons on SortedOrder off ExecutionContextIcon off ShowLinearizationAnnotations on ScopeRefreshTime 0.035000 OverrideScopeRefreshTime on DisableAllScopes off DataTypeOverride "UseLocalSettings" MinMaxOverflowLogging "UseLocalSettings" MinMaxOverflowArchiveMode "Overwrite" BlockNameDataTip off BlockParametersDataTip off BlockDescriptionStringDataTip off ToolBar on StatusBar on BrowserShowLibraryLinks off BrowserLookUnderMasks off Created "Wed Jan 07 15:32:06 2009" Creator "mduarte" UpdateHistory "UpdateHistoryNever" ModifiedByFormat "%" LastModifiedBy "sgupta" ModifiedDateFormat "%" LastModifiedDate "Thu Dec 10 12:20:28 2009" RTWModifiedTimeStamp 0 ModelVersionFormat "1.%" ConfigurationManager "None" SimulationMode "normal" LinearizationMsg "none" Profile off ParamWorkspaceSource "MATLABWorkspace" AccelSystemTargetFile "accel.tlc" AccelTemplateMakefile "accel_default_tmf" AccelMakeCommand "make_rtw" TryForcingSFcnDF off RecordCoverage off CovPath "/" CovSaveName "covdata" CovMetricSettings "dw" CovNameIncrementing off CovHtmlReporting on covSaveCumulativeToWorkspaceVar on CovSaveSingleToWorkspaceVar on CovCumulativeVarName "covCumulativeData" CovCumulativeReport off CovReportOnPause on CovModelRefEnable "Off" ExtModeBatchMode off ExtModeEnableFloating on ExtModeTrigType "manual" ExtModeTrigMode "normal" ExtModeTrigPort "1" ExtModeTrigElement "any" ExtModeTrigDuration 1000 ExtModeTrigDurationFloating "auto" ExtModeTrigHoldOff 0 ExtModeTrigDelay 0 ExtModeTrigDirection "rising" ExtModeTrigLevel 0 ExtModeArchiveMode "off" ExtModeAutoIncOneShot off ExtModeIncDirWhenArm off ExtModeAddSuffixToVar off ExtModeWriteAllDataToWs off ExtModeArmWhenConnect on ExtModeSkipDownloadWhenConnect off ExtModeLogAll on ExtModeAutoUpdateStatusClock on BufferReuse on ShowModelReferenceBlockVersion off ShowModelReferenceBlockIO off Array { Type "Handle" Dimension 1 Simulink.ConfigSet { $ObjectID 1 Version "1.4.0" Array { Type "Handle" Dimension 7 Simulink.SolverCC { $ObjectID 2 Version "1.4.0" StartTime "0.0" StopTime "50000" AbsTol "auto" FixedStep "auto" InitialStep "auto" MaxNumMinSteps "-1" MaxOrder 5 ZcThreshold "auto" ConsecutiveZCsStepRelTol "10*128*eps" MaxConsecutiveZCs "1000" ExtrapolationOrder 4 NumberNewtonIterations 1 MaxStep "auto" MinStep "auto" MaxConsecutiveMinStep "1" RelTol "1e-3" SolverMode "Auto" Solver "ode45" SolverName "ode45" ShapePreserveControl "DisableAll" ZeroCrossControl "UseLocalSettings" ZeroCrossAlgorithm "Non-adaptive" AlgebraicLoopSolver "TrustRegion" SolverResetMethod "Fast" PositivePriorityOrder off AutoInsertRateTranBlk off SampleTimeConstraint "Unconstrained" InsertRTBMode "Whenever possible" } Simulink.DataIOCC { $ObjectID 3 Version "1.4.0" Decimation "1" ExternalInput "[t, u]" FinalStateName "xFinal" InitialState "xInitial" LimitDataPoints on MaxDataPoints "1000" LoadExternalInput off LoadInitialState off SaveFinalState off SaveFormat "Array" SaveOutput on SaveState off SignalLogging on InspectSignalLogs off SaveTime on StateSaveName "xout" TimeSaveName "tout" OutputSaveName "yout" SignalLoggingName "logsout" OutputOption "RefineOutputTimes" OutputTimes "[]" Refine "1" } Simulink.OptimizationCC { $ObjectID 4 Array { Type "Cell" Dimension 5 Cell "ZeroExternalMemoryAtStartup" Cell "ZeroInternalMemoryAtStartup" Cell "InitFltsAndDblsToZero" Cell "OptimizeModelRefInitCode" Cell "NoFixptDivByZeroProtection" PropName "DisabledProps" } Version "1.4.0" BlockReduction on BooleanDataType on ConditionallyExecuteInputs on InlineParams off InlineInvariantSignals off OptimizeBlockIOStorage on BufferReuse on EnhancedBackFolding off EnforceIntegerDowncast on ExpressionFolding on ExpressionDepthLimit 2147483647 FoldNonRolledExpr on LocalBlockOutputs on RollThreshold 5 SystemCodeInlineAuto off StateBitsets off DataBitsets off UseTempVars off ZeroExternalMemoryAtStartup on ZeroInternalMemoryAtStartup on InitFltsAndDblsToZero on NoFixptDivByZeroProtection off EfficientFloat2IntCast off OptimizeModelRefInitCode off LifeSpan "inf" BufferReusableBoundary on SimCompilerOptimization "Off" AccelVerboseBuild off } Simulink.DebuggingCC { $ObjectID 5 Version "1.4.0" RTPrefix "error" ConsistencyChecking "none" ArrayBoundsChecking "none" SignalInfNanChecking "none" SignalRangeChecking "none" ReadBeforeWriteMsg "UseLocalSettings" WriteAfterWriteMsg "UseLocalSettings" WriteAfterReadMsg "UseLocalSettings" AlgebraicLoopMsg "warning" ArtificialAlgebraicLoopMsg "warning" SaveWithDisabledLinksMsg "warning" SaveWithParameterizedLinksMsg "none" CheckSSInitialOutputMsg on CheckExecutionContextPreStartOutputMsg off CheckExecutionContextRuntimeOutputMsg off SignalResolutionControl "UseLocalSettings" BlockPriorityViolationMsg "warning" MinStepSizeMsg "warning" TimeAdjustmentMsg "none" MaxConsecutiveZCsMsg "error" SolverPrmCheckMsg "warning" InheritedTsInSrcMsg "warning" DiscreteInheritContinuousMsg "warning" MultiTaskDSMMsg "error" MultiTaskCondExecSysMsg "error" MultiTaskRateTransMsg "error" SingleTaskRateTransMsg "none" TasksWithSamePriorityMsg "warning" SigSpecEnsureSampleTimeMsg "warning" CheckMatrixSingularityMsg "none" IntegerOverflowMsg "warning" Int32ToFloatConvMsg "warning" ParameterDowncastMsg "error" ParameterOverflowMsg "error" ParameterUnderflowMsg "none" ParameterPrecisionLossMsg "warning" ParameterTunabilityLossMsg "warning" UnderSpecifiedDataTypeMsg "none" UnnecessaryDatatypeConvMsg "none" VectorMatrixConversionMsg "none" InvalidFcnCallConnMsg "error" FcnCallInpInsideContextMsg "Use local settings" SignalLabelMismatchMsg "none" UnconnectedInputMsg "warning" UnconnectedOutputMsg "warning" UnconnectedLineMsg "warning" SFcnCompatibilityMsg "none" UniqueDataStoreMsg "none" BusObjectLabelMismatch "warning" RootOutportRequireBusObject "warning" AssertControl "UseLocalSettings" EnableOverflowDetection off ModelReferenceIOMsg "none" ModelReferenceVersionMismatchMessage "none" ModelReferenceIOMismatchMessage "none" ModelReferenceCSMismatchMessage "none" ModelReferenceSimTargetVerbose off UnknownTsInhSupMsg "warning" ModelReferenceDataLoggingMessage "warning" ModelReferenceSymbolNameMessage "warning" ModelReferenceExtraNoncontSigs "error" StateNameClashWarn "warning" StrictBusMsg "Warning" LoggingUnavailableSignals "error" BlockIODiagnostic "none" } Simulink.HardwareCC { $ObjectID 6 Version "1.4.0" ProdBitPerChar 8 ProdBitPerShort 16 ProdBitPerInt 32 ProdBitPerLong 32 ProdIntDivRoundTo "Undefined" ProdEndianess "Unspecified" ProdWordSize 32 ProdShiftRightIntArith on ProdHWDeviceType "32-bit Generic" TargetBitPerChar 8 TargetBitPerShort 16 TargetBitPerInt 32 TargetBitPerLong 32 TargetShiftRightIntArith on TargetIntDivRoundTo "Undefined" TargetEndianess "Unspecified" TargetWordSize 32 TargetTypeEmulationWarnSuppressLevel 0 TargetPreprocMaxBitsSint 32 TargetPreprocMaxBitsUint 32 TargetHWDeviceType "Specified" TargetUnknown off ProdEqTarget on } Simulink.ModelReferenceCC { $ObjectID 7 Version "1.4.0" UpdateModelReferenceTargets "IfOutOfDateOrStructuralChange" CheckModelReferenceTargetMessage "error" ModelReferenceNumInstancesAllowed "Multi" ModelReferenceSigSizeVariationType "Always allowed" ModelReferencePassRootInputsByReference on ModelReferenceMinAlgLoopOccurrences off } Simulink.RTWCC { $BackupClass "Simulink.RTWCC" $ObjectID 8 Array { Type "Cell" Dimension 1 Cell "IncludeHyperlinkInReport" PropName "DisabledProps" } Version "1.4.0" SystemTargetFile "grt.tlc" GenCodeOnly off MakeCommand "make_rtw" GenerateMakefile on TemplateMakefile "grt_default_tmf" GenerateReport off SaveLog off RTWVerbose on RetainRTWFile off ProfileTLC off TLCDebug off TLCCoverage off TLCAssert off ProcessScriptMode "Default" ConfigurationMode "Optimized" ConfigAtBuild off IncludeHyperlinkInReport off LaunchReport off TargetLang "C" IncludeBusHierarchyInRTWFileBlockHierarchyMap off IncludeERTFirstTime off GenerateTraceInfo off GenerateTraceReport off GenerateTraceReportSl off GenerateTraceReportSf off GenerateTraceReportEml off GenerateCodeInfo off RTWCompilerOptimization "Off" Array { Type "Handle" Dimension 2 Simulink.CodeAppCC { $ObjectID 9 Array { Type "Cell" Dimension 16 Cell "IgnoreCustomStorageClasses" Cell "InsertBlockDesc" Cell "SFDataObjDesc" Cell "SimulinkDataObjDesc" Cell "DefineNamingRule" Cell "SignalNamingRule" Cell "ParamNamingRule" Cell "InlinedPrmAccess" Cell "CustomSymbolStr" Cell "CustomSymbolStrGlobalVar" Cell "CustomSymbolStrType" Cell "CustomSymbolStrField" Cell "CustomSymbolStrFcn" Cell "CustomSymbolStrBlkIO" Cell "CustomSymbolStrTmpVar" Cell "CustomSymbolStrMacro" PropName "DisabledProps" } Version "1.4.0" ForceParamTrailComments off GenerateComments on IgnoreCustomStorageClasses on IncHierarchyInIds off MaxIdLength 31 PreserveName off PreserveNameWithParent off ShowEliminatedStatement off IncAutoGenComments off SimulinkDataObjDesc off SFDataObjDesc off IncDataTypeInIds off MangleLength 1 CustomSymbolStrGlobalVar "$R$N$M" CustomSymbolStrType "$N$R$M" CustomSymbolStrField "$N$M" CustomSymbolStrFcn "$R$N$M$F" CustomSymbolStrBlkIO "rtb_$N$M" CustomSymbolStrTmpVar "$N$M" CustomSymbolStrMacro "$R$N$M" DefineNamingRule "None" ParamNamingRule "None" SignalNamingRule "None" InsertBlockDesc off SimulinkBlockComments on EnableCustomComments off InlinedPrmAccess "Literals" ReqsInCode off } Simulink.GRTTargetCC { $BackupClass "Simulink.TargetCC" $ObjectID 10 Array { Type "Cell" Dimension 15 Cell "IncludeMdlTerminateFcn" Cell "CombineOutputUpdateFcns" Cell "SuppressErrorStatus" Cell "ERTCustomFileBanners" Cell "GenerateSampleERTMain" Cell "GenerateTestInterfaces" Cell "ModelStepFunctionPrototypeControlCompliant" Cell "MultiInstanceERTCode" Cell "PurelyIntegerCode" Cell "SupportNonFinite" Cell "SupportComplex" Cell "SupportAbsoluteTime" Cell "SupportContinuousTime" Cell "SupportNonInlinedSFcns" Cell "PortableWordSizes" PropName "DisabledProps" } Version "1.4.0" TargetFcnLib "ansi_tfl_tmw.mat" TargetLibSuffix "" TargetPreCompLibLocation "" TargetFunctionLibrary "ANSI_C" UtilityFuncGeneration "Auto" GenerateFullHeader on GenerateSampleERTMain off GenerateTestInterfaces off IsPILTarget off ModelReferenceCompliant on CompOptLevelCompliant on IncludeMdlTerminateFcn on CombineOutputUpdateFcns off SuppressErrorStatus off ERTFirstTimeCompliant off IncludeFileDelimiter "Auto" ERTCustomFileBanners off SupportAbsoluteTime on LogVarNameModifier "rt_" MatFileLogging on MultiInstanceERTCode off SupportNonFinite on SupportComplex on PurelyIntegerCode off SupportContinuousTime on SupportNonInlinedSFcns on EnableShiftOperators on ParenthesesLevel "Nominal" PortableWordSizes off ModelStepFunctionPrototypeControlCompliant off AutosarCompliant off ExtMode off ExtModeStaticAlloc off ExtModeTesting off ExtModeStaticAllocSize 1000000 ExtModeTransport 0 ExtModeMexFile "ext_comm" ExtModeIntrfLevel "Level1" RTWCAPISignals off RTWCAPIParams off RTWCAPIStates off GenerateASAP2 off } PropName "Components" } } PropName "Components" } Name "Configuration" CurrentDlgPage "Solver" } PropName "ConfigurationSets" } Simulink.ConfigSet { $PropName "ActiveConfigurationSet" $ObjectID 1 } BlockDefaults { Orientation "right" ForegroundColor "black" BackgroundColor "white" DropShadow off NamePlacement "normal" FontName "Arial" FontSize 10 FontWeight "normal" FontAngle "normal" ShowName on } BlockParameterDefaults { Block { BlockType From IconDisplay "Tag" TagVisibility "local" } Block { BlockType Goto IconDisplay "Tag" } Block { BlockType Inport Port "1" UseBusObject off BusObject "BusObject" BusOutputAsStruct off PortDimensions "-1" SampleTime "-1" OutMin "[]" OutMax "[]" DataType "auto" OutDataType "fixdt(1,16,0)" OutScaling "[]" OutDataTypeStr "Inherit: auto" SignalType "auto" SamplingMode "auto" LatchByDelayingOutsideSignal off LatchByCopyingInsideSignal off Interpolate on } Block { BlockType Outport Port "1" UseBusObject off BusObject "BusObject" BusOutputAsStruct off PortDimensions "-1" SampleTime "-1" OutMin "[]" OutMax "[]" DataType "auto" OutDataType "fixdt(1,16,0)" OutScaling "[]" OutDataTypeStr "Inherit: auto" SignalType "auto" SamplingMode "auto" OutputWhenDisabled "held" InitialOutput "[]" } Block { BlockType Scope ModelBased off TickLabels "OneTimeTick" ZoomMode "on" Grid "on" TimeRange "auto" YMin "-5" YMax "5" SaveToWorkspace off SaveName "ScopeData" LimitDataPoints on MaxDataPoints "5000" Decimation "1" SampleInput off SampleTime "-1" } Block { BlockType "S-Function" FunctionName "system" SFunctionModules "''" PortCounts "[]" SFunctionDeploymentMode off } Block { BlockType SubSystem ShowPortLabels "FromPortIcon" Permissions "ReadWrite" PermitHierarchicalResolution "All" TreatAsAtomicUnit off CheckFcnCallInpInsideContextMsg off SystemSampleTime "-1" RTWFcnNameOpts "Auto" RTWFileNameOpts "Auto" RTWMemSecFuncInitTerm "Inherit from model" RTWMemSecFuncExecute "Inherit from model" RTWMemSecDataConstants "Inherit from model" RTWMemSecDataInternal "Inherit from model" RTWMemSecDataParameters "Inherit from model" SimViewingDevice off DataTypeOverride "UseLocalSettings" MinMaxOverflowLogging "UseLocalSettings" } Block { BlockType Terminator } Block { BlockType Constant Value "1" VectorParams1D on SamplingMode "Sample based" OutMin "[]" OutMax "[]" OutDataTypeMode "Inherit from 'Constant value'" OutDataType "fixdt(1,16,0)" ConRadixGroup "Use specified scaling" OutScaling "[]" OutDataTypeStr "Inherit: Inherit from 'Constant value'" SampleTime "inf" FramePeriod "inf" } Block { BlockType DiscretePulseGenerator PulseType "Sample based" TimeSource "Use simulation time" Amplitude "1" Period "2" PulseWidth "1" PhaseDelay "0" SampleTime "1" VectorParams1D on } } AnnotationDefaults { HorizontalAlignment "center" VerticalAlignment "middle" ForegroundColor "black" BackgroundColor "white" DropShadow off FontName "Arial" FontSize 10 FontWeight "normal" FontAngle "normal" UseDisplayTextAsClickCallback off } LineDefaults { FontName "Arial" FontSize 9 FontWeight "normal" FontAngle "normal" } System { Name "warplab_mimo_4x4" Location [2, 70, 1894, 1150] Open on ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" ReportName "simulink-default.rpt" Block { BlockType Reference Name " " Ports [3, 1] Position [270, 627, 310, 693] SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "3" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,261" block_type "logical" block_version "9.1.01" sg_icon_stat "40,66,1,1,white,blue,0,bd50cad4,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 ],[0 0 66 66 ],[0.77 0.82 0.91]);\npatch([10 3 12 3 10 21 24 27 38 29 20 14 24 14 20 29 38 27 24 21 10 ],[17 24 33 42 49 49 46 49 49 40 49 43 33 23 17 26 17 17 20 17 17 ],[0.98 0.96 0.92]);\nplot([0 40 40 0 0 ],[0 0 66 66 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newlineor\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name " 1" Ports [2, 1] Position [270, 732, 310, 788] SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "9.1.01" sg_icon_stat "40,56,1,1,white,blue,0,f4a65842,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[8 17 30 43 52 52 48 52 52 40 52 43 30 17 8 20 8 8 12 8 8 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newlineor\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name " System Generator" Tag "genX" Ports [] Position [34, 24, 85, 74] ShowName off AttributesFormatString "System\\nGenerator" UserDataPersistent on UserData "DataTag0" SourceBlock "xbsIndex_r4/ System Generator" SourceType "Xilinx System Generator Block" ShowPortLabels "FromPortIcon" SystemSampleTime "-1" FunctionWithSeparateData off RTWMemSecFuncInitTerm "Inherit from model" RTWMemSecFuncExecute "Inherit from model" RTWMemSecDataConstants "Inherit from model" RTWMemSecDataInternal "Inherit from model" RTWMemSecDataParameters "Inherit from model" infoedit " System Generator" xilinxfamily "virtex2p" part "xc2vp70" speed "-6" package "ff1517" synthesis_tool "XST" clock_wrapper "Clock Enables" directory "C:/localhome/sgupta/tmp/netlist_4x4_v1" testbench off simulink_period "1" sysclk_period "10" dcm_input_clock_period "100" incr_netlist off trim_vbits "Everywhere in SubSystem" dbl_ovrd "According to Block Masks" core_generation "According to Block Masks" run_coregen off deprecated_control off eval_field "0" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "sysgen" block_version "10.1.3" sg_icon_stat "51,50,-1,-1,red,beige,0,07734,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 51 51 0 ],[0 0 50 50 ],[0.93 0.92 0.86]);\npatch([12 4 16 4 12 25 29 33 47 36 25 17 29 17 25 36 47 33 29 25 12 ],[5 13 25 37 45 45 41 45 45 34 45 37 25 13 5 16 5 5 9 5 5 ],[0.6 0.2 0.25]);\nplot([0 51 51 0 0 ],[0 0 50 50 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "AGC_Done" Ports [1, 1] Position [130, 1014, 185, 1026] NamePlacement "alternate" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, double and fixed point to Xilinx fixed point type.

Hardware notes: In hardware these blocks become top level input ports." arith_type "Unsigned" n_bits "1" bin_pt "0" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,356,432" block_type "gatewayin" block_version "VER_STRING_GOES_HERE" sg_icon_stat "55,12,1,1,white,yellow,0,bc55d28f,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([27 24 29 24 27 32 33 34 40 36 32 29 34 29 32 36 40 34 33 32 27 ],[2 5 10 15 18 18 17 18 18 14 18 15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Convert2" Ports [1, 1] Position [420, 1011, 455, 1029] ShowName off SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." arith_type "Boolean" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,461,375" block_type "convert" block_version "8.2" sg_icon_stat "35,18,1,1,white,blue,0,74901e60,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([15 10 17 10 15 23 25 27 35 28 22 17 23 17 22 28 35 27 25 23 15 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'cast');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType SubSystem Name "EDK Processor" Ports [] Position [146, 23, 208, 87] CopyFcn "xlProcBlockCopyCallback(gcbh);xlBlockMoveCallback(gcbh);" DeleteFcn "xlDestroyGui(gcbh);" LoadFcn "xlBlockLoadCallback(gcbh);" ModelCloseFcn "xlDestroyGui(gcbh);" PreSaveFcn "xlBlockPreSaveCallback(gcbh);" PostSaveFcn "xlBlockPostSaveCallback(gcbh);" DestroyFcn "xlDestroyGui(gcbh);" OpenFcn "bh=gcbh;xlProcBlockCallbacks('populatesharedmemorylistbox',bh);xlOpenGui(bh, 'edkprocessor_gui.xml', @xlProcBlockEnablement, @xlProcBlockAction)" CloseFcn "xlDestroyGui(gcbh);" MoveFcn "xlBlockMoveCallback(gcbh);" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskType "Xilinx EDK Processor Block" MaskDescription "Xilinx EDK Processor" MaskHelp "eval('');xlDoc('-book','sysgen','-topic','EDK_Processor');" MaskPromptString "Configure Processor for|EDK Project| |Available Memories| | |Bus Type|Base Address| |Lock| |Dual Clocks| |Register Read-Back|Constraint file| |Inherit Device Type| | | | | | | | | | | | | | | | " MaskStyleString "popup(EDK pcore generation|HDL netlisting),edit,edit,popup(),edit,edit,popup(PLB|FSL),edit,edit,checkbox,edit,checkbox,edit,checkbox,edit,edit,checkbox,edit,edit,edit,edit,edit,edit,edit,edit,edit,edit,edit,edit,edit,edit,edit,edit" MaskTunableValueString "on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on" MaskCallbackString "||||||||||||||||||||||||||||||||" MaskEnableString "on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on" MaskVisibilityString "on,on,off,on,on,off,on,on,off,on,off,on,off,on,on,off,on,off,off,off,off,off,off,off,off,off,off,off,off,off,off,off,off" MaskToolTipString "on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on" MaskVarAliasString ",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,," MaskVariables "mode=&1;xmp=&2;MemVisToProc=&3;AvailableMemories=&4;portInterfaceTable=&5;bus_type_sgadvanced=&6;bus_type=@7;baseaddr=&8;baseaddr_lock_sgadvanced=&9;baseaddr_lock=@10;dual_clock_sgadvanced=&11;dual_clock=@12;reg_readback_sgadvanced=&13;reg_readback=@14;ucf_file=&15;inheritDeviceType_sgadvanced=&16;inheritDeviceType=@17;clock_name=&18;internalPortList=&19;resetPolarity=&20;memxtable=&21;procinfo=&22;memmapdirty=&23;blockname=&24;xpsintstyle=&25;has_advanced_control=@26;sggui_pos=&27;block_type=&28;block_version=&29;sg_icon_stat=&30;sg_mask_display=&31;sg_list_contents=&32;sg_blockgui_xml=&33;" MaskInitialization "try\n tmp_gcb = gcb;\n tmp_gcbh = gcbh;\n if (strcmp('SysGenIndex',get_param(bdroot(tmp_gcbh),'tag')) && ~isempty(regexp(bdroot(tmp_gcb), '^xbs', 'once')))\n return;\n end;\n xlMungeMaskParams;\n\nblock_type='edkprocessor';\n serialized_declarations = '{,''block_type''=>''String''}';\n xledkprocessor_init();\n ptable_ = xlblockprep(get_param(tmp_gcb, 'MaskWSVariables'));\ncatch\n global dbgsysgen;\n if(~isempty(dbgsysgen) && dbgsysgen)\n e = regexprep(lasterr, '\\n', '\\nError: ');\n disp(['Error: While running MaskInit code on block ' tmp_gcb ': ' e]);\n error(e);\n end\nend\n" MaskDisplay "fprintf('','COMMENT: begin icon graphics');\npatch([0 62 62 0 ],[0 0 64 64 ],[0.77 0.82 0.91]);\npatch([14 4 19 4 14 30 34 38 56 42 29 19 33 19 29 42 56 38 34 30 14 ],[8 18 33 48 58 58 54 58 58 44 57 47 33 19 9 22 8 8 12 8 8 ],[0.98 0.96 0.92]);\nplot([0 62 62 0 0 ],[0 0 64 64 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ndisp('');\n\nfprintf('','COMMENT: end icon text');\n" MaskSelfModifiable on MaskIconFrame off MaskIconOpaque on MaskIconRotate "none" MaskIconUnits "autoscale" MaskValueString "EDK pcore generation||

<<AGCDoneAddr>>
<<CaptureDone>>
<<DCO_EN_SEL>>
<<DebugRx1Buffers>>
<<DebugRx2Buffers>>
<<DebugRx3Buffers>>
<<DebugRx4Buffers>>
<<MGC_AGC_SEL>>
<<RADIO1RXBUFF_RXEN>>
<<RADIO1TXBUFF_TXEN>>
<<RADIO2RXBUFF_RXEN>>
<<RADIO2TXBUFF_TXEN>>
<<RADIO3RXBUFF_RXEN>>
<<RADIO3TXBUFF_TXEN>>
<<RADIO4RXBUFF_RXEN>>
<<RADIO4TXBUFF_TXEN>>
<<Radio1AGCDoneRSSI>>
<<Radio2AGCDoneRSSI>>
<<Radio3AGCDoneRSSI>>
<<Radio4AGCDoneRSSI>>
<<StartCapture>>
<<StartTx>>
<<StopTx>>
<<TransMode>>
<<TxDelay>>
<<TxLength>>
<<StartTxRx>>
<<RxBuff_Radio1>>
<<RxBuff_Radio2>>
<<RxBuff_Radio3>>
<<RxBuff_Radio4>>
<<TxBuff_Radio1>>
<<TxBuff_Radio2>>
<<TxBuff_Radio3>>
<<TxBuff_Radio4>>
<<RSSIBuff_Radio1>>
<<RSSIBuff_Radio2>>
<<RSSIBuff_Radio3>>
<<RSSIBuff_Radio4>>
||{'exposed'=>[],'portdir'=>[],'portname'=>[],'shortname'=>[]}||PLB|0x80000000||off||on||on|||off|plb|{}|0|{'mlist'=>['warplab_mimo_4x4/Memmory-mapped Registers/AGCDoneAddr','warplab_mimo_4x4/Memmory-mapped Registers/To Register','warplab_mimo_4x4/Memmory-mapped Registers/From Register14','warplab_mimo_4x4/Memmory-mapped Registers/DebugRx1Buffers','warplab_mimo_4x4/Memmory-mapped Registers/DebugRx2Buffers','warplab_mimo_4x4/Memmory-mapped Registers/DebugRx3Buffers','warplab_mimo_4x4/Memmory-mapped Registers/DebugRx4Buffers','warplab_mimo_4x4/Memmory-mapped Registers/From Register13','warplab_mimo_4x4/Memmory-mapped Registers/From Register1','warplab_mimo_4x4/Memmory-mapped Registers/From Register6','warplab_mimo_4x4/Memmory-mapped Registers/From Register5','warplab_mimo_4x4/Memmory-mapped Registers/From Register9','warplab_mimo_4x4/Memmory-mapped Registers/From Register11','warplab_mimo_4x4/Memmory-mapped Registers/From Register10','warplab_mimo_4x4/Memmory-mapped Registers/From Register3','warplab_mimo_4x4/Memmory-mapped Registers/From Register12','warplab_mimo_4x4/Memmory-mapped Registers/Radio1AGCDoneRSSI','warplab_mimo_4x4/Memmory-mapped Registers/Radio2AGCDoneRSSI','warplab_mimo_4x4/Memmory-mapped Registers/Radio3AGCDoneRSSI','warplab_mimo_4x4/Memmory-mapped Registers/Radio4AGCDoneRSSI','warplab_mimo_4x4/Memmory-mapped Registers/From Register2','warplab_mimo_4x4/Memmory-mapped Registers/From Register4','warplab_mimo_4x4/Memmory-mapped Registers/From Register7','warplab_mimo_4x4/Memmory-mapped Registers/From Register8','warplab_mimo_4x4/Memmory-mapped Registers/TxDelay','warplab_mimo_4x4/Tx Control/From Register4','warplab_mimo_4x4/Memmory-mapped Registers/From Register15','warplab_mimo_4x4/Radio 1\nRx Buffers/Radio 1 I//Q\nBuffer/Shared Memory','warplab_mimo_4x4/Radio 2\nRx Buffers/Radio 2 I//Q\nBuffer/Shared Memory','warplab_mimo_4x4/Radio 3\nRx Buffers/Radio 3 I//Q\nBuffer/Shared Memory','warplab_mimo_4x4/Radio 4\nRx Buffers/Radio 4 I//Q\nBuffer/Shared Memory','warplab_mimo_4x4/Radio 1\nTx Buffer/Shared Memory','warplab_mimo_4x4/Radio 2\nTx Buffer/Shared Memory','warplab_mimo_4x4/Radio 3\nTx Buffer/Shared Memory','warplab_mimo_4x4/Radio 4\nTx Buffer/Shared Memory','warplab_mimo_4x4/Radio 1\nRx Buffers/Radio 1\nRSSI Buffer/Shared Memory','warplab_mimo_4x4/Radio 2\nRx Buffers/Radio 2\nRSSI Buffer/Shared Memory','warplab_mimo_4x4/Radio 3\nRx Buffers/Radio 3\nRSSI Buffer/Shared Memory','warplab_mimo_4x4/Radio 4\nRx Buffers/Radio 4\nRSSI Buffer/Shared Memory'],'mlname'=>['\\'AGCDoneAddr\\'','\\'CaptureDone\\'','\\'DCO_EN_SEL\\'','\\'DebugRx1Buffers\\'','\\'DebugRx2Buffers\\'','\\'DebugRx3Buffers\\'','\\'DebugRx4Buffers\\'','\\'MGC_AGC_SEL\\'','\\'RADIO1RXBUFF_RXEN\\'','\\'RADIO1TXBUFF_TXEN\\'','\\'RADIO2RXBUFF_RXEN\\'','\\'RADIO2TXBUFF_TXEN\\'','\\'RADIO3RXBUFF_RXEN\\'','\\'RADIO3TXBUFF_TXEN\\'','\\'RADIO4RXBUFF_RXEN\\'','\\'RADIO4TXBUFF_TXEN\\'','\\'Radio1AGCDoneRSSI\\'','\\'Radio2AGCDoneRSSI\\'','\\'Radio3AGCDoneRSSI\\'','\\'Radio4AGCDoneRSSI\\'','\\'StartCapture\\'','\\'StartTx\\'','\\'StopTx\\'','\\'TransMode\\'','\\'TxDelay\\'','\\'TxLength\\'','\\'StartTxRx\\'','\\'RxBuff_Radio1\\'','\\'RxBuff_Radio2\\'','\\'RxBuff_Radio3\\'','\\'RxBuff_Radio4\\'','\\'TxBuff_Radio1\\'','\\'TxBuff_Radio2\\'','\\'TxBuff_Radio3\\'','\\'TxBuff_Radio4\\'','\\'RSSIBuff_Radio1\\'','\\'RSSIBuff_Radio2\\'','\\'RSSIBuff_Radio3\\'','\\'RSSIBuff_Radio4\\''],'mlstate'=>[0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000]}|{'xmliface'=>'Xilinx//microblaze//iface.xml'}|off||default|0|55,59,383,441|edkprocessor|2.5|62,64,-1,-1,white,blue,0,07734,right|fprintf('','COMMENT: begin icon graphics');\npatch([0 62 62 0 ],[0 0 64 64 ],[0.77 0.82 0.91]);\npatch([14 4 19 4 14 30 34 38 56 42 29 19 33 19 29 42 56 38 34 30 14 ],[8 18 33 48 58 58 54 58 58 44 57 47 33 19 9 22 8 8 12 8 8 ],[0.98 0.96 0.92]);\nplot([0 62 62 0 0 ],[0 0 64 64 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\nfprintf('','COMMENT: end icon text');\n|{'table'=>{'AvailableMemories'=>'popup()','userSelections'=>{'AvailableMemories'=>''}}}|" MaskTabNameString ",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,," System { Name "EDK Processor" Location [514, 91, 900, 269] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Constant Name "Constant" Position [40, 565, 60, 585] } Block { BlockType Constant Name "Constant1" Position [40, 625, 60, 645] } Block { BlockType Constant Name "Constant2" Position [40, 680, 60, 700] } Block { BlockType Constant Name "Constant3" Position [40, 740, 60, 760] } Block { BlockType Constant Name "Constant4" Position [40, 800, 60, 820] } Block { BlockType Reference Name "Constant5" Ports [0, 1] Position [20, 492, 75, 518] ShowName off SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" arith_type "Unsigned" const "0" n_bits "1" bin_pt "0" explicit_period on period "xlGetSimulinkPeriod(gcb)" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "10.1.3" sg_icon_stat "55,26,1,1,white,blue,0,72d575a1,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 26 26 ],[0.77 0.82 0.91]);\npatch([20 16 22 16 20 27 29 31 38 32 26 22 28 22 26 32 38 31 29 27 20 ],[3 7 13 19 23 23 21 23 23 17 23 19 13 7 3 9 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 26 26 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'0');\nfprintf('','COMMENT: end icon text');\n" Port { PortNumber 1 Name "Sl_wait" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Constant Name "Constant6" Position [40, 915, 60, 935] } Block { BlockType Reference Name "From Register" Ports [0, 1] Position [260, 1467, 320, 1523] AttributesFormatString "<< % >>" SourceBlock "xbsIndex_r4/From Register" SourceType "Xilinx Shared Memory Based From Register Block" infoedit "Register block that reads data to a shared memory register. Delay of one sample period." shared_memory_name "'AGCDoneAddr'" init "0" period "xlGetSimulinkPeriod(gcb)" ownership "Owned and initialized elsewhere" arith_type "Unsigned" n_bits "14" bin_pt "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "fromreg" block_version "10.1.3" sg_icon_stat "60,56,1,1,white,blue,0,4b212927,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n" Port { PortNumber 1 Name "AGCDoneAddr_dout" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "From Register1" Ports [0, 1] Position [260, 1552, 320, 1608] AttributesFormatString "<< % >>" SourceBlock "xbsIndex_r4/From Register" SourceType "Xilinx Shared Memory Based From Register Block" infoedit "Register block that reads data to a shared memory register. Delay of one sample period." shared_memory_name "'CaptureDone'" init "0" period "xlGetSimulinkPeriod(gcb)" ownership "Owned and initialized elsewhere" arith_type "Unsigned" n_bits "1" bin_pt "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "fromreg" block_version "10.1.3" sg_icon_stat "60,56,1,1,white,blue,0,4b212927,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n" Port { PortNumber 1 Name "CaptureDone_dout" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "From Register2" Ports [0, 1] Position [260, 1637, 320, 1693] AttributesFormatString "<< % >>" SourceBlock "xbsIndex_r4/From Register" SourceType "Xilinx Shared Memory Based From Register Block" infoedit "Register block that reads data to a shared memory register. Delay of one sample period." shared_memory_name "'Radio1AGCDoneRSSI'" init "0" period "xlGetSimulinkPeriod(gcb)" ownership "Owned and initialized elsewhere" arith_type "Unsigned" n_bits "10" bin_pt "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "fromreg" block_version "10.1.3" sg_icon_stat "60,56,1,1,white,blue,0,4b212927,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n" Port { PortNumber 1 Name "Radio1AGCDoneRSSI_dout" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "From Register3" Ports [0, 1] Position [260, 1727, 320, 1783] AttributesFormatString "<< % >>" SourceBlock "xbsIndex_r4/From Register" SourceType "Xilinx Shared Memory Based From Register Block" infoedit "Register block that reads data to a shared memory register. Delay of one sample period." shared_memory_name "'Radio2AGCDoneRSSI'" init "0" period "xlGetSimulinkPeriod(gcb)" ownership "Owned and initialized elsewhere" arith_type "Unsigned" n_bits "10" bin_pt "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "fromreg" block_version "10.1.3" sg_icon_stat "60,56,1,1,white,blue,0,4b212927,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n" Port { PortNumber 1 Name "Radio2AGCDoneRSSI_dout" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "From Register4" Ports [0, 1] Position [260, 1812, 320, 1868] AttributesFormatString "<< % >>" SourceBlock "xbsIndex_r4/From Register" SourceType "Xilinx Shared Memory Based From Register Block" infoedit "Register block that reads data to a shared memory register. Delay of one sample period." shared_memory_name "'Radio3AGCDoneRSSI'" init "0" period "xlGetSimulinkPeriod(gcb)" ownership "Owned and initialized elsewhere" arith_type "Unsigned" n_bits "10" bin_pt "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "fromreg" block_version "10.1.3" sg_icon_stat "60,56,1,1,white,blue,0,4b212927,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n" Port { PortNumber 1 Name "Radio3AGCDoneRSSI_dout" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "From Register5" Ports [0, 1] Position [260, 1897, 320, 1953] AttributesFormatString "<< % >>" SourceBlock "xbsIndex_r4/From Register" SourceType "Xilinx Shared Memory Based From Register Block" infoedit "Register block that reads data to a shared memory register. Delay of one sample period." shared_memory_name "'Radio4AGCDoneRSSI'" init "0" period "xlGetSimulinkPeriod(gcb)" ownership "Owned and initialized elsewhere" arith_type "Unsigned" n_bits "10" bin_pt "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "fromreg" block_version "10.1.3" sg_icon_stat "60,56,1,1,white,blue,0,4b212927,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n" Port { PortNumber 1 Name "Radio4AGCDoneRSSI_dout" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "PLB_ABus" Ports [1, 1] Position [110, 625, 175, 645] SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, double and fixed point to Xilinx fixed point type.

Hardware notes: In hardware these blocks become top level input ports." arith_type "Unsigned" n_bits "32" bin_pt "0" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "xlGetSimulinkPeriod(gcb)" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" sginterface "{'Xilinx'=>{'jtaghwcosim'=>{'non_memory_mapped_port'=>'PLB_ABus'}},'iopad'=>{'constraint'=>'#'}}" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" block_version "10.1.3" sg_icon_stat "65,20,1,1,white,yellow,0,bc55d28f,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([27 24 29 24 27 32 33 34 40 36 32 29 34 29 32 36 40 34 33 32 27 ],[2 5 10 15 18 18 17 18 18 14 18 15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end icon text');\n" Port { PortNumber 1 Name "PLB_ABus" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "PLB_PAValid" Ports [1, 1] Position [110, 680, 175, 700] SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, double and fixed point to Xilinx fixed point type.

Hardware notes: In hardware these blocks become top level input ports." arith_type "Unsigned" n_bits "1" bin_pt "0" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "xlGetSimulinkPeriod(gcb)" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" sginterface "{'Xilinx'=>{'jtaghwcosim'=>{'non_memory_mapped_port'=>'PLB_PAValid'}},'iopad'=>{'constraint'=>'#'}}" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" block_version "10.1.3" sg_icon_stat "65,20,1,1,white,yellow,0,bc55d28f,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([27 24 29 24 27 32 33 34 40 36 32 29 34 29 32 36 40 34 33 32 27 ],[2 5 10 15 18 18 17 18 18 14 18 15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end icon text');\n" Port { PortNumber 1 Name "PLB_PAValid" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "PLB_RNW" Ports [1, 1] Position [110, 740, 175, 760] SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, double and fixed point to Xilinx fixed point type.

Hardware notes: In hardware these blocks become top level input ports." arith_type "Unsigned" n_bits "1" bin_pt "0" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "xlGetSimulinkPeriod(gcb)" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" sginterface "{'Xilinx'=>{'jtaghwcosim'=>{'non_memory_mapped_port'=>'PLB_RNW'}},'iopad'=>{'constraint'=>'#'}}" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" block_version "10.1.3" sg_icon_stat "65,20,1,1,white,yellow,0,bc55d28f,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([27 24 29 24 27 32 33 34 40 36 32 29 34 29 32 36 40 34 33 32 27 ],[2 5 10 15 18 18 17 18 18 14 18 15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end icon text');\n" Port { PortNumber 1 Name "PLB_RNW" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "PLB_wrDBus" Ports [1, 1] Position [110, 800, 175, 820] SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, double and fixed point to Xilinx fixed point type.

Hardware notes: In hardware these blocks become top level input ports." arith_type "Unsigned" n_bits "32" bin_pt "0" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "xlGetSimulinkPeriod(gcb)" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" sginterface "{'Xilinx'=>{'jtaghwcosim'=>{'non_memory_mapped_port'=>'PLB_wrDBus'}},'iopad'=>{'constraint'=>'#'}}" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" block_version "10.1.3" sg_icon_stat "65,20,1,1,white,yellow,0,bc55d28f,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([27 24 29 24 27 32 33 34 40 36 32 29 34 29 32 36 40 34 33 32 27 ],[2 5 10 15 18 18 17 18 18 14 18 15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end icon text');\n" Port { PortNumber 1 Name "PLB_wrDBus" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "SPLB_Rst" Ports [1, 1] Position [110, 565, 175, 585] SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, double and fixed point to Xilinx fixed point type.

Hardware notes: In hardware these blocks become top level input ports." arith_type "Unsigned" n_bits "1" bin_pt "0" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "xlGetSimulinkPeriod(gcb)" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" sginterface "{'Xilinx'=>{'jtaghwcosim'=>{'non_memory_mapped_port'=>'SPLB_Rst'}},'iopad'=>{'constraint'=>'#'}}" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" block_version "10.1.3" sg_icon_stat "65,20,1,1,white,yellow,0,bc55d28f,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([27 24 29 24 27 32 33 34 40 36 32 29 34 29 32 36 40 34 33 32 27 ],[2 5 10 15 18 18 17 18 18 14 18 15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end icon text');\n" Port { PortNumber 1 Name "SPLB_Rst" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Shared Memory" Ports [3, 1] Position [605, 2145, 685, 2235] AttributesFormatString "<< % >>" SourceBlock "xbsIndex_r4/Shared Memory" SourceType "Xilinx Shared Memory Random Access Memory Block" shared_memory_name "'RxBuff_Radio1'" depth "16384" ownership "Owned and Initialized Elsewhere" initVector "sin(pi*(0:15)/16)" mutex "Unprotected" mode "Read and Write" write_mode "Read After Write" time_out "0" latency "1" explicit_data_type off arith_type "Unsigned" n_bits "32" bin_pt "0" xl_use_area off xl_area "[0,0,0,0,0,0,0]" implementation "Block RAM" use_rpm "off" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "shmem" block_version "10.1.3" sg_icon_stat "80,90,1,1,white,blue,0,e2c38f9a,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 80 80 0 ],[0 0 90 90 ],[0.77 0.82 0.91]);\npatch([18 5 24 5 18 39 45 51 74 56 39 27 46 27 39 56 74 51 45 39 18 ],[14 27 46 65 78 78 72 78 78 60 77 65 46 27 15 32 14 14 20 14 14 ],[0.98 0.96 0.92]);\nplot([0 80 80 0 0 ],[0 0 90 90 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'addr');\ncolor('black');port_label('input',2,'din');\ncolor('black');port_label('input',3,'we');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n" Port { PortNumber 1 Name "RxBuff_Radio1_dout" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Shared Memory1" Ports [3, 1] Position [605, 2269, 685, 2361] AttributesFormatString "<< % >>" SourceBlock "xbsIndex_r4/Shared Memory" SourceType "Xilinx Shared Memory Random Access Memory Block" shared_memory_name "'RxBuff_Radio2'" depth "16384" ownership "Owned and Initialized Elsewhere" initVector "sin(pi*(0:15)/16)" mutex "Unprotected" mode "Read and Write" write_mode "Read After Write" time_out "0" latency "1" explicit_data_type off arith_type "Unsigned" n_bits "32" bin_pt "0" xl_use_area off xl_area "[0,0,0,0,0,0,0]" implementation "Block RAM" use_rpm "off" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "shmem" block_version "10.1.3" sg_icon_stat "80,92,1,1,white,blue,0,e2c38f9a,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 80 80 0 ],[0 0 92 92 ],[0.77 0.82 0.91]);\npatch([18 5 24 5 18 39 45 51 74 56 39 27 46 27 39 56 74 51 45 39 18 ],[15 28 47 66 79 79 73 79 79 61 78 66 47 28 16 33 15 15 21 15 15 ],[0.98 0.96 0.92]);\nplot([0 80 80 0 0 ],[0 0 92 92 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'addr');\ncolor('black');port_label('input',2,'din');\ncolor('black');port_label('input',3,'we');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n" Port { PortNumber 1 Name "RxBuff_Radio2_dout" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Shared Memory10" Ports [3, 1] Position [605, 3359, 685, 3451] AttributesFormatString "<< % >>" SourceBlock "xbsIndex_r4/Shared Memory" SourceType "Xilinx Shared Memory Random Access Memory Block" shared_memory_name "'RSSIBuff_Radio3'" depth "2048" ownership "Owned and Initialized Elsewhere" initVector "sin(pi*(0:15)/16)" mutex "Unprotected" mode "Read and Write" write_mode "Read After Write" time_out "0" latency "1" explicit_data_type off arith_type "Unsigned" n_bits "32" bin_pt "0" xl_use_area off xl_area "[0,0,0,0,0,0,0]" implementation "Block RAM" use_rpm "off" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "shmem" block_version "10.1.3" sg_icon_stat "80,92,1,1,white,blue,0,e2c38f9a,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 80 80 0 ],[0 0 92 92 ],[0.77 0.82 0.91]);\npatch([18 5 24 5 18 39 45 51 74 56 39 27 46 27 39 56 74 51 45 39 18 ],[15 28 47 66 79 79 73 79 79 61 78 66 47 28 16 33 15 15 21 15 15 ],[0.98 0.96 0.92]);\nplot([0 80 80 0 0 ],[0 0 92 92 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'addr');\ncolor('black');port_label('input',2,'din');\ncolor('black');port_label('input',3,'we');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n" Port { PortNumber 1 Name "RSSIBuff_Radio3_dout" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Shared Memory11" Ports [3, 1] Position [605, 3479, 685, 3571] AttributesFormatString "<< % >>" SourceBlock "xbsIndex_r4/Shared Memory" SourceType "Xilinx Shared Memory Random Access Memory Block" shared_memory_name "'RSSIBuff_Radio4'" depth "2048" ownership "Owned and Initialized Elsewhere" initVector "sin(pi*(0:15)/16)" mutex "Unprotected" mode "Read and Write" write_mode "Read After Write" time_out "0" latency "1" explicit_data_type off arith_type "Unsigned" n_bits "32" bin_pt "0" xl_use_area off xl_area "[0,0,0,0,0,0,0]" implementation "Block RAM" use_rpm "off" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "shmem" block_version "10.1.3" sg_icon_stat "80,92,1,1,white,blue,0,e2c38f9a,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 80 80 0 ],[0 0 92 92 ],[0.77 0.82 0.91]);\npatch([18 5 24 5 18 39 45 51 74 56 39 27 46 27 39 56 74 51 45 39 18 ],[15 28 47 66 79 79 73 79 79 61 78 66 47 28 16 33 15 15 21 15 15 ],[0.98 0.96 0.92]);\nplot([0 80 80 0 0 ],[0 0 92 92 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'addr');\ncolor('black');port_label('input',2,'din');\ncolor('black');port_label('input',3,'we');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n" Port { PortNumber 1 Name "RSSIBuff_Radio4_dout" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Shared Memory2" Ports [3, 1] Position [605, 2389, 685, 2481] AttributesFormatString "<< % >>" SourceBlock "xbsIndex_r4/Shared Memory" SourceType "Xilinx Shared Memory Random Access Memory Block" shared_memory_name "'RxBuff_Radio3'" depth "16384" ownership "Owned and Initialized Elsewhere" initVector "sin(pi*(0:15)/16)" mutex "Unprotected" mode "Read and Write" write_mode "Read After Write" time_out "0" latency "1" explicit_data_type off arith_type "Unsigned" n_bits "32" bin_pt "0" xl_use_area off xl_area "[0,0,0,0,0,0,0]" implementation "Block RAM" use_rpm "off" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "shmem" block_version "10.1.3" sg_icon_stat "80,92,1,1,white,blue,0,e2c38f9a,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 80 80 0 ],[0 0 92 92 ],[0.77 0.82 0.91]);\npatch([18 5 24 5 18 39 45 51 74 56 39 27 46 27 39 56 74 51 45 39 18 ],[15 28 47 66 79 79 73 79 79 61 78 66 47 28 16 33 15 15 21 15 15 ],[0.98 0.96 0.92]);\nplot([0 80 80 0 0 ],[0 0 92 92 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'addr');\ncolor('black');port_label('input',2,'din');\ncolor('black');port_label('input',3,'we');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n" Port { PortNumber 1 Name "RxBuff_Radio3_dout" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Shared Memory3" Ports [3, 1] Position [605, 2510, 685, 2600] AttributesFormatString "<< % >>" SourceBlock "xbsIndex_r4/Shared Memory" SourceType "Xilinx Shared Memory Random Access Memory Block" shared_memory_name "'RxBuff_Radio4'" depth "16384" ownership "Owned and Initialized Elsewhere" initVector "sin(pi*(0:15)/16)" mutex "Unprotected" mode "Read and Write" write_mode "Read After Write" time_out "0" latency "1" explicit_data_type off arith_type "Unsigned" n_bits "32" bin_pt "0" xl_use_area off xl_area "[0,0,0,0,0,0,0]" implementation "Block RAM" use_rpm "off" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "shmem" block_version "10.1.3" sg_icon_stat "80,90,1,1,white,blue,0,e2c38f9a,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 80 80 0 ],[0 0 90 90 ],[0.77 0.82 0.91]);\npatch([18 5 24 5 18 39 45 51 74 56 39 27 46 27 39 56 74 51 45 39 18 ],[14 27 46 65 78 78 72 78 78 60 77 65 46 27 15 32 14 14 20 14 14 ],[0.98 0.96 0.92]);\nplot([0 80 80 0 0 ],[0 0 90 90 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'addr');\ncolor('black');port_label('input',2,'din');\ncolor('black');port_label('input',3,'we');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n" Port { PortNumber 1 Name "RxBuff_Radio4_dout" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Shared Memory4" Ports [3, 1] Position [605, 2634, 685, 2726] AttributesFormatString "<< % >>" SourceBlock "xbsIndex_r4/Shared Memory" SourceType "Xilinx Shared Memory Random Access Memory Block" shared_memory_name "'TxBuff_Radio1'" depth "16384" ownership "Owned and Initialized Elsewhere" initVector "sin(pi*(0:15)/16)" mutex "Unprotected" mode "Read and Write" write_mode "Read After Write" time_out "0" latency "1" explicit_data_type off arith_type "Unsigned" n_bits "32" bin_pt "0" xl_use_area off xl_area "[0,0,0,0,0,0,0]" implementation "Block RAM" use_rpm "off" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "shmem" block_version "10.1.3" sg_icon_stat "80,92,1,1,white,blue,0,e2c38f9a,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 80 80 0 ],[0 0 92 92 ],[0.77 0.82 0.91]);\npatch([18 5 24 5 18 39 45 51 74 56 39 27 46 27 39 56 74 51 45 39 18 ],[15 28 47 66 79 79 73 79 79 61 78 66 47 28 16 33 15 15 21 15 15 ],[0.98 0.96 0.92]);\nplot([0 80 80 0 0 ],[0 0 92 92 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'addr');\ncolor('black');port_label('input',2,'din');\ncolor('black');port_label('input',3,'we');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n" Port { PortNumber 1 Name "TxBuff_Radio1_dout" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Shared Memory5" Ports [3, 1] Position [605, 2754, 685, 2846] AttributesFormatString "<< % >>" SourceBlock "xbsIndex_r4/Shared Memory" SourceType "Xilinx Shared Memory Random Access Memory Block" shared_memory_name "'TxBuff_Radio2'" depth "16384" ownership "Owned and Initialized Elsewhere" initVector "sin(pi*(0:15)/16)" mutex "Unprotected" mode "Read and Write" write_mode "Read After Write" time_out "0" latency "1" explicit_data_type off arith_type "Unsigned" n_bits "32" bin_pt "0" xl_use_area off xl_area "[0,0,0,0,0,0,0]" implementation "Block RAM" use_rpm "off" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "shmem" block_version "10.1.3" sg_icon_stat "80,92,1,1,white,blue,0,e2c38f9a,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 80 80 0 ],[0 0 92 92 ],[0.77 0.82 0.91]);\npatch([18 5 24 5 18 39 45 51 74 56 39 27 46 27 39 56 74 51 45 39 18 ],[15 28 47 66 79 79 73 79 79 61 78 66 47 28 16 33 15 15 21 15 15 ],[0.98 0.96 0.92]);\nplot([0 80 80 0 0 ],[0 0 92 92 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'addr');\ncolor('black');port_label('input',2,'din');\ncolor('black');port_label('input',3,'we');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n" Port { PortNumber 1 Name "TxBuff_Radio2_dout" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Shared Memory6" Ports [3, 1] Position [605, 2875, 685, 2965] AttributesFormatString "<< % >>" SourceBlock "xbsIndex_r4/Shared Memory" SourceType "Xilinx Shared Memory Random Access Memory Block" shared_memory_name "'TxBuff_Radio3'" depth "16384" ownership "Owned and Initialized Elsewhere" initVector "sin(pi*(0:15)/16)" mutex "Unprotected" mode "Read and Write" write_mode "Read After Write" time_out "0" latency "1" explicit_data_type off arith_type "Unsigned" n_bits "32" bin_pt "0" xl_use_area off xl_area "[0,0,0,0,0,0,0]" implementation "Block RAM" use_rpm "off" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "shmem" block_version "10.1.3" sg_icon_stat "80,90,1,1,white,blue,0,e2c38f9a,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 80 80 0 ],[0 0 90 90 ],[0.77 0.82 0.91]);\npatch([18 5 24 5 18 39 45 51 74 56 39 27 46 27 39 56 74 51 45 39 18 ],[14 27 46 65 78 78 72 78 78 60 77 65 46 27 15 32 14 14 20 14 14 ],[0.98 0.96 0.92]);\nplot([0 80 80 0 0 ],[0 0 90 90 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'addr');\ncolor('black');port_label('input',2,'din');\ncolor('black');port_label('input',3,'we');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n" Port { PortNumber 1 Name "TxBuff_Radio3_dout" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Shared Memory7" Ports [3, 1] Position [605, 2994, 685, 3086] AttributesFormatString "<< % >>" SourceBlock "xbsIndex_r4/Shared Memory" SourceType "Xilinx Shared Memory Random Access Memory Block" shared_memory_name "'TxBuff_Radio4'" depth "16384" ownership "Owned and Initialized Elsewhere" initVector "sin(pi*(0:15)/16)" mutex "Unprotected" mode "Read and Write" write_mode "Read After Write" time_out "0" latency "1" explicit_data_type off arith_type "Unsigned" n_bits "32" bin_pt "0" xl_use_area off xl_area "[0,0,0,0,0,0,0]" implementation "Block RAM" use_rpm "off" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "shmem" block_version "10.1.3" sg_icon_stat "80,92,1,1,white,blue,0,e2c38f9a,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 80 80 0 ],[0 0 92 92 ],[0.77 0.82 0.91]);\npatch([18 5 24 5 18 39 45 51 74 56 39 27 46 27 39 56 74 51 45 39 18 ],[15 28 47 66 79 79 73 79 79 61 78 66 47 28 16 33 15 15 21 15 15 ],[0.98 0.96 0.92]);\nplot([0 80 80 0 0 ],[0 0 92 92 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'addr');\ncolor('black');port_label('input',2,'din');\ncolor('black');port_label('input',3,'we');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n" Port { PortNumber 1 Name "TxBuff_Radio4_dout" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Shared Memory8" Ports [3, 1] Position [605, 3119, 685, 3211] AttributesFormatString "<< % >>" SourceBlock "xbsIndex_r4/Shared Memory" SourceType "Xilinx Shared Memory Random Access Memory Block" shared_memory_name "'RSSIBuff_Radio1'" depth "2048" ownership "Owned and Initialized Elsewhere" initVector "sin(pi*(0:15)/16)" mutex "Unprotected" mode "Read and Write" write_mode "Read After Write" time_out "0" latency "1" explicit_data_type off arith_type "Unsigned" n_bits "32" bin_pt "0" xl_use_area off xl_area "[0,0,0,0,0,0,0]" implementation "Block RAM" use_rpm "off" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "shmem" block_version "10.1.3" sg_icon_stat "80,92,1,1,white,blue,0,e2c38f9a,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 80 80 0 ],[0 0 92 92 ],[0.77 0.82 0.91]);\npatch([18 5 24 5 18 39 45 51 74 56 39 27 46 27 39 56 74 51 45 39 18 ],[15 28 47 66 79 79 73 79 79 61 78 66 47 28 16 33 15 15 21 15 15 ],[0.98 0.96 0.92]);\nplot([0 80 80 0 0 ],[0 0 92 92 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'addr');\ncolor('black');port_label('input',2,'din');\ncolor('black');port_label('input',3,'we');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n" Port { PortNumber 1 Name "RSSIBuff_Radio1_dout" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Shared Memory9" Ports [3, 1] Position [605, 3240, 685, 3330] AttributesFormatString "<< % >>" SourceBlock "xbsIndex_r4/Shared Memory" SourceType "Xilinx Shared Memory Random Access Memory Block" shared_memory_name "'RSSIBuff_Radio2'" depth "2048" ownership "Owned and Initialized Elsewhere" initVector "sin(pi*(0:15)/16)" mutex "Unprotected" mode "Read and Write" write_mode "Read After Write" time_out "0" latency "1" explicit_data_type off arith_type "Unsigned" n_bits "32" bin_pt "0" xl_use_area off xl_area "[0,0,0,0,0,0,0]" implementation "Block RAM" use_rpm "off" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "shmem" block_version "10.1.3" sg_icon_stat "80,90,1,1,white,blue,0,e2c38f9a,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 80 80 0 ],[0 0 90 90 ],[0.77 0.82 0.91]);\npatch([18 5 24 5 18 39 45 51 74 56 39 27 46 27 39 56 74 51 45 39 18 ],[14 27 46 65 78 78 72 78 78 60 77 65 46 27 15 32 14 14 20 14 14 ],[0.98 0.96 0.92]);\nplot([0 80 80 0 0 ],[0 0 90 90 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'addr');\ncolor('black');port_label('input',2,'din');\ncolor('black');port_label('input',3,'we');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n" Port { PortNumber 1 Name "RSSIBuff_Radio2_dout" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Sl_addrAck" Ports [1, 1] Position [460, 100, 520, 120] SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, double, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarded, depending on how they are configured." hdl_port on timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" sginterface "{'Xilinx'=>{'jtaghwcosim'=>{'non_memory_mapped_port'=>'Sl_addrAck'}},'iopad'=>{'constraint'=>'#'}}" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "10.1.3" sg_icon_stat "60,20,1,1,white,yellow,0,38220381,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([24 21 26 21 24 29 30 31 37 33 29 26 31 26 29 33 37 31 30 29 24 ],[2 5 10 15 18 18 17 18 18 14 18 15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Sl_rdComp" Ports [1, 1] Position [460, 210, 520, 230] SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, double, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarded, depending on how they are configured." hdl_port on timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" sginterface "{'Xilinx'=>{'jtaghwcosim'=>{'non_memory_mapped_port'=>'Sl_rdComp'}},'iopad'=>{'constraint'=>'#'}}" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "10.1.3" sg_icon_stat "60,20,1,1,white,yellow,0,38220381,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([24 21 26 21 24 29 30 31 37 33 29 26 31 26 29 33 37 31 30 29 24 ],[2 5 10 15 18 18 17 18 18 14 18 15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Sl_rdDAck" Ports [1, 1] Position [460, 755, 520, 775] SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, double, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarded, depending on how they are configured." hdl_port on timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" sginterface "{'Xilinx'=>{'jtaghwcosim'=>{'non_memory_mapped_port'=>'Sl_rdDAck'}},'iopad'=>{'constraint'=>'#'}}" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "10.1.3" sg_icon_stat "60,20,1,1,white,yellow,0,38220381,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([24 21 26 21 24 29 30 31 37 33 29 26 31 26 29 33 37 31 30 29 24 ],[2 5 10 15 18 18 17 18 18 14 18 15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Sl_rdDBus" Ports [1, 1] Position [460, 840, 520, 860] SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, double, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarded, depending on how they are configured." hdl_port on timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" sginterface "{'Xilinx'=>{'jtaghwcosim'=>{'non_memory_mapped_port'=>'Sl_rdDBus'}},'iopad'=>{'constraint'=>'#'}}" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "10.1.3" sg_icon_stat "60,20,1,1,white,yellow,0,38220381,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([24 21 26 21 24 29 30 31 37 33 29 26 31 26 29 33 37 31 30 29 24 ],[2 5 10 15 18 18 17 18 18 14 18 15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Sl_wait" Ports [1, 1] Position [110, 495, 170, 515] SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, double, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarded, depending on how they are configured." hdl_port on timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" sginterface "{'Xilinx'=>{'jtaghwcosim'=>{'non_memory_mapped_port'=>'Sl_wait'}},'iopad'=>{'constraint'=>'#'}}" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "10.1.3" sg_icon_stat "60,20,1,1,white,yellow,0,38220381,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([24 21 26 21 24 29 30 31 37 33 29 26 31 26 29 33 37 31 30 29 24 ],[2 5 10 15 18 18 17 18 18 14 18 15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Sl_wrComp" Ports [1, 1] Position [460, 665, 520, 685] SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, double, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarded, depending on how they are configured." hdl_port on timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" sginterface "{'Xilinx'=>{'jtaghwcosim'=>{'non_memory_mapped_port'=>'Sl_wrComp'}},'iopad'=>{'constraint'=>'#'}}" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "10.1.3" sg_icon_stat "60,20,1,1,white,yellow,0,38220381,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([24 21 26 21 24 29 30 31 37 33 29 26 31 26 29 33 37 31 30 29 24 ],[2 5 10 15 18 18 17 18 18 14 18 15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Sl_wrDAck" Ports [1, 1] Position [460, 380, 520, 400] SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, double, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarded, depending on how they are configured." hdl_port on timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" sginterface "{'Xilinx'=>{'jtaghwcosim'=>{'non_memory_mapped_port'=>'Sl_wrDAck'}},'iopad'=>{'constraint'=>'#'}}" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "10.1.3" sg_icon_stat "60,20,1,1,white,yellow,0,38220381,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([24 21 26 21 24 29 30 31 37 33 29 26 31 26 29 33 37 31 30 29 24 ],[2 5 10 15 18 18 17 18 18 14 18 15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Terminator Name "Terminator" Position [635, 30, 655, 50] ShowName off } Block { BlockType Terminator Name "Terminator1" Position [635, 80, 655, 100] ShowName off } Block { BlockType Terminator Name "Terminator2" Position [635, 225, 655, 245] ShowName off } Block { BlockType Terminator Name "Terminator3" Position [635, 275, 655, 295] ShowName off } Block { BlockType Terminator Name "Terminator4" Position [280, 495, 300, 515] ShowName off } Block { BlockType Terminator Name "Terminator5" Position [635, 130, 655, 150] ShowName off } Block { BlockType Terminator Name "Terminator6" Position [635, 180, 655, 200] ShowName off } Block { BlockType Reference Name "To Register" Ports [2, 1] Position [615, 327, 675, 383] AttributesFormatString "<< % >>" SourceBlock "xbsIndex_r4/To Register" SourceType "Xilinx Shared Memory Based To Register Block" infoedit "Register block that writes data to a shared memory register. Delay of one sample period." shared_memory_name "'DCO_EN_SEL'" init "0" ownership "Owned and initialized elsewhere" explicit_data_type on arith_type "Unsigned" n_bits "1" bin_pt "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "toreg" block_version "10.1.3" sg_icon_stat "60,56,1,1,white,blue,0,77cabcdf,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n" Port { PortNumber 1 Name "DCO_EN_SEL_dout" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "To Register1" Ports [2, 1] Position [615, 412, 675, 468] AttributesFormatString "<< % >>" SourceBlock "xbsIndex_r4/To Register" SourceType "Xilinx Shared Memory Based To Register Block" infoedit "Register block that writes data to a shared memory register. Delay of one sample period." shared_memory_name "'DebugRx1Buffers'" init "0" ownership "Owned and initialized elsewhere" explicit_data_type on arith_type "Unsigned" n_bits "1" bin_pt "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "toreg" block_version "10.1.3" sg_icon_stat "60,56,1,1,white,blue,0,77cabcdf,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n" Port { PortNumber 1 Name "DebugRx1Buffers_dout" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "To Register10" Ports [2, 1] Position [615, 1192, 675, 1248] AttributesFormatString "<< % >>" SourceBlock "xbsIndex_r4/To Register" SourceType "Xilinx Shared Memory Based To Register Block" infoedit "Register block that writes data to a shared memory register. Delay of one sample period." shared_memory_name "'RADIO3RXBUFF_RXEN'" init "0" ownership "Owned and initialized elsewhere" explicit_data_type on arith_type "Unsigned" n_bits "1" bin_pt "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "toreg" block_version "10.1.3" sg_icon_stat "60,56,1,1,white,blue,0,77cabcdf,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n" Port { PortNumber 1 Name "RADIO3RXBUFF_RXEN_dout" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "To Register11" Ports [2, 1] Position [615, 1282, 675, 1338] AttributesFormatString "<< % >>" SourceBlock "xbsIndex_r4/To Register" SourceType "Xilinx Shared Memory Based To Register Block" infoedit "Register block that writes data to a shared memory register. Delay of one sample period." shared_memory_name "'RADIO3TXBUFF_TXEN'" init "0" ownership "Owned and initialized elsewhere" explicit_data_type on arith_type "Unsigned" n_bits "1" bin_pt "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "toreg" block_version "10.1.3" sg_icon_stat "60,56,1,1,white,blue,0,77cabcdf,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n" Port { PortNumber 1 Name "RADIO3TXBUFF_TXEN_dout" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "To Register12" Ports [2, 1] Position [615, 1367, 675, 1423] AttributesFormatString "<< % >>" SourceBlock "xbsIndex_r4/To Register" SourceType "Xilinx Shared Memory Based To Register Block" infoedit "Register block that writes data to a shared memory register. Delay of one sample period." shared_memory_name "'RADIO4RXBUFF_RXEN'" init "0" ownership "Owned and initialized elsewhere" explicit_data_type on arith_type "Unsigned" n_bits "1" bin_pt "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "toreg" block_version "10.1.3" sg_icon_stat "60,56,1,1,white,blue,0,77cabcdf,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n" Port { PortNumber 1 Name "RADIO4RXBUFF_RXEN_dout" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "To Register13" Ports [2, 1] Position [615, 1452, 675, 1508] AttributesFormatString "<< % >>" SourceBlock "xbsIndex_r4/To Register" SourceType "Xilinx Shared Memory Based To Register Block" infoedit "Register block that writes data to a shared memory register. Delay of one sample period." shared_memory_name "'RADIO4TXBUFF_TXEN'" init "0" ownership "Owned and initialized elsewhere" explicit_data_type on arith_type "Unsigned" n_bits "1" bin_pt "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "toreg" block_version "10.1.3" sg_icon_stat "60,56,1,1,white,blue,0,77cabcdf,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n" Port { PortNumber 1 Name "RADIO4TXBUFF_TXEN_dout" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "To Register14" Ports [2, 1] Position [615, 1542, 675, 1598] AttributesFormatString "<< % >>" SourceBlock "xbsIndex_r4/To Register" SourceType "Xilinx Shared Memory Based To Register Block" infoedit "Register block that writes data to a shared memory register. Delay of one sample period." shared_memory_name "'StartCapture'" init "0" ownership "Owned and initialized elsewhere" explicit_data_type on arith_type "Unsigned" n_bits "1" bin_pt "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "toreg" block_version "10.1.3" sg_icon_stat "60,56,1,1,white,blue,0,77cabcdf,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n" Port { PortNumber 1 Name "StartCapture_dout" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "To Register15" Ports [2, 1] Position [615, 1627, 675, 1683] AttributesFormatString "<< % >>" SourceBlock "xbsIndex_r4/To Register" SourceType "Xilinx Shared Memory Based To Register Block" infoedit "Register block that writes data to a shared memory register. Delay of one sample period." shared_memory_name "'StartTx'" init "0" ownership "Owned and initialized elsewhere" explicit_data_type on arith_type "Unsigned" n_bits "1" bin_pt "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "toreg" block_version "10.1.3" sg_icon_stat "60,56,1,1,white,blue,0,77cabcdf,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n" Port { PortNumber 1 Name "StartTx_dout" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "To Register16" Ports [2, 1] Position [615, 1712, 675, 1768] AttributesFormatString "<< % >>" SourceBlock "xbsIndex_r4/To Register" SourceType "Xilinx Shared Memory Based To Register Block" infoedit "Register block that writes data to a shared memory register. Delay of one sample period." shared_memory_name "'StopTx'" init "0" ownership "Owned and initialized elsewhere" explicit_data_type on arith_type "Unsigned" n_bits "1" bin_pt "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "toreg" block_version "10.1.3" sg_icon_stat "60,56,1,1,white,blue,0,77cabcdf,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n" Port { PortNumber 1 Name "StopTx_dout" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "To Register17" Ports [2, 1] Position [615, 1802, 675, 1858] AttributesFormatString "<< % >>" SourceBlock "xbsIndex_r4/To Register" SourceType "Xilinx Shared Memory Based To Register Block" infoedit "Register block that writes data to a shared memory register. Delay of one sample period." shared_memory_name "'TransMode'" init "0" ownership "Owned and initialized elsewhere" explicit_data_type on arith_type "Unsigned" n_bits "1" bin_pt "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "toreg" block_version "10.1.3" sg_icon_stat "60,56,1,1,white,blue,0,77cabcdf,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n" Port { PortNumber 1 Name "TransMode_dout" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "To Register18" Ports [2, 1] Position [615, 1887, 675, 1943] AttributesFormatString "<< % >>" SourceBlock "xbsIndex_r4/To Register" SourceType "Xilinx Shared Memory Based To Register Block" infoedit "Register block that writes data to a shared memory register. Delay of one sample period." shared_memory_name "'TxDelay'" init "0" ownership "Owned and initialized elsewhere" explicit_data_type on arith_type "Unsigned" n_bits "14" bin_pt "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "toreg" block_version "10.1.3" sg_icon_stat "60,56,1,1,white,blue,0,77cabcdf,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n" Port { PortNumber 1 Name "TxDelay_dout" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "To Register19" Ports [2, 1] Position [615, 1972, 675, 2028] AttributesFormatString "<< % >>" SourceBlock "xbsIndex_r4/To Register" SourceType "Xilinx Shared Memory Based To Register Block" infoedit "Register block that writes data to a shared memory register. Delay of one sample period." shared_memory_name "'TxLength'" init "0" ownership "Owned and initialized elsewhere" explicit_data_type on arith_type "Unsigned" n_bits "14" bin_pt "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "toreg" block_version "10.1.3" sg_icon_stat "60,56,1,1,white,blue,0,77cabcdf,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n" Port { PortNumber 1 Name "TxLength_dout" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "To Register2" Ports [2, 1] Position [615, 502, 675, 558] AttributesFormatString "<< % >>" SourceBlock "xbsIndex_r4/To Register" SourceType "Xilinx Shared Memory Based To Register Block" infoedit "Register block that writes data to a shared memory register. Delay of one sample period." shared_memory_name "'DebugRx2Buffers'" init "0" ownership "Owned and initialized elsewhere" explicit_data_type on arith_type "Unsigned" n_bits "1" bin_pt "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "toreg" block_version "10.1.3" sg_icon_stat "60,56,1,1,white,blue,0,77cabcdf,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n" Port { PortNumber 1 Name "DebugRx2Buffers_dout" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "To Register20" Ports [2, 1] Position [615, 2062, 675, 2118] AttributesFormatString "<< % >>" SourceBlock "xbsIndex_r4/To Register" SourceType "Xilinx Shared Memory Based To Register Block" infoedit "Register block that writes data to a shared memory register. Delay of one sample period." shared_memory_name "'StartTxRx'" init "0" ownership "Owned and initialized elsewhere" explicit_data_type on arith_type "Unsigned" n_bits "1" bin_pt "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "toreg" block_version "10.1.3" sg_icon_stat "60,56,1,1,white,blue,0,77cabcdf,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n" Port { PortNumber 1 Name "StartTxRx_dout" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "To Register3" Ports [2, 1] Position [615, 587, 675, 643] AttributesFormatString "<< % >>" SourceBlock "xbsIndex_r4/To Register" SourceType "Xilinx Shared Memory Based To Register Block" infoedit "Register block that writes data to a shared memory register. Delay of one sample period." shared_memory_name "'DebugRx3Buffers'" init "0" ownership "Owned and initialized elsewhere" explicit_data_type on arith_type "Unsigned" n_bits "1" bin_pt "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "toreg" block_version "10.1.3" sg_icon_stat "60,56,1,1,white,blue,0,77cabcdf,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n" Port { PortNumber 1 Name "DebugRx3Buffers_dout" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "To Register4" Ports [2, 1] Position [615, 672, 675, 728] AttributesFormatString "<< % >>" SourceBlock "xbsIndex_r4/To Register" SourceType "Xilinx Shared Memory Based To Register Block" infoedit "Register block that writes data to a shared memory register. Delay of one sample period." shared_memory_name "'DebugRx4Buffers'" init "0" ownership "Owned and initialized elsewhere" explicit_data_type on arith_type "Unsigned" n_bits "1" bin_pt "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "toreg" block_version "10.1.3" sg_icon_stat "60,56,1,1,white,blue,0,77cabcdf,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n" Port { PortNumber 1 Name "DebugRx4Buffers_dout" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "To Register5" Ports [2, 1] Position [615, 762, 675, 818] AttributesFormatString "<< % >>" SourceBlock "xbsIndex_r4/To Register" SourceType "Xilinx Shared Memory Based To Register Block" infoedit "Register block that writes data to a shared memory register. Delay of one sample period." shared_memory_name "'MGC_AGC_SEL'" init "0" ownership "Owned and initialized elsewhere" explicit_data_type on arith_type "Unsigned" n_bits "1" bin_pt "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "toreg" block_version "10.1.3" sg_icon_stat "60,56,1,1,white,blue,0,77cabcdf,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n" Port { PortNumber 1 Name "MGC_AGC_SEL_dout" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "To Register6" Ports [2, 1] Position [615, 847, 675, 903] AttributesFormatString "<< % >>" SourceBlock "xbsIndex_r4/To Register" SourceType "Xilinx Shared Memory Based To Register Block" infoedit "Register block that writes data to a shared memory register. Delay of one sample period." shared_memory_name "'RADIO1RXBUFF_RXEN'" init "0" ownership "Owned and initialized elsewhere" explicit_data_type on arith_type "Unsigned" n_bits "1" bin_pt "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "toreg" block_version "10.1.3" sg_icon_stat "60,56,1,1,white,blue,0,77cabcdf,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n" Port { PortNumber 1 Name "RADIO1RXBUFF_RXEN_dout" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "To Register7" Ports [2, 1] Position [615, 932, 675, 988] AttributesFormatString "<< % >>" SourceBlock "xbsIndex_r4/To Register" SourceType "Xilinx Shared Memory Based To Register Block" infoedit "Register block that writes data to a shared memory register. Delay of one sample period." shared_memory_name "'RADIO1TXBUFF_TXEN'" init "0" ownership "Owned and initialized elsewhere" explicit_data_type on arith_type "Unsigned" n_bits "1" bin_pt "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "toreg" block_version "10.1.3" sg_icon_stat "60,56,1,1,white,blue,0,77cabcdf,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n" Port { PortNumber 1 Name "RADIO1TXBUFF_TXEN_dout" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "To Register8" Ports [2, 1] Position [615, 1022, 675, 1078] AttributesFormatString "<< % >>" SourceBlock "xbsIndex_r4/To Register" SourceType "Xilinx Shared Memory Based To Register Block" infoedit "Register block that writes data to a shared memory register. Delay of one sample period." shared_memory_name "'RADIO2RXBUFF_RXEN'" init "0" ownership "Owned and initialized elsewhere" explicit_data_type on arith_type "Unsigned" n_bits "1" bin_pt "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "toreg" block_version "10.1.3" sg_icon_stat "60,56,1,1,white,blue,0,77cabcdf,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n" Port { PortNumber 1 Name "RADIO2RXBUFF_RXEN_dout" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "To Register9" Ports [2, 1] Position [615, 1107, 675, 1163] AttributesFormatString "<< % >>" SourceBlock "xbsIndex_r4/To Register" SourceType "Xilinx Shared Memory Based To Register Block" infoedit "Register block that writes data to a shared memory register. Delay of one sample period." shared_memory_name "'RADIO2TXBUFF_TXEN'" init "0" ownership "Owned and initialized elsewhere" explicit_data_type on arith_type "Unsigned" n_bits "1" bin_pt "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "toreg" block_version "10.1.3" sg_icon_stat "60,56,1,1,white,blue,0,77cabcdf,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n" Port { PortNumber 1 Name "RADIO2TXBUFF_TXEN_dout" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "plb_decode" Ports [7, 9] Position [205, 544, 375, 956] SourceBlock "xbsIndex_r4/MCode" SourceType "Xilinx MCode Block Block" infoedit "Pass input values to a MATLAB function for evaluation in Xilinx fixed-point type. The input ports of the block are input arguments of the function. The output ports of the block are output arguments of the function." mfname "xlmax" explicit_period off period "1" dbl_ovrd off enable_stdout off enable_debug off xl_use_area off xl_area "[0,0,0,0,0,0,0]" mfilecontent "function [wrDBusReg, addrAck, rdComp, wrDAck, bankAddr, RNWReg, rdDAck, rdDBus, linearAddr] = ...\n plb_bus_decode(plbRst, plbABus, plbPAValid, plbRNW, plbWrDBus, rdData, addrPref)\n\n% constant variables (TODO: should pass from outside)\nADDRPREF_LEN = 10;\nBANKADDR_LEN = 2;\nLINEARADDR_LEN = 18;\nABUS_LEN = 32;\nDBUS_LEN = 32;\n\n% declare and initialize persistent variables\n% register input bus signals\npersistent plbRstReg_, plbRstReg_ = xl_state(0, {xlBoolean});\npersistent plbABusReg_, plbABusReg_ = xl_state(0, {xlUnsigned, ABUS_LEN, 0});\npersistent plbPAValidReg_, plbPAValidReg_ = xl_state(0, {xlBoolean});\npersistent plbRNWReg_, plbRNWReg_ = xl_state(0, {xlUnsigned, 1, 0});\npersistent plbWrDBusReg_, plbWrDBusReg_ = xl_state(0, {xlUnsigned, DBUS_LEN, 0});\n\n% ===== rest of the outputs =====\n\nbankAddr = xl_slice(plbABusReg_, 2+BANKADDR_LEN+LINEARADDR_LEN-1, 2+LINEARADDR_LEN);\nlinearAddr = xl_slice(plbABusReg_, 2+LINEARADDR_LEN-1, 2);\nRNWReg = plbRNWReg_;\nwrDBusReg = plbWrDBusReg_;\n\n% ===== p_select =====\n\n% register PAValid\npersistent aValidReg, aValidReg = xl_state(0, {xlBoolean});\naValidReg = plbPAValidReg_;\n\n% extract and register the address prefix\naddrPref_in = xl_slice(plbABusReg_, xl_nbits(plbABusReg_)-1, xl_nbits(plbABusReg_)-ADDRPREF_LEN);\nif addrPref_in == addrPref\n ps1 = true;\nelse \n ps1 = false;\nend \n\npersistent ps1Reg, ps1Reg = xl_state(0, ps1);\nps1Reg = ps1;\n\nps = xl_and(ps1Reg, aValidReg);\n\n% ===== addrAck =====\n\n% register ps\npersistent psReg, psReg = xl_state(0, ps);\n\naddrAck = xfix({xlUnsigned, 1, 0}, xl_and(xl_not(plbRstReg_), ps, xl_not(psReg)));\n\npsReg = ps;\n\n% ===== rdComp, rd/wr DAck =====\n \nrdComp1 = xfix({xlUnsigned, 1, 0}, xl_and(addrAck, RNWReg));\n\nNUM_rdCompDelay = 3;\npersistent rdCompDelay, rdCompDelay = xl_state(zeros(1, NUM_rdCompDelay), rdComp1, NUM_rdCompDelay);\nrdComp2 = rdCompDelay.back;\nrdCompDelay.push_front_pop_back(rdComp1);\n\npersistent rdCompReg, rdCompReg = xl_state(0, rdComp1);\nrdComp = rdCompReg;\nrdCompReg = rdComp2;\n\npersistent rdDAckReg, rdDAckReg = xl_state(0, rdComp1);\nrdDAck = rdDAckReg;\nrdDAckReg = rdComp;\n\npersistent wrDAckReg, wrDAckReg = xl_state(0, addrAck);\nwrDAck = wrDAckReg;\nwrDAckReg = xl_and(addrAck, xl_not(RNWReg));\n\n% ===== rdDBus =====\n\nrdSel = xl_or(rdComp2, rdComp);\n\nif rdSel == 1\n rdDBus1 = rdData;\nelse\n rdDBus1 = 0;\nend % if\n\npersistent rdDBusReg, rdDBusReg = xl_state(0, rdDBus1);\nrdDBus = rdDBusReg;\nrdDBusReg = rdDBus1;\n\n% rdDBus = xl_concat(rdDBus32, rdDBus32);\n% rdDBus = rdDBus32;\n\n% ===== update the persistent variables =====\n\nplbRstReg_ = plbRst;\nplbABusReg_ = plbABus;\nplbPAValidReg_ = plbPAValid;\nplbRNWReg_ = plbRNW;\nplbWrDBusReg_ = xl_slice(plbWrDBus, DBUS_LEN-1, 0);\n" suppress_output "1" defparams "{}" hide_port_list "{}" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mcode" block_version "10.1.3" sg_icon_stat "170,412,7,9,white,blue,0,8b15b975,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 170 170 0 ],[0 0 412 412 ],[0.77 0.82 0.91]);\npatch([40 12 52 12 40 85 97 109 157 119 83 57 97 57 83 119 157 109 97 85 40 ],[139 167 207 247 275 275 263 275 275 237 273 247 207 167 141 177 139 139 151 139 139 ],[0.98 0.96 0.92]);\nplot([0 170 170 0 0 ],[0 0 412 412 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'plbRst');\ncolor('black');port_label('input',2,'plbABus');\ncolor('black');port_label('input',3,'plbPAValid');\ncolor('black');port_label('input',4,'plbRNW');\ncolor('black');port_label('input',5,'plbWrDBus');\ncolor('black');port_label('input',6,'rdData');\ncolor('black');port_label('input',7,'addrPref');\ncolor('black');port_label('output',1,'wrDBusReg');\ncolor('black');port_label('output',2,'addrAck');\ncolor('black');port_label('output',3,'rdComp');\ncolor('black');port_label('output',4,'wrDAck');\ncolor('black');port_label('output',5,'bankAddr');\ncolor('black');port_label('output',6,'RNWReg');\ncolor('black');port_label('output',7,'rdDAck');\ncolor('black');port_label('output',8,'rdDBus');\ncolor('black');port_label('output',9,'linearAddr');\ncolor('black');disp('\\bf{xlmax}','texmode','on');\nfprintf('','COMMENT: end icon text');\n" Port { PortNumber 1 Name "wrDBusReg" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 2 Name "Sl_addrAck" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 3 Name "Sl_rdComp" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 4 Name "Sl_wrDAck" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 5 Name "bankAddr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 6 Name "RNWReg" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 7 Name "Sl_rdDAck" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 8 Name "Sl_rdDBus" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 9 Name "linearAddr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "plb_memmap" Ports [44, 79] Position [405, 1639, 575, 2031] SourceBlock "xbsIndex_r4/MCode" SourceType "Xilinx MCode Block Block" infoedit "Pass input values to a MATLAB function for evaluation in Xilinx fixed-point type. The input ports of the block are input arguments of the function. The output ports of the block are output arguments of the function." mfname "xlmax" explicit_period off period "1" dbl_ovrd off enable_stdout off enable_debug off xl_use_area off xl_area "[0,0,0,0,0,0,0]" mfilecontent "function [read_bank_out, sm_DCO_EN_SEL_din, sm_DCO_EN_SEL_en, sm_DebugRx1Buffers_din, sm_DebugRx1Buffers_en, sm_DebugRx2Buffers_din, sm_DebugRx2Buffers_en, sm_DebugRx3Buffers_din, sm_DebugRx3Buffers_en, sm_DebugRx4Buffers_din, sm_DebugRx4Buffers_en, sm_MGC_AGC_SEL_din, sm_MGC_AGC_SEL_en, sm_RADIO1RXBUFF_RXEN_din, sm_RADIO1RXBUFF_RXEN_en, sm_RADIO1TXBUFF_TXEN_din, sm_RADIO1TXBUFF_TXEN_en, sm_RADIO2RXBUFF_RXEN_din, sm_RADIO2RXBUFF_RXEN_en, sm_RADIO2TXBUFF_TXEN_din, sm_RADIO2TXBUFF_TXEN_en, sm_RADIO3RXBUFF_RXEN_din, sm_RADIO3RXBUFF_RXEN_en, sm_RADIO3TXBUFF_TXEN_din, sm_RADIO3TXBUFF_TXEN_en, sm_RADIO4RXBUFF_RXEN_din, sm_RADIO4RXBUFF_RXEN_en, sm_RADIO4TXBUFF_TXEN_din, sm_RADIO4TXBUFF_TXEN_en, sm_StartCapture_din, sm_StartCapture_en, sm_StartTx_din, sm_StartTx_en, sm_StopTx_din, sm_StopTx_en, sm_TransMode_din, sm_TransMode_en, sm_TxDelay_din, sm_TxDelay_en, sm_TxLength_din, sm_TxLength_en, sm_StartTxRx_din, sm_StartTxRx_en, sm_RxBuff_Radio1_addr, sm_RxBuff_Radio1_din, sm_RxBuff_Radio1_we, sm_RxBuff_Radio2_addr, sm_RxBuff_Radio2_din, sm_RxBuff_Radio2_we, sm_RxBuff_Radio3_addr, sm_RxBuff_Radio3_din, sm_RxBuff_Radio3_we, sm_RxBuff_Radio4_addr, sm_RxBuff_Radio4_din, sm_RxBuff_Radio4_we, sm_TxBuff_Radio1_addr, sm_TxBuff_Radio1_din, sm_TxBuff_Radio1_we, sm_TxBuff_Radio2_addr, sm_TxBuff_Radio2_din, sm_TxBuff_Radio2_we, sm_TxBuff_Radio3_addr, sm_TxBuff_Radio3_din, sm_TxBuff_Radio3_we, sm_TxBuff_Radio4_addr, sm_TxBuff_Radio4_din, sm_TxBuff_Radio4_we, sm_RSSIBuff_Radio1_addr, sm_RSSIBuff_Radio1_din, sm_RSSIBuff_Radio1_we, sm_RSSIBuff_Radio2_addr, sm_RSSIBuff_Radio2_din, sm_RSSIBuff_Radio2_we, sm_RSSIBuff_Radio3_addr, sm_RSSIBuff_Radio3_din, sm_RSSIBuff_Radio3_we, sm_RSSIBuff_Radio4_addr, sm_RSSIBuff_Radio4_din, sm_RSSIBuff_Radio4_we] = plb_memmap(wrDBus, bankAddr, linearAddr, RNWReg, addrAck, sm_AGCDoneAddr, sm_CaptureDone, sm_Radio1AGCDoneRSSI, sm_Radio2AGCDoneRSSI, sm_Radio3AGCDoneRSSI, sm_Radio4AGCDoneRSSI, sm_DCO_EN_SEL, sm_DebugRx1Buffers, sm_DebugRx2Buffers, sm_DebugRx3Buffers, sm_DebugRx4Buffers, sm_MGC_AGC_SEL, sm_RADIO1RXBUFF_RXEN, sm_RADIO1TXBUFF_TXEN, sm_RADIO2RXBUFF_RXEN, sm_RADIO2TXBUFF_TXEN, sm_RADIO3RXBUFF_RXEN, sm_RADIO3TXBUFF_TXEN, sm_RADIO4RXBUFF_RXEN, sm_RADIO4TXBUFF_TXEN, sm_StartCapture, sm_StartTx, sm_StopTx, sm_TransMode, sm_TxDelay, sm_TxLength, sm_StartTxRx, sm_RxBuff_Radio1, sm_RxBuff_Radio2, sm_RxBuff_Radio3, sm_RxBuff_Radio4, sm_TxBuff_Radio1, sm_TxBuff_Radio2, sm_TxBuff_Radio3, sm_TxBuff_Radio4, sm_RSSIBuff_Radio1, sm_RSSIBuff_Radio2, sm_RSSIBuff_Radio3, sm_RSSIBuff_Radio4)\n\n\n% connvert the input data to UFix_32_0 (the bus data type)\n% 'From Register' blocks\n% sm_AGCDoneAddr_bus = xfix({xlUnsigned, 32, 0}, 0);\nsm_AGCDoneAddr_bus = xl_force(sm_AGCDoneAddr, xlUnsigned, 0);\n\n% sm_CaptureDone_bus = xfix({xlUnsigned, 32, 0}, 0);\nsm_CaptureDone_bus = xl_force(sm_CaptureDone, xlUnsigned, 0);\n\n% sm_Radio1AGCDoneRSSI_bus = xfix({xlUnsigned, 32, 0}, 0);\nsm_Radio1AGCDoneRSSI_bus = xl_force(sm_Radio1AGCDoneRSSI, xlUnsigned, 0);\n\n% sm_Radio2AGCDoneRSSI_bus = xfix({xlUnsigned, 32, 0}, 0);\nsm_Radio2AGCDoneRSSI_bus = xl_force(sm_Radio2AGCDoneRSSI, xlUnsigned, 0);\n\n% sm_Radio3AGCDoneRSSI_bus = xfix({xlUnsigned, 32, 0}, 0);\nsm_Radio3AGCDoneRSSI_bus = xl_force(sm_Radio3AGCDoneRSSI, xlUnsigned, 0);\n\n% sm_Radio4AGCDoneRSSI_bus = xfix({xlUnsigned, 32, 0}, 0);\nsm_Radio4AGCDoneRSSI_bus = xl_force(sm_Radio4AGCDoneRSSI, xlUnsigned, 0);\n\n% 'To Register' blocks\n\n% sm_DCO_EN_SEL_dout = xfix({xlUnsigned, 32, 0}, 0);\nsm_DCO_EN_SEL_dout = xl_force(sm_DCO_EN_SEL, xlUnsigned, 0);\n\n% sm_DebugRx1Buffers_dout = xfix({xlUnsigned, 32, 0}, 0);\nsm_DebugRx1Buffers_dout = xl_force(sm_DebugRx1Buffers, xlUnsigned, 0);\n\n% sm_DebugRx2Buffers_dout = xfix({xlUnsigned, 32, 0}, 0);\nsm_DebugRx2Buffers_dout = xl_force(sm_DebugRx2Buffers, xlUnsigned, 0);\n\n% sm_DebugRx3Buffers_dout = xfix({xlUnsigned, 32, 0}, 0);\nsm_DebugRx3Buffers_dout = xl_force(sm_DebugRx3Buffers, xlUnsigned, 0);\n\n% sm_DebugRx4Buffers_dout = xfix({xlUnsigned, 32, 0}, 0);\nsm_DebugRx4Buffers_dout = xl_force(sm_DebugRx4Buffers, xlUnsigned, 0);\n\n% sm_MGC_AGC_SEL_dout = xfix({xlUnsigned, 32, 0}, 0);\nsm_MGC_AGC_SEL_dout = xl_force(sm_MGC_AGC_SEL, xlUnsigned, 0);\n\n% sm_RADIO1RXBUFF_RXEN_dout = xfix({xlUnsigned, 32, 0}, 0);\nsm_RADIO1RXBUFF_RXEN_dout = xl_force(sm_RADIO1RXBUFF_RXEN, xlUnsigned, 0);\n\n% sm_RADIO1TXBUFF_TXEN_dout = xfix({xlUnsigned, 32, 0}, 0);\nsm_RADIO1TXBUFF_TXEN_dout = xl_force(sm_RADIO1TXBUFF_TXEN, xlUnsigned, 0);\n\n% sm_RADIO2RXBUFF_RXEN_dout = xfix({xlUnsigned, 32, 0}, 0);\nsm_RADIO2RXBUFF_RXEN_dout = xl_force(sm_RADIO2RXBUFF_RXEN, xlUnsigned, 0);\n\n% sm_RADIO2TXBUFF_TXEN_dout = xfix({xlUnsigned, 32, 0}, 0);\nsm_RADIO2TXBUFF_TXEN_dout = xl_force(sm_RADIO2TXBUFF_TXEN, xlUnsigned, 0);\n\n% sm_RADIO3RXBUFF_RXEN_dout = xfix({xlUnsigned, 32, 0}, 0);\nsm_RADIO3RXBUFF_RXEN_dout = xl_force(sm_RADIO3RXBUFF_RXEN, xlUnsigned, 0);\n\n% sm_RADIO3TXBUFF_TXEN_dout = xfix({xlUnsigned, 32, 0}, 0);\nsm_RADIO3TXBUFF_TXEN_dout = xl_force(sm_RADIO3TXBUFF_TXEN, xlUnsigned, 0);\n\n% sm_RADIO4RXBUFF_RXEN_dout = xfix({xlUnsigned, 32, 0}, 0);\nsm_RADIO4RXBUFF_RXEN_dout = xl_force(sm_RADIO4RXBUFF_RXEN, xlUnsigned, 0);\n\n% sm_RADIO4TXBUFF_TXEN_dout = xfix({xlUnsigned, 32, 0}, 0);\nsm_RADIO4TXBUFF_TXEN_dout = xl_force(sm_RADIO4TXBUFF_TXEN, xlUnsigned, 0);\n\n% sm_StartCapture_dout = xfix({xlUnsigned, 32, 0}, 0);\nsm_StartCapture_dout = xl_force(sm_StartCapture, xlUnsigned, 0);\n\n% sm_StartTx_dout = xfix({xlUnsigned, 32, 0}, 0);\nsm_StartTx_dout = xl_force(sm_StartTx, xlUnsigned, 0);\n\n% sm_StopTx_dout = xfix({xlUnsigned, 32, 0}, 0);\nsm_StopTx_dout = xl_force(sm_StopTx, xlUnsigned, 0);\n\n% sm_TransMode_dout = xfix({xlUnsigned, 32, 0}, 0);\nsm_TransMode_dout = xl_force(sm_TransMode, xlUnsigned, 0);\n\n% sm_TxDelay_dout = xfix({xlUnsigned, 32, 0}, 0);\nsm_TxDelay_dout = xl_force(sm_TxDelay, xlUnsigned, 0);\n\n% sm_TxLength_dout = xfix({xlUnsigned, 32, 0}, 0);\nsm_TxLength_dout = xl_force(sm_TxLength, xlUnsigned, 0);\n\n% sm_StartTxRx_dout = xfix({xlUnsigned, 32, 0}, 0);\nsm_StartTxRx_dout = xl_force(sm_StartTxRx, xlUnsigned, 0);\n\n\n% 'From FIFO' blocks\n% 'To FIFO' blocks\n% 'Shared Memory' blocks\n% RxBuff_Radio1_bus = xfix({xlUnsigned, 32, 0}, 0);\nsm_RxBuff_Radio1_bus = xl_force(sm_RxBuff_Radio1, xlUnsigned, 0);\n\n% RxBuff_Radio2_bus = xfix({xlUnsigned, 32, 0}, 0);\nsm_RxBuff_Radio2_bus = xl_force(sm_RxBuff_Radio2, xlUnsigned, 0);\n\n% RxBuff_Radio3_bus = xfix({xlUnsigned, 32, 0}, 0);\nsm_RxBuff_Radio3_bus = xl_force(sm_RxBuff_Radio3, xlUnsigned, 0);\n\n% RxBuff_Radio4_bus = xfix({xlUnsigned, 32, 0}, 0);\nsm_RxBuff_Radio4_bus = xl_force(sm_RxBuff_Radio4, xlUnsigned, 0);\n\n% TxBuff_Radio1_bus = xfix({xlUnsigned, 32, 0}, 0);\nsm_TxBuff_Radio1_bus = xl_force(sm_TxBuff_Radio1, xlUnsigned, 0);\n\n% TxBuff_Radio2_bus = xfix({xlUnsigned, 32, 0}, 0);\nsm_TxBuff_Radio2_bus = xl_force(sm_TxBuff_Radio2, xlUnsigned, 0);\n\n% TxBuff_Radio3_bus = xfix({xlUnsigned, 32, 0}, 0);\nsm_TxBuff_Radio3_bus = xl_force(sm_TxBuff_Radio3, xlUnsigned, 0);\n\n% TxBuff_Radio4_bus = xfix({xlUnsigned, 32, 0}, 0);\nsm_TxBuff_Radio4_bus = xl_force(sm_TxBuff_Radio4, xlUnsigned, 0);\n\n% RSSIBuff_Radio1_bus = xfix({xlUnsigned, 32, 0}, 0);\nsm_RSSIBuff_Radio1_bus = xl_force(sm_RSSIBuff_Radio1, xlUnsigned, 0);\n\n% RSSIBuff_Radio2_bus = xfix({xlUnsigned, 32, 0}, 0);\nsm_RSSIBuff_Radio2_bus = xl_force(sm_RSSIBuff_Radio2, xlUnsigned, 0);\n\n% RSSIBuff_Radio3_bus = xfix({xlUnsigned, 32, 0}, 0);\nsm_RSSIBuff_Radio3_bus = xl_force(sm_RSSIBuff_Radio3, xlUnsigned, 0);\n\n% RSSIBuff_Radio4_bus = xfix({xlUnsigned, 32, 0}, 0);\nsm_RSSIBuff_Radio4_bus = xl_force(sm_RSSIBuff_Radio4, xlUnsigned, 0);\n\n\n% 'dout' ports of 'From Register' blocks\n\n% registered register mux output\npersistent reg_bank_out_reg; reg_bank_out_reg = xl_state(0, {xlUnsigned, 32, 0});\nreg_bank_out = reg_bank_out_reg;\n\nif linearAddr == 21\n reg_bank_out_reg = sm_AGCDoneAddr_bus;\nelseif linearAddr == 22\n reg_bank_out_reg = sm_CaptureDone_bus;\nelseif linearAddr == 23\n reg_bank_out_reg = sm_Radio1AGCDoneRSSI_bus;\nelseif linearAddr == 24\n reg_bank_out_reg = sm_Radio2AGCDoneRSSI_bus;\nelseif linearAddr == 25\n reg_bank_out_reg = sm_Radio3AGCDoneRSSI_bus;\nelseif linearAddr == 26\n reg_bank_out_reg = sm_Radio4AGCDoneRSSI_bus;\nelseif linearAddr == 0\n reg_bank_out_reg = sm_DCO_EN_SEL_dout;\nelseif linearAddr == 1\n reg_bank_out_reg = sm_DebugRx1Buffers_dout;\nelseif linearAddr == 2\n reg_bank_out_reg = sm_DebugRx2Buffers_dout;\nelseif linearAddr == 3\n reg_bank_out_reg = sm_DebugRx3Buffers_dout;\nelseif linearAddr == 4\n reg_bank_out_reg = sm_DebugRx4Buffers_dout;\nelseif linearAddr == 5\n reg_bank_out_reg = sm_MGC_AGC_SEL_dout;\nelseif linearAddr == 6\n reg_bank_out_reg = sm_RADIO1RXBUFF_RXEN_dout;\nelseif linearAddr == 7\n reg_bank_out_reg = sm_RADIO1TXBUFF_TXEN_dout;\nelseif linearAddr == 8\n reg_bank_out_reg = sm_RADIO2RXBUFF_RXEN_dout;\nelseif linearAddr == 9\n reg_bank_out_reg = sm_RADIO2TXBUFF_TXEN_dout;\nelseif linearAddr == 10\n reg_bank_out_reg = sm_RADIO3RXBUFF_RXEN_dout;\nelseif linearAddr == 11\n reg_bank_out_reg = sm_RADIO3TXBUFF_TXEN_dout;\nelseif linearAddr == 12\n reg_bank_out_reg = sm_RADIO4RXBUFF_RXEN_dout;\nelseif linearAddr == 13\n reg_bank_out_reg = sm_RADIO4TXBUFF_TXEN_dout;\nelseif linearAddr == 14\n reg_bank_out_reg = sm_StartCapture_dout;\nelseif linearAddr == 15\n reg_bank_out_reg = sm_StartTx_dout;\nelseif linearAddr == 16\n reg_bank_out_reg = sm_StopTx_dout;\nelseif linearAddr == 17\n reg_bank_out_reg = sm_TransMode_dout;\nelseif linearAddr == 18\n reg_bank_out_reg = sm_TxDelay_dout;\nelseif linearAddr == 19\n reg_bank_out_reg = sm_TxLength_dout;\nelseif linearAddr == 20\n reg_bank_out_reg = sm_StartTxRx_dout;\n\nend\n\n\n% 'From FIFO' and 'To FIFO' blocks\n\n\n\n\n\nopCode = xl_concat(addrAck, RNWReg, bankAddr, linearAddr);\n\n% 'Shared Memory' blocks\n\nsm_RxBuff_Radio1_sel_value = xl_concat(xl_slice(linearAddr, ...\n xl_nbits(linearAddr) - 1, ...\n 14) ...\n );\nif sm_RxBuff_Radio1_sel_value == xfix({xlUnsigned, ...\n xl_nbits(linearAddr) - 14, ...\n 0}, ...\n 0);\n sm_RxBuff_Radio1_sel = true;\nelse\n sm_RxBuff_Radio1_sel = false;\nend\nsm_RxBuff_Radio2_sel_value = xl_concat(xl_slice(linearAddr, ...\n xl_nbits(linearAddr) - 1, ...\n 14) ...\n );\nif sm_RxBuff_Radio2_sel_value == xfix({xlUnsigned, ...\n xl_nbits(linearAddr) - 14, ...\n 0}, ...\n 1);\n sm_RxBuff_Radio2_sel = true;\nelse\n sm_RxBuff_Radio2_sel = false;\nend\nsm_RxBuff_Radio3_sel_value = xl_concat(xl_slice(linearAddr, ...\n xl_nbits(linearAddr) - 1, ...\n 14) ...\n );\nif sm_RxBuff_Radio3_sel_value == xfix({xlUnsigned, ...\n xl_nbits(linearAddr) - 14, ...\n 0}, ...\n 2);\n sm_RxBuff_Radio3_sel = true;\nelse\n sm_RxBuff_Radio3_sel = false;\nend\nsm_RxBuff_Radio4_sel_value = xl_concat(xl_slice(linearAddr, ...\n xl_nbits(linearAddr) - 1, ...\n 14) ...\n );\nif sm_RxBuff_Radio4_sel_value == xfix({xlUnsigned, ...\n xl_nbits(linearAddr) - 14, ...\n 0}, ...\n 3);\n sm_RxBuff_Radio4_sel = true;\nelse\n sm_RxBuff_Radio4_sel = false;\nend\nsm_TxBuff_Radio1_sel_value = xl_concat(xl_slice(linearAddr, ...\n xl_nbits(linearAddr) - 1, ...\n 14) ...\n );\nif sm_TxBuff_Radio1_sel_value == xfix({xlUnsigned, ...\n xl_nbits(linearAddr) - 14, ...\n 0}, ...\n 4);\n sm_TxBuff_Radio1_sel = true;\nelse\n sm_TxBuff_Radio1_sel = false;\nend\nsm_TxBuff_Radio2_sel_value = xl_concat(xl_slice(linearAddr, ...\n xl_nbits(linearAddr) - 1, ...\n 14) ...\n );\nif sm_TxBuff_Radio2_sel_value == xfix({xlUnsigned, ...\n xl_nbits(linearAddr) - 14, ...\n 0}, ...\n 5);\n sm_TxBuff_Radio2_sel = true;\nelse\n sm_TxBuff_Radio2_sel = false;\nend\nsm_TxBuff_Radio3_sel_value = xl_concat(xl_slice(linearAddr, ...\n xl_nbits(linearAddr) - 1, ...\n 14) ...\n );\nif sm_TxBuff_Radio3_sel_value == xfix({xlUnsigned, ...\n xl_nbits(linearAddr) - 14, ...\n 0}, ...\n 6);\n sm_TxBuff_Radio3_sel = true;\nelse\n sm_TxBuff_Radio3_sel = false;\nend\nsm_TxBuff_Radio4_sel_value = xl_concat(xl_slice(linearAddr, ...\n xl_nbits(linearAddr) - 1, ...\n 14) ...\n );\nif sm_TxBuff_Radio4_sel_value == xfix({xlUnsigned, ...\n xl_nbits(linearAddr) - 14, ...\n 0}, ...\n 7);\n sm_TxBuff_Radio4_sel = true;\nelse\n sm_TxBuff_Radio4_sel = false;\nend\nsm_RSSIBuff_Radio1_sel_value = xl_concat(xl_slice(linearAddr, ...\n xl_nbits(linearAddr) - 1, ...\n 11) ...\n );\nif sm_RSSIBuff_Radio1_sel_value == xfix({xlUnsigned, ...\n xl_nbits(linearAddr) - 11, ...\n 0}, ...\n 64);\n sm_RSSIBuff_Radio1_sel = true;\nelse\n sm_RSSIBuff_Radio1_sel = false;\nend\nsm_RSSIBuff_Radio2_sel_value = xl_concat(xl_slice(linearAddr, ...\n xl_nbits(linearAddr) - 1, ...\n 11) ...\n );\nif sm_RSSIBuff_Radio2_sel_value == xfix({xlUnsigned, ...\n xl_nbits(linearAddr) - 11, ...\n 0}, ...\n 65);\n sm_RSSIBuff_Radio2_sel = true;\nelse\n sm_RSSIBuff_Radio2_sel = false;\nend\nsm_RSSIBuff_Radio3_sel_value = xl_concat(xl_slice(linearAddr, ...\n xl_nbits(linearAddr) - 1, ...\n 11) ...\n );\nif sm_RSSIBuff_Radio3_sel_value == xfix({xlUnsigned, ...\n xl_nbits(linearAddr) - 11, ...\n 0}, ...\n 66);\n sm_RSSIBuff_Radio3_sel = true;\nelse\n sm_RSSIBuff_Radio3_sel = false;\nend\nsm_RSSIBuff_Radio4_sel_value = xl_concat(xl_slice(linearAddr, ...\n xl_nbits(linearAddr) - 1, ...\n 11) ...\n );\nif sm_RSSIBuff_Radio4_sel_value == xfix({xlUnsigned, ...\n xl_nbits(linearAddr) - 11, ...\n 0}, ...\n 67);\n sm_RSSIBuff_Radio4_sel = true;\nelse\n sm_RSSIBuff_Radio4_sel = false;\nend\n\n\n% registered Shared Memory mux output\npersistent ram_bank_out_reg; ram_bank_out_reg = xl_state(0, {xlUnsigned, 32, 0});\nram_bank_out = ram_bank_out_reg;\nif sm_RxBuff_Radio1_sel\n ram_bank_out_reg = sm_RxBuff_Radio1_bus;\nelseif sm_RxBuff_Radio2_sel\n ram_bank_out_reg = sm_RxBuff_Radio2_bus;\nelseif sm_RxBuff_Radio3_sel\n ram_bank_out_reg = sm_RxBuff_Radio3_bus;\nelseif sm_RxBuff_Radio4_sel\n ram_bank_out_reg = sm_RxBuff_Radio4_bus;\nelseif sm_TxBuff_Radio1_sel\n ram_bank_out_reg = sm_TxBuff_Radio1_bus;\nelseif sm_TxBuff_Radio2_sel\n ram_bank_out_reg = sm_TxBuff_Radio2_bus;\nelseif sm_TxBuff_Radio3_sel\n ram_bank_out_reg = sm_TxBuff_Radio3_bus;\nelseif sm_TxBuff_Radio4_sel\n ram_bank_out_reg = sm_TxBuff_Radio4_bus;\nelseif sm_RSSIBuff_Radio1_sel\n ram_bank_out_reg = sm_RSSIBuff_Radio1_bus;\nelseif sm_RSSIBuff_Radio2_sel\n ram_bank_out_reg = sm_RSSIBuff_Radio2_bus;\nelseif sm_RSSIBuff_Radio3_sel\n ram_bank_out_reg = sm_RSSIBuff_Radio3_bus;\nelseif sm_RSSIBuff_Radio4_sel\n ram_bank_out_reg = sm_RSSIBuff_Radio4_bus;\nend\n\n% 'din' ports of 'Shared Memory' blocks\nsm_RxBuff_Radio1_din = xl_force(xl_slice(wrDBus, 32 - 1, 0), ...\n xlUnsigned, ...\n 0);\nsm_RxBuff_Radio2_din = xl_force(xl_slice(wrDBus, 32 - 1, 0), ...\n xlUnsigned, ...\n 0);\nsm_RxBuff_Radio3_din = xl_force(xl_slice(wrDBus, 32 - 1, 0), ...\n xlUnsigned, ...\n 0);\nsm_RxBuff_Radio4_din = xl_force(xl_slice(wrDBus, 32 - 1, 0), ...\n xlUnsigned, ...\n 0);\nsm_TxBuff_Radio1_din = xl_force(xl_slice(wrDBus, 32 - 1, 0), ...\n xlUnsigned, ...\n 0);\nsm_TxBuff_Radio2_din = xl_force(xl_slice(wrDBus, 32 - 1, 0), ...\n xlUnsigned, ...\n 0);\nsm_TxBuff_Radio3_din = xl_force(xl_slice(wrDBus, 32 - 1, 0), ...\n xlUnsigned, ...\n 0);\nsm_TxBuff_Radio4_din = xl_force(xl_slice(wrDBus, 32 - 1, 0), ...\n xlUnsigned, ...\n 0);\nsm_RSSIBuff_Radio1_din = xl_force(xl_slice(wrDBus, 32 - 1, 0), ...\n xlUnsigned, ...\n 0);\nsm_RSSIBuff_Radio2_din = xl_force(xl_slice(wrDBus, 32 - 1, 0), ...\n xlUnsigned, ...\n 0);\nsm_RSSIBuff_Radio3_din = xl_force(xl_slice(wrDBus, 32 - 1, 0), ...\n xlUnsigned, ...\n 0);\nsm_RSSIBuff_Radio4_din = xl_force(xl_slice(wrDBus, 32 - 1, 0), ...\n xlUnsigned, ...\n 0);\n\n\n% 'we' ports of 'Shared Memory' blocks\npersistent sm_RxBuff_Radio1_we_reg; sm_RxBuff_Radio1_we_reg = xl_state(false, {xlBoolean});\nsm_RxBuff_Radio1_we = sm_RxBuff_Radio1_we_reg;\nopCode_sm_RxBuff_Radio1 = xl_concat(addrAck, ...\n RNWReg, ...\n bankAddr, ...\n xl_slice(linearAddr, ...\n xl_nbits(linearAddr) - 1, ...\n 14) ...\n );\nif opCode_sm_RxBuff_Radio1 == xl_concat(xfix({xlUnsigned, 4, 0}, 8), ...\n xfix({xlUnsigned, ...\n xl_nbits(linearAddr) - 14, ...\n 0}, ...\n 0) ...\n );\n sm_RxBuff_Radio1_we_reg = true;\nelse\n sm_RxBuff_Radio1_we_reg = false;\nend\npersistent sm_RxBuff_Radio2_we_reg; sm_RxBuff_Radio2_we_reg = xl_state(false, {xlBoolean});\nsm_RxBuff_Radio2_we = sm_RxBuff_Radio2_we_reg;\nopCode_sm_RxBuff_Radio2 = xl_concat(addrAck, ...\n RNWReg, ...\n bankAddr, ...\n xl_slice(linearAddr, ...\n xl_nbits(linearAddr) - 1, ...\n 14) ...\n );\nif opCode_sm_RxBuff_Radio2 == xl_concat(xfix({xlUnsigned, 4, 0}, 8), ...\n xfix({xlUnsigned, ...\n xl_nbits(linearAddr) - 14, ...\n 0}, ...\n 1) ...\n );\n sm_RxBuff_Radio2_we_reg = true;\nelse\n sm_RxBuff_Radio2_we_reg = false;\nend\npersistent sm_RxBuff_Radio3_we_reg; sm_RxBuff_Radio3_we_reg = xl_state(false, {xlBoolean});\nsm_RxBuff_Radio3_we = sm_RxBuff_Radio3_we_reg;\nopCode_sm_RxBuff_Radio3 = xl_concat(addrAck, ...\n RNWReg, ...\n bankAddr, ...\n xl_slice(linearAddr, ...\n xl_nbits(linearAddr) - 1, ...\n 14) ...\n );\nif opCode_sm_RxBuff_Radio3 == xl_concat(xfix({xlUnsigned, 4, 0}, 8), ...\n xfix({xlUnsigned, ...\n xl_nbits(linearAddr) - 14, ...\n 0}, ...\n 2) ...\n );\n sm_RxBuff_Radio3_we_reg = true;\nelse\n sm_RxBuff_Radio3_we_reg = false;\nend\npersistent sm_RxBuff_Radio4_we_reg; sm_RxBuff_Radio4_we_reg = xl_state(false, {xlBoolean});\nsm_RxBuff_Radio4_we = sm_RxBuff_Radio4_we_reg;\nopCode_sm_RxBuff_Radio4 = xl_concat(addrAck, ...\n RNWReg, ...\n bankAddr, ...\n xl_slice(linearAddr, ...\n xl_nbits(linearAddr) - 1, ...\n 14) ...\n );\nif opCode_sm_RxBuff_Radio4 == xl_concat(xfix({xlUnsigned, 4, 0}, 8), ...\n xfix({xlUnsigned, ...\n xl_nbits(linearAddr) - 14, ...\n 0}, ...\n 3) ...\n );\n sm_RxBuff_Radio4_we_reg = true;\nelse\n sm_RxBuff_Radio4_we_reg = false;\nend\npersistent sm_TxBuff_Radio1_we_reg; sm_TxBuff_Radio1_we_reg = xl_state(false, {xlBoolean});\nsm_TxBuff_Radio1_we = sm_TxBuff_Radio1_we_reg;\nopCode_sm_TxBuff_Radio1 = xl_concat(addrAck, ...\n RNWReg, ...\n bankAddr, ...\n xl_slice(linearAddr, ...\n xl_nbits(linearAddr) - 1, ...\n 14) ...\n );\nif opCode_sm_TxBuff_Radio1 == xl_concat(xfix({xlUnsigned, 4, 0}, 8), ...\n xfix({xlUnsigned, ...\n xl_nbits(linearAddr) - 14, ...\n 0}, ...\n 4) ...\n );\n sm_TxBuff_Radio1_we_reg = true;\nelse\n sm_TxBuff_Radio1_we_reg = false;\nend\npersistent sm_TxBuff_Radio2_we_reg; sm_TxBuff_Radio2_we_reg = xl_state(false, {xlBoolean});\nsm_TxBuff_Radio2_we = sm_TxBuff_Radio2_we_reg;\nopCode_sm_TxBuff_Radio2 = xl_concat(addrAck, ...\n RNWReg, ...\n bankAddr, ...\n xl_slice(linearAddr, ...\n xl_nbits(linearAddr) - 1, ...\n 14) ...\n );\nif opCode_sm_TxBuff_Radio2 == xl_concat(xfix({xlUnsigned, 4, 0}, 8), ...\n xfix({xlUnsigned, ...\n xl_nbits(linearAddr) - 14, ...\n 0}, ...\n 5) ...\n );\n sm_TxBuff_Radio2_we_reg = true;\nelse\n sm_TxBuff_Radio2_we_reg = false;\nend\npersistent sm_TxBuff_Radio3_we_reg; sm_TxBuff_Radio3_we_reg = xl_state(false, {xlBoolean});\nsm_TxBuff_Radio3_we = sm_TxBuff_Radio3_we_reg;\nopCode_sm_TxBuff_Radio3 = xl_concat(addrAck, ...\n RNWReg, ...\n bankAddr, ...\n xl_slice(linearAddr, ...\n xl_nbits(linearAddr) - 1, ...\n 14) ...\n );\nif opCode_sm_TxBuff_Radio3 == xl_concat(xfix({xlUnsigned, 4, 0}, 8), ...\n xfix({xlUnsigned, ...\n xl_nbits(linearAddr) - 14, ...\n 0}, ...\n 6) ...\n );\n sm_TxBuff_Radio3_we_reg = true;\nelse\n sm_TxBuff_Radio3_we_reg = false;\nend\npersistent sm_TxBuff_Radio4_we_reg; sm_TxBuff_Radio4_we_reg = xl_state(false, {xlBoolean});\nsm_TxBuff_Radio4_we = sm_TxBuff_Radio4_we_reg;\nopCode_sm_TxBuff_Radio4 = xl_concat(addrAck, ...\n RNWReg, ...\n bankAddr, ...\n xl_slice(linearAddr, ...\n xl_nbits(linearAddr) - 1, ...\n 14) ...\n );\nif opCode_sm_TxBuff_Radio4 == xl_concat(xfix({xlUnsigned, 4, 0}, 8), ...\n xfix({xlUnsigned, ...\n xl_nbits(linearAddr) - 14, ...\n 0}, ...\n 7) ...\n );\n sm_TxBuff_Radio4_we_reg = true;\nelse\n sm_TxBuff_Radio4_we_reg = false;\nend\npersistent sm_RSSIBuff_Radio1_we_reg; sm_RSSIBuff_Radio1_we_reg = xl_state(false, {xlBoolean});\nsm_RSSIBuff_Radio1_we = sm_RSSIBuff_Radio1_we_reg;\nopCode_sm_RSSIBuff_Radio1 = xl_concat(addrAck, ...\n RNWReg, ...\n bankAddr, ...\n xl_slice(linearAddr, ...\n xl_nbits(linearAddr) - 1, ...\n 11) ...\n );\nif opCode_sm_RSSIBuff_Radio1 == xl_concat(xfix({xlUnsigned, 4, 0}, 8), ...\n xfix({xlUnsigned, ...\n xl_nbits(linearAddr) - 11, ...\n 0}, ...\n 64) ...\n );\n sm_RSSIBuff_Radio1_we_reg = true;\nelse\n sm_RSSIBuff_Radio1_we_reg = false;\nend\npersistent sm_RSSIBuff_Radio2_we_reg; sm_RSSIBuff_Radio2_we_reg = xl_state(false, {xlBoolean});\nsm_RSSIBuff_Radio2_we = sm_RSSIBuff_Radio2_we_reg;\nopCode_sm_RSSIBuff_Radio2 = xl_concat(addrAck, ...\n RNWReg, ...\n bankAddr, ...\n xl_slice(linearAddr, ...\n xl_nbits(linearAddr) - 1, ...\n 11) ...\n );\nif opCode_sm_RSSIBuff_Radio2 == xl_concat(xfix({xlUnsigned, 4, 0}, 8), ...\n xfix({xlUnsigned, ...\n xl_nbits(linearAddr) - 11, ...\n 0}, ...\n 65) ...\n );\n sm_RSSIBuff_Radio2_we_reg = true;\nelse\n sm_RSSIBuff_Radio2_we_reg = false;\nend\npersistent sm_RSSIBuff_Radio3_we_reg; sm_RSSIBuff_Radio3_we_reg = xl_state(false, {xlBoolean});\nsm_RSSIBuff_Radio3_we = sm_RSSIBuff_Radio3_we_reg;\nopCode_sm_RSSIBuff_Radio3 = xl_concat(addrAck, ...\n RNWReg, ...\n bankAddr, ...\n xl_slice(linearAddr, ...\n xl_nbits(linearAddr) - 1, ...\n 11) ...\n );\nif opCode_sm_RSSIBuff_Radio3 == xl_concat(xfix({xlUnsigned, 4, 0}, 8), ...\n xfix({xlUnsigned, ...\n xl_nbits(linearAddr) - 11, ...\n 0}, ...\n 66) ...\n );\n sm_RSSIBuff_Radio3_we_reg = true;\nelse\n sm_RSSIBuff_Radio3_we_reg = false;\nend\npersistent sm_RSSIBuff_Radio4_we_reg; sm_RSSIBuff_Radio4_we_reg = xl_state(false, {xlBoolean});\nsm_RSSIBuff_Radio4_we = sm_RSSIBuff_Radio4_we_reg;\nopCode_sm_RSSIBuff_Radio4 = xl_concat(addrAck, ...\n RNWReg, ...\n bankAddr, ...\n xl_slice(linearAddr, ...\n xl_nbits(linearAddr) - 1, ...\n 11) ...\n );\nif opCode_sm_RSSIBuff_Radio4 == xl_concat(xfix({xlUnsigned, 4, 0}, 8), ...\n xfix({xlUnsigned, ...\n xl_nbits(linearAddr) - 11, ...\n 0}, ...\n 67) ...\n );\n sm_RSSIBuff_Radio4_we_reg = true;\nelse\n sm_RSSIBuff_Radio4_we_reg = false;\nend\n\n\n% 'addr' ports of 'Shared Memory' blocks\npersistent sm_RxBuff_Radio1_addr_reg; \nsm_RxBuff_Radio1_addr_reg = xl_state(0, {xlUnsigned, 14, 0});\nsm_RxBuff_Radio1_addr = sm_RxBuff_Radio1_addr_reg;\nif addrAck == 1\n sm_RxBuff_Radio1_addr_reg = xl_slice(linearAddr, 14, 0);\nelse\n sm_RxBuff_Radio1_addr_reg = sm_RxBuff_Radio1_addr_reg;\nend\npersistent sm_RxBuff_Radio2_addr_reg; \nsm_RxBuff_Radio2_addr_reg = xl_state(0, {xlUnsigned, 14, 0});\nsm_RxBuff_Radio2_addr = sm_RxBuff_Radio2_addr_reg;\nif addrAck == 1\n sm_RxBuff_Radio2_addr_reg = xl_slice(linearAddr, 14, 0);\nelse\n sm_RxBuff_Radio2_addr_reg = sm_RxBuff_Radio2_addr_reg;\nend\npersistent sm_RxBuff_Radio3_addr_reg; \nsm_RxBuff_Radio3_addr_reg = xl_state(0, {xlUnsigned, 14, 0});\nsm_RxBuff_Radio3_addr = sm_RxBuff_Radio3_addr_reg;\nif addrAck == 1\n sm_RxBuff_Radio3_addr_reg = xl_slice(linearAddr, 14, 0);\nelse\n sm_RxBuff_Radio3_addr_reg = sm_RxBuff_Radio3_addr_reg;\nend\npersistent sm_RxBuff_Radio4_addr_reg; \nsm_RxBuff_Radio4_addr_reg = xl_state(0, {xlUnsigned, 14, 0});\nsm_RxBuff_Radio4_addr = sm_RxBuff_Radio4_addr_reg;\nif addrAck == 1\n sm_RxBuff_Radio4_addr_reg = xl_slice(linearAddr, 14, 0);\nelse\n sm_RxBuff_Radio4_addr_reg = sm_RxBuff_Radio4_addr_reg;\nend\npersistent sm_TxBuff_Radio1_addr_reg; \nsm_TxBuff_Radio1_addr_reg = xl_state(0, {xlUnsigned, 14, 0});\nsm_TxBuff_Radio1_addr = sm_TxBuff_Radio1_addr_reg;\nif addrAck == 1\n sm_TxBuff_Radio1_addr_reg = xl_slice(linearAddr, 14, 0);\nelse\n sm_TxBuff_Radio1_addr_reg = sm_TxBuff_Radio1_addr_reg;\nend\npersistent sm_TxBuff_Radio2_addr_reg; \nsm_TxBuff_Radio2_addr_reg = xl_state(0, {xlUnsigned, 14, 0});\nsm_TxBuff_Radio2_addr = sm_TxBuff_Radio2_addr_reg;\nif addrAck == 1\n sm_TxBuff_Radio2_addr_reg = xl_slice(linearAddr, 14, 0);\nelse\n sm_TxBuff_Radio2_addr_reg = sm_TxBuff_Radio2_addr_reg;\nend\npersistent sm_TxBuff_Radio3_addr_reg; \nsm_TxBuff_Radio3_addr_reg = xl_state(0, {xlUnsigned, 14, 0});\nsm_TxBuff_Radio3_addr = sm_TxBuff_Radio3_addr_reg;\nif addrAck == 1\n sm_TxBuff_Radio3_addr_reg = xl_slice(linearAddr, 14, 0);\nelse\n sm_TxBuff_Radio3_addr_reg = sm_TxBuff_Radio3_addr_reg;\nend\npersistent sm_TxBuff_Radio4_addr_reg; \nsm_TxBuff_Radio4_addr_reg = xl_state(0, {xlUnsigned, 14, 0});\nsm_TxBuff_Radio4_addr = sm_TxBuff_Radio4_addr_reg;\nif addrAck == 1\n sm_TxBuff_Radio4_addr_reg = xl_slice(linearAddr, 14, 0);\nelse\n sm_TxBuff_Radio4_addr_reg = sm_TxBuff_Radio4_addr_reg;\nend\npersistent sm_RSSIBuff_Radio1_addr_reg; \nsm_RSSIBuff_Radio1_addr_reg = xl_state(0, {xlUnsigned, 11, 0});\nsm_RSSIBuff_Radio1_addr = sm_RSSIBuff_Radio1_addr_reg;\nif addrAck == 1\n sm_RSSIBuff_Radio1_addr_reg = xl_slice(linearAddr, 11, 0);\nelse\n sm_RSSIBuff_Radio1_addr_reg = sm_RSSIBuff_Radio1_addr_reg;\nend\npersistent sm_RSSIBuff_Radio2_addr_reg; \nsm_RSSIBuff_Radio2_addr_reg = xl_state(0, {xlUnsigned, 11, 0});\nsm_RSSIBuff_Radio2_addr = sm_RSSIBuff_Radio2_addr_reg;\nif addrAck == 1\n sm_RSSIBuff_Radio2_addr_reg = xl_slice(linearAddr, 11, 0);\nelse\n sm_RSSIBuff_Radio2_addr_reg = sm_RSSIBuff_Radio2_addr_reg;\nend\npersistent sm_RSSIBuff_Radio3_addr_reg; \nsm_RSSIBuff_Radio3_addr_reg = xl_state(0, {xlUnsigned, 11, 0});\nsm_RSSIBuff_Radio3_addr = sm_RSSIBuff_Radio3_addr_reg;\nif addrAck == 1\n sm_RSSIBuff_Radio3_addr_reg = xl_slice(linearAddr, 11, 0);\nelse\n sm_RSSIBuff_Radio3_addr_reg = sm_RSSIBuff_Radio3_addr_reg;\nend\npersistent sm_RSSIBuff_Radio4_addr_reg; \nsm_RSSIBuff_Radio4_addr_reg = xl_state(0, {xlUnsigned, 11, 0});\nsm_RSSIBuff_Radio4_addr = sm_RSSIBuff_Radio4_addr_reg;\nif addrAck == 1\n sm_RSSIBuff_Radio4_addr_reg = xl_slice(linearAddr, 11, 0);\nelse\n sm_RSSIBuff_Radio4_addr_reg = sm_RSSIBuff_Radio4_addr_reg;\nend\n\n\n% 're' ports of 'From FIFO' blocks\n\n\n% 'en' ports of 'To Register' blocks\nif opCode == xl_concat(xfix({xlUnsigned, 4, 0}, 10), ...\n xfix({xlUnsigned, xl_nbits(linearAddr), 0}, 0))\n sm_DCO_EN_SEL_en = true;\nelse\n sm_DCO_EN_SEL_en = false;\nend\nif opCode == xl_concat(xfix({xlUnsigned, 4, 0}, 10), ...\n xfix({xlUnsigned, xl_nbits(linearAddr), 0}, 1))\n sm_DebugRx1Buffers_en = true;\nelse\n sm_DebugRx1Buffers_en = false;\nend\nif opCode == xl_concat(xfix({xlUnsigned, 4, 0}, 10), ...\n xfix({xlUnsigned, xl_nbits(linearAddr), 0}, 2))\n sm_DebugRx2Buffers_en = true;\nelse\n sm_DebugRx2Buffers_en = false;\nend\nif opCode == xl_concat(xfix({xlUnsigned, 4, 0}, 10), ...\n xfix({xlUnsigned, xl_nbits(linearAddr), 0}, 3))\n sm_DebugRx3Buffers_en = true;\nelse\n sm_DebugRx3Buffers_en = false;\nend\nif opCode == xl_concat(xfix({xlUnsigned, 4, 0}, 10), ...\n xfix({xlUnsigned, xl_nbits(linearAddr), 0}, 4))\n sm_DebugRx4Buffers_en = true;\nelse\n sm_DebugRx4Buffers_en = false;\nend\nif opCode == xl_concat(xfix({xlUnsigned, 4, 0}, 10), ...\n xfix({xlUnsigned, xl_nbits(linearAddr), 0}, 5))\n sm_MGC_AGC_SEL_en = true;\nelse\n sm_MGC_AGC_SEL_en = false;\nend\nif opCode == xl_concat(xfix({xlUnsigned, 4, 0}, 10), ...\n xfix({xlUnsigned, xl_nbits(linearAddr), 0}, 6))\n sm_RADIO1RXBUFF_RXEN_en = true;\nelse\n sm_RADIO1RXBUFF_RXEN_en = false;\nend\nif opCode == xl_concat(xfix({xlUnsigned, 4, 0}, 10), ...\n xfix({xlUnsigned, xl_nbits(linearAddr), 0}, 7))\n sm_RADIO1TXBUFF_TXEN_en = true;\nelse\n sm_RADIO1TXBUFF_TXEN_en = false;\nend\nif opCode == xl_concat(xfix({xlUnsigned, 4, 0}, 10), ...\n xfix({xlUnsigned, xl_nbits(linearAddr), 0}, 8))\n sm_RADIO2RXBUFF_RXEN_en = true;\nelse\n sm_RADIO2RXBUFF_RXEN_en = false;\nend\nif opCode == xl_concat(xfix({xlUnsigned, 4, 0}, 10), ...\n xfix({xlUnsigned, xl_nbits(linearAddr), 0}, 9))\n sm_RADIO2TXBUFF_TXEN_en = true;\nelse\n sm_RADIO2TXBUFF_TXEN_en = false;\nend\nif opCode == xl_concat(xfix({xlUnsigned, 4, 0}, 10), ...\n xfix({xlUnsigned, xl_nbits(linearAddr), 0}, 10))\n sm_RADIO3RXBUFF_RXEN_en = true;\nelse\n sm_RADIO3RXBUFF_RXEN_en = false;\nend\nif opCode == xl_concat(xfix({xlUnsigned, 4, 0}, 10), ...\n xfix({xlUnsigned, xl_nbits(linearAddr), 0}, 11))\n sm_RADIO3TXBUFF_TXEN_en = true;\nelse\n sm_RADIO3TXBUFF_TXEN_en = false;\nend\nif opCode == xl_concat(xfix({xlUnsigned, 4, 0}, 10), ...\n xfix({xlUnsigned, xl_nbits(linearAddr), 0}, 12))\n sm_RADIO4RXBUFF_RXEN_en = true;\nelse\n sm_RADIO4RXBUFF_RXEN_en = false;\nend\nif opCode == xl_concat(xfix({xlUnsigned, 4, 0}, 10), ...\n xfix({xlUnsigned, xl_nbits(linearAddr), 0}, 13))\n sm_RADIO4TXBUFF_TXEN_en = true;\nelse\n sm_RADIO4TXBUFF_TXEN_en = false;\nend\nif opCode == xl_concat(xfix({xlUnsigned, 4, 0}, 10), ...\n xfix({xlUnsigned, xl_nbits(linearAddr), 0}, 14))\n sm_StartCapture_en = true;\nelse\n sm_StartCapture_en = false;\nend\nif opCode == xl_concat(xfix({xlUnsigned, 4, 0}, 10), ...\n xfix({xlUnsigned, xl_nbits(linearAddr), 0}, 15))\n sm_StartTx_en = true;\nelse\n sm_StartTx_en = false;\nend\nif opCode == xl_concat(xfix({xlUnsigned, 4, 0}, 10), ...\n xfix({xlUnsigned, xl_nbits(linearAddr), 0}, 16))\n sm_StopTx_en = true;\nelse\n sm_StopTx_en = false;\nend\nif opCode == xl_concat(xfix({xlUnsigned, 4, 0}, 10), ...\n xfix({xlUnsigned, xl_nbits(linearAddr), 0}, 17))\n sm_TransMode_en = true;\nelse\n sm_TransMode_en = false;\nend\nif opCode == xl_concat(xfix({xlUnsigned, 4, 0}, 10), ...\n xfix({xlUnsigned, xl_nbits(linearAddr), 0}, 18))\n sm_TxDelay_en = true;\nelse\n sm_TxDelay_en = false;\nend\nif opCode == xl_concat(xfix({xlUnsigned, 4, 0}, 10), ...\n xfix({xlUnsigned, xl_nbits(linearAddr), 0}, 19))\n sm_TxLength_en = true;\nelse\n sm_TxLength_en = false;\nend\nif opCode == xl_concat(xfix({xlUnsigned, 4, 0}, 10), ...\n xfix({xlUnsigned, xl_nbits(linearAddr), 0}, 20))\n sm_StartTxRx_en = true;\nelse\n sm_StartTxRx_en = false;\nend\n\n\n% 'din' ports of 'To FIFO' blocks\n\n\n% 'we' ports of 'To FIFO' blocks\n\n\n% 'din' ports of 'To Register' blocks\nsm_DCO_EN_SEL_din = xl_force(xl_slice(wrDBus, 1 - 1, 0), ...\n xlUnsigned, ...\n 0);\nsm_DebugRx1Buffers_din = xl_force(xl_slice(wrDBus, 1 - 1, 0), ...\n xlUnsigned, ...\n 0);\nsm_DebugRx2Buffers_din = xl_force(xl_slice(wrDBus, 1 - 1, 0), ...\n xlUnsigned, ...\n 0);\nsm_DebugRx3Buffers_din = xl_force(xl_slice(wrDBus, 1 - 1, 0), ...\n xlUnsigned, ...\n 0);\nsm_DebugRx4Buffers_din = xl_force(xl_slice(wrDBus, 1 - 1, 0), ...\n xlUnsigned, ...\n 0);\nsm_MGC_AGC_SEL_din = xl_force(xl_slice(wrDBus, 1 - 1, 0), ...\n xlUnsigned, ...\n 0);\nsm_RADIO1RXBUFF_RXEN_din = xl_force(xl_slice(wrDBus, 1 - 1, 0), ...\n xlUnsigned, ...\n 0);\nsm_RADIO1TXBUFF_TXEN_din = xl_force(xl_slice(wrDBus, 1 - 1, 0), ...\n xlUnsigned, ...\n 0);\nsm_RADIO2RXBUFF_RXEN_din = xl_force(xl_slice(wrDBus, 1 - 1, 0), ...\n xlUnsigned, ...\n 0);\nsm_RADIO2TXBUFF_TXEN_din = xl_force(xl_slice(wrDBus, 1 - 1, 0), ...\n xlUnsigned, ...\n 0);\nsm_RADIO3RXBUFF_RXEN_din = xl_force(xl_slice(wrDBus, 1 - 1, 0), ...\n xlUnsigned, ...\n 0);\nsm_RADIO3TXBUFF_TXEN_din = xl_force(xl_slice(wrDBus, 1 - 1, 0), ...\n xlUnsigned, ...\n 0);\nsm_RADIO4RXBUFF_RXEN_din = xl_force(xl_slice(wrDBus, 1 - 1, 0), ...\n xlUnsigned, ...\n 0);\nsm_RADIO4TXBUFF_TXEN_din = xl_force(xl_slice(wrDBus, 1 - 1, 0), ...\n xlUnsigned, ...\n 0);\nsm_StartCapture_din = xl_force(xl_slice(wrDBus, 1 - 1, 0), ...\n xlUnsigned, ...\n 0);\nsm_StartTx_din = xl_force(xl_slice(wrDBus, 1 - 1, 0), ...\n xlUnsigned, ...\n 0);\nsm_StopTx_din = xl_force(xl_slice(wrDBus, 1 - 1, 0), ...\n xlUnsigned, ...\n 0);\nsm_TransMode_din = xl_force(xl_slice(wrDBus, 1 - 1, 0), ...\n xlUnsigned, ...\n 0);\nsm_TxDelay_din = xl_force(xl_slice(wrDBus, 14 - 1, 0), ...\n xlUnsigned, ...\n 0);\nsm_TxLength_din = xl_force(xl_slice(wrDBus, 14 - 1, 0), ...\n xlUnsigned, ...\n 0);\nsm_StartTxRx_din = xl_force(xl_slice(wrDBus, 1 - 1, 0), ...\n xlUnsigned, ...\n 0);\n\n\npersistent read_bank_out_reg; read_bank_out_reg = xl_state(0, {xlUnsigned, 32, 0});\nread_bank_out = read_bank_out_reg;\n\npersistent bankAddr_reg; bankAddr_reg = xl_state(0, bankAddr);\n\nif bankAddr_reg == 0\n % Bank 0: Shared Memories\n read_bank_out_reg = ram_bank_out;\nelseif bankAddr_reg == 1\n % Bank 1: From/To FIFOs\n read_bank_out_reg = 0;\nelseif bankAddr_reg == 2\n % Bank 2: From/To Registers\n read_bank_out_reg = reg_bank_out;\nelseif bankAddr_reg == 3\n % Bank 3: Configuration Registers\n read_bank_out_reg = 0;\nend\n\nbankAddr_reg = bankAddr;\n" suppress_output "1" defparams "{}" hide_port_list "{}" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mcode" block_version "10.1.3" sg_icon_stat "170,392,44,79,white,blue,0,1500f9ed,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 170 170 0 ],[0 0 392 392 ],[0.77 0.82 0.91]);\npatch([40 12 52 12 40 85 97 109 157 119 83 57 97 57 83 119 157 109 97 85 40 ],[129 157 197 237 265 265 253 265 265 227 263 237 197 157 131 167 129 129 141 129 129 ],[0.98 0.96 0.92]);\nplot([0 170 170 0 0 ],[0 0 392 392 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'wrDBus');\ncolor('black');port_label('input',2,'bankAddr');\ncolor('black');port_label('input',3,'linearAddr');\ncolor('black');port_label('input',4,'RNWReg');\ncolor('black');port_label('input',5,'addrAck');\ncolor('black');port_label('input',6,'sm_AGCDoneAddr');\ncolor('black');port_label('input',7,'sm_CaptureDone');\ncolor('black');port_label('input',8,'sm_Radio1AGCDoneRSSI');\ncolor('black');port_label('input',9,'sm_Radio2AGCDoneRSSI');\ncolor('black');port_label('input',10,'sm_Radio3AGCDoneRSSI');\ncolor('black');port_label('input',11,'sm_Radio4AGCDoneRSSI');\ncolor('black');port_label('input',12,'sm_DCO_EN_SEL');\ncolor('black');port_label('input',13,'sm_DebugRx1Buffers');\ncolor('black');port_label('input',14,'sm_DebugRx2Buffers');\ncolor('black');port_label('input',15,'sm_DebugRx3Buffers');\ncolor('black');port_label('input',16,'sm_DebugRx4Buffers');\ncolor('black');port_label('input',17,'sm_MGC_AGC_SEL');\ncolor('black');port_label('input',18,'sm_RADIO1RXBUFF_RXEN');\ncolor('black');port_label('input',19,'sm_RADIO1TXBUFF_TXEN');\ncolor('black');port_label('input',20,'sm_RADIO2RXBUFF_RXEN');\ncolor('black');port_label('input',21,'sm_RADIO2TXBUFF_TXEN');\ncolor('black');port_label('input',22,'sm_RADIO3RXBUFF_RXEN');\ncolor('black');port_label('input',23,'sm_RADIO3TXBUFF_TXEN');\ncolor('black');port_label('input',24,'sm_RADIO4RXBUFF_RXEN');\ncolor('black');port_label('input',25,'sm_RADIO4TXBUFF_TXEN');\ncolor('black');port_label('input',26,'sm_StartCapture');\ncolor('black');port_label('input',27,'sm_StartTx');\ncolor('black');port_label('input',28,'sm_StopTx');\ncolor('black');port_label('input',29,'sm_TransMode');\ncolor('black');port_label('input',30,'sm_TxDelay');\ncolor('black');port_label('input',31,'sm_TxLength');\ncolor('black');port_label('input',32,'sm_StartTxRx');\ncolor('black');port_label('input',33,'sm_RxBuff_Radio1');\ncolor('black');port_label('input',34,'sm_RxBuff_Radio2');\ncolor('black');port_label('input',35,'sm_RxBuff_Radio3');\ncolor('black');port_label('input',36,'sm_RxBuff_Radio4');\ncolor('black');port_label('input',37,'sm_TxBuff_Radio1');\ncolor('black');port_label('input',38,'sm_TxBuff_Radio2');\ncolor('black');port_label('input',39,'sm_TxBuff_Radio3');\ncolor('black');port_label('input',40,'sm_TxBuff_Radio4');\ncolor('black');port_label('input',41,'sm_RSSIBuff_Radio1');\ncolor('black');port_label('input',42,'sm_RSSIBuff_Radio2');\ncolor('black');port_label('input',43,'sm_RSSIBuff_Radio3');\ncolor('black');port_label('input',44,'sm_RSSIBuff_Radio4');\ncolor('black');port_label('output',1,'read_bank_out');\ncolor('black');port_label('output',2,'sm_DCO_EN_SEL_din');\ncolor('black');port_label('output',3,'sm_DCO_EN_SEL_en');\ncolor('black');port_label('output',4,'sm_DebugRx1Buffers_din');\ncolor('black');port_label('output',5,'sm_DebugRx1Buffers_en');\ncolor('black');port_label('output',6,'sm_DebugRx2Buffers_din');\ncolor('black');port_label('output',7,'sm_DebugRx2Buffers_en');\ncolor('black');port_label('output',8,'sm_DebugRx3Buffers_din');\ncolor('black');port_label('output',9,'sm_DebugRx3Buffers_en');\ncolor('black');port_label('output',10,'sm_DebugRx4Buffers_din');\ncolor('black');port_label('output',11,'sm_DebugRx4Buffers_en');\ncolor('black');port_label('output',12,'sm_MGC_AGC_SEL_din');\ncolor('black');port_label('output',13,'sm_MGC_AGC_SEL_en');\ncolor('black');port_label('output',14,'sm_RADIO1RXBUFF_RXEN_din');\ncolor('black');port_label('output',15,'sm_RADIO1RXBUFF_RXEN_en');\ncolor('black');port_label('output',16,'sm_RADIO1TXBUFF_TXEN_din');\ncolor('black');port_label('output',17,'sm_RADIO1TXBUFF_TXEN_en');\ncolor('black');port_label('output',18,'sm_RADIO2RXBUFF_RXEN_din');\ncolor('black');port_label('output',19,'sm_RADIO2RXBUFF_RXEN_en');\ncolor('black');port_label('output',20,'sm_RADIO2TXBUFF_TXEN_din');\ncolor('black');port_label('output',21,'sm_RADIO2TXBUFF_TXEN_en');\ncolor('black');port_label('output',22,'sm_RADIO3RXBUFF_RXEN_din');\ncolor('black');port_label('output',23,'sm_RADIO3RXBUFF_RXEN_en');\ncolor('black');port_label('output',24,'sm_RADIO3TXBUFF_TXEN_din');\ncolor('black');port_label('output',25,'sm_RADIO3TXBUFF_TXEN_en');\ncolor('black');port_label('output',26,'sm_RADIO4RXBUFF_RXEN_din');\ncolor('black');port_label('output',27,'sm_RADIO4RXBUFF_RXEN_en');\ncolor('black');port_label('output',28,'sm_RADIO4TXBUFF_TXEN_din');\ncolor('black');port_label('output',29,'sm_RADIO4TXBUFF_TXEN_en');\ncolor('black');port_label('output',30,'sm_StartCapture_din');\ncolor('black');port_label('output',31,'sm_StartCapture_en');\ncolor('black');port_label('output',32,'sm_StartTx_din');\ncolor('black');port_label('output',33,'sm_StartTx_en');\ncolor('black');port_label('output',34,'sm_StopTx_din');\ncolor('black');port_label('output',35,'sm_StopTx_en');\ncolor('black');port_label('output',36,'sm_TransMode_din');\ncolor('black');port_label('output',37,'sm_TransMode_en');\ncolor('black');port_label('output',38,'sm_TxDelay_din');\ncolor('black');port_label('output',39,'sm_TxDelay_en');\ncolor('black');port_label('output',40,'sm_TxLength_din');\ncolor('black');port_label('output',41,'sm_TxLength_en');\ncolor('black');port_label('output',42,'sm_StartTxRx_din');\ncolor('black');port_label('output',43,'sm_StartTxRx_en');\ncolor('black');port_label('output',44,'sm_RxBuff_Radio1_addr');\ncolor('black');port_label('output',45,'sm_RxBuff_Radio1_din');\ncolor('black');port_label('output',46,'sm_RxBuff_Radio1_we');\ncolor('black');port_label('output',47,'sm_RxBuff_Radio2_addr');\ncolor('black');port_label('output',48,'sm_RxBuff_Radio2_din');\ncolor('black');port_label('output',49,'sm_RxBuff_Radio2_we');\ncolor('black');port_label('output',50,'sm_RxBuff_Radio3_addr');\ncolor('black');port_label('output',51,'sm_RxBuff_Radio3_din');\ncolor('black');port_label('output',52,'sm_RxBuff_Radio3_we');\ncolor('black');port_label('output',53,'sm_RxBuff_Radio4_addr');\ncolor('black');port_label('output',54,'sm_RxBuff_Radio4_din');\ncolor('black');port_label('output',55,'sm_RxBuff_Radio4_we');\ncolor('black');port_label('output',56,'sm_TxBuff_Radio1_addr');\ncolor('black');port_label('output',57,'sm_TxBuff_Radio1_din');\ncolor('black');port_label('output',58,'sm_TxBuff_Radio1_we');\ncolor('black');port_label('output',59,'sm_TxBuff_Radio2_addr');\ncolor('black');port_label('output',60,'sm_TxBuff_Radio2_din');\ncolor('black');port_label('output',61,'sm_TxBuff_Radio2_we');\ncolor('black');port_label('output',62,'sm_TxBuff_Radio3_addr');\ncolor('black');port_label('output',63,'sm_TxBuff_Radio3_din');\ncolor('black');port_label('output',64,'sm_TxBuff_Radio3_we');\ncolor('black');port_label('output',65,'sm_TxBuff_Radio4_addr');\ncolor('black');port_label('output',66,'sm_TxBuff_Radio4_din');\ncolor('black');port_label('output',67,'sm_TxBuff_Radio4_we');\ncolor('black');port_label('output',68,'sm_RSSIBuff_Radio1_addr');\ncolor('black');port_label('output',69,'sm_RSSIBuff_Radio1_din');\ncolor('black');port_label('output',70,'sm_RSSIBuff_Radio1_we');\ncolor('black');port_label('output',71,'sm_RSSIBuff_Radio2_addr');\ncolor('black');port_label('output',72,'sm_RSSIBuff_Radio2_din');\ncolor('black');port_label('output',73,'sm_RSSIBuff_Radio2_we');\ncolor('black');port_label('output',74,'sm_RSSIBuff_Radio3_addr');\ncolor('black');port_label('output',75,'sm_RSSIBuff_Radio3_din');\ncolor('black');port_label('output',76,'sm_RSSIBuff_Radio3_we');\ncolor('black');port_label('output',77,'sm_RSSIBuff_Radio4_addr');\ncolor('black');port_label('output',78,'sm_RSSIBuff_Radio4_din');\ncolor('black');port_label('output',79,'sm_RSSIBuff_Radio4_we');\ncolor('black');disp('\\bf{xlmax}','texmode','on');\nfprintf('','COMMENT: end icon text');\n" Port { PortNumber 1 Name "rdData" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 2 Name "DCO_EN_SEL_din" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 3 Name "DCO_EN_SEL_en" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 4 Name "DebugRx1Buffers_din" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 5 Name "DebugRx1Buffers_en" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 6 Name "DebugRx2Buffers_din" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 7 Name "DebugRx2Buffers_en" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 8 Name "DebugRx3Buffers_din" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 9 Name "DebugRx3Buffers_en" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 10 Name "DebugRx4Buffers_din" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 11 Name "DebugRx4Buffers_en" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 12 Name "MGC_AGC_SEL_din" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 13 Name "MGC_AGC_SEL_en" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 14 Name "RADIO1RXBUFF_RXEN_din" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 15 Name "RADIO1RXBUFF_RXEN_en" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 16 Name "RADIO1TXBUFF_TXEN_din" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 17 Name "RADIO1TXBUFF_TXEN_en" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 18 Name "RADIO2RXBUFF_RXEN_din" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 19 Name "RADIO2RXBUFF_RXEN_en" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 20 Name "RADIO2TXBUFF_TXEN_din" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 21 Name "RADIO2TXBUFF_TXEN_en" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 22 Name "RADIO3RXBUFF_RXEN_din" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 23 Name "RADIO3RXBUFF_RXEN_en" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 24 Name "RADIO3TXBUFF_TXEN_din" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 25 Name "RADIO3TXBUFF_TXEN_en" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 26 Name "RADIO4RXBUFF_RXEN_din" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 27 Name "RADIO4RXBUFF_RXEN_en" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 28 Name "RADIO4TXBUFF_TXEN_din" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 29 Name "RADIO4TXBUFF_TXEN_en" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 30 Name "StartCapture_din" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 31 Name "StartCapture_en" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 32 Name "StartTx_din" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 33 Name "StartTx_en" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 34 Name "StopTx_din" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 35 Name "StopTx_en" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 36 Name "TransMode_din" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 37 Name "TransMode_en" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 38 Name "TxDelay_din" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 39 Name "TxDelay_en" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 40 Name "TxLength_din" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 41 Name "TxLength_en" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 42 Name "StartTxRx_din" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 43 Name "StartTxRx_en" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 44 Name "RxBuff_Radio1_addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 45 Name "RxBuff_Radio1_din" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 46 Name "RxBuff_Radio1_we" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 47 Name "RxBuff_Radio2_addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 48 Name "RxBuff_Radio2_din" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 49 Name "RxBuff_Radio2_we" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 50 Name "RxBuff_Radio3_addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 51 Name "RxBuff_Radio3_din" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 52 Name "RxBuff_Radio3_we" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 53 Name "RxBuff_Radio4_addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 54 Name "RxBuff_Radio4_din" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 55 Name "RxBuff_Radio4_we" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 56 Name "TxBuff_Radio1_addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 57 Name "TxBuff_Radio1_din" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 58 Name "TxBuff_Radio1_we" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 59 Name "TxBuff_Radio2_addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 60 Name "TxBuff_Radio2_din" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 61 Name "TxBuff_Radio2_we" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 62 Name "TxBuff_Radio3_addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 63 Name "TxBuff_Radio3_din" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 64 Name "TxBuff_Radio3_we" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 65 Name "TxBuff_Radio4_addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 66 Name "TxBuff_Radio4_din" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 67 Name "TxBuff_Radio4_we" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 68 Name "RSSIBuff_Radio1_addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 69 Name "RSSIBuff_Radio1_din" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 70 Name "RSSIBuff_Radio1_we" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 71 Name "RSSIBuff_Radio2_addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 72 Name "RSSIBuff_Radio2_din" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 73 Name "RSSIBuff_Radio2_we" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 74 Name "RSSIBuff_Radio3_addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 75 Name "RSSIBuff_Radio3_din" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 76 Name "RSSIBuff_Radio3_we" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 77 Name "RSSIBuff_Radio4_addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 78 Name "RSSIBuff_Radio4_din" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 79 Name "RSSIBuff_Radio4_we" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "sg_plb_addrpref" Ports [1, 1] Position [110, 915, 175, 935] SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, double and fixed point to Xilinx fixed point type.

Hardware notes: In hardware these blocks become top level input ports." arith_type "Unsigned" n_bits "10" bin_pt "0" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "xlGetSimulinkPeriod(gcb)" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" sginterface "{'Xilinx'=>{'jtaghwcosim'=>{'non_memory_mapped_port'=>'sg_plb_addrpref'}},'iopad'=>{'constraint'=>'#'}}" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" block_version "10.1.3" sg_icon_stat "65,20,1,1,white,yellow,0,bc55d28f,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([27 24 29 24 27 32 33 34 40 36 32 29 34 29 32 36 40 34 33 32 27 ],[2 5 10 15 18 18 17 18 18 14 18 15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end icon text');\n" Port { PortNumber 1 Name "addrPref" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Line { Name "Sl_addrAck" SrcBlock "plb_decode" SrcPort 2 Points [0, 0] Branch { Labels [1, 0] Points [5, 0; 0, 1135] DstBlock "plb_memmap" DstPort 5 } Branch { Labels [0, 0] Points [30, 0; 0, -505] DstBlock "Sl_addrAck" DstPort 1 } } Line { Name "Sl_wrDAck" SrcBlock "plb_decode" SrcPort 4 Points [0, 0] Branch { Labels [1, 0] Points [30, 0; 0, -315] DstBlock "Sl_wrDAck" DstPort 1 } Branch { Labels [0, 0] Points [30, 0; 0, -30] DstBlock "Sl_wrComp" DstPort 1 } } Line { Name "RSSIBuff_Radio4_we" Labels [0, 0] SrcBlock "plb_memmap" SrcPort 79 Points [5, 0; 0, 1525] DstBlock "Shared Memory11" DstPort 3 } Line { Name "RSSIBuff_Radio4_din" Labels [0, 0] SrcBlock "plb_memmap" SrcPort 78 Points [5, 0; 0, 1500] DstBlock "Shared Memory11" DstPort 2 } Line { Name "RSSIBuff_Radio4_addr" Labels [0, 0] SrcBlock "plb_memmap" SrcPort 77 Points [5, 0; 0, 1475] DstBlock "Shared Memory11" DstPort 1 } Line { Name "RSSIBuff_Radio3_we" Labels [0, 0] SrcBlock "plb_memmap" SrcPort 76 Points [5, 0; 0, 1420] DstBlock "Shared Memory10" DstPort 3 } Line { Name "RSSIBuff_Radio3_din" Labels [0, 0] SrcBlock "plb_memmap" SrcPort 75 Points [5, 0; 0, 1395] DstBlock "Shared Memory10" DstPort 2 } Line { Name "RSSIBuff_Radio3_addr" Labels [0, 0] SrcBlock "plb_memmap" SrcPort 74 Points [5, 0; 0, 1370] DstBlock "Shared Memory10" DstPort 1 } Line { Name "RSSIBuff_Radio2_we" Labels [0, 0] SrcBlock "plb_memmap" SrcPort 73 Points [5, 0; 0, 1315] DstBlock "Shared Memory9" DstPort 3 } Line { Name "RSSIBuff_Radio2_din" Labels [0, 0] SrcBlock "plb_memmap" SrcPort 72 Points [5, 0; 0, 1290] DstBlock "Shared Memory9" DstPort 2 } Line { Name "RSSIBuff_Radio2_addr" Labels [0, 0] SrcBlock "plb_memmap" SrcPort 71 Points [5, 0; 0, 1265] DstBlock "Shared Memory9" DstPort 1 } Line { Name "RSSIBuff_Radio1_we" Labels [0, 0] SrcBlock "plb_memmap" SrcPort 70 Points [5, 0; 0, 1210] DstBlock "Shared Memory8" DstPort 3 } Line { Name "RSSIBuff_Radio1_din" Labels [0, 0] SrcBlock "plb_memmap" SrcPort 69 Points [5, 0; 0, 1185] DstBlock "Shared Memory8" DstPort 2 } Line { Name "RSSIBuff_Radio1_addr" Labels [0, 0] SrcBlock "plb_memmap" SrcPort 68 Points [5, 0; 0, 1160] DstBlock "Shared Memory8" DstPort 1 } Line { Name "TxBuff_Radio4_we" Labels [0, 0] SrcBlock "plb_memmap" SrcPort 67 Points [5, 0; 0, 1100] DstBlock "Shared Memory7" DstPort 3 } Line { Name "TxBuff_Radio4_din" Labels [0, 0] SrcBlock "plb_memmap" SrcPort 66 Points [5, 0; 0, 1075] DstBlock "Shared Memory7" DstPort 2 } Line { Name "TxBuff_Radio4_addr" Labels [0, 0] SrcBlock "plb_memmap" SrcPort 65 Points [5, 0; 0, 1050] DstBlock "Shared Memory7" DstPort 1 } Line { Name "TxBuff_Radio3_we" Labels [0, 0] SrcBlock "plb_memmap" SrcPort 64 Points [5, 0; 0, 995] DstBlock "Shared Memory6" DstPort 3 } Line { Name "TxBuff_Radio3_din" Labels [0, 0] SrcBlock "plb_memmap" SrcPort 63 Points [5, 0; 0, 970] DstBlock "Shared Memory6" DstPort 2 } Line { Name "TxBuff_Radio3_addr" Labels [0, 0] SrcBlock "plb_memmap" SrcPort 62 Points [5, 0; 0, 945] DstBlock "Shared Memory6" DstPort 1 } Line { Name "TxBuff_Radio2_we" Labels [0, 0] SrcBlock "plb_memmap" SrcPort 61 Points [5, 0; 0, 890] DstBlock "Shared Memory5" DstPort 3 } Line { Name "TxBuff_Radio2_din" Labels [0, 0] SrcBlock "plb_memmap" SrcPort 60 Points [5, 0; 0, 865] DstBlock "Shared Memory5" DstPort 2 } Line { Name "TxBuff_Radio2_addr" Labels [0, 0] SrcBlock "plb_memmap" SrcPort 59 Points [5, 0; 0, 840] DstBlock "Shared Memory5" DstPort 1 } Line { Name "TxBuff_Radio1_we" Labels [0, 0] SrcBlock "plb_memmap" SrcPort 58 Points [5, 0; 0, 785] DstBlock "Shared Memory4" DstPort 3 } Line { Name "TxBuff_Radio1_din" Labels [0, 0] SrcBlock "plb_memmap" SrcPort 57 Points [5, 0; 0, 760] DstBlock "Shared Memory4" DstPort 2 } Line { Name "TxBuff_Radio1_addr" Labels [0, 0] SrcBlock "plb_memmap" SrcPort 56 Points [5, 0; 0, 735] DstBlock "Shared Memory4" DstPort 1 } Line { Name "RxBuff_Radio4_we" Labels [0, 0] SrcBlock "plb_memmap" SrcPort 55 Points [5, 0; 0, 675] DstBlock "Shared Memory3" DstPort 3 } Line { Name "RxBuff_Radio4_din" Labels [0, 0] SrcBlock "plb_memmap" SrcPort 54 Points [5, 0; 0, 650] DstBlock "Shared Memory3" DstPort 2 } Line { Name "RxBuff_Radio4_addr" Labels [0, 0] SrcBlock "plb_memmap" SrcPort 53 Points [5, 0; 0, 625] DstBlock "Shared Memory3" DstPort 1 } Line { Name "RxBuff_Radio3_we" Labels [0, 0] SrcBlock "plb_memmap" SrcPort 52 Points [5, 0; 0, 570] DstBlock "Shared Memory2" DstPort 3 } Line { Name "RxBuff_Radio3_din" Labels [0, 0] SrcBlock "plb_memmap" SrcPort 51 Points [5, 0; 0, 545] DstBlock "Shared Memory2" DstPort 2 } Line { Name "RxBuff_Radio3_addr" Labels [0, 0] SrcBlock "plb_memmap" SrcPort 50 Points [5, 0; 0, 520] DstBlock "Shared Memory2" DstPort 1 } Line { Name "RxBuff_Radio2_we" Labels [0, 0] SrcBlock "plb_memmap" SrcPort 49 Points [5, 0; 0, 465] DstBlock "Shared Memory1" DstPort 3 } Line { Name "RxBuff_Radio2_din" Labels [0, 0] SrcBlock "plb_memmap" SrcPort 48 Points [5, 0; 0, 440] DstBlock "Shared Memory1" DstPort 2 } Line { Name "RxBuff_Radio2_addr" Labels [0, 0] SrcBlock "plb_memmap" SrcPort 47 Points [5, 0; 0, 415] DstBlock "Shared Memory1" DstPort 1 } Line { Name "RxBuff_Radio1_we" Labels [0, 0] SrcBlock "plb_memmap" SrcPort 46 Points [5, 0; 0, 355] DstBlock "Shared Memory" DstPort 3 } Line { Name "RxBuff_Radio1_din" Labels [0, 0] SrcBlock "plb_memmap" SrcPort 45 Points [5, 0; 0, 330] DstBlock "Shared Memory" DstPort 2 } Line { Name "RxBuff_Radio1_addr" Labels [0, 0] SrcBlock "plb_memmap" SrcPort 44 Points [10, 0] DstBlock "Shared Memory" DstPort 1 } Line { Name "StartTxRx_en" Labels [0, 0] SrcBlock "plb_memmap" SrcPort 43 Points [15, 0; 0, 255] DstBlock "To Register20" DstPort 2 } Line { Name "StartTxRx_din" Labels [0, 0] SrcBlock "plb_memmap" SrcPort 42 Points [15, 0; 0, 230] DstBlock "To Register20" DstPort 1 } Line { Name "TxLength_en" Labels [0, 0] SrcBlock "plb_memmap" SrcPort 41 Points [15, 0; 0, 175] DstBlock "To Register19" DstPort 2 } Line { Name "TxLength_din" Labels [0, 0] SrcBlock "plb_memmap" SrcPort 40 Points [15, 0; 0, 150] DstBlock "To Register19" DstPort 1 } Line { Name "TxDelay_en" Labels [0, 0] SrcBlock "plb_memmap" SrcPort 39 Points [15, 0; 0, 100] DstBlock "To Register18" DstPort 2 } Line { Name "TxDelay_din" Labels [0, 0] SrcBlock "plb_memmap" SrcPort 38 Points [15, 0; 0, 75] DstBlock "To Register18" DstPort 1 } Line { Name "TransMode_en" Labels [0, 0] SrcBlock "plb_memmap" SrcPort 37 Points [15, 0; 0, 25] DstBlock "To Register17" DstPort 2 } Line { Name "TransMode_din" Labels [0, 0] SrcBlock "plb_memmap" SrcPort 36 DstBlock "To Register17" DstPort 1 } Line { Name "StopTx_en" Labels [0, 0] SrcBlock "plb_memmap" SrcPort 35 Points [15, 0; 0, -55] DstBlock "To Register16" DstPort 2 } Line { Name "StopTx_din" Labels [0, 0] SrcBlock "plb_memmap" SrcPort 34 Points [15, 0; 0, -80] DstBlock "To Register16" DstPort 1 } Line { Name "StartTx_en" Labels [0, 0] SrcBlock "plb_memmap" SrcPort 33 Points [15, 0; 0, -130] DstBlock "To Register15" DstPort 2 } Line { Name "StartTx_din" Labels [0, 0] SrcBlock "plb_memmap" SrcPort 32 Points [15, 0; 0, -155] DstBlock "To Register15" DstPort 1 } Line { Name "StartCapture_en" Labels [0, 0] SrcBlock "plb_memmap" SrcPort 31 Points [15, 0; 0, -205] DstBlock "To Register14" DstPort 2 } Line { Name "StartCapture_din" Labels [0, 0] SrcBlock "plb_memmap" SrcPort 30 Points [15, 0; 0, -230] DstBlock "To Register14" DstPort 1 } Line { Name "RADIO4TXBUFF_TXEN_en" Labels [0, 0] SrcBlock "plb_memmap" SrcPort 29 Points [15, 0; 0, -285] DstBlock "To Register13" DstPort 2 } Line { Name "RADIO4TXBUFF_TXEN_din" Labels [0, 0] SrcBlock "plb_memmap" SrcPort 28 Points [15, 0; 0, -310] DstBlock "To Register13" DstPort 1 } Line { Name "RADIO4RXBUFF_RXEN_en" Labels [0, 0] SrcBlock "plb_memmap" SrcPort 27 Points [15, 0; 0, -360] DstBlock "To Register12" DstPort 2 } Line { Name "RADIO4RXBUFF_RXEN_din" Labels [0, 0] SrcBlock "plb_memmap" SrcPort 26 Points [15, 0; 0, -385] DstBlock "To Register12" DstPort 1 } Line { Name "RADIO3TXBUFF_TXEN_en" Labels [0, 0] SrcBlock "plb_memmap" SrcPort 25 Points [15, 0; 0, -435] DstBlock "To Register11" DstPort 2 } Line { Name "RADIO3TXBUFF_TXEN_din" Labels [0, 0] SrcBlock "plb_memmap" SrcPort 24 Points [15, 0; 0, -460] DstBlock "To Register11" DstPort 1 } Line { Name "RADIO3RXBUFF_RXEN_en" Labels [0, 0] SrcBlock "plb_memmap" SrcPort 23 Points [15, 0; 0, -515] DstBlock "To Register10" DstPort 2 } Line { Name "RADIO3RXBUFF_RXEN_din" Labels [0, 0] SrcBlock "plb_memmap" SrcPort 22 Points [15, 0; 0, -540] DstBlock "To Register10" DstPort 1 } Line { Name "RADIO2TXBUFF_TXEN_en" Labels [0, 0] SrcBlock "plb_memmap" SrcPort 21 Points [15, 0; 0, -590] DstBlock "To Register9" DstPort 2 } Line { Name "RADIO2TXBUFF_TXEN_din" Labels [0, 0] SrcBlock "plb_memmap" SrcPort 20 Points [15, 0; 0, -615] DstBlock "To Register9" DstPort 1 } Line { Name "RADIO2RXBUFF_RXEN_en" Labels [0, 0] SrcBlock "plb_memmap" SrcPort 19 Points [15, 0; 0, -665] DstBlock "To Register8" DstPort 2 } Line { Name "RADIO2RXBUFF_RXEN_din" Labels [0, 0] SrcBlock "plb_memmap" SrcPort 18 Points [15, 0; 0, -690] DstBlock "To Register8" DstPort 1 } Line { Name "RADIO1TXBUFF_TXEN_en" Labels [0, 0] SrcBlock "plb_memmap" SrcPort 17 Points [15, 0; 0, -745] DstBlock "To Register7" DstPort 2 } Line { Name "RADIO1TXBUFF_TXEN_din" Labels [0, 0] SrcBlock "plb_memmap" SrcPort 16 Points [15, 0; 0, -770] DstBlock "To Register7" DstPort 1 } Line { Name "RADIO1RXBUFF_RXEN_en" Labels [0, 0] SrcBlock "plb_memmap" SrcPort 15 Points [15, 0; 0, -820] DstBlock "To Register6" DstPort 2 } Line { Name "RADIO1RXBUFF_RXEN_din" Labels [0, 0] SrcBlock "plb_memmap" SrcPort 14 Points [15, 0; 0, -845] DstBlock "To Register6" DstPort 1 } Line { Name "MGC_AGC_SEL_en" Labels [0, 0] SrcBlock "plb_memmap" SrcPort 13 Points [15, 0; 0, -895] DstBlock "To Register5" DstPort 2 } Line { Name "MGC_AGC_SEL_din" Labels [0, 0] SrcBlock "plb_memmap" SrcPort 12 Points [15, 0; 0, -920] DstBlock "To Register5" DstPort 1 } Line { Name "DebugRx4Buffers_en" Labels [0, 0] SrcBlock "plb_memmap" SrcPort 11 Points [15, 0; 0, -975] DstBlock "To Register4" DstPort 2 } Line { Name "DebugRx4Buffers_din" Labels [0, 0] SrcBlock "plb_memmap" SrcPort 10 Points [15, 0; 0, -1000] DstBlock "To Register4" DstPort 1 } Line { Name "DebugRx3Buffers_en" Labels [0, 0] SrcBlock "plb_memmap" SrcPort 9 Points [15, 0; 0, -1050] DstBlock "To Register3" DstPort 2 } Line { Name "DebugRx3Buffers_din" Labels [0, 0] SrcBlock "plb_memmap" SrcPort 8 Points [15, 0; 0, -1075] DstBlock "To Register3" DstPort 1 } Line { Name "DebugRx2Buffers_en" Labels [0, 0] SrcBlock "plb_memmap" SrcPort 7 Points [15, 0; 0, -1125] DstBlock "To Register2" DstPort 2 } Line { Name "DebugRx2Buffers_din" Labels [0, 0] SrcBlock "plb_memmap" SrcPort 6 Points [15, 0; 0, -1150] DstBlock "To Register2" DstPort 1 } Line { Name "DebugRx1Buffers_en" Labels [0, 0] SrcBlock "plb_memmap" SrcPort 5 Points [15, 0; 0, -1205] DstBlock "To Register1" DstPort 2 } Line { Name "DebugRx1Buffers_din" Labels [0, 0] SrcBlock "plb_memmap" SrcPort 4 Points [15, 0; 0, -1230] DstBlock "To Register1" DstPort 1 } Line { Name "DCO_EN_SEL_en" Labels [0, 0] SrcBlock "plb_memmap" SrcPort 3 Points [15, 0; 0, -1280] DstBlock "To Register" DstPort 2 } Line { Name "DCO_EN_SEL_din" Labels [0, 0] SrcBlock "plb_memmap" SrcPort 2 Points [15, 0; 0, -1305] DstBlock "To Register" DstPort 1 } Line { Name "rdData" Labels [0, 0] SrcBlock "plb_memmap" SrcPort 1 Points [0, -675; -395, 0; 0, -95] DstBlock "plb_decode" DstPort 6 } Line { Name "RSSIBuff_Radio4_dout" Labels [0, 0] SrcBlock "Shared Memory11" SrcPort 1 Points [0, -65; -300, 0] DstBlock "plb_memmap" DstPort 44 } Line { Name "RSSIBuff_Radio3_dout" Labels [0, 0] SrcBlock "Shared Memory10" SrcPort 1 Points [0, -70; -305, 0; 0, -1395] DstBlock "plb_memmap" DstPort 43 } Line { Name "RSSIBuff_Radio2_dout" Labels [0, 0] SrcBlock "Shared Memory9" SrcPort 1 Points [0, -65; -305, 0; 0, -1285] DstBlock "plb_memmap" DstPort 42 } Line { Name "RSSIBuff_Radio1_dout" Labels [0, 0] SrcBlock "Shared Memory8" SrcPort 1 Points [0, -70; -305, 0; 0, -1165] DstBlock "plb_memmap" DstPort 41 } Line { Name "TxBuff_Radio4_dout" Labels [0, 0] SrcBlock "Shared Memory7" SrcPort 1 Points [0, -70; -305, 0; 0, -1045] DstBlock "plb_memmap" DstPort 40 } Line { Name "TxBuff_Radio3_dout" Labels [0, 0] SrcBlock "Shared Memory6" SrcPort 1 Points [0, -65; -305, 0; 0, -935] DstBlock "plb_memmap" DstPort 39 } Line { Name "TxBuff_Radio2_dout" Labels [0, 0] SrcBlock "Shared Memory5" SrcPort 1 Points [0, -65; -305, 0; 0, -820] DstBlock "plb_memmap" DstPort 38 } Line { Name "TxBuff_Radio1_dout" Labels [0, 0] SrcBlock "Shared Memory4" SrcPort 1 Points [0, -75; -305, 0; 0, -695] DstBlock "plb_memmap" DstPort 37 } Line { Name "RxBuff_Radio4_dout" Labels [0, 0] SrcBlock "Shared Memory3" SrcPort 1 Points [0, -65; -305, 0; 0, -585] DstBlock "plb_memmap" DstPort 36 } Line { Name "RxBuff_Radio3_dout" Labels [0, 0] SrcBlock "Shared Memory2" SrcPort 1 Points [0, -65; -305, 0; 0, -470] DstBlock "plb_memmap" DstPort 35 } Line { Name "RxBuff_Radio2_dout" Labels [0, 0] SrcBlock "Shared Memory1" SrcPort 1 Points [0, -75; -305, 0; 0, -345] DstBlock "plb_memmap" DstPort 34 } Line { Name "RxBuff_Radio1_dout" Labels [0, 0] SrcBlock "Shared Memory" SrcPort 1 Points [0, -150; -305, 0; 0, -150] DstBlock "plb_memmap" DstPort 33 } Line { Name "StartTxRx_dout" Labels [0, 0] SrcBlock "To Register20" SrcPort 1 Points [0, -50; -295, 0; 0, -155] DstBlock "plb_memmap" DstPort 32 } Line { Name "TxLength_dout" Labels [0, 0] SrcBlock "To Register19" SrcPort 1 Points [0, 40; -295, 0; 0, -160] DstBlock "plb_memmap" DstPort 31 } Line { Name "TxDelay_dout" Labels [0, 0] SrcBlock "To Register18" SrcPort 1 Points [0, 50; -95, 0; 0, 75; -200, 0; 0, -165] DstBlock "plb_memmap" DstPort 30 } Line { Name "TransMode_dout" Labels [0, 0] SrcBlock "To Register17" SrcPort 1 Points [0, 50; -95, 0; 0, 160; -200, 0; 0, -170] DstBlock "plb_memmap" DstPort 29 } Line { Name "StopTx_dout" Labels [0, 0] SrcBlock "To Register16" SrcPort 1 Points [0, -50; -95, 0; 0, -55; -200, 0; 0, 230] DstBlock "plb_memmap" DstPort 28 } Line { Name "StartTx_dout" Labels [0, 0] SrcBlock "To Register15" SrcPort 1 Points [0, -35; -295, 0; 0, 240] DstBlock "plb_memmap" DstPort 27 } Line { Name "StartCapture_dout" Labels [0, 0] SrcBlock "To Register14" SrcPort 1 Points [0, 50; -295, 0; 0, 235] DstBlock "plb_memmap" DstPort 26 } Line { Name "RADIO4TXBUFF_TXEN_dout" Labels [0, 0] SrcBlock "To Register13" SrcPort 1 Points [0, 55; -295, 0; 0, 315] DstBlock "plb_memmap" DstPort 25 } Line { Name "RADIO4RXBUFF_RXEN_dout" Labels [0, 0] SrcBlock "To Register12" SrcPort 1 Points [0, 50; -295, 0; 0, 400] DstBlock "plb_memmap" DstPort 24 } Line { Name "RADIO3TXBUFF_TXEN_dout" Labels [0, 0] SrcBlock "To Register11" SrcPort 1 Points [0, 50; -295, 0; 0, 480] DstBlock "plb_memmap" DstPort 23 } Line { Name "RADIO3RXBUFF_RXEN_dout" Labels [0, 0] SrcBlock "To Register10" SrcPort 1 Points [0, 55; -295, 0; 0, 560] DstBlock "plb_memmap" DstPort 22 } Line { Name "RADIO2TXBUFF_TXEN_dout" Labels [0, 0] SrcBlock "To Register9" SrcPort 1 Points [0, 50; -295, 0; 0, 645] DstBlock "plb_memmap" DstPort 21 } Line { Name "RADIO2RXBUFF_RXEN_dout" Labels [0, 0] SrcBlock "To Register8" SrcPort 1 Points [0, 50; -295, 0; 0, 725] DstBlock "plb_memmap" DstPort 20 } Line { Name "RADIO1TXBUFF_TXEN_dout" Labels [0, 0] SrcBlock "To Register7" SrcPort 1 Points [0, 55; -295, 0; 0, 805] DstBlock "plb_memmap" DstPort 19 } Line { Name "RADIO1RXBUFF_RXEN_dout" Labels [0, 0] SrcBlock "To Register6" SrcPort 1 Points [0, 50; -295, 0; 0, 890] DstBlock "plb_memmap" DstPort 18 } Line { Name "MGC_AGC_SEL_dout" Labels [0, 0] SrcBlock "To Register5" SrcPort 1 Points [0, 50; -150, 0; 0, 795; -145, 0; 0, 175] DstBlock "plb_memmap" DstPort 17 } Line { Name "DebugRx4Buffers_dout" Labels [0, 0] SrcBlock "To Register4" SrcPort 1 Points [0, 55; -150, 0; 0, 880; -145, 0; 0, 170] DstBlock "plb_memmap" DstPort 16 } Line { Name "DebugRx3Buffers_dout" Labels [0, 0] SrcBlock "To Register3" SrcPort 1 Points [0, 50; -150, 0; 0, 970; -145, 0; 0, 165] DstBlock "plb_memmap" DstPort 15 } Line { Name "DebugRx2Buffers_dout" Labels [0, 0] SrcBlock "To Register2" SrcPort 1 Points [0, 50; -295, 0; 0, 1215] DstBlock "plb_memmap" DstPort 14 } Line { Name "DebugRx1Buffers_dout" Labels [0, 0] SrcBlock "To Register1" SrcPort 1 Points [0, 55; -295, 0; 0, 1295] DstBlock "plb_memmap" DstPort 13 } Line { Name "DCO_EN_SEL_dout" Labels [0, 0] SrcBlock "To Register" SrcPort 1 Points [0, 50; -295, 0; 0, 1380] DstBlock "plb_memmap" DstPort 12 } Line { Name "Radio4AGCDoneRSSI_dout" Labels [0, 0] SrcBlock "From Register5" SrcPort 1 Points [60, 0; 0, -145] DstBlock "plb_memmap" DstPort 11 } Line { Name "Radio3AGCDoneRSSI_dout" Labels [0, 0] SrcBlock "From Register4" SrcPort 1 Points [60, 0; 0, -65] DstBlock "plb_memmap" DstPort 10 } Line { Name "Radio2AGCDoneRSSI_dout" Labels [0, 0] SrcBlock "From Register3" SrcPort 1 Points [60, 0; 0, 15] DstBlock "plb_memmap" DstPort 9 } Line { Name "Radio1AGCDoneRSSI_dout" Labels [0, 0] SrcBlock "From Register2" SrcPort 1 Points [60, 0; 0, 100] DstBlock "plb_memmap" DstPort 8 } Line { Name "CaptureDone_dout" Labels [0, 0] SrcBlock "From Register1" SrcPort 1 Points [60, 0; 0, 180] DstBlock "plb_memmap" DstPort 7 } Line { Name "AGCDoneAddr_dout" Labels [0, 0] SrcBlock "From Register" SrcPort 1 Points [60, 0; 0, 260] DstBlock "plb_memmap" DstPort 6 } Line { Name "RNWReg" Labels [0, 0] SrcBlock "plb_decode" SrcPort 6 Points [5, 0; 0, 950] DstBlock "plb_memmap" DstPort 4 } Line { Name "linearAddr" Labels [0, 0] SrcBlock "plb_decode" SrcPort 9 Points [5, 0; 0, 810] DstBlock "plb_memmap" DstPort 3 } Line { Name "bankAddr" Labels [0, 0] SrcBlock "plb_decode" SrcPort 5 Points [5, 0; 0, 985] DstBlock "plb_memmap" DstPort 2 } Line { Name "wrDBusReg" Labels [0, 0] SrcBlock "plb_decode" SrcPort 1 Points [10, 0] DstBlock "plb_memmap" DstPort 1 } Line { Name "Sl_rdDBus" Labels [0, 0] SrcBlock "plb_decode" SrcPort 8 Points [65, 0] DstBlock "Sl_rdDBus" DstPort 1 } Line { Name "Sl_rdDAck" Labels [0, 0] SrcBlock "plb_decode" SrcPort 7 Points [65, 0] DstBlock "Sl_rdDAck" DstPort 1 } Line { Name "Sl_rdComp" Labels [0, 0] SrcBlock "plb_decode" SrcPort 3 Points [60, 0; 0, -440] DstBlock "Sl_rdComp" DstPort 1 } Line { Name "addrPref" Labels [0, 0] SrcBlock "sg_plb_addrpref" SrcPort 1 Points [10, 0] DstBlock "plb_decode" DstPort 7 } Line { Name "PLB_wrDBus" Labels [0, 0] SrcBlock "PLB_wrDBus" SrcPort 1 DstBlock "plb_decode" DstPort 5 } Line { Name "PLB_RNW" Labels [0, 0] SrcBlock "PLB_RNW" SrcPort 1 DstBlock "plb_decode" DstPort 4 } Line { Name "PLB_PAValid" Labels [0, 0] SrcBlock "PLB_PAValid" SrcPort 1 DstBlock "plb_decode" DstPort 3 } Line { Name "PLB_ABus" Labels [0, 0] SrcBlock "PLB_ABus" SrcPort 1 Points [5, 0; 0, -5] DstBlock "plb_decode" DstPort 2 } Line { Name "SPLB_Rst" Labels [0, 0] SrcBlock "SPLB_Rst" SrcPort 1 Points [5, 0; 0, -5] DstBlock "plb_decode" DstPort 1 } Line { SrcBlock "Constant6" SrcPort 1 DstBlock "sg_plb_addrpref" DstPort 1 } Line { Name "Sl_wait" Labels [0, 0] SrcBlock "Constant5" SrcPort 1 DstBlock "Sl_wait" DstPort 1 } Line { SrcBlock "Constant4" SrcPort 1 DstBlock "PLB_wrDBus" DstPort 1 } Line { SrcBlock "Constant3" SrcPort 1 DstBlock "PLB_RNW" DstPort 1 } Line { SrcBlock "Constant2" SrcPort 1 DstBlock "PLB_PAValid" DstPort 1 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "PLB_ABus" DstPort 1 } Line { SrcBlock "Constant" SrcPort 1 DstBlock "SPLB_Rst" DstPort 1 } Line { SrcBlock "Sl_wrComp" SrcPort 1 Points [70, 0; 0, -485] DstBlock "Terminator6" DstPort 1 } Line { SrcBlock "Sl_wrDAck" SrcPort 1 Points [70, 0; 0, -250] DstBlock "Terminator5" DstPort 1 } Line { SrcBlock "Sl_wait" SrcPort 1 DstBlock "Terminator4" DstPort 1 } Line { SrcBlock "Sl_rdDBus" SrcPort 1 Points [70, 0; 0, -565] DstBlock "Terminator3" DstPort 1 } Line { SrcBlock "Sl_rdDAck" SrcPort 1 Points [70, 0; 0, -530] DstBlock "Terminator2" DstPort 1 } Line { SrcBlock "Sl_rdComp" SrcPort 1 Points [90, 0; 0, -130] DstBlock "Terminator1" DstPort 1 } Line { SrcBlock "Sl_addrAck" SrcPort 1 Points [45, 0; 0, -70] DstBlock "Terminator" DstPort 1 } } } Block { BlockType From Name "From1" Position [115, 766, 250, 784] ShowName off CloseFcn "tagdialog Close" GotoTag "StopTx" TagVisibility "global" } Block { BlockType From Name "From10" Position [940, 121, 1075, 139] ShowName off CloseFcn "tagdialog Close" GotoTag "RADIO1RXBUFF_RXEN" TagVisibility "global" } Block { BlockType From Name "From11" Position [945, 266, 1080, 284] ShowName off CloseFcn "tagdialog Close" GotoTag "RADIO2RXBUFF_RXEN" TagVisibility "global" } Block { BlockType From Name "From12" Position [945, 406, 1080, 424] ShowName off CloseFcn "tagdialog Close" GotoTag "RADIO3RXBUFF_RXEN" TagVisibility "global" } Block { BlockType From Name "From13" Position [945, 546, 1080, 564] ShowName off CloseFcn "tagdialog Close" GotoTag "RADIO4RXBUFF_RXEN" TagVisibility "global" } Block { BlockType From Name "From14" Position [710, 36, 845, 54] ShowName off CloseFcn "tagdialog Close" GotoTag "DebugRx1Buffers" TagVisibility "global" } Block { BlockType From Name "From15" Position [715, 181, 850, 199] ShowName off CloseFcn "tagdialog Close" GotoTag "DebugRx2Buffers" TagVisibility "global" } Block { BlockType From Name "From16" Position [715, 316, 850, 334] ShowName off CloseFcn "tagdialog Close" GotoTag "DebugRx3Buffers" TagVisibility "global" } Block { BlockType From Name "From17" Position [710, 456, 845, 474] ShowName off CloseFcn "tagdialog Close" GotoTag "DebugRx4Buffers" TagVisibility "global" } Block { BlockType From Name "From18" Position [705, 549, 855, 571] ShowName off CloseFcn "tagdialog Close" GotoTag "MGCAGC_AGCDCO_SEL" TagVisibility "global" } Block { BlockType From Name "From19" Position [40, 466, 175, 484] ShowName off CloseFcn "tagdialog Close" GotoTag "StartTxRx" TagVisibility "global" } Block { BlockType From Name "From2" Position [275, 821, 410, 839] ShowName off CloseFcn "tagdialog Close" GotoTag "TransMode" TagVisibility "global" } Block { BlockType From Name "From3" Position [110, 671, 245, 689] ShowName off CloseFcn "tagdialog Close" GotoTag "StartTx" TagVisibility "global" } Block { BlockType From Name "From4" Position [270, 896, 405, 914] ShowName off CloseFcn "tagdialog Close" GotoTag "TxDelay" TagVisibility "global" } Block { BlockType From Name "From5" Position [860, 701, 995, 719] ShowName off CloseFcn "tagdialog Close" GotoTag "RADIO1TXBUFF_TXEN" TagVisibility "global" } Block { BlockType From Name "From6" Position [860, 796, 995, 814] ShowName off CloseFcn "tagdialog Close" GotoTag "RADIO2TXBUFF_TXEN" TagVisibility "global" } Block { BlockType From Name "From7" Position [860, 891, 995, 909] ShowName off CloseFcn "tagdialog Close" GotoTag "RADIO3TXBUFF_TXEN" TagVisibility "global" } Block { BlockType From Name "From8" Position [860, 991, 995, 1009] ShowName off CloseFcn "tagdialog Close" GotoTag "RADIO4TXBUFF_TXEN" TagVisibility "global" } Block { BlockType From Name "From9" Position [80, 236, 215, 254] ShowName off CloseFcn "tagdialog Close" GotoTag "StartCapture" TagVisibility "global" } Block { BlockType Goto Name "Goto1" Position [555, 129, 660, 151] ShowName off GotoTag "WR_ADDR" TagVisibility "global" } Block { BlockType Goto Name "Goto2" Position [1270, 17, 1430, 43] ShowName off GotoTag "Radio1_RSSI" TagVisibility "global" } Block { BlockType Goto Name "Goto3" Position [495, 1007, 655, 1033] ShowName off GotoTag "AGC_Done_Detect" TagVisibility "global" } Block { BlockType Goto Name "Goto4" Position [1275, 162, 1435, 188] ShowName off GotoTag "Radio2_RSSI" TagVisibility "global" } Block { BlockType Goto Name "Goto5" Position [1275, 297, 1435, 323] ShowName off GotoTag "Radio3_RSSI" TagVisibility "global" } Block { BlockType Goto Name "Goto6" Position [1275, 437, 1435, 463] ShowName off GotoTag "Radio4_RSSI" TagVisibility "global" } Block { BlockType Reference Name "Inverter" Ports [1, 1] Position [770, 691, 795, 709] ShowName off SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "8.2" sg_icon_stat "25,18,1,1,white,blue,0,1ab4a85f,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 58 58 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[7 16 29 42 51 51 47 51 51 39 51 42 29 16 7 19 7 7 11 7 7 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Logical" Ports [3, 1] Position [235, 205, 275, 285] ShowName off SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "3" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,261" block_type "logical" block_version "8.2" sg_icon_stat "40,80,1,1,white,blue,0,bd50cad4,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[8 17 30 43 52 52 48 52 52 40 52 43 30 17 8 20 8 8 12 8 8 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newlineor\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType SubSystem Name "Memmory-mapped Registers" Ports [] Position [270, 25, 310, 85] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Memmory-mapped Registers" Location [280, 119, 1540, 841] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Reference Name "AGCDoneAddr" Ports [2, 1] Position [975, 17, 1035, 73] AttributesFormatString "<< % >>" SourceBlock "xbsIndex_r4/To Register" SourceType "Xilinx Shared Memory Based To Register Block" infoedit "Register block that writes data to a shared memory register. Delay of one sample period." shared_memory_name "'AGCDoneAddr'" init "0" ownership "Locally owned and initialized" explicit_data_type on arith_type "Unsigned" n_bits "14" bin_pt "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,381,266" block_type "toreg" block_version "10.1.3" sg_icon_stat "60,56,1,1,white,blue,0,77cabcdf,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Convert1" Ports [1, 1] Position [870, 512, 895, 528] ShowName off SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." arith_type "Boolean" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,461,375" block_type "convert" block_version "8.2" sg_icon_stat "25,16,1,1,white,blue,0,74901e60,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([15 10 17 10 15 23 25 27 35 28 22 17 23 17 22 28 35 27 25 23 15 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'cast');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Convert2" Ports [1, 1] Position [870, 582, 895, 598] ShowName off SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." arith_type "Boolean" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,461,375" block_type "convert" block_version "8.2" sg_icon_stat "25,16,1,1,white,blue,0,74901e60,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([15 10 17 10 15 23 25 27 35 28 22 17 23 17 22 28 35 27 25 23 15 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'cast');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Convert3" Ports [1, 1] Position [1035, 527, 1060, 543] ShowName off SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." arith_type "Unsigned" n_bits "1" bin_pt "0" quantization "Truncate" overflow "Wrap" latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,461,375" block_type "convert" block_version "8.2" sg_icon_stat "25,16,1,1,white,blue,0,74901e60,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([15 10 17 10 15 23 25 27 35 28 22 17 23 17 22 28 35 27 25 23 15 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'cast');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "DebugRx1Buffers" Ports [0, 1] Position [450, 430, 495, 460] AttributesFormatString "<< % >>" SourceBlock "xbsIndex_r4/From Register" SourceType "Xilinx Shared Memory Based From Register Block" infoedit "Register block that reads data to a shared memory register. Delay of one sample period." shared_memory_name "'DebugRx1Buffers'" init "0" period "1" ownership "Locally owned and initialized" arith_type "Unsigned" n_bits "1" bin_pt "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,381,234" block_type "fromreg" block_version "10.1.2" sg_icon_stat "45,30,1,1,white,blue,0,4b212927,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "DebugRx2Buffers" Ports [0, 1] Position [450, 510, 495, 540] AttributesFormatString "<< % >>" SourceBlock "xbsIndex_r4/From Register" SourceType "Xilinx Shared Memory Based From Register Block" infoedit "Register block that reads data to a shared memory register. Delay of one sample period." shared_memory_name "'DebugRx2Buffers'" init "0" period "1" ownership "Locally owned and initialized" arith_type "Unsigned" n_bits "1" bin_pt "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,381,234" block_type "fromreg" block_version "10.1.2" sg_icon_stat "45,30,1,1,white,blue,0,4b212927,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "DebugRx3Buffers" Ports [0, 1] Position [450, 595, 495, 625] AttributesFormatString "<< % >>" SourceBlock "xbsIndex_r4/From Register" SourceType "Xilinx Shared Memory Based From Register Block" infoedit "Register block that reads data to a shared memory register. Delay of one sample period." shared_memory_name "'DebugRx3Buffers'" init "0" period "1" ownership "Locally owned and initialized" arith_type "Unsigned" n_bits "1" bin_pt "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,381,234" block_type "fromreg" block_version "10.1.2" sg_icon_stat "45,30,1,1,white,blue,0,4b212927,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "DebugRx4Buffers" Ports [0, 1] Position [450, 695, 495, 725] AttributesFormatString "<< % >>" SourceBlock "xbsIndex_r4/From Register" SourceType "Xilinx Shared Memory Based From Register Block" infoedit "Register block that reads data to a shared memory register. Delay of one sample period." shared_memory_name "'DebugRx4Buffers'" init "0" period "1" ownership "Locally owned and initialized" arith_type "Unsigned" n_bits "1" bin_pt "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,381,234" block_type "fromreg" block_version "10.1.2" sg_icon_stat "45,30,1,1,white,blue,0,4b212927,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "From Register1" Ports [0, 1] Position [450, 100, 495, 130] ShowName off AttributesFormatString "RADIO1RXBUFF_RXEN\\n<< % >>" SourceBlock "xbsIndex_r4/From Register" SourceType "Xilinx Shared Memory Based From Register Block" infoedit "Register block that reads data to a shared memory register. Delay of one sample period." shared_memory_name "'RADIO1RXBUFF_RXEN'" init "0" period "1" ownership "Locally owned and initialized" arith_type "Unsigned" n_bits "1" bin_pt "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,381,246" block_type "fromreg" block_version "8.2" sg_icon_stat "45,30,1,1,white,blue,0,4b212927,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "From Register10" Ports [0, 1] Position [55, 590, 100, 620] ShowName off AttributesFormatString "RADIO3TXBUFF_TXEN\\n<< % >>" SourceBlock "xbsIndex_r4/From Register" SourceType "Xilinx Shared Memory Based From Register Block" infoedit "Register block that reads data to a shared memory register. Delay of one sample period." shared_memory_name "'RADIO3TXBUFF_TXEN'" init "0" period "1" ownership "Locally owned and initialized" arith_type "Unsigned" n_bits "1" bin_pt "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,379,246" block_type "fromreg" block_version "8.2" sg_icon_stat "45,30,1,1,white,blue,0,4b212927,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "From Register11" Ports [0, 1] Position [450, 265, 495, 295] ShowName off AttributesFormatString "RADIO3RXBUFF_RXEN\\n<< % >>" SourceBlock "xbsIndex_r4/From Register" SourceType "Xilinx Shared Memory Based From Register Block" infoedit "Register block that reads data to a shared memory register. Delay of one sample period." shared_memory_name "'RADIO3RXBUFF_RXEN'" init "0" period "1" ownership "Locally owned and initialized" arith_type "Unsigned" n_bits "1" bin_pt "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,381,246" block_type "fromreg" block_version "8.2" sg_icon_stat "45,30,1,1,white,blue,0,4b212927,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "From Register12" Ports [0, 1] Position [55, 670, 100, 700] ShowName off AttributesFormatString "RADIO4TXBUFF_TXEN\\n<< % >>" SourceBlock "xbsIndex_r4/From Register" SourceType "Xilinx Shared Memory Based From Register Block" infoedit "Register block that reads data to a shared memory register. Delay of one sample period." shared_memory_name "'RADIO4TXBUFF_TXEN'" init "0" period "1" ownership "Locally owned and initialized" arith_type "Unsigned" n_bits "1" bin_pt "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,381,246" block_type "fromreg" block_version "8.2" sg_icon_stat "45,30,1,1,white,blue,0,4b212927,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "From Register13" Ports [0, 1] Position [770, 505, 815, 535] ShowName off AttributesFormatString "MGC_AGC_SEL\\n<< % >>" SourceBlock "xbsIndex_r4/From Register" SourceType "Xilinx Shared Memory Based From Register Block" infoedit "Register block that reads data to a shared memory register. Delay of one sample period." shared_memory_name "'MGC_AGC_SEL'" init "1" period "1" ownership "Locally owned and initialized" arith_type "Unsigned" n_bits "1" bin_pt "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,447,246" block_type "fromreg" block_version "8.2" sg_icon_stat "45,30,1,1,white,blue,0,4b212927,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "From Register14" Ports [0, 1] Position [770, 575, 815, 605] ShowName off AttributesFormatString "DCO_EN_SEL\\n<< % >>" SourceBlock "xbsIndex_r4/From Register" SourceType "Xilinx Shared Memory Based From Register Block" infoedit "Register block that reads data to a shared memory register. Delay of one sample period." shared_memory_name "'DCO_EN_SEL'" init "1" period "1" ownership "Locally owned and initialized" arith_type "Unsigned" n_bits "1" bin_pt "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,447,246" block_type "fromreg" block_version "8.2" sg_icon_stat "45,30,1,1,white,blue,0,4b212927,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "From Register15" Ports [0, 1] Position [55, 185, 100, 215] ShowName off AttributesFormatString "StartTxRx\\n<< % >>" SourceBlock "xbsIndex_r4/From Register" SourceType "Xilinx Shared Memory Based From Register Block" infoedit "Register block that reads data to a shared memory register. Delay of one sample period." shared_memory_name "'StartTxRx'" init "0" period "1" ownership "Locally owned and initialized" arith_type "Unsigned" n_bits "1" bin_pt "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,381,246" block_type "fromreg" block_version "8.2" sg_icon_stat "45,30,1,1,white,blue,0,4b212927,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "From Register2" Ports [0, 1] Position [450, 15, 495, 45] ShowName off AttributesFormatString "StartCapture\\n<< % >>" SourceBlock "xbsIndex_r4/From Register" SourceType "Xilinx Shared Memory Based From Register Block" infoedit "Register block that reads data to a shared memory register. Delay of one sample period." shared_memory_name "'StartCapture'" init "0" period "1" ownership "Locally owned and initialized" arith_type "Unsigned" n_bits "1" bin_pt "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,447,246" block_type "fromreg" block_version "8.2" sg_icon_stat "45,30,1,1,white,blue,0,4b212927,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "From Register3" Ports [0, 1] Position [450, 345, 495, 375] ShowName off AttributesFormatString "RADIO4RXBUFF_RXEN\\n<< % >>" SourceBlock "xbsIndex_r4/From Register" SourceType "Xilinx Shared Memory Based From Register Block" infoedit "Register block that reads data to a shared memory register. Delay of one sample period." shared_memory_name "'RADIO4RXBUFF_RXEN'" init "0" period "1" ownership "Locally owned and initialized" arith_type "Unsigned" n_bits "1" bin_pt "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,381,246" block_type "fromreg" block_version "8.2" sg_icon_stat "45,30,1,1,white,blue,0,4b212927,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "From Register4" Ports [0, 1] Position [55, 25, 100, 55] ShowName off AttributesFormatString "StartTx\\n<< % >>" SourceBlock "xbsIndex_r4/From Register" SourceType "Xilinx Shared Memory Based From Register Block" infoedit "Register block that reads data to a shared memory register. Delay of one sample period." shared_memory_name "'StartTx'" init "0" period "1" ownership "Locally owned and initialized" arith_type "Unsigned" n_bits "1" bin_pt "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,379,246" block_type "fromreg" block_version "8.2" sg_icon_stat "45,30,1,1,white,blue,0,4b212927,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "From Register5" Ports [0, 1] Position [450, 185, 495, 215] ShowName off AttributesFormatString "RADIO2RXBUFF_RXEN\\n<< % >>" SourceBlock "xbsIndex_r4/From Register" SourceType "Xilinx Shared Memory Based From Register Block" infoedit "Register block that reads data to a shared memory register. Delay of one sample period." shared_memory_name "'RADIO2RXBUFF_RXEN'" init "0" period "1" ownership "Locally owned and initialized" arith_type "Unsigned" n_bits "1" bin_pt "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,381,246" block_type "fromreg" block_version "8.2" sg_icon_stat "45,30,1,1,white,blue,0,4b212927,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "From Register6" Ports [0, 1] Position [55, 430, 100, 460] ShowName off AttributesFormatString "RADIO1TXBUFF_TXEN\\n<< % >>" SourceBlock "xbsIndex_r4/From Register" SourceType "Xilinx Shared Memory Based From Register Block" infoedit "Register block that reads data to a shared memory register. Delay of one sample period." shared_memory_name "'RADIO1TXBUFF_TXEN'" init "0" period "1" ownership "Locally owned and initialized" arith_type "Unsigned" n_bits "1" bin_pt "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,381,246" block_type "fromreg" block_version "8.2" sg_icon_stat "45,30,1,1,white,blue,0,4b212927,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "From Register7" Ports [0, 1] Position [55, 105, 100, 135] ShowName off AttributesFormatString "StopTx\\n<< % >>" SourceBlock "xbsIndex_r4/From Register" SourceType "Xilinx Shared Memory Based From Register Block" infoedit "Register block that reads data to a shared memory register. Delay of one sample period." shared_memory_name "'StopTx'" init "0" period "1" ownership "Locally owned and initialized" arith_type "Unsigned" n_bits "1" bin_pt "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,381,246" block_type "fromreg" block_version "8.2" sg_icon_stat "45,30,1,1,white,blue,0,4b212927,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "From Register8" Ports [0, 1] Position [55, 265, 100, 295] ShowName off AttributesFormatString "TransMode\\n<< % >>" SourceBlock "xbsIndex_r4/From Register" SourceType "Xilinx Shared Memory Based From Register Block" infoedit "Register block that reads data to a shared memory register. Delay of one sample period." shared_memory_name "'TransMode'" init "0" period "1" ownership "Locally owned and initialized" arith_type "Unsigned" n_bits "1" bin_pt "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,381,246" block_type "fromreg" block_version "8.2" sg_icon_stat "45,30,1,1,white,blue,0,4b212927,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "From Register9" Ports [0, 1] Position [55, 510, 100, 540] ShowName off AttributesFormatString "RADIO2TXBUFF_TXEN\\n<< % >>" SourceBlock "xbsIndex_r4/From Register" SourceType "Xilinx Shared Memory Based From Register Block" infoedit "Register block that reads data to a shared memory register. Delay of one sample period." shared_memory_name "'RADIO2TXBUFF_TXEN'" init "0" period "1" ownership "Locally owned and initialized" arith_type "Unsigned" n_bits "1" bin_pt "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,379,246" block_type "fromreg" block_version "8.2" sg_icon_stat "45,30,1,1,white,blue,0,4b212927,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType From Name "From1" Position [770, 21, 905, 39] ShowName off CloseFcn "tagdialog Close" GotoTag "WR_ADDR" TagVisibility "global" } Block { BlockType From Name "From10" Position [765, 116, 900, 134] ShowName off CloseFcn "tagdialog Close" GotoTag "Radio1_RSSI" TagVisibility "global" } Block { BlockType From Name "From2" Position [770, 51, 905, 69] ShowName off CloseFcn "tagdialog Close" GotoTag "AGC_Done_Detect" TagVisibility "global" } Block { BlockType From Name "From3" Position [765, 676, 900, 694] ShowName off CloseFcn "tagdialog Close" GotoTag "CAPTURE_IS_DONE" TagVisibility "global" } Block { BlockType From Name "From4" Position [765, 206, 900, 224] ShowName off CloseFcn "tagdialog Close" GotoTag "Radio2_RSSI" TagVisibility "global" } Block { BlockType From Name "From6" Position [765, 296, 900, 314] ShowName off CloseFcn "tagdialog Close" GotoTag "Radio3_RSSI" TagVisibility "global" } Block { BlockType From Name "From8" Position [770, 401, 905, 419] ShowName off CloseFcn "tagdialog Close" GotoTag "Radio4_RSSI" TagVisibility "global" } Block { BlockType Goto Name "Goto1" Position [175, 107, 335, 133] ShowName off GotoTag "StopTx" TagVisibility "global" } Block { BlockType Goto Name "Goto10" Position [175, 27, 335, 53] ShowName off GotoTag "StartTx" TagVisibility "global" } Block { BlockType Goto Name "Goto11" Position [575, 187, 735, 213] ShowName off GotoTag "RADIO2RXBUFF_RXEN" TagVisibility "global" } Block { BlockType Goto Name "Goto12" Position [575, 267, 735, 293] ShowName off GotoTag "RADIO3RXBUFF_RXEN" TagVisibility "global" } Block { BlockType Goto Name "Goto13" Position [575, 347, 735, 373] ShowName off GotoTag "RADIO4RXBUFF_RXEN" TagVisibility "global" } Block { BlockType Goto Name "Goto14" Position [575, 432, 735, 458] ShowName off GotoTag "DebugRx1Buffers" TagVisibility "global" } Block { BlockType Goto Name "Goto15" Position [575, 512, 735, 538] ShowName off GotoTag "DebugRx2Buffers" TagVisibility "global" } Block { BlockType Goto Name "Goto16" Position [575, 597, 735, 623] ShowName off GotoTag "DebugRx3Buffers" TagVisibility "global" } Block { BlockType Goto Name "Goto17" Position [575, 697, 735, 723] ShowName off GotoTag "DebugRx4Buffers" TagVisibility "global" } Block { BlockType Goto Name "Goto18" Position [1090, 522, 1250, 548] ShowName off GotoTag "MGCAGC_AGCDCO_SEL" TagVisibility "global" } Block { BlockType Goto Name "Goto19" Position [175, 187, 335, 213] ShowName off GotoTag "StartTxRx" TagVisibility "global" } Block { BlockType Goto Name "Goto2" Position [175, 347, 335, 373] ShowName off GotoTag "TxDelay" TagVisibility "global" } Block { BlockType Goto Name "Goto3" Position [175, 267, 335, 293] ShowName off GotoTag "TransMode" TagVisibility "global" } Block { BlockType Goto Name "Goto4" Position [175, 432, 335, 458] ShowName off GotoTag "RADIO1TXBUFF_TXEN" TagVisibility "global" } Block { BlockType Goto Name "Goto5" Position [175, 512, 335, 538] ShowName off GotoTag "RADIO2TXBUFF_TXEN" TagVisibility "global" } Block { BlockType Goto Name "Goto6" Position [175, 592, 335, 618] ShowName off GotoTag "RADIO3TXBUFF_TXEN" TagVisibility "global" } Block { BlockType Goto Name "Goto7" Position [175, 672, 335, 698] ShowName off GotoTag "RADIO4TXBUFF_TXEN" TagVisibility "global" } Block { BlockType Goto Name "Goto8" Position [575, 17, 735, 43] ShowName off GotoTag "StartCapture" TagVisibility "global" } Block { BlockType Goto Name "Goto9" Position [575, 102, 735, 128] ShowName off GotoTag "RADIO1RXBUFF_RXEN" TagVisibility "global" } Block { BlockType Reference Name "Logical" Ports [2, 1] Position [945, 505, 1000, 565] SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,261" block_type "logical" block_version "10.1.3" sg_icon_stat "55,60,1,1,white,blue,0,087b5522,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[8 17 30 43 52 52 48 52 52 40 52 43 30 17 8 20 8 8 12 8 8 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newlineand\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Radio1AGCDoneRSSI" Ports [2, 1] Position [970, 112, 1030, 168] AttributesFormatString "<< % >>" SourceBlock "xbsIndex_r4/To Register" SourceType "Xilinx Shared Memory Based To Register Block" infoedit "Register block that writes data to a shared memory register. Delay of one sample period." shared_memory_name "'Radio1AGCDoneRSSI'" init "0" ownership "Locally owned and initialized" explicit_data_type on arith_type "Unsigned" n_bits "10" bin_pt "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,381,266" block_type "toreg" block_version "10.1.3" sg_icon_stat "60,56,1,1,white,blue,0,77cabcdf,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Radio2AGCDoneRSSI" Ports [2, 1] Position [970, 202, 1030, 258] AttributesFormatString "<< % >>" SourceBlock "xbsIndex_r4/To Register" SourceType "Xilinx Shared Memory Based To Register Block" infoedit "Register block that writes data to a shared memory register. Delay of one sample period." shared_memory_name "'Radio2AGCDoneRSSI'" init "0" ownership "Locally owned and initialized" explicit_data_type on arith_type "Unsigned" n_bits "10" bin_pt "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,381,266" block_type "toreg" block_version "10.1.3" sg_icon_stat "60,56,1,1,white,blue,0,77cabcdf,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Radio3AGCDoneRSSI" Ports [2, 1] Position [970, 292, 1030, 348] AttributesFormatString "<< % >>" SourceBlock "xbsIndex_r4/To Register" SourceType "Xilinx Shared Memory Based To Register Block" infoedit "Register block that writes data to a shared memory register. Delay of one sample period." shared_memory_name "'Radio3AGCDoneRSSI'" init "0" ownership "Locally owned and initialized" explicit_data_type on arith_type "Unsigned" n_bits "10" bin_pt "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,381,266" block_type "toreg" block_version "10.1.3" sg_icon_stat "60,56,1,1,white,blue,0,77cabcdf,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Radio4AGCDoneRSSI" Ports [2, 1] Position [975, 397, 1035, 453] AttributesFormatString "<< % >>" SourceBlock "xbsIndex_r4/To Register" SourceType "Xilinx Shared Memory Based To Register Block" infoedit "Register block that writes data to a shared memory register. Delay of one sample period." shared_memory_name "'Radio4AGCDoneRSSI'" init "0" ownership "Locally owned and initialized" explicit_data_type on arith_type "Unsigned" n_bits "10" bin_pt "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,381,266" block_type "toreg" block_version "10.1.3" sg_icon_stat "60,56,1,1,white,blue,0,77cabcdf,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "To Register" Ports [2, 1] Position [935, 671, 980, 729] NamePlacement "alternate" ShowName off AttributesFormatString "CaptureDone\\n<< % >>" SourceBlock "xbsIndex_r4/To Register" SourceType "Xilinx Shared Memory Based To Register Block" infoedit "Register block that writes data to a shared memory register. Delay of one sample period." shared_memory_name "'CaptureDone'" init "0" ownership "Locally owned and initialized" explicit_data_type on arith_type "Unsigned" n_bits "1" bin_pt "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,381,270" block_type "toreg" block_version "8.2" sg_icon_stat "45,58,1,1,white,blue,0,77cabcdf,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "TxDelay" Ports [0, 1] Position [55, 345, 100, 375] AttributesFormatString "<< % >>" SourceBlock "xbsIndex_r4/From Register" SourceType "Xilinx Shared Memory Based From Register Block" infoedit "Register block that reads data to a shared memory register. Delay of one sample period." shared_memory_name "'TxDelay'" init "1000" period "1" ownership "Locally owned and initialized" arith_type "Unsigned" n_bits "14" bin_pt "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,381,234" block_type "fromreg" block_version "10.1.2" sg_icon_stat "45,30,1,1,white,blue,0,4b212927,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "zero1" Ports [0, 1] Position [865, 706, 885, 724] ShowName off SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" arith_type "Boolean" const "1" n_bits "1" bin_pt "0" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "20,18,1,1,white,blue,0,06094819,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 26 26 ],[0.77 0.82 0.91]);\npatch([20 16 22 16 20 27 29 31 38 32 26 22 28 22 26 32 38 31 29 27 20 ],[3 7 13 19 23 23 21 23 23 17 23 19 13 7 3 9 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 26 26 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nfprintf('','COMMENT: end icon text');\n" } Line { SrcBlock "From Register4" SrcPort 1 DstBlock "Goto10" DstPort 1 } Line { SrcBlock "From Register7" SrcPort 1 DstBlock "Goto1" DstPort 1 } Line { SrcBlock "From Register8" SrcPort 1 DstBlock "Goto3" DstPort 1 } Line { SrcBlock "TxDelay" SrcPort 1 DstBlock "Goto2" DstPort 1 } Line { SrcBlock "From Register6" SrcPort 1 DstBlock "Goto4" DstPort 1 } Line { SrcBlock "From Register9" SrcPort 1 DstBlock "Goto5" DstPort 1 } Line { SrcBlock "From Register10" SrcPort 1 DstBlock "Goto6" DstPort 1 } Line { SrcBlock "From Register12" SrcPort 1 DstBlock "Goto7" DstPort 1 } Line { SrcBlock "From Register2" SrcPort 1 DstBlock "Goto8" DstPort 1 } Line { SrcBlock "From Register5" SrcPort 1 DstBlock "Goto11" DstPort 1 } Line { SrcBlock "From Register11" SrcPort 1 DstBlock "Goto12" DstPort 1 } Line { SrcBlock "From Register3" SrcPort 1 DstBlock "Goto13" DstPort 1 } Line { SrcBlock "From Register1" SrcPort 1 DstBlock "Goto9" DstPort 1 } Line { SrcBlock "DebugRx1Buffers" SrcPort 1 DstBlock "Goto14" DstPort 1 } Line { SrcBlock "DebugRx2Buffers" SrcPort 1 DstBlock "Goto15" DstPort 1 } Line { SrcBlock "DebugRx3Buffers" SrcPort 1 DstBlock "Goto16" DstPort 1 } Line { SrcBlock "DebugRx4Buffers" SrcPort 1 DstBlock "Goto17" DstPort 1 } Line { SrcBlock "From2" SrcPort 1 Points [15, 0] Branch { DstBlock "AGCDoneAddr" DstPort 2 } Branch { Points [0, 95] Branch { DstBlock "Radio1AGCDoneRSSI" DstPort 2 } Branch { Points [0, 90] Branch { Points [0, 90] Branch { Points [0, 105] DstBlock "Radio4AGCDoneRSSI" DstPort 2 } Branch { DstBlock "Radio3AGCDoneRSSI" DstPort 2 } } Branch { DstBlock "Radio2AGCDoneRSSI" DstPort 2 } } } } Line { SrcBlock "From1" SrcPort 1 DstBlock "AGCDoneAddr" DstPort 1 } Line { SrcBlock "From4" SrcPort 1 DstBlock "Radio2AGCDoneRSSI" DstPort 1 } Line { SrcBlock "From6" SrcPort 1 DstBlock "Radio3AGCDoneRSSI" DstPort 1 } Line { SrcBlock "From8" SrcPort 1 DstBlock "Radio4AGCDoneRSSI" DstPort 1 } Line { SrcBlock "From10" SrcPort 1 DstBlock "Radio1AGCDoneRSSI" DstPort 1 } Line { SrcBlock "From Register13" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "From Register14" SrcPort 1 DstBlock "Convert2" DstPort 1 } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "Logical" DstPort 1 } Line { SrcBlock "Convert2" SrcPort 1 Points [25, 0; 0, -40] DstBlock "Logical" DstPort 2 } Line { SrcBlock "Logical" SrcPort 1 DstBlock "Convert3" DstPort 1 } Line { SrcBlock "Convert3" SrcPort 1 DstBlock "Goto18" DstPort 1 } Line { SrcBlock "zero1" SrcPort 1 DstBlock "To Register" DstPort 2 } Line { SrcBlock "From3" SrcPort 1 DstBlock "To Register" DstPort 1 } Line { SrcBlock "From Register15" SrcPort 1 DstBlock "Goto19" DstPort 1 } Annotation { Name "MGCAGC_AGCDCO_SEL will go high\nonly when AGC is selected (MGC_AGC_SEL=1) AND\nDC Offset (DCO) Correction in enabled (DCO_EN_SEL=1)" Position [1140, 572] } } } Block { BlockType SubSystem Name "Posedge" Ports [1, 1] Position [330, 233, 375, 257] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Posedge" Location [132, 719, 452, 817] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" Position [25, 33, 55, 47] IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Reference Name "Delay" Ports [1, 1] Position [145, 45, 175, 75] ShowName off SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. If register retiming is enabled, the delay line is a chain of flip-flops." en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "8.2" sg_icon_stat "30,30,1,1,white,blue,0,fc531c0e,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Inverter" Ports [1, 1] Position [90, 47, 120, 73] ShowName off SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "8.2" sg_icon_stat "30,26,1,1,white,blue,0,1ab4a85f,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 58 58 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[7 16 29 42 51 51 47 51 51 39 51 42 29 16 7 19 7 7 11 7 7 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Logical" Ports [2, 1] Position [205, 29, 240, 71] ShowName off SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "8.2" sg_icon_stat "35,42,1,1,white,blue,0,087b5522,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[8 17 30 43 52 52 48 52 52 40 52 43 30 17 8 20 8 8 12 8 8 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newlineand\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Outport Name "Q" Position [265, 43, 295, 57] IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Line { SrcBlock "D" SrcPort 1 Points [0, 0; 15, 0] Branch { DstBlock "Inverter" DstPort 1 } Branch { DstBlock "Logical" DstPort 1 } } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Delay" DstPort 1 } Line { SrcBlock "Delay" SrcPort 1 Points [0, 0] DstBlock "Logical" DstPort 2 } Line { SrcBlock "Logical" SrcPort 1 Points [0, 0] DstBlock "Q" DstPort 1 } } } Block { BlockType SubSystem Name "Posedge1" Ports [1, 1] Position [365, 648, 410, 672] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Posedge1" Location [132, 719, 452, 817] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" Position [25, 33, 55, 47] IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Reference Name "Delay" Ports [1, 1] Position [145, 45, 175, 75] ShowName off SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. If register retiming is enabled, the delay line is a chain of flip-flops." en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "8.2" sg_icon_stat "30,30,1,1,white,blue,0,fc531c0e,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Inverter" Ports [1, 1] Position [90, 47, 120, 73] ShowName off SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "8.2" sg_icon_stat "30,26,1,1,white,blue,0,1ab4a85f,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 58 58 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[7 16 29 42 51 51 47 51 51 39 51 42 29 16 7 19 7 7 11 7 7 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Logical" Ports [2, 1] Position [205, 29, 240, 71] ShowName off SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "8.2" sg_icon_stat "35,42,1,1,white,blue,0,087b5522,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[8 17 30 43 52 52 48 52 52 40 52 43 30 17 8 20 8 8 12 8 8 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newlineand\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Outport Name "Q" Position [265, 43, 295, 57] IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Line { SrcBlock "Logical" SrcPort 1 Points [0, 0] DstBlock "Q" DstPort 1 } Line { SrcBlock "Delay" SrcPort 1 Points [0, 0] DstBlock "Logical" DstPort 2 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Delay" DstPort 1 } Line { SrcBlock "D" SrcPort 1 Points [0, 0; 15, 0] Branch { DstBlock "Logical" DstPort 1 } Branch { DstBlock "Inverter" DstPort 1 } } } } Block { BlockType SubSystem Name "Posedge2" Ports [1, 1] Position [365, 748, 410, 772] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Posedge2" Location [132, 719, 452, 817] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" Position [25, 33, 55, 47] IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Reference Name "Delay" Ports [1, 1] Position [145, 45, 175, 75] ShowName off SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. If register retiming is enabled, the delay line is a chain of flip-flops." en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "8.2" sg_icon_stat "30,30,1,1,white,blue,0,fc531c0e,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Inverter" Ports [1, 1] Position [90, 47, 120, 73] ShowName off SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "8.2" sg_icon_stat "30,26,1,1,white,blue,0,1ab4a85f,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 58 58 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[7 16 29 42 51 51 47 51 51 39 51 42 29 16 7 19 7 7 11 7 7 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Logical" Ports [2, 1] Position [205, 29, 240, 71] ShowName off SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "8.2" sg_icon_stat "35,42,1,1,white,blue,0,087b5522,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[8 17 30 43 52 52 48 52 52 40 52 43 30 17 8 20 8 8 12 8 8 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newlineand\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Outport Name "Q" Position [265, 43, 295, 57] IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Line { SrcBlock "Logical" SrcPort 1 Points [0, 0] DstBlock "Q" DstPort 1 } Line { SrcBlock "Delay" SrcPort 1 Points [0, 0] DstBlock "Logical" DstPort 2 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Delay" DstPort 1 } Line { SrcBlock "D" SrcPort 1 Points [0, 0; 15, 0] Branch { DstBlock "Logical" DstPort 1 } Branch { DstBlock "Inverter" DstPort 1 } } } } Block { BlockType SubSystem Name "Posedge3" Ports [1, 1] Position [325, 1008, 370, 1032] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Posedge3" Location [132, 719, 452, 817] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" Position [25, 33, 55, 47] IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Reference Name "Delay" Ports [1, 1] Position [145, 45, 175, 75] ShowName off SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. If register retiming is enabled, the delay line is a chain of flip-flops." en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "8.2" sg_icon_stat "30,30,1,1,white,blue,0,fc531c0e,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Inverter" Ports [1, 1] Position [90, 47, 120, 73] ShowName off SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "8.2" sg_icon_stat "30,26,1,1,white,blue,0,1ab4a85f,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 58 58 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[7 16 29 42 51 51 47 51 51 39 51 42 29 16 7 19 7 7 11 7 7 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Logical" Ports [2, 1] Position [205, 29, 240, 71] ShowName off SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "8.2" sg_icon_stat "35,42,1,1,white,blue,0,087b5522,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[8 17 30 43 52 52 48 52 52 40 52 43 30 17 8 20 8 8 12 8 8 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newlineand\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Outport Name "Q" Position [265, 43, 295, 57] IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Line { SrcBlock "D" SrcPort 1 Points [0, 0; 15, 0] Branch { DstBlock "Inverter" DstPort 1 } Branch { DstBlock "Logical" DstPort 1 } } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Delay" DstPort 1 } Line { SrcBlock "Delay" SrcPort 1 Points [0, 0] DstBlock "Logical" DstPort 2 } Line { SrcBlock "Logical" SrcPort 1 Points [0, 0] DstBlock "Q" DstPort 1 } } } Block { BlockType DiscretePulseGenerator Name "Pulse\nGenerator" Ports [0, 1] Position [35, 202, 65, 238] Period "1000000" PulseWidth "50" PhaseDelay "2" } Block { BlockType DiscretePulseGenerator Name "Pulse\nGenerator1" Ports [0, 1] Position [60, 643, 105, 677] Period "10 * 2^14" PulseWidth "50" PhaseDelay "2" } Block { BlockType DiscretePulseGenerator Name "Pulse\nGenerator2" Ports [0, 1] Position [60, 728, 105, 762] Period "10 * 2^14" PulseWidth "50" PhaseDelay "2.5 * 2^14" } Block { BlockType DiscretePulseGenerator Name "Pulse\nGenerator3" Ports [0, 1] Position [55, 1003, 100, 1037] Period "20000" PulseWidth "50" PhaseDelay "374" } Block { BlockType Reference Name "RSSI Clock\nGenerator" Ports [0, 1] Position [65, 942, 110, 968] SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited counter is implemented by combining a counter with a comparator." cnt_type "Free Running" cnt_to "Inf" operation "Up" start_count "0" cnt_by_val "1" arith_type "Unsigned" n_bits "1" bin_pt "0" load_pin off rst off en off explicit_period "on" period "2" dbl_ovrd off use_behavioral_HDL off use_rpm off implementation "Fabric" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,356,630" block_type "counter" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,26,1,1,white,blue,0,a170c862,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([14 4 18 4 14 30 34 38 55 42 29 20 35 20 29 42 55 38 34 30 14 ],[6 16 30 44 54 54 50 54 54 41 54 45 30 15 6 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'out');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "RSSI_ADC_CLK" Ports [1, 1] Position [170, 948, 210, 962] SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, double, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarded, depending on how they are configured." hdl_port on timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "8.2" sg_icon_stat "40,14,1,1,white,yellow,0,38220381,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 ],[0 0 14 14 ],[0.95 0.93 0.65]);\npatch([16 14 17 14 16 20 21 22 26 23 20 18 21 18 20 23 26 22 21 20 16 ],[2 4 7 10 12 12 11 12 12 9 12 10 7 4 2 5 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType SubSystem Name "Radio 1\nRx Buffers" Ports [5] Position [1175, 38, 1240, 142] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Radio 1\nRx Buffers" Location [2, 74, 1270, 726] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "RSSI" Position [450, 313, 480, 327] IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Inport Name "I/Q" Position [545, 163, 575, 177] Port "2" IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Inport Name "Addr" Position [325, 128, 355, 142] Port "3" IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Inport Name "WE" Position [110, 183, 140, 197] Port "4" IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Inport Name "EN" Position [110, 213, 140, 227] Port "5" IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Reference Name "Convert1" Ports [1, 1] Position [185, 212, 210, 228] ShowName off SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." arith_type "Boolean" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,374,375" block_type "convert" block_version "8.2" sg_icon_stat "25,16,1,1,white,blue,0,74901e60,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([15 10 17 10 15 23 25 27 35 28 22 17 23 17 22 28 35 27 25 23 15 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'cast');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Gateway Out" Ports [1, 1] Position [500, 30, 530, 40] ShowName off SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, double, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarded, depending on how they are configured." hdl_port off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,336,386" block_type "gatewayout" block_version "10.1.2" sg_icon_stat "30,10,1,1,white,grey,0,b3a044a9,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 ],[0 0 10 10 ],[0.88 0.88 0.88]);\npatch([13 11 13 11 13 16 17 18 21 19 17 15 17 15 17 19 21 18 17 16 13 ],[1 3 5 7 9 9 8 9 9 7 9 7 5 3 1 3 1 1 2 1 1 ],[0.98 0.96 0.92]);\nplot([0 30 30 0 0 ],[0 0 10 10 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Gateway Out1" Ports [1, 1] Position [500, 70, 530, 80] ShowName off SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, double, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarded, depending on how they are configured." hdl_port off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,336,386" block_type "gatewayout" block_version "10.1.2" sg_icon_stat "30,10,1,1,white,grey,0,b3a044a9,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 ],[0 0 10 10 ],[0.88 0.88 0.88]);\npatch([13 11 13 11 13 16 17 18 21 19 17 15 17 15 17 19 21 18 17 16 13 ],[1 3 5 7 9 9 8 9 9 7 9 7 5 3 1 3 1 1 2 1 1 ],[0.98 0.96 0.92]);\nplot([0 30 30 0 0 ],[0 0 10 10 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Logical" Ports [2, 1] Position [255, 175, 310, 235] SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "9.1.01" sg_icon_stat "55,60,1,1,white,blue,0,087b5522,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[8 17 30 43 52 52 48 52 52 40 52 43 30 17 8 20 8 8 12 8 8 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newlineand\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType SubSystem Name "Radio 1\nRSSI Buffer" Ports [3] Position [645, 264, 700, 376] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Radio 1\nRSSI Buffer" Location [2, 70, 1918, 1150] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Addr_14b" Position [325, 348, 355, 362] NamePlacement "alternate" IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Inport Name "RSSI" Position [95, 383, 125, 397] Port "2" IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Inport Name "WE" Position [720, 478, 750, 492] Port "3" IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Reference Name "11MSB" Ports [1, 1] Position [430, 346, 470, 364] NamePlacement "alternate" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardware notes: In hardware this block costs nothing." nbits "11" boolean_output off mode "Upper Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,407" block_type "slice" block_version "8.2" sg_icon_stat "40,18,1,1,white,blue,0,b1026674,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "BIT[2]" Ports [1, 1] Position [430, 401, 470, 419] SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "2" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,407" block_type "slice" block_version "8.2" sg_icon_stat "40,18,1,1,white,blue,0,b1026674,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Concat" Ports [2, 1] Position [685, 381, 725, 459] ShowName off SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point at zero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" block_version "10.1.2" sg_icon_stat "40,78,1,1,white,blue,0,df1e5aba,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([14 4 18 4 14 30 34 38 55 42 29 20 35 20 29 42 55 38 34 30 14 ],[6 16 30 44 54 54 50 54 54 41 54 45 30 15 6 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'hi');\ncolor('black');port_label('input',2,'lo');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Convert" Ports [1, 1] Position [285, 382, 320, 398] ShowName off SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." arith_type "Unsigned" n_bits "16" bin_pt "0" quantization "Truncate" overflow "Wrap" latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,461,375" block_type "convert" block_version "8.2" sg_icon_stat "35,16,1,1,white,blue,0,74901e60,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([15 10 17 10 15 23 25 27 35 28 22 17 23 17 22 28 35 27 25 23 15 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'cast');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Inverter" Ports [1, 1] Position [510, 402, 540, 418] ShowName off SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,251" block_type "inv" block_version "10.1.2" sg_icon_stat "30,16,1,1,white,blue,0,1ab4a85f,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 58 58 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[7 16 29 42 51 51 47 51 51 39 51 42 29 16 7 19 7 7 11 7 7 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Register" Ports [2, 1] Position [580, 378, 625, 422] ShowName off SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "10.1.2" sg_icon_stat "45,44,1,1,white,blue,0,cc3303a0,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('\\bf{z^{-1}}','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Reinterpret1" Ports [1, 1] Position [180, 382, 215, 398] ShowName off SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can changed the signal between signed and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothing.

Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsigned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111000 in binary)." force_arith_type on arith_type "Unsigned" force_bin_pt on bin_pt "0" has_advanced_control "0" sggui_pos "436,54,356,312" block_type "reinterpret" block_version "9.1.01" sg_icon_stat "35,16,1,1,white,blue,0,8982c1db,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 ],[0 0 32 32 ],[0.77 0.82 0.91]);\npatch([16 11 18 11 16 24 26 28 37 30 23 18 25 18 23 30 37 28 26 24 16 ],[3 8 15 22 27 27 25 27 27 20 27 22 15 8 3 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 50 50 0 0 ],[0 0 32 32 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('reinterpret');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Shared Memory" Ports [3, 1] Position [800, 323, 880, 517] AttributesFormatString "<< % >>" SourceBlock "xbsIndex_r4/Shared Memory" SourceType "Xilinx Shared Memory Random Access Memory Block" shared_memory_name "'RSSIBuff_Radio1'" depth "2^11" ownership "Locally Owned and Initialized" initVector "0" mutex "Unprotected" mode "Read and Write" write_mode "Read After Write" time_out "0" latency "1" explicit_data_type on arith_type "Unsigned" n_bits "32" bin_pt "0" xl_use_area off xl_area "[0,0,0,0,0,0,0]" implementation "Block RAM" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,384,381" block_type "shmem" block_version "10.1.2" sg_icon_stat "80,194,1,1,white,blue,0,e2c38f9a,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 80 80 0 ],[0 0 90 90 ],[0.77 0.82 0.91]);\npatch([18 5 24 5 18 39 45 51 74 56 39 27 46 27 39 56 74 51 45 39 18 ],[14 27 46 65 78 78 72 78 78 60 77 65 46 27 15 32 14 14 20 14 14 ],[0.98 0.96 0.92]);\nplot([0 80 80 0 0 ],[0 0 90 90 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'addr');\ncolor('black');port_label('input',2,'din');\ncolor('black');port_label('input',3,'we');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Terminator Name "Terminator2" Position [945, 410, 965, 430] ShowName off } Line { SrcBlock "RSSI" SrcPort 1 DstBlock "Reinterpret1" DstPort 1 } Line { SrcBlock "Convert" SrcPort 1 Points [35, 0] Branch { DstBlock "Register" DstPort 1 } Branch { Points [0, 50] DstBlock "Concat" DstPort 2 } } Line { SrcBlock "Addr_14b" SrcPort 1 Points [40, 0] Branch { DstBlock "11MSB" DstPort 1 } Branch { Points [0, 55] DstBlock "BIT[2]" DstPort 1 } } Line { SrcBlock "WE" SrcPort 1 DstBlock "Shared Memory" DstPort 3 } Line { SrcBlock "Reinterpret1" SrcPort 1 DstBlock "Convert" DstPort 1 } Line { SrcBlock "Concat" SrcPort 1 DstBlock "Shared Memory" DstPort 2 } Line { SrcBlock "BIT[2]" SrcPort 1 DstBlock "Inverter" DstPort 1 } Line { SrcBlock "11MSB" SrcPort 1 DstBlock "Shared Memory" DstPort 1 } Line { SrcBlock "Shared Memory" SrcPort 1 DstBlock "Terminator2" DstPort 1 } Line { SrcBlock "Register" SrcPort 1 DstBlock "Concat" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Register" DstPort 2 } } } Block { BlockType SubSystem Name "Radio 1 I/Q\nBuffer" Ports [3] Position [645, 118, 700, 222] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Radio 1 I/Q\nBuffer" Location [2, 74, 1270, 726] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Addr_14b" Position [190, 68, 220, 82] IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Inport Name "I/Q_32b" Position [190, 98, 220, 112] Port "2" IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Inport Name "WE" Position [190, 128, 220, 142] Port "3" IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Reference Name "Shared Memory" Ports [3, 1] Position [320, 60, 400, 150] AttributesFormatString "<< % >>" SourceBlock "xbsIndex_r4/Shared Memory" SourceType "Xilinx Shared Memory Random Access Memory Block" shared_memory_name "'RxBuff_Radio1'" depth "2^14" ownership "Locally Owned and Initialized" initVector "0" mutex "Unprotected" mode "Read and Write" write_mode "Read After Write" time_out "0" latency "1" explicit_data_type on arith_type "Unsigned" n_bits "32" bin_pt "0" xl_use_area off xl_area "[0,0,0,0,0,0,0]" implementation "Block RAM" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,384,381" block_type "shmem" block_version "10.1.2" sg_icon_stat "80,90,1,1,white,blue,0,e2c38f9a,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 80 80 0 ],[0 0 90 90 ],[0.77 0.82 0.91]);\npatch([18 5 24 5 18 39 45 51 74 56 39 27 46 27 39 56 74 51 45 39 18 ],[14 27 46 65 78 78 72 78 78 60 77 65 46 27 15 32 14 14 20 14 14 ],[0.98 0.96 0.92]);\nplot([0 80 80 0 0 ],[0 0 90 90 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'addr');\ncolor('black');port_label('input',2,'din');\ncolor('black');port_label('input',3,'we');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Terminator Name "Terminator" Position [450, 95, 470, 115] ShowName off } Line { SrcBlock "Addr_14b" SrcPort 1 DstBlock "Shared Memory" DstPort 1 } Line { SrcBlock "I/Q_32b" SrcPort 1 DstBlock "Shared Memory" DstPort 2 } Line { SrcBlock "WE" SrcPort 1 DstBlock "Shared Memory" DstPort 3 } Line { SrcBlock "Shared Memory" SrcPort 1 DstBlock "Terminator" DstPort 1 } } } Block { BlockType Scope Name "Scope" Ports [2] Position [585, 14, 625, 96] Floating off Location [5, 49, 1285, 757] Open off NumInputPorts "2" ZoomMode "yonly" List { ListType AxesTitles axes1 "%" axes2 "%" } YMin "-5~-5" YMax "5~5" SaveName "ScopeData2" DataFormat "StructureWithTime" MaxDataPoints "40000" SampleTime "0" } Line { SrcBlock "Logical" SrcPort 1 Points [55, 0] Branch { Points [95, 0] Branch { Points [0, -130] DstBlock "Gateway Out1" DstPort 1 } Branch { Labels [0, 0] DstBlock "Radio 1 I/Q\nBuffer" DstPort 3 } } Branch { Points [0, 150] DstBlock "Radio 1\nRSSI Buffer" DstPort 3 } } Line { SrcBlock "Addr" SrcPort 1 Points [75, 0] Branch { Points [0, -100] DstBlock "Gateway Out" DstPort 1 } Branch { Labels [0, 0] DstBlock "Radio 1 I/Q\nBuffer" DstPort 1 } Branch { Points [0, 150] DstBlock "Radio 1\nRSSI Buffer" DstPort 1 } } Line { SrcBlock "WE" SrcPort 1 DstBlock "Logical" DstPort 1 } Line { SrcBlock "EN" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "Logical" DstPort 2 } Line { SrcBlock "I/Q" SrcPort 1 DstBlock "Radio 1 I/Q\nBuffer" DstPort 2 } Line { SrcBlock "Gateway Out" SrcPort 1 DstBlock "Scope" DstPort 1 } Line { SrcBlock "Gateway Out1" SrcPort 1 DstBlock "Scope" DstPort 2 } Line { SrcBlock "RSSI" SrcPort 1 DstBlock "Radio 1\nRSSI Buffer" DstPort 2 } } } Block { BlockType SubSystem Name "Radio 1\nTx Buffer" Ports [3, 1] Position [1015, 661, 1095, 719] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Radio 1\nTx Buffer" Location [6, 74, 1274, 696] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "RdAddr_14b" Position [350, 288, 380, 302] NamePlacement "alternate" IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Inport Name "Rst" Position [30, 173, 60, 187] Port "2" IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Inport Name "En" Position [30, 203, 60, 217] Port "3" IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Reference Name "Constant" Ports [0, 1] Position [630, 350, 655, 370] ShowName off SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" arith_type "Unsigned" const "0" n_bits "32" bin_pt "0" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,400,346" block_type "constant" block_version "10.1.2" sg_icon_stat "25,20,1,1,white,blue,0,72d575a1,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 26 26 ],[0.77 0.82 0.91]);\npatch([20 16 22 16 20 27 29 31 38 32 26 22 28 22 26 32 38 31 29 27 20 ],[3 7 13 19 23 23 21 23 23 17 23 19 13 7 3 9 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 26 26 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'0');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Constant1" Ports [0, 1] Position [355, 345, 380, 365] ShowName off SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" arith_type "Boolean" const "0" n_bits "32" bin_pt "0" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,400,346" block_type "constant" block_version "10.1.2" sg_icon_stat "25,20,1,1,white,blue,0,72d575a1,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 26 26 ],[0.77 0.82 0.91]);\npatch([20 16 22 16 20 27 29 31 38 32 26 22 28 22 26 32 38 31 29 27 20 ],[3 7 13 19 23 23 21 23 23 17 23 19 13 7 3 9 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 26 26 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'0');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Constant2" Ports [0, 1] Position [355, 315, 380, 335] ShowName off SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" arith_type "Unsigned" const "0" n_bits "32" bin_pt "0" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,400,346" block_type "constant" block_version "10.1.2" sg_icon_stat "25,20,1,1,white,blue,0,72d575a1,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 26 26 ],[0.77 0.82 0.91]);\npatch([20 16 22 16 20 27 29 31 38 32 26 22 28 22 26 32 38 31 29 27 20 ],[3 7 13 19 23 23 21 23 23 17 23 19 13 7 3 9 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 26 26 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'0');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Convert" Ports [1, 1] Position [350, 188, 375, 202] ShowName off SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." arith_type "Boolean" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,374,375" block_type "convert" block_version "8.2" sg_icon_stat "25,14,1,1,white,blue,0,74901e60,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([15 10 17 10 15 23 25 27 35 28 22 17 23 17 22 28 35 27 25 23 15 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'cast');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Convert1" Ports [1, 1] Position [100, 203, 120, 217] ShowName off SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." arith_type "Boolean" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,374,375" block_type "convert" block_version "8.2" sg_icon_stat "20,14,1,1,white,blue,0,74901e60,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([15 10 17 10 15 23 25 27 35 28 22 17 23 17 22 28 35 27 25 23 15 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'cast');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Inverter" Ports [1, 1] Position [150, 201, 180, 219] SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "9.1.01" sg_icon_stat "30,18,1,1,white,blue,0,1ab4a85f,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 58 58 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[7 16 29 42 51 51 47 51 51 39 51 42 29 16 7 19 7 7 11 7 7 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Logical" Ports [2, 1] Position [215, 165, 270, 225] SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,261" block_type "logical" block_version "9.1.01" sg_icon_stat "55,60,1,1,white,blue,0,f4a65842,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[8 17 30 43 52 52 48 52 52 40 52 43 30 17 8 20 8 8 12 8 8 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newlineor\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Mux" Ports [3, 1] Position [750, 273, 795, 377] SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,303" block_type "mux" block_version "10.1.2" sg_icon_stat "45,104,1,1,white,blue,3,613f58e1,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 ],[0 14.8571 89.1429 104 ],[0.77 0.82 0.91]);\npatch([10 3 14 3 10 22 25 28 41 31 21 14 25 14 21 31 41 28 25 22 10 ],[34 41 52 63 70 70 67 70 70 60 70 63 52 41 34 44 34 34 37 34 34 ],[0.98 0.96 0.92]);\nplot([0 45 45 0 0 ],[0 14.8571 89.1429 104 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('input',3,'d1');\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Shared Memory" Ports [3, 1] Position [445, 280, 525, 370] AttributesFormatString "<< % >>" SourceBlock "xbsIndex_r4/Shared Memory" SourceType "Xilinx Shared Memory Random Access Memory Block" shared_memory_name "'TxBuff_Radio1'" depth "2^14" ownership "Locally Owned and Initialized" initVector "0" mutex "Unprotected" mode "Read and Write" write_mode "Read After Write" time_out "0" latency "1" explicit_data_type on arith_type "Unsigned" n_bits "32" bin_pt "0" xl_use_area off xl_area "[0,0,0,0,0,0,0]" implementation "Block RAM" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,384,381" block_type "shmem" block_version "10.1.2" sg_icon_stat "80,90,1,1,white,blue,0,e2c38f9a,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 80 80 0 ],[0 0 90 90 ],[0.77 0.82 0.91]);\npatch([18 5 24 5 18 39 45 51 74 56 39 27 46 27 39 56 74 51 45 39 18 ],[14 27 46 65 78 78 72 78 78 60 77 65 46 27 15 32 14 14 20 14 14 ],[0.98 0.96 0.92]);\nplot([0 80 80 0 0 ],[0 0 90 90 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'addr');\ncolor('black');port_label('input',2,'din');\ncolor('black');port_label('input',3,'we');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Outport Name "IQ_32b" Position [885, 318, 915, 332] IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Line { SrcBlock "Logical" SrcPort 1 DstBlock "Convert" DstPort 1 } Line { SrcBlock "Convert" SrcPort 1 Points [160, 0; 0, 95] DstBlock "Mux" DstPort 1 } Line { SrcBlock "Rst" SrcPort 1 DstBlock "Logical" DstPort 1 } Line { SrcBlock "En" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "Inverter" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical" DstPort 2 } Line { SrcBlock "RdAddr_14b" SrcPort 1 DstBlock "Shared Memory" DstPort 1 } Line { SrcBlock "Constant" SrcPort 1 DstBlock "Mux" DstPort 3 } Line { SrcBlock "Shared Memory" SrcPort 1 DstBlock "Mux" DstPort 2 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Shared Memory" DstPort 3 } Line { SrcBlock "Constant2" SrcPort 1 DstBlock "Shared Memory" DstPort 2 } Line { SrcBlock "Mux" SrcPort 1 DstBlock "IQ_32b" DstPort 1 } } } Block { BlockType SubSystem Name "Radio 1 Inputs" Ports [2, 2] Position [900, 32, 1085, 83] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Radio 1 Inputs" Location [534, 197, 1546, 748] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "DebugRxBuffers" Position [180, 258, 210, 272] IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Inport Name "MGCAGC_AGCDCO_SEL" Position [185, 348, 215, 362] Port "2" IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType SubSystem Name "ADC I" Ports [2, 2] Position [420, 254, 575, 301] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "ADC I" Location [693, 213, 1705, 865] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Debug" Position [685, 53, 715, 67] IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Inport Name "MGCAGC_AGCDCO_SEL" Position [130, 243, 160, 257] Port "2" IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Constant Name "Constant1" Position [15, 320, 45, 350] ShowName off Value "0" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Reference Name "Counter" Ports [0, 1] Position [520, 340, 580, 400] SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited counter is implemented by combining a counter with a comparator." cnt_type "Free Running" cnt_to "Inf" operation "Down" start_count "2^14-1" cnt_by_val "1" arith_type "Unsigned" n_bits "14" bin_pt "0" load_pin off rst off en off explicit_period "on" period "1" dbl_ovrd off use_behavioral_HDL off use_rpm off implementation "Fabric" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,619" block_type "counter" block_version "10.1.3" sg_icon_stat "60,60,1,1,white,blue,0,a170c862,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([14 4 18 4 14 30 34 38 55 42 29 20 35 20 29 42 55 38 34 30 14 ],[6 16 30 44 54 54 50 54 54 41 54 45 30 15 6 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'out');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "FromAGC_Radio1_I" Ports [1, 1] Position [115, 425, 180, 445] SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, double and fixed point to Xilinx fixed point type.

Hardware notes: In hardware these blocks become top level input ports." arith_type "Signed (2's comp)" n_bits "14" bin_pt "13" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,406" block_type "gatewayin" block_version "10.1.3" sg_icon_stat "65,20,1,1,white,yellow,0,bc55d28f,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([27 24 29 24 27 32 33 34 40 36 32 29 34 29 32 36 40 34 33 32 27 ],[2 5 10 15 18 18 17 18 18 14 18 15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Mux" Ports [3, 1] Position [820, 88, 865, 192] SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "1" bin_pt "0" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,303" block_type "mux" block_version "10.1.3" sg_icon_stat "45,104,1,1,white,blue,3,613f58e1,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 ],[0 14.8571 89.1429 104 ],[0.77 0.82 0.91]);\npatch([10 3 14 3 10 22 25 28 41 31 21 14 25 14 21 31 41 28 25 22 10 ],[34 41 52 63 70 70 67 70 70 60 70 63 52 41 34 44 34 34 37 34 34 ],[0.98 0.96 0.92]);\nplot([0 45 45 0 0 ],[0 14.8571 89.1429 104 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('input',3,'d1');\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Mux1" Ports [3, 1] Position [820, 283, 865, 387] SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "1" bin_pt "0" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,303" block_type "mux" block_version "10.1.3" sg_icon_stat "45,104,1,1,white,blue,3,613f58e1,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 ],[0 14.8571 89.1429 104 ],[0.77 0.82 0.91]);\npatch([10 3 14 3 10 22 25 28 41 31 21 14 25 14 21 31 41 28 25 22 10 ],[34 41 52 63 70 70 67 70 70 60 70 63 52 41 34 44 34 34 37 34 34 ],[0.98 0.96 0.92]);\nplot([0 45 45 0 0 ],[0 14.8571 89.1429 104 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('input',3,'d1');\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Mux2" Ports [3, 1] Position [275, 283, 320, 387] SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "1" bin_pt "0" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,303" block_type "mux" block_version "10.1.3" sg_icon_stat "45,104,1,1,white,blue,3,613f58e1,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 ],[0 14.8571 89.1429 104 ],[0.77 0.82 0.91]);\npatch([10 3 14 3 10 22 25 28 41 31 21 14 25 14 21 31 41 28 25 22 10 ],[34 41 52 63 70 70 67 70 70 60 70 63 52 41 34 44 34 34 37 34 34 ],[0.98 0.96 0.92]);\nplot([0 45 45 0 0 ],[0 14.8571 89.1429 104 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('input',3,'d1');\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Radio 1 ADC I" Ports [1, 1] Position [105, 314, 200, 356] LinkData { BlockName "radio1_adc_I" DialogParameters { sg_icon_stat "65,20,1,1,white,yellow,0,bc55d28f,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([27 24 29 24 27 32 33 34 40 36 32 29 34 29 32 36 40 34 33 32 27 ],[2 5 10 15 18 18 17 18 18 14 18 15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end icon text');\n" } } SourceBlock "WARP_Blockset/WARP Radio Board ADC//DACs/Radio 1 ADC I" SourceType "" ShowPortLabels "FromPortIcon" SystemSampleTime "-1" FunctionWithSeparateData off RTWMemSecFuncInitTerm "Inherit from model" RTWMemSecFuncExecute "Inherit from model" RTWMemSecDataConstants "Inherit from model" RTWMemSecDataInternal "Inherit from model" RTWMemSecDataParameters "Inherit from model" samp_period "1" } Block { BlockType Reference Name "Register" Ports [1, 1] Position [450, 321, 485, 349] ShowName off SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "8.2" sg_icon_stat "35,28,1,1,white,blue,0,ac6b57db,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('\\bf{z^{-1}}','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Reinterpret" Ports [1, 1] Position [665, 354, 715, 386] SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can changed the signal between signed and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothing.

Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsigned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111000 in binary)." force_arith_type on arith_type "Signed (2's comp)" force_bin_pt on bin_pt "13" has_advanced_control "0" sggui_pos "20,20,336,312" block_type "reinterpret" block_version "10.1.3" sg_icon_stat "50,32,1,1,white,blue,0,8982c1db,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 ],[0 0 32 32 ],[0.77 0.82 0.91]);\npatch([16 11 18 11 16 24 26 28 37 30 23 18 25 18 23 30 37 28 26 24 16 ],[3 8 15 22 27 27 25 27 27 20 27 22 15 8 3 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 50 50 0 0 ],[0 0 32 32 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('reinterpret');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Slice" Ports [1, 1] Position [670, 160, 730, 190] SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,376" block_type "slice" block_version "10.1.3" sg_icon_stat "60,30,1,1,white,blue,0,b1026674,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "radio1_ADC_I_OTR" Ports [1, 1] Position [110, 134, 165, 146] NamePlacement "alternate" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, double and fixed point to Xilinx fixed point type.

Hardware notes: In hardware these blocks become top level input ports." arith_type "Unsigned" n_bits "1" bin_pt "0" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,356,432" block_type "gatewayin" block_version "VER_STRING_GOES_HERE" sg_icon_stat "55,12,1,1,white,yellow,0,bc55d28f,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([27 24 29 24 27 32 33 34 40 36 32 29 34 29 32 36 40 34 33 32 27 ],[2 5 10 15 18 18 17 18 18 14 18 15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Outport Name "OTR I" Position [925, 133, 955, 147] IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Outport Name "ADC I" Position [925, 328, 955, 342] Port "2" IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Line { SrcBlock "Constant1" SrcPort 1 Points [20, 0] Branch { Points [0, -195] DstBlock "radio1_ADC_I_OTR" DstPort 1 } Branch { DstBlock "Radio 1 ADC I" DstPort 1 } Branch { Points [0, 100] DstBlock "FromAGC_Radio1_I" DstPort 1 } } Line { SrcBlock "Mux" SrcPort 1 DstBlock "OTR I" DstPort 1 } Line { SrcBlock "Debug" SrcPort 1 Points [40, 0; 0, 45] Branch { DstBlock "Mux" DstPort 1 } Branch { Points [0, 195] DstBlock "Mux1" DstPort 1 } } Line { SrcBlock "radio1_ADC_I_OTR" SrcPort 1 DstBlock "Mux" DstPort 2 } Line { SrcBlock "Slice" SrcPort 1 DstBlock "Mux" DstPort 3 } Line { SrcBlock "Mux1" SrcPort 1 DstBlock "ADC I" DstPort 1 } Line { SrcBlock "Register" SrcPort 1 DstBlock "Mux1" DstPort 2 } Line { SrcBlock "Reinterpret" SrcPort 1 DstBlock "Mux1" DstPort 3 } Line { SrcBlock "Counter" SrcPort 1 Points [25, 0] Branch { DstBlock "Reinterpret" DstPort 1 } Branch { Points [0, -195] DstBlock "Slice" DstPort 1 } } Line { SrcBlock "MGCAGC_AGCDCO_SEL" SrcPort 1 Points [70, 0; 0, 50] DstBlock "Mux2" DstPort 1 } Line { SrcBlock "FromAGC_Radio1_I" SrcPort 1 Points [50, 0; 0, -65] DstBlock "Mux2" DstPort 3 } Line { SrcBlock "Mux2" SrcPort 1 DstBlock "Register" DstPort 1 } Line { SrcBlock "Radio 1 ADC I" SrcPort 1 DstBlock "Mux2" DstPort 2 } } } Block { BlockType SubSystem Name "ADC Q" Ports [2, 2] Position [420, 324, 575, 366] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "ADC Q" Location [66, 91, 1078, 743] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Debug" Position [630, 43, 660, 57] IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Inport Name "MGCAGC_AGCDCO_SEL" Position [120, 233, 150, 247] Port "2" IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Constant Name "Constant1" Position [15, 310, 45, 340] ShowName off Value "0" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Reference Name "Counter" Ports [0, 1] Position [460, 330, 520, 390] SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited counter is implemented by combining a counter with a comparator." cnt_type "Free Running" cnt_to "Inf" operation "Up" start_count "0" cnt_by_val "1" arith_type "Unsigned" n_bits "14" bin_pt "0" load_pin off rst off en off explicit_period "on" period "1" dbl_ovrd off use_behavioral_HDL off use_rpm off implementation "Fabric" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,619" block_type "counter" block_version "10.1.3" sg_icon_stat "60,60,1,1,white,blue,0,a170c862,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([14 4 18 4 14 30 34 38 55 42 29 20 35 20 29 42 55 38 34 30 14 ],[6 16 30 44 54 54 50 54 54 41 54 45 30 15 6 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'out');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "FromAGC_Radio1_Q" Ports [1, 1] Position [105, 415, 170, 435] SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, double and fixed point to Xilinx fixed point type.

Hardware notes: In hardware these blocks become top level input ports." arith_type "Signed (2's comp)" n_bits "14" bin_pt "13" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,406" block_type "gatewayin" block_version "10.1.3" sg_icon_stat "65,20,1,1,white,yellow,0,bc55d28f,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([27 24 29 24 27 32 33 34 40 36 32 29 34 29 32 36 40 34 33 32 27 ],[2 5 10 15 18 18 17 18 18 14 18 15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Mux" Ports [3, 1] Position [765, 78, 810, 182] SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "1" bin_pt "0" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,303" block_type "mux" block_version "10.1.3" sg_icon_stat "45,104,1,1,white,blue,3,613f58e1,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 ],[0 14.8571 89.1429 104 ],[0.77 0.82 0.91]);\npatch([10 3 14 3 10 22 25 28 41 31 21 14 25 14 21 31 41 28 25 22 10 ],[34 41 52 63 70 70 67 70 70 60 70 63 52 41 34 44 34 34 37 34 34 ],[0.98 0.96 0.92]);\nplot([0 45 45 0 0 ],[0 14.8571 89.1429 104 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('input',3,'d1');\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Mux1" Ports [3, 1] Position [765, 273, 810, 377] SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "1" bin_pt "0" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,303" block_type "mux" block_version "10.1.3" sg_icon_stat "45,104,1,1,white,blue,3,613f58e1,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 ],[0 14.8571 89.1429 104 ],[0.77 0.82 0.91]);\npatch([10 3 14 3 10 22 25 28 41 31 21 14 25 14 21 31 41 28 25 22 10 ],[34 41 52 63 70 70 67 70 70 60 70 63 52 41 34 44 34 34 37 34 34 ],[0.98 0.96 0.92]);\nplot([0 45 45 0 0 ],[0 14.8571 89.1429 104 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('input',3,'d1');\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Mux2" Ports [3, 1] Position [265, 273, 310, 377] SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "1" bin_pt "0" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,303" block_type "mux" block_version "10.1.3" sg_icon_stat "45,104,1,1,white,blue,3,613f58e1,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 ],[0 14.8571 89.1429 104 ],[0.77 0.82 0.91]);\npatch([10 3 14 3 10 22 25 28 41 31 21 14 25 14 21 31 41 28 25 22 10 ],[34 41 52 63 70 70 67 70 70 60 70 63 52 41 34 44 34 34 37 34 34 ],[0.98 0.96 0.92]);\nplot([0 45 45 0 0 ],[0 14.8571 89.1429 104 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('input',3,'d1');\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Radio 1 ADC Q" Ports [1, 1] Position [90, 304, 185, 346] LinkData { BlockName "radio1_adc_Q" DialogParameters { sg_icon_stat "65,20,1,1,white,yellow,0,bc55d28f,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([27 24 29 24 27 32 33 34 40 36 32 29 34 29 32 36 40 34 33 32 27 ],[2 5 10 15 18 18 17 18 18 14 18 15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end icon text');\n" } } SourceBlock "WARP_Blockset/WARP Radio Board ADC//DACs/Radio 1 ADC Q" SourceType "" ShowPortLabels "FromPortIcon" SystemSampleTime "-1" FunctionWithSeparateData off RTWMemSecFuncInitTerm "Inherit from model" RTWMemSecFuncExecute "Inherit from model" RTWMemSecDataConstants "Inherit from model" RTWMemSecDataInternal "Inherit from model" RTWMemSecDataParameters "Inherit from model" samp_period "1" } Block { BlockType Reference Name "Register" Ports [1, 1] Position [390, 311, 425, 339] ShowName off SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "8.2" sg_icon_stat "35,28,1,1,white,blue,0,ac6b57db,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('\\bf{z^{-1}}','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Reinterpret" Ports [1, 1] Position [610, 344, 660, 376] SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can changed the signal between signed and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothing.

Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsigned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111000 in binary)." force_arith_type on arith_type "Signed (2's comp)" force_bin_pt on bin_pt "13" has_advanced_control "0" sggui_pos "20,20,336,312" block_type "reinterpret" block_version "10.1.3" sg_icon_stat "50,32,1,1,white,blue,0,8982c1db,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 ],[0 0 32 32 ],[0.77 0.82 0.91]);\npatch([16 11 18 11 16 24 26 28 37 30 23 18 25 18 23 30 37 28 26 24 16 ],[3 8 15 22 27 27 25 27 27 20 27 22 15 8 3 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 50 50 0 0 ],[0 0 32 32 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('reinterpret');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Slice" Ports [1, 1] Position [615, 150, 675, 180] SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,376" block_type "slice" block_version "10.1.3" sg_icon_stat "60,30,1,1,white,blue,0,b1026674,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "radio1_ADC_Q_OTR" Ports [1, 1] Position [115, 124, 170, 136] SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, double and fixed point to Xilinx fixed point type.

Hardware notes: In hardware these blocks become top level input ports." arith_type "Unsigned" n_bits "1" bin_pt "0" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,356,432" block_type "gatewayin" block_version "VER_STRING_GOES_HERE" sg_icon_stat "55,12,1,1,white,yellow,0,bc55d28f,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([27 24 29 24 27 32 33 34 40 36 32 29 34 29 32 36 40 34 33 32 27 ],[2 5 10 15 18 18 17 18 18 14 18 15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Outport Name "OTR Q" Position [905, 123, 935, 137] IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Outport Name "ADC Q" Position [905, 318, 935, 332] Port "2" IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Line { SrcBlock "Constant1" SrcPort 1 Points [20, 0] Branch { Points [0, -195] DstBlock "radio1_ADC_Q_OTR" DstPort 1 } Branch { DstBlock "Radio 1 ADC Q" DstPort 1 } Branch { Points [0, 100] DstBlock "FromAGC_Radio1_Q" DstPort 1 } } Line { SrcBlock "Mux" SrcPort 1 DstBlock "OTR Q" DstPort 1 } Line { SrcBlock "Debug" SrcPort 1 Points [40, 0; 0, 45] Branch { DstBlock "Mux" DstPort 1 } Branch { Points [0, 195] DstBlock "Mux1" DstPort 1 } } Line { SrcBlock "radio1_ADC_Q_OTR" SrcPort 1 DstBlock "Mux" DstPort 2 } Line { SrcBlock "Slice" SrcPort 1 DstBlock "Mux" DstPort 3 } Line { SrcBlock "Mux1" SrcPort 1 DstBlock "ADC Q" DstPort 1 } Line { SrcBlock "Register" SrcPort 1 DstBlock "Mux1" DstPort 2 } Line { SrcBlock "Reinterpret" SrcPort 1 DstBlock "Mux1" DstPort 3 } Line { SrcBlock "Counter" SrcPort 1 Points [30, 0] Branch { DstBlock "Reinterpret" DstPort 1 } Branch { Points [0, -195] DstBlock "Slice" DstPort 1 } } Line { SrcBlock "MGCAGC_AGCDCO_SEL" SrcPort 1 Points [70, 0; 0, 50] DstBlock "Mux2" DstPort 1 } Line { SrcBlock "FromAGC_Radio1_Q" SrcPort 1 Points [50, 0; 0, -65] DstBlock "Mux2" DstPort 3 } Line { SrcBlock "Radio 1 ADC Q" SrcPort 1 DstBlock "Mux2" DstPort 2 } Line { SrcBlock "Mux2" SrcPort 1 DstBlock "Register" DstPort 1 } } } Block { BlockType SubSystem Name "Concatenates_1" Ports [4, 1] Position [695, 218, 740, 372] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Concatenates_1" Location [2, 74, 1270, 726] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "OTR_I" Position [395, 43, 425, 57] IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Inport Name "ADC_I" Position [330, 93, 360, 107] Port "2" IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Inport Name "OTR_Q" Position [390, 163, 420, 177] Port "3" IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Inport Name "ADC_Q" Position [330, 213, 360, 227] Port "4" IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Reference Name "Concat1" Ports [2, 1] Position [490, 191, 520, 229] ShowName off SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point at zero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" block_version "8.2" sg_icon_stat "30,38,1,1,white,blue,0,df1e5aba,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([14 4 18 4 14 30 34 38 55 42 29 20 35 20 29 42 55 38 34 30 14 ],[6 16 30 44 54 54 50 54 54 41 54 45 30 15 6 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'hi');\ncolor('black');port_label('input',2,'lo');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Concat2" Ports [2, 1] Position [490, 71, 520, 109] ShowName off SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point at zero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" block_version "8.2" sg_icon_stat "30,38,1,1,white,blue,0,df1e5aba,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([14 4 18 4 14 30 34 38 55 42 29 20 35 20 29 42 55 38 34 30 14 ],[6 16 30 44 54 54 50 54 54 41 54 45 30 15 6 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'hi');\ncolor('black');port_label('input',2,'lo');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Concat3" Ports [2, 1] Position [550, 150, 575, 230] ShowName off SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point at zero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" block_version "8.2" sg_icon_stat "25,80,1,1,white,blue,0,df1e5aba,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([14 4 18 4 14 30 34 38 55 42 29 20 35 20 29 42 55 38 34 30 14 ],[6 16 30 44 54 54 50 54 54 41 54 45 30 15 6 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'hi');\ncolor('black');port_label('input',2,'lo');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Concat4" Ports [2, 1] Position [550, 30, 575, 110] ShowName off SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point at zero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" block_version "8.2" sg_icon_stat "25,80,1,1,white,blue,0,df1e5aba,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([14 4 18 4 14 30 34 38 55 42 29 20 35 20 29 42 55 38 34 30 14 ],[6 16 30 44 54 54 50 54 54 41 54 45 30 15 6 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'hi');\ncolor('black');port_label('input',2,'lo');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Concat5" Ports [2, 1] Position [635, 50, 660, 130] ShowName off SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point at zero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" block_version "8.2" sg_icon_stat "25,80,1,1,white,blue,0,df1e5aba,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([14 4 18 4 14 30 34 38 55 42 29 20 35 20 29 42 55 38 34 30 14 ],[6 16 30 44 54 54 50 54 54 41 54 45 30 15 6 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'hi');\ncolor('black');port_label('input',2,'lo');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Reinterpret" Ports [1, 1] Position [385, 90, 420, 110] ShowName off SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can changed the signal between signed and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothing.

Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsigned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111000 in binary)." force_arith_type on arith_type "Unsigned" force_bin_pt on bin_pt "0" has_advanced_control "0" sggui_pos "20,20,356,309" block_type "reinterpret" block_version "8.2" sg_icon_stat "35,20,1,1,white,blue,0,8982c1db,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 ],[0 0 32 32 ],[0.77 0.82 0.91]);\npatch([16 11 18 11 16 24 26 28 37 30 23 18 25 18 23 30 37 28 26 24 16 ],[3 8 15 22 27 27 25 27 27 20 27 22 15 8 3 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 50 50 0 0 ],[0 0 32 32 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('reinterpret');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Reinterpret1" Ports [1, 1] Position [390, 210, 425, 230] ShowName off SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can changed the signal between signed and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothing.

Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsigned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111000 in binary)." force_arith_type on arith_type "Unsigned" force_bin_pt on bin_pt "0" has_advanced_control "0" sggui_pos "20,20,356,309" block_type "reinterpret" block_version "8.2" sg_icon_stat "35,20,1,1,white,blue,0,8982c1db,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 ],[0 0 32 32 ],[0.77 0.82 0.91]);\npatch([16 11 18 11 16 24 26 28 37 30 23 18 25 18 23 30 37 28 26 24 16 ],[3 8 15 22 27 27 25 27 27 20 27 22 15 8 3 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 50 50 0 0 ],[0 0 32 32 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('reinterpret');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "zero" Ports [0, 1] Position [440, 191, 460, 209] ShowName off SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" arith_type "Unsigned" const "0" n_bits "1" bin_pt "0" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "20,18,1,1,white,blue,0,72d575a1,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 26 26 ],[0.77 0.82 0.91]);\npatch([20 16 22 16 20 27 29 31 38 32 26 22 28 22 26 32 38 31 29 27 20 ],[3 7 13 19 23 23 21 23 23 17 23 19 13 7 3 9 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 26 26 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'0');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "zero1" Ports [0, 1] Position [440, 71, 460, 89] ShowName off SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" arith_type "Unsigned" const "0" n_bits "1" bin_pt "0" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "20,18,1,1,white,blue,0,72d575a1,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 26 26 ],[0.77 0.82 0.91]);\npatch([20 16 22 16 20 27 29 31 38 32 26 22 28 22 26 32 38 31 29 27 20 ],[3 7 13 19 23 23 21 23 23 17 23 19 13 7 3 9 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 26 26 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'0');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Outport Name "32b" Position [685, 83, 715, 97] IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Line { SrcBlock "Reinterpret1" SrcPort 1 DstBlock "Concat1" DstPort 2 } Line { SrcBlock "Reinterpret" SrcPort 1 DstBlock "Concat2" DstPort 2 } Line { SrcBlock "ADC_Q" SrcPort 1 DstBlock "Reinterpret1" DstPort 1 } Line { SrcBlock "OTR_Q" SrcPort 1 DstBlock "Concat3" DstPort 1 } Line { SrcBlock "ADC_I" SrcPort 1 DstBlock "Reinterpret" DstPort 1 } Line { SrcBlock "Concat5" SrcPort 1 DstBlock "32b" DstPort 1 } Line { SrcBlock "OTR_I" SrcPort 1 DstBlock "Concat4" DstPort 1 } Line { SrcBlock "Concat3" SrcPort 1 Points [25, 0; 0, -80] DstBlock "Concat5" DstPort 2 } Line { SrcBlock "Concat4" SrcPort 1 DstBlock "Concat5" DstPort 1 } Line { SrcBlock "Concat2" SrcPort 1 Points [0, 0] DstBlock "Concat4" DstPort 2 } Line { SrcBlock "zero1" SrcPort 1 DstBlock "Concat2" DstPort 1 } Line { SrcBlock "Concat1" SrcPort 1 DstBlock "Concat3" DstPort 2 } Line { SrcBlock "zero" SrcPort 1 DstBlock "Concat1" DstPort 1 } } } Block { BlockType Reference Name "Gateway Out1" Ports [1, 1] Position [710, 135, 740, 145] ShowName off SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, double, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarded, depending on how they are configured." hdl_port off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,336,386" block_type "gatewayout" block_version "10.1.2" sg_icon_stat "30,10,1,1,white,grey,0,b3a044a9,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 ],[0 0 10 10 ],[0.88 0.88 0.88]);\npatch([13 11 13 11 13 16 17 18 21 19 17 15 17 15 17 19 21 18 17 16 13 ],[1 3 5 7 9 9 8 9 9 7 9 7 5 3 1 3 1 1 2 1 1 ],[0.98 0.96 0.92]);\nplot([0 30 30 0 0 ],[0 0 10 10 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Gateway Out4" Ports [1, 1] Position [710, 120, 740, 130] ShowName off SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, double, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarded, depending on how they are configured." hdl_port off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,336,386" block_type "gatewayout" block_version "10.1.2" sg_icon_stat "30,10,1,1,white,grey,0,b3a044a9,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 ],[0 0 10 10 ],[0.88 0.88 0.88]);\npatch([13 11 13 11 13 16 17 18 21 19 17 15 17 15 17 19 21 18 17 16 13 ],[1 3 5 7 9 9 8 9 9 7 9 7 5 3 1 3 1 1 2 1 1 ],[0.98 0.96 0.92]);\nplot([0 30 30 0 0 ],[0 0 10 10 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType SubSystem Name "RSSI" Ports [1, 1] Position [470, 397, 540, 433] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "RSSI" Location [2, 74, 1184, 726] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Debug" Position [465, 28, 495, 42] IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Constant Name "Constant1" Position [160, 100, 190, 130] ShowName off Value "0" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Reference Name "Counter" Ports [0, 1] Position [380, 120, 440, 180] SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited counter is implemented by combining a counter with a comparator." cnt_type "Free Running" cnt_to "Inf" operation "Up" start_count "0" cnt_by_val "1" arith_type "Unsigned" n_bits "10" bin_pt "0" load_pin off rst off en off explicit_period "on" period "1" dbl_ovrd off use_behavioral_HDL off use_rpm off implementation "Fabric" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,619" block_type "counter" block_version "10.1.3" sg_icon_stat "60,60,1,1,white,blue,0,a170c862,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([14 4 18 4 14 30 34 38 55 42 29 20 35 20 29 42 55 38 34 30 14 ],[6 16 30 44 54 54 50 54 54 41 54 45 30 15 6 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'out');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Mux" Ports [3, 1] Position [600, 63, 645, 167] SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "1" bin_pt "0" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,303" block_type "mux" block_version "10.1.3" sg_icon_stat "45,104,1,1,white,blue,3,613f58e1,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 ],[0 14.8571 89.1429 104 ],[0.77 0.82 0.91]);\npatch([10 3 14 3 10 22 25 28 41 31 21 14 25 14 21 31 41 28 25 22 10 ],[34 41 52 63 70 70 67 70 70 60 70 63 52 41 34 44 34 34 37 34 34 ],[0.98 0.96 0.92]);\nplot([0 45 45 0 0 ],[0 14.8571 89.1429 104 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('input',3,'d1');\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "radio1_RSSI" Ports [1, 1] Position [280, 109, 335, 121] NamePlacement "alternate" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, double and fixed point to Xilinx fixed point type.

Hardware notes: In hardware these blocks become top level input ports." arith_type "Unsigned" n_bits "10" bin_pt "0" quantization "Truncate" overflow "Wrap" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,356,432" block_type "gatewayin" block_version "VER_STRING_GOES_HERE" sg_icon_stat "55,12,1,1,white,yellow,0,bc55d28f,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([27 24 29 24 27 32 33 34 40 36 32 29 34 29 32 36 40 34 33 32 27 ],[2 5 10 15 18 18 17 18 18 14 18 15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Outport Name "RSSI" Position [740, 108, 770, 122] IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "radio1_RSSI" DstPort 1 } Line { SrcBlock "Debug" SrcPort 1 Points [40, 0; 0, 45] DstBlock "Mux" DstPort 1 } Line { SrcBlock "radio1_RSSI" SrcPort 1 DstBlock "Mux" DstPort 2 } Line { SrcBlock "Counter" SrcPort 1 DstBlock "Mux" DstPort 3 } Line { SrcBlock "Mux" SrcPort 1 DstBlock "RSSI" DstPort 1 } } } Block { BlockType Scope Name "Scope" Ports [2] Position [800, 111, 830, 164] Floating off Location [5, 34, 1285, 912] Open off NumInputPorts "2" List { ListType AxesTitles axes1 "%" axes2 "%" } YMin "-5~-5" YMax "5~5" DataFormat "StructureWithTime" SampleTime "0" } Block { BlockType Outport Name "Radio 1 RSSI" Position [655, 408, 685, 422] IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Outport Name "Radio 1 I/Q" Position [865, 288, 895, 302] Port "2" IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Line { SrcBlock "ADC Q" SrcPort 2 Points [85, 0] Branch { DstBlock "Concatenates_1" DstPort 4 } Branch { Points [0, -215] DstBlock "Gateway Out1" DstPort 1 } } Line { SrcBlock "ADC Q" SrcPort 1 Points [0, -20] DstBlock "Concatenates_1" DstPort 3 } Line { Labels [0, 0] SrcBlock "ADC I" SrcPort 2 Points [0, -15; 75, 0] Branch { DstBlock "Concatenates_1" DstPort 2 } Branch { Points [0, -150] DstBlock "Gateway Out4" DstPort 1 } } Line { SrcBlock "ADC I" SrcPort 1 Points [35, 0; 0, -30] DstBlock "Concatenates_1" DstPort 1 } Line { SrcBlock "Concatenates_1" SrcPort 1 Points [0, 0] DstBlock "Radio 1 I/Q" DstPort 1 } Line { SrcBlock "Gateway Out4" SrcPort 1 DstBlock "Scope" DstPort 1 } Line { SrcBlock "Gateway Out1" SrcPort 1 Points [40, 0] DstBlock "Scope" DstPort 2 } Line { SrcBlock "DebugRxBuffers" SrcPort 1 Points [160, 0] Branch { DstBlock "ADC I" DstPort 1 } Branch { Points [0, 70] Branch { DstBlock "ADC Q" DstPort 1 } Branch { Points [0, 80] DstBlock "RSSI" DstPort 1 } } } Line { SrcBlock "RSSI" SrcPort 1 DstBlock "Radio 1 RSSI" DstPort 1 } Line { SrcBlock "MGCAGC_AGCDCO_SEL" SrcPort 1 Points [110, 0] Branch { DstBlock "ADC Q" DstPort 2 } Branch { Points [0, -65] DstBlock "ADC I" DstPort 2 } } } } Block { BlockType SubSystem Name "Radio 1 Outputs" Ports [1] Position [1180, 666, 1230, 714] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Radio 1 Outputs" Location [2, 74, 1078, 531] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "32b" Position [250, 93, 280, 107] IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Reference Name "16LSB" Ports [1, 1] Position [430, 92, 470, 108] SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardware notes: In hardware this block costs nothing." nbits "16" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,442,407" block_type "slice" block_version "8.2" sg_icon_stat "40,16,1,1,white,blue,0,b1026674,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "16MSB" Ports [1, 1] Position [430, 36, 470, 54] NamePlacement "alternate" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardware notes: In hardware this block costs nothing." nbits "16" boolean_output off mode "Upper Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,442,407" block_type "slice" block_version "8.2" sg_icon_stat "40,18,1,1,white,blue,0,b1026674,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Radio 1 DAC I" Ports [1, 1] Position [685, 24, 780, 66] LinkData { BlockName "Convert" DialogParameters { sg_icon_stat "45,30,1,1,white,blue,0,74901e60,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([15 10 17 10 15 23 25 27 35 28 22 17 23 17 22 28 35 27 25 23 15 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'cast');\nfprintf('','COMMENT: end icon text');\n" } BlockName "radio1_dac_I" DialogParameters { sg_icon_stat "60,20,1,1,white,yellow,0,38220381,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([24 21 26 21 24 29 30 31 37 33 29 26 31 26 29 33 37 31 30 29 24 ],[2 5 10 15 18 18 17 18 18 14 18 15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } } SourceBlock "WARP_Blockset/WARP Radio Board ADC//DACs/Radio 1 DAC I" SourceType "" ShowPortLabels "FromPortIcon" SystemSampleTime "-1" FunctionWithSeparateData off RTWMemSecFuncInitTerm "Inherit from model" RTWMemSecFuncExecute "Inherit from model" RTWMemSecDataConstants "Inherit from model" RTWMemSecDataInternal "Inherit from model" RTWMemSecDataParameters "Inherit from model" } Block { BlockType Reference Name "Radio 1 DAC Q" Ports [1, 1] Position [685, 79, 780, 121] LinkData { BlockName "Convert" DialogParameters { sg_icon_stat "45,30,1,1,white,blue,0,74901e60,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([15 10 17 10 15 23 25 27 35 28 22 17 23 17 22 28 35 27 25 23 15 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'cast');\nfprintf('','COMMENT: end icon text');\n" } BlockName "radio1_dac_Q" DialogParameters { sg_icon_stat "60,20,1,1,white,yellow,0,38220381,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([24 21 26 21 24 29 30 31 37 33 29 26 31 26 29 33 37 31 30 29 24 ],[2 5 10 15 18 18 17 18 18 14 18 15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } } SourceBlock "WARP_Blockset/WARP Radio Board ADC//DACs/Radio 1 DAC Q" SourceType "" ShowPortLabels "FromPortIcon" SystemSampleTime "-1" FunctionWithSeparateData off RTWMemSecFuncInitTerm "Inherit from model" RTWMemSecFuncExecute "Inherit from model" RTWMemSecDataConstants "Inherit from model" RTWMemSecDataInternal "Inherit from model" RTWMemSecDataParameters "Inherit from model" } Block { BlockType Reference Name "Register" Ports [1, 1] Position [595, 31, 630, 59] ShowName off SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "8.2" sg_icon_stat "35,28,1,1,white,blue,0,ac6b57db,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('\\bf{z^{-1}}','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Register1" Ports [1, 1] Position [595, 86, 630, 114] ShowName off SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "8.2" sg_icon_stat "35,28,1,1,white,blue,0,ac6b57db,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('\\bf{z^{-1}}','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Reinterpret" Ports [1, 1] Position [530, 35, 575, 55] ShowName off SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can changed the signal between signed and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothing.

Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsigned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111000 in binary)." force_arith_type on arith_type "Signed (2's comp)" force_bin_pt on bin_pt "15" has_advanced_control "0" sggui_pos "20,20,356,309" block_type "reinterpret" block_version "8.2" sg_icon_stat "45,20,1,1,white,blue,0,8982c1db,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 ],[0 0 32 32 ],[0.77 0.82 0.91]);\npatch([16 11 18 11 16 24 26 28 37 30 23 18 25 18 23 30 37 28 26 24 16 ],[3 8 15 22 27 27 25 27 27 20 27 22 15 8 3 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 50 50 0 0 ],[0 0 32 32 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('reinterpret');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Reinterpret1" Ports [1, 1] Position [530, 90, 575, 110] ShowName off SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can changed the signal between signed and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothing.

Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsigned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111000 in binary)." force_arith_type on arith_type "Signed (2's comp)" force_bin_pt on bin_pt "15" has_advanced_control "0" sggui_pos "20,20,356,309" block_type "reinterpret" block_version "8.2" sg_icon_stat "45,20,1,1,white,blue,0,8982c1db,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 ],[0 0 32 32 ],[0.77 0.82 0.91]);\npatch([16 11 18 11 16 24 26 28 37 30 23 18 25 18 23 30 37 28 26 24 16 ],[3 8 15 22 27 27 25 27 27 20 27 22 15 8 3 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 50 50 0 0 ],[0 0 32 32 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('reinterpret');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Terminator Name "Terminator1" Position [840, 35, 860, 55] ShowName off } Block { BlockType Terminator Name "Terminator2" Position [840, 90, 860, 110] ShowName off } Line { SrcBlock "Radio 1 DAC Q" SrcPort 1 DstBlock "Terminator2" DstPort 1 } Line { SrcBlock "Radio 1 DAC I" SrcPort 1 DstBlock "Terminator1" DstPort 1 } Line { SrcBlock "Reinterpret1" SrcPort 1 DstBlock "Register1" DstPort 1 } Line { SrcBlock "Reinterpret" SrcPort 1 DstBlock "Register" DstPort 1 } Line { SrcBlock "16LSB" SrcPort 1 DstBlock "Reinterpret1" DstPort 1 } Line { SrcBlock "16MSB" SrcPort 1 DstBlock "Reinterpret" DstPort 1 } Line { SrcBlock "Register" SrcPort 1 DstBlock "Radio 1 DAC I" DstPort 1 } Line { SrcBlock "Register1" SrcPort 1 DstBlock "Radio 1 DAC Q" DstPort 1 } Line { SrcBlock "32b" SrcPort 1 Points [65, 0] Branch { Points [0, -55] DstBlock "16MSB" DstPort 1 } Branch { DstBlock "16LSB" DstPort 1 } } } } Block { BlockType SubSystem Name "Radio 2\nRx Buffers" Ports [5] Position [1175, 184, 1240, 286] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Radio 2\nRx Buffers" Location [2, 74, 1270, 726] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "RSSI" Position [450, 313, 480, 327] IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Inport Name "I/Q" Position [545, 163, 575, 177] Port "2" IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Inport Name "Addr" Position [325, 128, 355, 142] Port "3" IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Inport Name "WE" Position [110, 183, 140, 197] Port "4" IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Inport Name "EN" Position [110, 213, 140, 227] Port "5" IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Reference Name "Convert1" Ports [1, 1] Position [185, 212, 210, 228] ShowName off SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." arith_type "Boolean" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,374,375" block_type "convert" block_version "8.2" sg_icon_stat "25,16,1,1,white,blue,0,74901e60,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([15 10 17 10 15 23 25 27 35 28 22 17 23 17 22 28 35 27 25 23 15 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'cast');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Gateway Out" Ports [1, 1] Position [500, 30, 530, 40] ShowName off SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, double, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarded, depending on how they are configured." hdl_port off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,336,386" block_type "gatewayout" block_version "10.1.2" sg_icon_stat "30,10,1,1,white,grey,0,b3a044a9,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 ],[0 0 10 10 ],[0.88 0.88 0.88]);\npatch([13 11 13 11 13 16 17 18 21 19 17 15 17 15 17 19 21 18 17 16 13 ],[1 3 5 7 9 9 8 9 9 7 9 7 5 3 1 3 1 1 2 1 1 ],[0.98 0.96 0.92]);\nplot([0 30 30 0 0 ],[0 0 10 10 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Gateway Out1" Ports [1, 1] Position [500, 70, 530, 80] ShowName off SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, double, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarded, depending on how they are configured." hdl_port off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,336,386" block_type "gatewayout" block_version "10.1.2" sg_icon_stat "30,10,1,1,white,grey,0,b3a044a9,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 ],[0 0 10 10 ],[0.88 0.88 0.88]);\npatch([13 11 13 11 13 16 17 18 21 19 17 15 17 15 17 19 21 18 17 16 13 ],[1 3 5 7 9 9 8 9 9 7 9 7 5 3 1 3 1 1 2 1 1 ],[0.98 0.96 0.92]);\nplot([0 30 30 0 0 ],[0 0 10 10 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Logical" Ports [2, 1] Position [255, 175, 310, 235] SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "9.1.01" sg_icon_stat "55,60,1,1,white,blue,0,087b5522,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[8 17 30 43 52 52 48 52 52 40 52 43 30 17 8 20 8 8 12 8 8 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newlineand\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType SubSystem Name "Radio 2\nRSSI Buffer" Ports [3] Position [645, 264, 700, 376] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Radio 2\nRSSI Buffer" Location [6, 74, 1682, 1006] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Addr_14b" Position [325, 348, 355, 362] NamePlacement "alternate" IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Inport Name "RSSI" Position [95, 383, 125, 397] Port "2" IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Inport Name "WE" Position [720, 478, 750, 492] Port "3" IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Reference Name "11MSB" Ports [1, 1] Position [430, 346, 470, 364] NamePlacement "alternate" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardware notes: In hardware this block costs nothing." nbits "11" boolean_output off mode "Upper Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,407" block_type "slice" block_version "8.2" sg_icon_stat "40,18,1,1,white,blue,0,b1026674,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "BIT[2]" Ports [1, 1] Position [430, 401, 470, 419] SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "2" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,407" block_type "slice" block_version "8.2" sg_icon_stat "40,18,1,1,white,blue,0,b1026674,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Concat" Ports [2, 1] Position [685, 381, 725, 459] ShowName off SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point at zero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" block_version "10.1.2" sg_icon_stat "40,78,1,1,white,blue,0,df1e5aba,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([14 4 18 4 14 30 34 38 55 42 29 20 35 20 29 42 55 38 34 30 14 ],[6 16 30 44 54 54 50 54 54 41 54 45 30 15 6 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'hi');\ncolor('black');port_label('input',2,'lo');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Convert" Ports [1, 1] Position [285, 382, 320, 398] ShowName off SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." arith_type "Unsigned" n_bits "16" bin_pt "0" quantization "Truncate" overflow "Wrap" latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,461,375" block_type "convert" block_version "8.2" sg_icon_stat "35,16,1,1,white,blue,0,74901e60,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([15 10 17 10 15 23 25 27 35 28 22 17 23 17 22 28 35 27 25 23 15 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'cast');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Inverter" Ports [1, 1] Position [510, 402, 540, 418] ShowName off SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,251" block_type "inv" block_version "10.1.2" sg_icon_stat "30,16,1,1,white,blue,0,1ab4a85f,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 58 58 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[7 16 29 42 51 51 47 51 51 39 51 42 29 16 7 19 7 7 11 7 7 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Register" Ports [2, 1] Position [580, 378, 625, 422] ShowName off SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "10.1.2" sg_icon_stat "45,44,1,1,white,blue,0,cc3303a0,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('\\bf{z^{-1}}','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Reinterpret1" Ports [1, 1] Position [180, 382, 215, 398] ShowName off SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can changed the signal between signed and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothing.

Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsigned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111000 in binary)." force_arith_type on arith_type "Unsigned" force_bin_pt on bin_pt "0" has_advanced_control "0" sggui_pos "436,54,356,312" block_type "reinterpret" block_version "9.1.01" sg_icon_stat "35,16,1,1,white,blue,0,8982c1db,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 ],[0 0 32 32 ],[0.77 0.82 0.91]);\npatch([16 11 18 11 16 24 26 28 37 30 23 18 25 18 23 30 37 28 26 24 16 ],[3 8 15 22 27 27 25 27 27 20 27 22 15 8 3 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 50 50 0 0 ],[0 0 32 32 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('reinterpret');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Shared Memory" Ports [3, 1] Position [800, 323, 880, 517] AttributesFormatString "<< % >>" SourceBlock "xbsIndex_r4/Shared Memory" SourceType "Xilinx Shared Memory Random Access Memory Block" shared_memory_name "'RSSIBuff_Radio2'" depth "2^11" ownership "Locally Owned and Initialized" initVector "0" mutex "Unprotected" mode "Read and Write" write_mode "Read After Write" time_out "0" latency "1" explicit_data_type on arith_type "Unsigned" n_bits "32" bin_pt "0" xl_use_area off xl_area "[0,0,0,0,0,0,0]" implementation "Block RAM" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,384,381" block_type "shmem" block_version "10.1.2" sg_icon_stat "80,194,1,1,white,blue,0,e2c38f9a,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 80 80 0 ],[0 0 90 90 ],[0.77 0.82 0.91]);\npatch([18 5 24 5 18 39 45 51 74 56 39 27 46 27 39 56 74 51 45 39 18 ],[14 27 46 65 78 78 72 78 78 60 77 65 46 27 15 32 14 14 20 14 14 ],[0.98 0.96 0.92]);\nplot([0 80 80 0 0 ],[0 0 90 90 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'addr');\ncolor('black');port_label('input',2,'din');\ncolor('black');port_label('input',3,'we');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Terminator Name "Terminator2" Position [945, 410, 965, 430] ShowName off } Line { SrcBlock "RSSI" SrcPort 1 DstBlock "Reinterpret1" DstPort 1 } Line { SrcBlock "Convert" SrcPort 1 Points [35, 0] Branch { DstBlock "Register" DstPort 1 } Branch { Points [0, 50] DstBlock "Concat" DstPort 2 } } Line { SrcBlock "Addr_14b" SrcPort 1 Points [40, 0] Branch { DstBlock "11MSB" DstPort 1 } Branch { Points [0, 55] DstBlock "BIT[2]" DstPort 1 } } Line { SrcBlock "WE" SrcPort 1 DstBlock "Shared Memory" DstPort 3 } Line { SrcBlock "Reinterpret1" SrcPort 1 DstBlock "Convert" DstPort 1 } Line { SrcBlock "Concat" SrcPort 1 DstBlock "Shared Memory" DstPort 2 } Line { SrcBlock "BIT[2]" SrcPort 1 DstBlock "Inverter" DstPort 1 } Line { SrcBlock "11MSB" SrcPort 1 DstBlock "Shared Memory" DstPort 1 } Line { SrcBlock "Shared Memory" SrcPort 1 DstBlock "Terminator2" DstPort 1 } Line { SrcBlock "Register" SrcPort 1 DstBlock "Concat" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Register" DstPort 2 } } } Block { BlockType SubSystem Name "Radio 2 I/Q\nBuffer" Ports [3] Position [645, 118, 700, 222] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Radio 2 I/Q\nBuffer" Location [2, 74, 1270, 726] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Addr_14b" Position [205, 68, 235, 82] IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Inport Name "I/Q_32b" Position [205, 98, 235, 112] Port "2" IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Inport Name "WE" Position [205, 128, 235, 142] Port "3" IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Reference Name "Shared Memory" Ports [3, 1] Position [315, 60, 395, 150] AttributesFormatString "<< % >>" SourceBlock "xbsIndex_r4/Shared Memory" SourceType "Xilinx Shared Memory Random Access Memory Block" shared_memory_name "'RxBuff_Radio2'" depth "2^14" ownership "Locally Owned and Initialized" initVector "0" mutex "Unprotected" mode "Read and Write" write_mode "Read After Write" time_out "0" latency "1" explicit_data_type on arith_type "Unsigned" n_bits "32" bin_pt "0" xl_use_area off xl_area "[0,0,0,0,0,0,0]" implementation "Block RAM" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,384,381" block_type "shmem" block_version "10.1.2" sg_icon_stat "80,90,1,1,white,blue,0,e2c38f9a,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 80 80 0 ],[0 0 90 90 ],[0.77 0.82 0.91]);\npatch([18 5 24 5 18 39 45 51 74 56 39 27 46 27 39 56 74 51 45 39 18 ],[14 27 46 65 78 78 72 78 78 60 77 65 46 27 15 32 14 14 20 14 14 ],[0.98 0.96 0.92]);\nplot([0 80 80 0 0 ],[0 0 90 90 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'addr');\ncolor('black');port_label('input',2,'din');\ncolor('black');port_label('input',3,'we');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Terminator Name "Terminator" Position [445, 95, 465, 115] ShowName off } Line { SrcBlock "Addr_14b" SrcPort 1 DstBlock "Shared Memory" DstPort 1 } Line { SrcBlock "I/Q_32b" SrcPort 1 DstBlock "Shared Memory" DstPort 2 } Line { SrcBlock "WE" SrcPort 1 DstBlock "Shared Memory" DstPort 3 } Line { SrcBlock "Shared Memory" SrcPort 1 DstBlock "Terminator" DstPort 1 } } } Block { BlockType Scope Name "Scope" Ports [2] Position [585, 14, 625, 96] Floating off Location [5, 49, 1285, 757] Open off NumInputPorts "2" ZoomMode "yonly" List { ListType AxesTitles axes1 "%" axes2 "%" } YMin "-5~-5" YMax "5~5" SaveName "ScopeData2" DataFormat "StructureWithTime" MaxDataPoints "40000" SampleTime "0" } Line { SrcBlock "Logical" SrcPort 1 Points [45, 0] Branch { Points [105, 0] Branch { Points [0, -130] DstBlock "Gateway Out1" DstPort 1 } Branch { Labels [0, 0] DstBlock "Radio 2 I/Q\nBuffer" DstPort 3 } } Branch { Points [0, 150] DstBlock "Radio 2\nRSSI Buffer" DstPort 3 } } Line { SrcBlock "Addr" SrcPort 1 Points [75, 0] Branch { Points [0, -100] DstBlock "Gateway Out" DstPort 1 } Branch { Labels [0, 0] DstBlock "Radio 2 I/Q\nBuffer" DstPort 1 } Branch { Points [0, 150] DstBlock "Radio 2\nRSSI Buffer" DstPort 1 } } Line { SrcBlock "WE" SrcPort 1 DstBlock "Logical" DstPort 1 } Line { SrcBlock "EN" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "Logical" DstPort 2 } Line { SrcBlock "I/Q" SrcPort 1 DstBlock "Radio 2 I/Q\nBuffer" DstPort 2 } Line { SrcBlock "Gateway Out" SrcPort 1 DstBlock "Scope" DstPort 1 } Line { SrcBlock "Gateway Out1" SrcPort 1 DstBlock "Scope" DstPort 2 } Line { SrcBlock "RSSI" SrcPort 1 DstBlock "Radio 2\nRSSI Buffer" DstPort 2 } } } Block { BlockType SubSystem Name "Radio 2\nTx Buffer" Ports [3, 1] Position [1015, 756, 1095, 814] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Radio 2\nTx Buffer" Location [2, 74, 827, 638] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "RdAddr_14b" Position [355, 288, 385, 302] NamePlacement "alternate" IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Inport Name "Rst" Position [30, 173, 60, 187] Port "2" IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Inport Name "En" Position [30, 203, 60, 217] Port "3" IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Reference Name "Constant" Ports [0, 1] Position [630, 350, 655, 370] ShowName off SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" arith_type "Unsigned" const "0" n_bits "32" bin_pt "0" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,400,346" block_type "constant" block_version "10.1.2" sg_icon_stat "25,20,1,1,white,blue,0,72d575a1,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 26 26 ],[0.77 0.82 0.91]);\npatch([20 16 22 16 20 27 29 31 38 32 26 22 28 22 26 32 38 31 29 27 20 ],[3 7 13 19 23 23 21 23 23 17 23 19 13 7 3 9 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 26 26 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'0');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Constant1" Ports [0, 1] Position [355, 345, 380, 365] ShowName off SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" arith_type "Boolean" const "0" n_bits "32" bin_pt "0" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,400,346" block_type "constant" block_version "10.1.2" sg_icon_stat "25,20,1,1,white,blue,0,72d575a1,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 26 26 ],[0.77 0.82 0.91]);\npatch([20 16 22 16 20 27 29 31 38 32 26 22 28 22 26 32 38 31 29 27 20 ],[3 7 13 19 23 23 21 23 23 17 23 19 13 7 3 9 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 26 26 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'0');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Constant2" Ports [0, 1] Position [355, 315, 380, 335] ShowName off SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" arith_type "Unsigned" const "0" n_bits "32" bin_pt "0" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,400,346" block_type "constant" block_version "10.1.2" sg_icon_stat "25,20,1,1,white,blue,0,72d575a1,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 26 26 ],[0.77 0.82 0.91]);\npatch([20 16 22 16 20 27 29 31 38 32 26 22 28 22 26 32 38 31 29 27 20 ],[3 7 13 19 23 23 21 23 23 17 23 19 13 7 3 9 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 26 26 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'0');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Convert" Ports [1, 1] Position [350, 188, 375, 202] ShowName off SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." arith_type "Boolean" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,374,375" block_type "convert" block_version "8.2" sg_icon_stat "25,14,1,1,white,blue,0,74901e60,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([15 10 17 10 15 23 25 27 35 28 22 17 23 17 22 28 35 27 25 23 15 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'cast');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Convert1" Ports [1, 1] Position [100, 203, 120, 217] ShowName off SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." arith_type "Boolean" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,374,375" block_type "convert" block_version "8.2" sg_icon_stat "20,14,1,1,white,blue,0,74901e60,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([15 10 17 10 15 23 25 27 35 28 22 17 23 17 22 28 35 27 25 23 15 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'cast');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Inverter" Ports [1, 1] Position [150, 201, 180, 219] SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "9.1.01" sg_icon_stat "30,18,1,1,white,blue,0,1ab4a85f,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 58 58 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[7 16 29 42 51 51 47 51 51 39 51 42 29 16 7 19 7 7 11 7 7 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Logical" Ports [2, 1] Position [215, 165, 270, 225] SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "9.1.01" sg_icon_stat "55,60,1,1,white,blue,0,f4a65842,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[8 17 30 43 52 52 48 52 52 40 52 43 30 17 8 20 8 8 12 8 8 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newlineor\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Mux" Ports [3, 1] Position [750, 273, 795, 377] SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,303" block_type "mux" block_version "10.1.2" sg_icon_stat "45,104,1,1,white,blue,3,613f58e1,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 ],[0 14.8571 89.1429 104 ],[0.77 0.82 0.91]);\npatch([10 3 14 3 10 22 25 28 41 31 21 14 25 14 21 31 41 28 25 22 10 ],[34 41 52 63 70 70 67 70 70 60 70 63 52 41 34 44 34 34 37 34 34 ],[0.98 0.96 0.92]);\nplot([0 45 45 0 0 ],[0 14.8571 89.1429 104 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('input',3,'d1');\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Shared Memory" Ports [3, 1] Position [445, 280, 525, 370] AttributesFormatString "<< % >>" SourceBlock "xbsIndex_r4/Shared Memory" SourceType "Xilinx Shared Memory Random Access Memory Block" shared_memory_name "'TxBuff_Radio2'" depth "2^14" ownership "Locally Owned and Initialized" initVector "0" mutex "Unprotected" mode "Read and Write" write_mode "Read After Write" time_out "0" latency "1" explicit_data_type on arith_type "Unsigned" n_bits "32" bin_pt "0" xl_use_area off xl_area "[0,0,0,0,0,0,0]" implementation "Block RAM" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,384,381" block_type "shmem" block_version "10.1.2" sg_icon_stat "80,90,1,1,white,blue,0,e2c38f9a,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 80 80 0 ],[0 0 90 90 ],[0.77 0.82 0.91]);\npatch([18 5 24 5 18 39 45 51 74 56 39 27 46 27 39 56 74 51 45 39 18 ],[14 27 46 65 78 78 72 78 78 60 77 65 46 27 15 32 14 14 20 14 14 ],[0.98 0.96 0.92]);\nplot([0 80 80 0 0 ],[0 0 90 90 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'addr');\ncolor('black');port_label('input',2,'din');\ncolor('black');port_label('input',3,'we');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Outport Name "IQ_32b" Position [885, 318, 915, 332] IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Line { SrcBlock "Logical" SrcPort 1 DstBlock "Convert" DstPort 1 } Line { SrcBlock "Convert" SrcPort 1 Points [160, 0; 0, 95] DstBlock "Mux" DstPort 1 } Line { SrcBlock "Rst" SrcPort 1 DstBlock "Logical" DstPort 1 } Line { SrcBlock "En" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "Inverter" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical" DstPort 2 } Line { SrcBlock "RdAddr_14b" SrcPort 1 DstBlock "Shared Memory" DstPort 1 } Line { SrcBlock "Constant" SrcPort 1 DstBlock "Mux" DstPort 3 } Line { SrcBlock "Shared Memory" SrcPort 1 DstBlock "Mux" DstPort 2 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Shared Memory" DstPort 3 } Line { SrcBlock "Constant2" SrcPort 1 DstBlock "Shared Memory" DstPort 2 } Line { SrcBlock "Mux" SrcPort 1 DstBlock "IQ_32b" DstPort 1 } } } Block { BlockType SubSystem Name "Radio 2 Inputs" Ports [2, 2] Position [905, 178, 1085, 227] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Radio 2 Inputs" Location [2, 74, 1014, 726] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "DebugRxBuffers" Position [175, 243, 205, 257] IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Inport Name "MGCAGC_AGCDCO_SEL" Position [175, 333, 205, 347] Port "2" IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType SubSystem Name "ADC I" Ports [2, 2] Position [440, 237, 595, 288] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "ADC I" Location [2, 74, 1014, 726] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Debug" Position [695, 53, 725, 67] IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Inport Name "MGCAGC_AGCDCO_SEL" Position [210, 243, 240, 257] Port "2" IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Constant Name "Constant1" Position [25, 320, 55, 350] ShowName off Value "0" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Reference Name "Counter" Ports [0, 1] Position [530, 340, 590, 400] SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited counter is implemented by combining a counter with a comparator." cnt_type "Free Running" cnt_to "Inf" operation "Down" start_count "2^14-1" cnt_by_val "1" arith_type "Unsigned" n_bits "14" bin_pt "0" load_pin off rst off en off explicit_period "on" period "1" dbl_ovrd off use_behavioral_HDL off use_rpm off implementation "Fabric" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,619" block_type "counter" block_version "10.1.3" sg_icon_stat "60,60,1,1,white,blue,0,a170c862,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([14 4 18 4 14 30 34 38 55 42 29 20 35 20 29 42 55 38 34 30 14 ],[6 16 30 44 54 54 50 54 54 41 54 45 30 15 6 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'out');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "FromAGC_Radio2_I" Ports [1, 1] Position [170, 425, 235, 445] SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, double and fixed point to Xilinx fixed point type.

Hardware notes: In hardware these blocks become top level input ports." arith_type "Signed (2's comp)" n_bits "14" bin_pt "13" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,406" block_type "gatewayin" block_version "10.1.3" sg_icon_stat "65,20,1,1,white,yellow,0,bc55d28f,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([27 24 29 24 27 32 33 34 40 36 32 29 34 29 32 36 40 34 33 32 27 ],[2 5 10 15 18 18 17 18 18 14 18 15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Mux" Ports [3, 1] Position [830, 88, 875, 192] SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "1" bin_pt "0" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,303" block_type "mux" block_version "10.1.3" sg_icon_stat "45,104,1,1,white,blue,3,613f58e1,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 ],[0 14.8571 89.1429 104 ],[0.77 0.82 0.91]);\npatch([10 3 14 3 10 22 25 28 41 31 21 14 25 14 21 31 41 28 25 22 10 ],[34 41 52 63 70 70 67 70 70 60 70 63 52 41 34 44 34 34 37 34 34 ],[0.98 0.96 0.92]);\nplot([0 45 45 0 0 ],[0 14.8571 89.1429 104 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('input',3,'d1');\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Mux1" Ports [3, 1] Position [830, 283, 875, 387] SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "1" bin_pt "0" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,303" block_type "mux" block_version "10.1.3" sg_icon_stat "45,104,1,1,white,blue,3,613f58e1,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 ],[0 14.8571 89.1429 104 ],[0.77 0.82 0.91]);\npatch([10 3 14 3 10 22 25 28 41 31 21 14 25 14 21 31 41 28 25 22 10 ],[34 41 52 63 70 70 67 70 70 60 70 63 52 41 34 44 34 34 37 34 34 ],[0.98 0.96 0.92]);\nplot([0 45 45 0 0 ],[0 14.8571 89.1429 104 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('input',3,'d1');\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Mux2" Ports [3, 1] Position [355, 283, 400, 387] SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "1" bin_pt "0" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,303" block_type "mux" block_version "10.1.3" sg_icon_stat "45,104,1,1,white,blue,3,613f58e1,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 ],[0 14.8571 89.1429 104 ],[0.77 0.82 0.91]);\npatch([10 3 14 3 10 22 25 28 41 31 21 14 25 14 21 31 41 28 25 22 10 ],[34 41 52 63 70 70 67 70 70 60 70 63 52 41 34 44 34 34 37 34 34 ],[0.98 0.96 0.92]);\nplot([0 45 45 0 0 ],[0 14.8571 89.1429 104 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('input',3,'d1');\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Radio 2 ADC I" Ports [1, 1] Position [150, 314, 245, 356] LinkData { BlockName "radio2_adc_I" DialogParameters { sg_icon_stat "65,20,1,1,white,yellow,0,bc55d28f,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([27 24 29 24 27 32 33 34 40 36 32 29 34 29 32 36 40 34 33 32 27 ],[2 5 10 15 18 18 17 18 18 14 18 15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end icon text');\n" } } SourceBlock "WARP_Blockset/WARP Radio Board ADC//DACs/Radio 2 ADC I" SourceType "" ShowPortLabels "FromPortIcon" SystemSampleTime "-1" FunctionWithSeparateData off RTWMemSecFuncInitTerm "Inherit from model" RTWMemSecFuncExecute "Inherit from model" RTWMemSecDataConstants "Inherit from model" RTWMemSecDataInternal "Inherit from model" RTWMemSecDataParameters "Inherit from model" samp_period "1" } Block { BlockType Reference Name "Register" Ports [1, 1] Position [460, 321, 495, 349] ShowName off SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "8.2" sg_icon_stat "35,28,1,1,white,blue,0,ac6b57db,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('\\bf{z^{-1}}','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Reinterpret" Ports [1, 1] Position [675, 354, 725, 386] SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can changed the signal between signed and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothing.

Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsigned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111000 in binary)." force_arith_type on arith_type "Signed (2's comp)" force_bin_pt on bin_pt "13" has_advanced_control "0" sggui_pos "20,20,336,312" block_type "reinterpret" block_version "10.1.3" sg_icon_stat "50,32,1,1,white,blue,0,8982c1db,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 ],[0 0 32 32 ],[0.77 0.82 0.91]);\npatch([16 11 18 11 16 24 26 28 37 30 23 18 25 18 23 30 37 28 26 24 16 ],[3 8 15 22 27 27 25 27 27 20 27 22 15 8 3 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 50 50 0 0 ],[0 0 32 32 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('reinterpret');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Slice" Ports [1, 1] Position [680, 160, 740, 190] SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,376" block_type "slice" block_version "10.1.3" sg_icon_stat "60,30,1,1,white,blue,0,b1026674,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "radio2_ADC_I_OTR" Ports [1, 1] Position [295, 134, 350, 146] NamePlacement "alternate" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, double and fixed point to Xilinx fixed point type.

Hardware notes: In hardware these blocks become top level input ports." arith_type "Unsigned" n_bits "1" bin_pt "0" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,356,432" block_type "gatewayin" block_version "VER_STRING_GOES_HERE" sg_icon_stat "55,12,1,1,white,yellow,0,bc55d28f,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([27 24 29 24 27 32 33 34 40 36 32 29 34 29 32 36 40 34 33 32 27 ],[2 5 10 15 18 18 17 18 18 14 18 15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Outport Name "OTR I" Position [935, 133, 965, 147] IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Outport Name "ADC I" Position [935, 328, 965, 342] Port "2" IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Line { SrcBlock "Constant1" SrcPort 1 Points [20, 0] Branch { Points [0, -195] DstBlock "radio2_ADC_I_OTR" DstPort 1 } Branch { DstBlock "Radio 2 ADC I" DstPort 1 } Branch { Points [0, 100] DstBlock "FromAGC_Radio2_I" DstPort 1 } } Line { SrcBlock "Mux" SrcPort 1 DstBlock "OTR I" DstPort 1 } Line { SrcBlock "Debug" SrcPort 1 Points [40, 0; 0, 45] Branch { DstBlock "Mux" DstPort 1 } Branch { Points [0, 195] DstBlock "Mux1" DstPort 1 } } Line { SrcBlock "radio2_ADC_I_OTR" SrcPort 1 DstBlock "Mux" DstPort 2 } Line { SrcBlock "Slice" SrcPort 1 DstBlock "Mux" DstPort 3 } Line { SrcBlock "Mux1" SrcPort 1 DstBlock "ADC I" DstPort 1 } Line { SrcBlock "Register" SrcPort 1 DstBlock "Mux1" DstPort 2 } Line { SrcBlock "Reinterpret" SrcPort 1 DstBlock "Mux1" DstPort 3 } Line { SrcBlock "Counter" SrcPort 1 Points [25, 0] Branch { DstBlock "Reinterpret" DstPort 1 } Branch { Points [0, -195] DstBlock "Slice" DstPort 1 } } Line { SrcBlock "MGCAGC_AGCDCO_SEL" SrcPort 1 Points [70, 0; 0, 50] DstBlock "Mux2" DstPort 1 } Line { SrcBlock "FromAGC_Radio2_I" SrcPort 1 Points [75, 0; 0, -65] DstBlock "Mux2" DstPort 3 } Line { SrcBlock "Mux2" SrcPort 1 DstBlock "Register" DstPort 1 } Line { SrcBlock "Radio 2 ADC I" SrcPort 1 DstBlock "Mux2" DstPort 2 } } } Block { BlockType SubSystem Name "ADC Q" Ports [2, 2] Position [440, 304, 595, 351] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "ADC Q" Location [66, 91, 1078, 743] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Debug" Position [670, 43, 700, 57] IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Inport Name "MGCAGC_AGCDCO_SEL" Position [135, 233, 165, 247] Port "2" IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Constant Name "Constant1" Position [15, 310, 45, 340] ShowName off Value "0" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Reference Name "Counter" Ports [0, 1] Position [500, 330, 560, 390] SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited counter is implemented by combining a counter with a comparator." cnt_type "Free Running" cnt_to "Inf" operation "Up" start_count "0" cnt_by_val "1" arith_type "Unsigned" n_bits "14" bin_pt "0" load_pin off rst off en off explicit_period "on" period "1" dbl_ovrd off use_behavioral_HDL off use_rpm off implementation "Fabric" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,619" block_type "counter" block_version "10.1.3" sg_icon_stat "60,60,1,1,white,blue,0,a170c862,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([14 4 18 4 14 30 34 38 55 42 29 20 35 20 29 42 55 38 34 30 14 ],[6 16 30 44 54 54 50 54 54 41 54 45 30 15 6 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'out');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "FromAGC_Radio2_Q" Ports [1, 1] Position [120, 415, 185, 435] SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, double and fixed point to Xilinx fixed point type.

Hardware notes: In hardware these blocks become top level input ports." arith_type "Signed (2's comp)" n_bits "14" bin_pt "13" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,406" block_type "gatewayin" block_version "10.1.3" sg_icon_stat "65,20,1,1,white,yellow,0,bc55d28f,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([27 24 29 24 27 32 33 34 40 36 32 29 34 29 32 36 40 34 33 32 27 ],[2 5 10 15 18 18 17 18 18 14 18 15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Mux" Ports [3, 1] Position [805, 78, 850, 182] SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "1" bin_pt "0" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,303" block_type "mux" block_version "10.1.3" sg_icon_stat "45,104,1,1,white,blue,3,613f58e1,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 ],[0 14.8571 89.1429 104 ],[0.77 0.82 0.91]);\npatch([10 3 14 3 10 22 25 28 41 31 21 14 25 14 21 31 41 28 25 22 10 ],[34 41 52 63 70 70 67 70 70 60 70 63 52 41 34 44 34 34 37 34 34 ],[0.98 0.96 0.92]);\nplot([0 45 45 0 0 ],[0 14.8571 89.1429 104 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('input',3,'d1');\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Mux1" Ports [3, 1] Position [805, 273, 850, 377] SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "1" bin_pt "0" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,303" block_type "mux" block_version "10.1.3" sg_icon_stat "45,104,1,1,white,blue,3,613f58e1,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 ],[0 14.8571 89.1429 104 ],[0.77 0.82 0.91]);\npatch([10 3 14 3 10 22 25 28 41 31 21 14 25 14 21 31 41 28 25 22 10 ],[34 41 52 63 70 70 67 70 70 60 70 63 52 41 34 44 34 34 37 34 34 ],[0.98 0.96 0.92]);\nplot([0 45 45 0 0 ],[0 14.8571 89.1429 104 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('input',3,'d1');\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Mux2" Ports [3, 1] Position [280, 273, 325, 377] SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "1" bin_pt "0" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,303" block_type "mux" block_version "10.1.3" sg_icon_stat "45,104,1,1,white,blue,3,613f58e1,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 ],[0 14.8571 89.1429 104 ],[0.77 0.82 0.91]);\npatch([10 3 14 3 10 22 25 28 41 31 21 14 25 14 21 31 41 28 25 22 10 ],[34 41 52 63 70 70 67 70 70 60 70 63 52 41 34 44 34 34 37 34 34 ],[0.98 0.96 0.92]);\nplot([0 45 45 0 0 ],[0 14.8571 89.1429 104 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('input',3,'d1');\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Radio 2 ADC Q" Ports [1, 1] Position [100, 304, 195, 346] LinkData { BlockName "radio2_adc_Q" DialogParameters { sg_icon_stat "65,20,1,1,white,yellow,0,bc55d28f,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([27 24 29 24 27 32 33 34 40 36 32 29 34 29 32 36 40 34 33 32 27 ],[2 5 10 15 18 18 17 18 18 14 18 15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end icon text');\n" } } SourceBlock "WARP_Blockset/WARP Radio Board ADC//DACs/Radio 2 ADC Q" SourceType "" ShowPortLabels "FromPortIcon" SystemSampleTime "-1" FunctionWithSeparateData off RTWMemSecFuncInitTerm "Inherit from model" RTWMemSecFuncExecute "Inherit from model" RTWMemSecDataConstants "Inherit from model" RTWMemSecDataInternal "Inherit from model" RTWMemSecDataParameters "Inherit from model" samp_period "1" } Block { BlockType Reference Name "Register" Ports [1, 1] Position [430, 311, 465, 339] ShowName off SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "8.2" sg_icon_stat "35,28,1,1,white,blue,0,ac6b57db,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('\\bf{z^{-1}}','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Reinterpret" Ports [1, 1] Position [650, 344, 700, 376] SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can changed the signal between signed and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothing.

Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsigned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111000 in binary)." force_arith_type on arith_type "Signed (2's comp)" force_bin_pt on bin_pt "13" has_advanced_control "0" sggui_pos "20,20,336,312" block_type "reinterpret" block_version "10.1.3" sg_icon_stat "50,32,1,1,white,blue,0,8982c1db,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 ],[0 0 32 32 ],[0.77 0.82 0.91]);\npatch([16 11 18 11 16 24 26 28 37 30 23 18 25 18 23 30 37 28 26 24 16 ],[3 8 15 22 27 27 25 27 27 20 27 22 15 8 3 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 50 50 0 0 ],[0 0 32 32 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('reinterpret');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Slice" Ports [1, 1] Position [655, 150, 715, 180] SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,376" block_type "slice" block_version "10.1.3" sg_icon_stat "60,30,1,1,white,blue,0,b1026674,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "radio2_ADC_Q_OTR" Ports [1, 1] Position [240, 124, 295, 136] SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, double and fixed point to Xilinx fixed point type.

Hardware notes: In hardware these blocks become top level input ports." arith_type "Unsigned" n_bits "1" bin_pt "0" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,356,432" block_type "gatewayin" block_version "VER_STRING_GOES_HERE" sg_icon_stat "55,12,1,1,white,yellow,0,bc55d28f,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([27 24 29 24 27 32 33 34 40 36 32 29 34 29 32 36 40 34 33 32 27 ],[2 5 10 15 18 18 17 18 18 14 18 15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Outport Name "OTR Q" Position [945, 123, 975, 137] IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Outport Name "ADC Q" Position [945, 318, 975, 332] Port "2" IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Line { SrcBlock "Constant1" SrcPort 1 Points [10, 0] Branch { Points [0, 0] Branch { Points [0, 0; 0, -195] DstBlock "radio2_ADC_Q_OTR" DstPort 1 } Branch { DstBlock "Radio 2 ADC Q" DstPort 1 } } Branch { Points [0, 100] DstBlock "FromAGC_Radio2_Q" DstPort 1 } } Line { SrcBlock "Mux" SrcPort 1 DstBlock "OTR Q" DstPort 1 } Line { SrcBlock "Debug" SrcPort 1 Points [40, 0; 0, 45] Branch { DstBlock "Mux" DstPort 1 } Branch { Points [0, 195] DstBlock "Mux1" DstPort 1 } } Line { SrcBlock "radio2_ADC_Q_OTR" SrcPort 1 DstBlock "Mux" DstPort 2 } Line { SrcBlock "Slice" SrcPort 1 DstBlock "Mux" DstPort 3 } Line { SrcBlock "Mux1" SrcPort 1 DstBlock "ADC Q" DstPort 1 } Line { SrcBlock "Register" SrcPort 1 DstBlock "Mux1" DstPort 2 } Line { SrcBlock "Reinterpret" SrcPort 1 DstBlock "Mux1" DstPort 3 } Line { SrcBlock "Counter" SrcPort 1 Points [30, 0] Branch { DstBlock "Reinterpret" DstPort 1 } Branch { Points [0, -195] DstBlock "Slice" DstPort 1 } } Line { SrcBlock "MGCAGC_AGCDCO_SEL" SrcPort 1 Points [70, 0; 0, 50] DstBlock "Mux2" DstPort 1 } Line { SrcBlock "FromAGC_Radio2_Q" SrcPort 1 Points [50, 0; 0, -65] DstBlock "Mux2" DstPort 3 } Line { SrcBlock "Radio 2 ADC Q" SrcPort 1 DstBlock "Mux2" DstPort 2 } Line { SrcBlock "Mux2" SrcPort 1 DstBlock "Register" DstPort 1 } } } Block { BlockType SubSystem Name "Concatenates_1" Ports [4, 1] Position [695, 218, 740, 372] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Concatenates_1" Location [2, 74, 1270, 726] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "OTR_I" Position [395, 43, 425, 57] IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Inport Name "ADC_I" Position [330, 93, 360, 107] Port "2" IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Inport Name "OTR_Q" Position [390, 163, 420, 177] Port "3" IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Inport Name "ADC_Q" Position [330, 213, 360, 227] Port "4" IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Reference Name "Concat1" Ports [2, 1] Position [490, 191, 520, 229] ShowName off SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point at zero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" block_version "8.2" sg_icon_stat "30,38,1,1,white,blue,0,df1e5aba,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([14 4 18 4 14 30 34 38 55 42 29 20 35 20 29 42 55 38 34 30 14 ],[6 16 30 44 54 54 50 54 54 41 54 45 30 15 6 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'hi');\ncolor('black');port_label('input',2,'lo');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Concat2" Ports [2, 1] Position [490, 71, 520, 109] ShowName off SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point at zero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" block_version "8.2" sg_icon_stat "30,38,1,1,white,blue,0,df1e5aba,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([14 4 18 4 14 30 34 38 55 42 29 20 35 20 29 42 55 38 34 30 14 ],[6 16 30 44 54 54 50 54 54 41 54 45 30 15 6 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'hi');\ncolor('black');port_label('input',2,'lo');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Concat3" Ports [2, 1] Position [550, 150, 575, 230] ShowName off SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point at zero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" block_version "8.2" sg_icon_stat "25,80,1,1,white,blue,0,df1e5aba,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([14 4 18 4 14 30 34 38 55 42 29 20 35 20 29 42 55 38 34 30 14 ],[6 16 30 44 54 54 50 54 54 41 54 45 30 15 6 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'hi');\ncolor('black');port_label('input',2,'lo');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Concat4" Ports [2, 1] Position [550, 30, 575, 110] ShowName off SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point at zero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" block_version "8.2" sg_icon_stat "25,80,1,1,white,blue,0,df1e5aba,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([14 4 18 4 14 30 34 38 55 42 29 20 35 20 29 42 55 38 34 30 14 ],[6 16 30 44 54 54 50 54 54 41 54 45 30 15 6 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'hi');\ncolor('black');port_label('input',2,'lo');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Concat5" Ports [2, 1] Position [635, 50, 660, 130] ShowName off SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point at zero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" block_version "8.2" sg_icon_stat "25,80,1,1,white,blue,0,df1e5aba,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([14 4 18 4 14 30 34 38 55 42 29 20 35 20 29 42 55 38 34 30 14 ],[6 16 30 44 54 54 50 54 54 41 54 45 30 15 6 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'hi');\ncolor('black');port_label('input',2,'lo');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Reinterpret" Ports [1, 1] Position [385, 90, 420, 110] ShowName off SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can changed the signal between signed and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothing.

Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsigned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111000 in binary)." force_arith_type on arith_type "Unsigned" force_bin_pt on bin_pt "0" has_advanced_control "0" sggui_pos "20,20,356,309" block_type "reinterpret" block_version "8.2" sg_icon_stat "35,20,1,1,white,blue,0,8982c1db,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 ],[0 0 32 32 ],[0.77 0.82 0.91]);\npatch([16 11 18 11 16 24 26 28 37 30 23 18 25 18 23 30 37 28 26 24 16 ],[3 8 15 22 27 27 25 27 27 20 27 22 15 8 3 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 50 50 0 0 ],[0 0 32 32 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('reinterpret');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Reinterpret1" Ports [1, 1] Position [390, 210, 425, 230] ShowName off SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can changed the signal between signed and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothing.

Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsigned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111000 in binary)." force_arith_type on arith_type "Unsigned" force_bin_pt on bin_pt "0" has_advanced_control "0" sggui_pos "20,20,356,309" block_type "reinterpret" block_version "8.2" sg_icon_stat "35,20,1,1,white,blue,0,8982c1db,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 ],[0 0 32 32 ],[0.77 0.82 0.91]);\npatch([16 11 18 11 16 24 26 28 37 30 23 18 25 18 23 30 37 28 26 24 16 ],[3 8 15 22 27 27 25 27 27 20 27 22 15 8 3 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 50 50 0 0 ],[0 0 32 32 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('reinterpret');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "zero" Ports [0, 1] Position [440, 191, 460, 209] ShowName off SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" arith_type "Unsigned" const "0" n_bits "1" bin_pt "0" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "20,18,1,1,white,blue,0,72d575a1,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 26 26 ],[0.77 0.82 0.91]);\npatch([20 16 22 16 20 27 29 31 38 32 26 22 28 22 26 32 38 31 29 27 20 ],[3 7 13 19 23 23 21 23 23 17 23 19 13 7 3 9 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 26 26 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'0');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "zero1" Ports [0, 1] Position [440, 71, 460, 89] ShowName off SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" arith_type "Unsigned" const "0" n_bits "1" bin_pt "0" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "20,18,1,1,white,blue,0,72d575a1,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 26 26 ],[0.77 0.82 0.91]);\npatch([20 16 22 16 20 27 29 31 38 32 26 22 28 22 26 32 38 31 29 27 20 ],[3 7 13 19 23 23 21 23 23 17 23 19 13 7 3 9 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 26 26 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'0');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Outport Name "32b" Position [685, 83, 715, 97] IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Line { SrcBlock "Reinterpret1" SrcPort 1 DstBlock "Concat1" DstPort 2 } Line { SrcBlock "Reinterpret" SrcPort 1 DstBlock "Concat2" DstPort 2 } Line { SrcBlock "ADC_Q" SrcPort 1 DstBlock "Reinterpret1" DstPort 1 } Line { SrcBlock "OTR_Q" SrcPort 1 DstBlock "Concat3" DstPort 1 } Line { SrcBlock "ADC_I" SrcPort 1 DstBlock "Reinterpret" DstPort 1 } Line { SrcBlock "Concat5" SrcPort 1 DstBlock "32b" DstPort 1 } Line { SrcBlock "OTR_I" SrcPort 1 DstBlock "Concat4" DstPort 1 } Line { SrcBlock "Concat3" SrcPort 1 Points [25, 0; 0, -80] DstBlock "Concat5" DstPort 2 } Line { SrcBlock "Concat4" SrcPort 1 DstBlock "Concat5" DstPort 1 } Line { SrcBlock "Concat2" SrcPort 1 Points [0, 0] DstBlock "Concat4" DstPort 2 } Line { SrcBlock "zero1" SrcPort 1 DstBlock "Concat2" DstPort 1 } Line { SrcBlock "Concat1" SrcPort 1 DstBlock "Concat3" DstPort 2 } Line { SrcBlock "zero" SrcPort 1 DstBlock "Concat1" DstPort 1 } } } Block { BlockType Reference Name "Gateway Out1" Ports [1, 1] Position [710, 135, 740, 145] ShowName off SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, double, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarded, depending on how they are configured." hdl_port off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,336,386" block_type "gatewayout" block_version "10.1.2" sg_icon_stat "30,10,1,1,white,grey,0,b3a044a9,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 ],[0 0 10 10 ],[0.88 0.88 0.88]);\npatch([13 11 13 11 13 16 17 18 21 19 17 15 17 15 17 19 21 18 17 16 13 ],[1 3 5 7 9 9 8 9 9 7 9 7 5 3 1 3 1 1 2 1 1 ],[0.98 0.96 0.92]);\nplot([0 30 30 0 0 ],[0 0 10 10 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Gateway Out4" Ports [1, 1] Position [710, 120, 740, 130] ShowName off SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, double, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarded, depending on how they are configured." hdl_port off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,336,386" block_type "gatewayout" block_version "10.1.2" sg_icon_stat "30,10,1,1,white,grey,0,b3a044a9,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 ],[0 0 10 10 ],[0.88 0.88 0.88]);\npatch([13 11 13 11 13 16 17 18 21 19 17 15 17 15 17 19 21 18 17 16 13 ],[1 3 5 7 9 9 8 9 9 7 9 7 5 3 1 3 1 1 2 1 1 ],[0.98 0.96 0.92]);\nplot([0 30 30 0 0 ],[0 0 10 10 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType SubSystem Name "RSSI" Ports [1, 1] Position [490, 392, 560, 428] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "RSSI" Location [2, 74, 1184, 726] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Debug" Position [465, 28, 495, 42] IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Constant Name "Constant1" Position [160, 100, 190, 130] ShowName off Value "0" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Reference Name "Counter" Ports [0, 1] Position [380, 120, 440, 180] SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited counter is implemented by combining a counter with a comparator." cnt_type "Free Running" cnt_to "Inf" operation "Up" start_count "0" cnt_by_val "1" arith_type "Unsigned" n_bits "10" bin_pt "0" load_pin off rst off en off explicit_period "on" period "1" dbl_ovrd off use_behavioral_HDL off use_rpm off implementation "Fabric" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,619" block_type "counter" block_version "10.1.3" sg_icon_stat "60,60,1,1,white,blue,0,a170c862,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([14 4 18 4 14 30 34 38 55 42 29 20 35 20 29 42 55 38 34 30 14 ],[6 16 30 44 54 54 50 54 54 41 54 45 30 15 6 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'out');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Mux" Ports [3, 1] Position [600, 63, 645, 167] SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "1" bin_pt "0" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,303" block_type "mux" block_version "10.1.3" sg_icon_stat "45,104,1,1,white,blue,3,613f58e1,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 ],[0 14.8571 89.1429 104 ],[0.77 0.82 0.91]);\npatch([10 3 14 3 10 22 25 28 41 31 21 14 25 14 21 31 41 28 25 22 10 ],[34 41 52 63 70 70 67 70 70 60 70 63 52 41 34 44 34 34 37 34 34 ],[0.98 0.96 0.92]);\nplot([0 45 45 0 0 ],[0 14.8571 89.1429 104 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('input',3,'d1');\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "radio2_RSSI" Ports [1, 1] Position [280, 109, 335, 121] NamePlacement "alternate" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, double and fixed point to Xilinx fixed point type.

Hardware notes: In hardware these blocks become top level input ports." arith_type "Unsigned" n_bits "10" bin_pt "0" quantization "Truncate" overflow "Wrap" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,356,432" block_type "gatewayin" block_version "VER_STRING_GOES_HERE" sg_icon_stat "55,12,1,1,white,yellow,0,bc55d28f,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([27 24 29 24 27 32 33 34 40 36 32 29 34 29 32 36 40 34 33 32 27 ],[2 5 10 15 18 18 17 18 18 14 18 15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Outport Name "RSSI" Position [740, 108, 770, 122] IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "radio2_RSSI" DstPort 1 } Line { SrcBlock "Debug" SrcPort 1 Points [40, 0; 0, 45] DstBlock "Mux" DstPort 1 } Line { SrcBlock "radio2_RSSI" SrcPort 1 DstBlock "Mux" DstPort 2 } Line { SrcBlock "Counter" SrcPort 1 DstBlock "Mux" DstPort 3 } Line { SrcBlock "Mux" SrcPort 1 DstBlock "RSSI" DstPort 1 } } } Block { BlockType Scope Name "Scope" Ports [2] Position [800, 111, 830, 164] Floating off Location [5, 34, 1285, 912] Open off NumInputPorts "2" List { ListType AxesTitles axes1 "%" axes2 "%" } YMin "-5~-5" YMax "5~5" DataFormat "StructureWithTime" SampleTime "0" } Block { BlockType Outport Name "Radio 2 RSSI" Position [655, 403, 685, 417] IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Outport Name "Radio 2 I/Q" Position [865, 288, 895, 302] Port "2" IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Line { SrcBlock "ADC Q" SrcPort 2 Points [35, 0; 0, 20; 30, 0] Branch { DstBlock "Concatenates_1" DstPort 4 } Branch { Points [0, -215] DstBlock "Gateway Out1" DstPort 1 } } Line { SrcBlock "ADC Q" SrcPort 1 DstBlock "Concatenates_1" DstPort 3 } Line { Labels [0, 0] SrcBlock "ADC I" SrcPort 2 Points [55, 0] Branch { DstBlock "Concatenates_1" DstPort 2 } Branch { Points [0, -150] DstBlock "Gateway Out4" DstPort 1 } } Line { SrcBlock "ADC I" SrcPort 1 Points [15, 0; 0, -15] DstBlock "Concatenates_1" DstPort 1 } Line { SrcBlock "Concatenates_1" SrcPort 1 Points [0, 0] DstBlock "Radio 2 I/Q" DstPort 1 } Line { SrcBlock "Gateway Out4" SrcPort 1 DstBlock "Scope" DstPort 1 } Line { SrcBlock "Gateway Out1" SrcPort 1 Points [40, 0] DstBlock "Scope" DstPort 2 } Line { SrcBlock "DebugRxBuffers" SrcPort 1 Points [165, 0] Branch { DstBlock "ADC I" DstPort 1 } Branch { Points [0, 65] Branch { DstBlock "ADC Q" DstPort 1 } Branch { Points [0, 95] DstBlock "RSSI" DstPort 1 } } } Line { SrcBlock "RSSI" SrcPort 1 DstBlock "Radio 2 RSSI" DstPort 1 } Line { SrcBlock "MGCAGC_AGCDCO_SEL" SrcPort 1 Points [115, 0] Branch { Points [0, -65] DstBlock "ADC I" DstPort 2 } Branch { DstBlock "ADC Q" DstPort 2 } } } } Block { BlockType SubSystem Name "Radio 2 Outputs" Ports [1] Position [1180, 761, 1230, 809] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Radio 2 Outputs" Location [2, 74, 1078, 531] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "32b" Position [250, 93, 280, 107] IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Reference Name "16LSB" Ports [1, 1] Position [430, 92, 470, 108] SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardware notes: In hardware this block costs nothing." nbits "16" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,442,407" block_type "slice" block_version "8.2" sg_icon_stat "40,16,1,1,white,blue,0,b1026674,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "16MSB" Ports [1, 1] Position [430, 36, 470, 54] NamePlacement "alternate" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardware notes: In hardware this block costs nothing." nbits "16" boolean_output off mode "Upper Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,442,407" block_type "slice" block_version "8.2" sg_icon_stat "40,18,1,1,white,blue,0,b1026674,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Radio 2 DAC I" Ports [1, 1] Position [680, 24, 775, 66] LinkData { BlockName "Convert" DialogParameters { sg_icon_stat "45,30,1,1,white,blue,0,74901e60,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([15 10 17 10 15 23 25 27 35 28 22 17 23 17 22 28 35 27 25 23 15 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'cast');\nfprintf('','COMMENT: end icon text');\n" } BlockName "radio2_dac_I" DialogParameters { sg_icon_stat "60,20,1,1,white,yellow,0,38220381,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([24 21 26 21 24 29 30 31 37 33 29 26 31 26 29 33 37 31 30 29 24 ],[2 5 10 15 18 18 17 18 18 14 18 15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } } SourceBlock "WARP_Blockset/WARP Radio Board ADC//DACs/Radio 2 DAC I" SourceType "" ShowPortLabels "FromPortIcon" SystemSampleTime "-1" FunctionWithSeparateData off RTWMemSecFuncInitTerm "Inherit from model" RTWMemSecFuncExecute "Inherit from model" RTWMemSecDataConstants "Inherit from model" RTWMemSecDataInternal "Inherit from model" RTWMemSecDataParameters "Inherit from model" } Block { BlockType Reference Name "Radio 2 DAC Q" Ports [1, 1] Position [680, 79, 775, 121] LinkData { BlockName "Convert" DialogParameters { sg_icon_stat "45,30,1,1,white,blue,0,74901e60,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([15 10 17 10 15 23 25 27 35 28 22 17 23 17 22 28 35 27 25 23 15 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'cast');\nfprintf('','COMMENT: end icon text');\n" } BlockName "radio2_dac_Q" DialogParameters { sg_icon_stat "60,20,1,1,white,yellow,0,38220381,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([24 21 26 21 24 29 30 31 37 33 29 26 31 26 29 33 37 31 30 29 24 ],[2 5 10 15 18 18 17 18 18 14 18 15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } } SourceBlock "WARP_Blockset/WARP Radio Board ADC//DACs/Radio 2 DAC Q" SourceType "" ShowPortLabels "FromPortIcon" SystemSampleTime "-1" FunctionWithSeparateData off RTWMemSecFuncInitTerm "Inherit from model" RTWMemSecFuncExecute "Inherit from model" RTWMemSecDataConstants "Inherit from model" RTWMemSecDataInternal "Inherit from model" RTWMemSecDataParameters "Inherit from model" } Block { BlockType Reference Name "Register" Ports [1, 1] Position [595, 31, 630, 59] ShowName off SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "8.2" sg_icon_stat "35,28,1,1,white,blue,0,ac6b57db,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('\\bf{z^{-1}}','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Register1" Ports [1, 1] Position [595, 86, 630, 114] ShowName off SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "8.2" sg_icon_stat "35,28,1,1,white,blue,0,ac6b57db,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('\\bf{z^{-1}}','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Reinterpret" Ports [1, 1] Position [530, 35, 575, 55] ShowName off SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can changed the signal between signed and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothing.

Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsigned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111000 in binary)." force_arith_type on arith_type "Signed (2's comp)" force_bin_pt on bin_pt "15" has_advanced_control "0" sggui_pos "20,20,356,309" block_type "reinterpret" block_version "8.2" sg_icon_stat "45,20,1,1,white,blue,0,8982c1db,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 ],[0 0 32 32 ],[0.77 0.82 0.91]);\npatch([16 11 18 11 16 24 26 28 37 30 23 18 25 18 23 30 37 28 26 24 16 ],[3 8 15 22 27 27 25 27 27 20 27 22 15 8 3 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 50 50 0 0 ],[0 0 32 32 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('reinterpret');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Reinterpret1" Ports [1, 1] Position [530, 90, 575, 110] ShowName off SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can changed the signal between signed and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothing.

Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsigned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111000 in binary)." force_arith_type on arith_type "Signed (2's comp)" force_bin_pt on bin_pt "15" has_advanced_control "0" sggui_pos "20,20,356,309" block_type "reinterpret" block_version "8.2" sg_icon_stat "45,20,1,1,white,blue,0,8982c1db,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 ],[0 0 32 32 ],[0.77 0.82 0.91]);\npatch([16 11 18 11 16 24 26 28 37 30 23 18 25 18 23 30 37 28 26 24 16 ],[3 8 15 22 27 27 25 27 27 20 27 22 15 8 3 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 50 50 0 0 ],[0 0 32 32 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('reinterpret');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Terminator Name "Terminator1" Position [840, 35, 860, 55] ShowName off } Block { BlockType Terminator Name "Terminator2" Position [840, 90, 860, 110] ShowName off } Line { SrcBlock "Radio 2 DAC Q" SrcPort 1 DstBlock "Terminator2" DstPort 1 } Line { SrcBlock "Radio 2 DAC I" SrcPort 1 DstBlock "Terminator1" DstPort 1 } Line { SrcBlock "Reinterpret1" SrcPort 1 DstBlock "Register1" DstPort 1 } Line { SrcBlock "Reinterpret" SrcPort 1 DstBlock "Register" DstPort 1 } Line { SrcBlock "16LSB" SrcPort 1 DstBlock "Reinterpret1" DstPort 1 } Line { SrcBlock "16MSB" SrcPort 1 DstBlock "Reinterpret" DstPort 1 } Line { SrcBlock "Register" SrcPort 1 DstBlock "Radio 2 DAC I" DstPort 1 } Line { SrcBlock "Register1" SrcPort 1 DstBlock "Radio 2 DAC Q" DstPort 1 } Line { SrcBlock "32b" SrcPort 1 Points [65, 0] Branch { Points [0, -55] DstBlock "16MSB" DstPort 1 } Branch { DstBlock "16LSB" DstPort 1 } } } } Block { BlockType SubSystem Name "Radio 3\nRx Buffers" Ports [5] Position [1175, 323, 1240, 427] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Radio 3\nRx Buffers" Location [2, 74, 1014, 726] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "RSSI" Position [450, 313, 480, 327] IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Inport Name "I/Q" Position [545, 163, 575, 177] Port "2" IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Inport Name "Addr" Position [325, 128, 355, 142] Port "3" IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Inport Name "WE" Position [110, 183, 140, 197] Port "4" IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Inport Name "EN" Position [110, 213, 140, 227] Port "5" IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Reference Name "Convert1" Ports [1, 1] Position [185, 212, 210, 228] ShowName off SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." arith_type "Boolean" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,461,375" block_type "convert" block_version "8.2" sg_icon_stat "25,16,1,1,white,blue,0,74901e60,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([15 10 17 10 15 23 25 27 35 28 22 17 23 17 22 28 35 27 25 23 15 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'cast');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Gateway Out" Ports [1, 1] Position [500, 30, 530, 40] ShowName off SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, double, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarded, depending on how they are configured." hdl_port off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,336,386" block_type "gatewayout" block_version "10.1.2" sg_icon_stat "30,10,1,1,white,grey,0,b3a044a9,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 ],[0 0 10 10 ],[0.88 0.88 0.88]);\npatch([13 11 13 11 13 16 17 18 21 19 17 15 17 15 17 19 21 18 17 16 13 ],[1 3 5 7 9 9 8 9 9 7 9 7 5 3 1 3 1 1 2 1 1 ],[0.98 0.96 0.92]);\nplot([0 30 30 0 0 ],[0 0 10 10 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Gateway Out1" Ports [1, 1] Position [500, 70, 530, 80] ShowName off SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, double, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarded, depending on how they are configured." hdl_port off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,336,386" block_type "gatewayout" block_version "10.1.2" sg_icon_stat "30,10,1,1,white,grey,0,b3a044a9,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 ],[0 0 10 10 ],[0.88 0.88 0.88]);\npatch([13 11 13 11 13 16 17 18 21 19 17 15 17 15 17 19 21 18 17 16 13 ],[1 3 5 7 9 9 8 9 9 7 9 7 5 3 1 3 1 1 2 1 1 ],[0.98 0.96 0.92]);\nplot([0 30 30 0 0 ],[0 0 10 10 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Logical" Ports [2, 1] Position [255, 175, 310, 235] SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "9.1.01" sg_icon_stat "55,60,1,1,white,blue,0,087b5522,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[8 17 30 43 52 52 48 52 52 40 52 43 30 17 8 20 8 8 12 8 8 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newlineand\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType SubSystem Name "Radio 3\nRSSI Buffer" Ports [3] Position [650, 264, 705, 376] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Radio 3\nRSSI Buffer" Location [2, 70, 1918, 1150] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Addr_14b" Position [325, 348, 355, 362] NamePlacement "alternate" IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Inport Name "RSSI" Position [95, 383, 125, 397] Port "2" IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Inport Name "WE" Position [720, 478, 750, 492] Port "3" IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Reference Name "11MSB" Ports [1, 1] Position [430, 346, 470, 364] NamePlacement "alternate" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardware notes: In hardware this block costs nothing." nbits "11" boolean_output off mode "Upper Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,407" block_type "slice" block_version "8.2" sg_icon_stat "40,18,1,1,white,blue,0,b1026674,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "BIT[2]" Ports [1, 1] Position [430, 401, 470, 419] SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "2" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,407" block_type "slice" block_version "8.2" sg_icon_stat "40,18,1,1,white,blue,0,b1026674,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Concat" Ports [2, 1] Position [685, 381, 725, 459] ShowName off SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point at zero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" block_version "10.1.2" sg_icon_stat "40,78,1,1,white,blue,0,df1e5aba,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([14 4 18 4 14 30 34 38 55 42 29 20 35 20 29 42 55 38 34 30 14 ],[6 16 30 44 54 54 50 54 54 41 54 45 30 15 6 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'hi');\ncolor('black');port_label('input',2,'lo');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Convert" Ports [1, 1] Position [285, 382, 320, 398] ShowName off SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." arith_type "Unsigned" n_bits "16" bin_pt "0" quantization "Truncate" overflow "Wrap" latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,461,375" block_type "convert" block_version "8.2" sg_icon_stat "35,16,1,1,white,blue,0,74901e60,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([15 10 17 10 15 23 25 27 35 28 22 17 23 17 22 28 35 27 25 23 15 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'cast');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Inverter" Ports [1, 1] Position [510, 402, 540, 418] ShowName off SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,251" block_type "inv" block_version "10.1.2" sg_icon_stat "30,16,1,1,white,blue,0,1ab4a85f,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 58 58 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[7 16 29 42 51 51 47 51 51 39 51 42 29 16 7 19 7 7 11 7 7 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Register" Ports [2, 1] Position [580, 378, 625, 422] ShowName off SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "10.1.2" sg_icon_stat "45,44,1,1,white,blue,0,cc3303a0,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('\\bf{z^{-1}}','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Reinterpret1" Ports [1, 1] Position [180, 382, 215, 398] ShowName off SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can changed the signal between signed and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothing.

Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsigned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111000 in binary)." force_arith_type on arith_type "Unsigned" force_bin_pt on bin_pt "0" has_advanced_control "0" sggui_pos "436,54,356,312" block_type "reinterpret" block_version "9.1.01" sg_icon_stat "35,16,1,1,white,blue,0,8982c1db,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 ],[0 0 32 32 ],[0.77 0.82 0.91]);\npatch([16 11 18 11 16 24 26 28 37 30 23 18 25 18 23 30 37 28 26 24 16 ],[3 8 15 22 27 27 25 27 27 20 27 22 15 8 3 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 50 50 0 0 ],[0 0 32 32 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('reinterpret');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Shared Memory" Ports [3, 1] Position [800, 323, 880, 517] AttributesFormatString "<< % >>" SourceBlock "xbsIndex_r4/Shared Memory" SourceType "Xilinx Shared Memory Random Access Memory Block" shared_memory_name "'RSSIBuff_Radio3'" depth "2^11" ownership "Locally Owned and Initialized" initVector "0" mutex "Unprotected" mode "Read and Write" write_mode "Read After Write" time_out "0" latency "1" explicit_data_type on arith_type "Unsigned" n_bits "32" bin_pt "0" xl_use_area off xl_area "[0,0,0,0,0,0,0]" implementation "Block RAM" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,384,381" block_type "shmem" block_version "10.1.2" sg_icon_stat "80,194,1,1,white,blue,0,e2c38f9a,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 80 80 0 ],[0 0 90 90 ],[0.77 0.82 0.91]);\npatch([18 5 24 5 18 39 45 51 74 56 39 27 46 27 39 56 74 51 45 39 18 ],[14 27 46 65 78 78 72 78 78 60 77 65 46 27 15 32 14 14 20 14 14 ],[0.98 0.96 0.92]);\nplot([0 80 80 0 0 ],[0 0 90 90 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'addr');\ncolor('black');port_label('input',2,'din');\ncolor('black');port_label('input',3,'we');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Terminator Name "Terminator2" Position [945, 410, 965, 430] ShowName off } Line { SrcBlock "RSSI" SrcPort 1 DstBlock "Reinterpret1" DstPort 1 } Line { SrcBlock "Convert" SrcPort 1 Points [35, 0] Branch { DstBlock "Register" DstPort 1 } Branch { Points [0, 50] DstBlock "Concat" DstPort 2 } } Line { SrcBlock "Addr_14b" SrcPort 1 Points [40, 0] Branch { DstBlock "11MSB" DstPort 1 } Branch { Points [0, 55] DstBlock "BIT[2]" DstPort 1 } } Line { SrcBlock "WE" SrcPort 1 DstBlock "Shared Memory" DstPort 3 } Line { SrcBlock "Reinterpret1" SrcPort 1 DstBlock "Convert" DstPort 1 } Line { SrcBlock "Concat" SrcPort 1 DstBlock "Shared Memory" DstPort 2 } Line { SrcBlock "BIT[2]" SrcPort 1 DstBlock "Inverter" DstPort 1 } Line { SrcBlock "11MSB" SrcPort 1 DstBlock "Shared Memory" DstPort 1 } Line { SrcBlock "Shared Memory" SrcPort 1 DstBlock "Terminator2" DstPort 1 } Line { SrcBlock "Register" SrcPort 1 DstBlock "Concat" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Register" DstPort 2 } } } Block { BlockType SubSystem Name "Radio 3 I/Q\nBuffer" Ports [3] Position [650, 116, 705, 224] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Radio 3 I/Q\nBuffer" Location [2, 74, 1270, 726] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Addr_14b" Position [200, 68, 230, 82] IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Inport Name "I/Q_32b" Position [200, 98, 230, 112] Port "2" IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Inport Name "WE" Position [200, 128, 230, 142] Port "3" IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Reference Name "Shared Memory" Ports [3, 1] Position [320, 60, 400, 150] AttributesFormatString "<< % >>" SourceBlock "xbsIndex_r4/Shared Memory" SourceType "Xilinx Shared Memory Random Access Memory Block" shared_memory_name "'RxBuff_Radio3'" depth "2^14" ownership "Locally Owned and Initialized" initVector "0" mutex "Unprotected" mode "Read and Write" write_mode "Read After Write" time_out "0" latency "1" explicit_data_type on arith_type "Unsigned" n_bits "32" bin_pt "0" xl_use_area off xl_area "[0,0,0,0,0,0,0]" implementation "Block RAM" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,384,381" block_type "shmem" block_version "10.1.2" sg_icon_stat "80,90,1,1,white,blue,0,e2c38f9a,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 80 80 0 ],[0 0 90 90 ],[0.77 0.82 0.91]);\npatch([18 5 24 5 18 39 45 51 74 56 39 27 46 27 39 56 74 51 45 39 18 ],[14 27 46 65 78 78 72 78 78 60 77 65 46 27 15 32 14 14 20 14 14 ],[0.98 0.96 0.92]);\nplot([0 80 80 0 0 ],[0 0 90 90 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'addr');\ncolor('black');port_label('input',2,'din');\ncolor('black');port_label('input',3,'we');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Terminator Name "Terminator" Position [450, 95, 470, 115] ShowName off } Line { SrcBlock "Shared Memory" SrcPort 1 DstBlock "Terminator" DstPort 1 } Line { SrcBlock "WE" SrcPort 1 DstBlock "Shared Memory" DstPort 3 } Line { SrcBlock "I/Q_32b" SrcPort 1 DstBlock "Shared Memory" DstPort 2 } Line { SrcBlock "Addr_14b" SrcPort 1 DstBlock "Shared Memory" DstPort 1 } } } Block { BlockType Scope Name "Scope" Ports [2] Position [585, 14, 625, 96] Floating off Location [5, 49, 1285, 757] Open off NumInputPorts "2" ZoomMode "yonly" List { ListType AxesTitles axes1 "%" axes2 "%" } YMin "-5~-5" YMax "5~5" SaveName "ScopeData2" DataFormat "StructureWithTime" MaxDataPoints "40000" SampleTime "0" } Line { SrcBlock "Gateway Out1" SrcPort 1 DstBlock "Scope" DstPort 2 } Line { SrcBlock "Gateway Out" SrcPort 1 DstBlock "Scope" DstPort 1 } Line { SrcBlock "I/Q" SrcPort 1 DstBlock "Radio 3 I/Q\nBuffer" DstPort 2 } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "Logical" DstPort 2 } Line { SrcBlock "EN" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "WE" SrcPort 1 DstBlock "Logical" DstPort 1 } Line { SrcBlock "Addr" SrcPort 1 Points [75, 0] Branch { Points [0, -100] DstBlock "Gateway Out" DstPort 1 } Branch { Labels [0, 0] DstBlock "Radio 3 I/Q\nBuffer" DstPort 1 } Branch { Points [0, 150] DstBlock "Radio 3\nRSSI Buffer" DstPort 1 } } Line { SrcBlock "Logical" SrcPort 1 Points [65, 0] Branch { Points [85, 0] Branch { Points [0, -130] DstBlock "Gateway Out1" DstPort 1 } Branch { Labels [0, 0] DstBlock "Radio 3 I/Q\nBuffer" DstPort 3 } } Branch { Points [0, 150] DstBlock "Radio 3\nRSSI Buffer" DstPort 3 } } Line { SrcBlock "RSSI" SrcPort 1 DstBlock "Radio 3\nRSSI Buffer" DstPort 2 } } } Block { BlockType SubSystem Name "Radio 3\nTx Buffer" Ports [3, 1] Position [1015, 852, 1095, 908] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Radio 3\nTx Buffer" Location [2, 74, 1270, 726] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "RdAddr_14b" Position [350, 288, 380, 302] NamePlacement "alternate" IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Inport Name "Rst" Position [30, 173, 60, 187] Port "2" IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Inport Name "En" Position [30, 203, 60, 217] Port "3" IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Reference Name "Constant" Ports [0, 1] Position [630, 350, 655, 370] ShowName off SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" arith_type "Unsigned" const "0" n_bits "32" bin_pt "0" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,400,346" block_type "constant" block_version "10.1.2" sg_icon_stat "25,20,1,1,white,blue,0,72d575a1,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 26 26 ],[0.77 0.82 0.91]);\npatch([20 16 22 16 20 27 29 31 38 32 26 22 28 22 26 32 38 31 29 27 20 ],[3 7 13 19 23 23 21 23 23 17 23 19 13 7 3 9 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 26 26 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'0');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Constant1" Ports [0, 1] Position [355, 345, 380, 365] ShowName off SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" arith_type "Boolean" const "0" n_bits "32" bin_pt "0" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,400,346" block_type "constant" block_version "10.1.2" sg_icon_stat "25,20,1,1,white,blue,0,72d575a1,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 26 26 ],[0.77 0.82 0.91]);\npatch([20 16 22 16 20 27 29 31 38 32 26 22 28 22 26 32 38 31 29 27 20 ],[3 7 13 19 23 23 21 23 23 17 23 19 13 7 3 9 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 26 26 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'0');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Constant2" Ports [0, 1] Position [355, 315, 380, 335] ShowName off SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" arith_type "Unsigned" const "0" n_bits "32" bin_pt "0" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,400,346" block_type "constant" block_version "10.1.2" sg_icon_stat "25,20,1,1,white,blue,0,72d575a1,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 26 26 ],[0.77 0.82 0.91]);\npatch([20 16 22 16 20 27 29 31 38 32 26 22 28 22 26 32 38 31 29 27 20 ],[3 7 13 19 23 23 21 23 23 17 23 19 13 7 3 9 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 26 26 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'0');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Convert" Ports [1, 1] Position [350, 188, 375, 202] ShowName off SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." arith_type "Boolean" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,374,375" block_type "convert" block_version "8.2" sg_icon_stat "25,14,1,1,white,blue,0,74901e60,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([15 10 17 10 15 23 25 27 35 28 22 17 23 17 22 28 35 27 25 23 15 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'cast');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Convert1" Ports [1, 1] Position [100, 203, 120, 217] ShowName off SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." arith_type "Boolean" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,374,375" block_type "convert" block_version "8.2" sg_icon_stat "20,14,1,1,white,blue,0,74901e60,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([15 10 17 10 15 23 25 27 35 28 22 17 23 17 22 28 35 27 25 23 15 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'cast');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Inverter" Ports [1, 1] Position [150, 201, 180, 219] SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "9.1.01" sg_icon_stat "30,18,1,1,white,blue,0,1ab4a85f,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 58 58 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[7 16 29 42 51 51 47 51 51 39 51 42 29 16 7 19 7 7 11 7 7 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Logical" Ports [2, 1] Position [215, 165, 270, 225] SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "9.1.01" sg_icon_stat "55,60,1,1,white,blue,0,f4a65842,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[8 17 30 43 52 52 48 52 52 40 52 43 30 17 8 20 8 8 12 8 8 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newlineor\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Mux" Ports [3, 1] Position [750, 273, 795, 377] SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,303" block_type "mux" block_version "10.1.2" sg_icon_stat "45,104,1,1,white,blue,3,613f58e1,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 ],[0 14.8571 89.1429 104 ],[0.77 0.82 0.91]);\npatch([10 3 14 3 10 22 25 28 41 31 21 14 25 14 21 31 41 28 25 22 10 ],[34 41 52 63 70 70 67 70 70 60 70 63 52 41 34 44 34 34 37 34 34 ],[0.98 0.96 0.92]);\nplot([0 45 45 0 0 ],[0 14.8571 89.1429 104 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('input',3,'d1');\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Shared Memory" Ports [3, 1] Position [445, 280, 525, 370] AttributesFormatString "<< % >>" SourceBlock "xbsIndex_r4/Shared Memory" SourceType "Xilinx Shared Memory Random Access Memory Block" shared_memory_name "'TxBuff_Radio3'" depth "2^14" ownership "Locally Owned and Initialized" initVector "0" mutex "Unprotected" mode "Read and Write" write_mode "Read After Write" time_out "0" latency "1" explicit_data_type on arith_type "Unsigned" n_bits "32" bin_pt "0" xl_use_area off xl_area "[0,0,0,0,0,0,0]" implementation "Block RAM" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,384,381" block_type "shmem" block_version "10.1.2" sg_icon_stat "80,90,1,1,white,blue,0,e2c38f9a,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 80 80 0 ],[0 0 90 90 ],[0.77 0.82 0.91]);\npatch([18 5 24 5 18 39 45 51 74 56 39 27 46 27 39 56 74 51 45 39 18 ],[14 27 46 65 78 78 72 78 78 60 77 65 46 27 15 32 14 14 20 14 14 ],[0.98 0.96 0.92]);\nplot([0 80 80 0 0 ],[0 0 90 90 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'addr');\ncolor('black');port_label('input',2,'din');\ncolor('black');port_label('input',3,'we');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Outport Name "IQ_32b" Position [885, 318, 915, 332] IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Line { SrcBlock "Mux" SrcPort 1 DstBlock "IQ_32b" DstPort 1 } Line { SrcBlock "Constant2" SrcPort 1 DstBlock "Shared Memory" DstPort 2 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Shared Memory" DstPort 3 } Line { SrcBlock "Shared Memory" SrcPort 1 DstBlock "Mux" DstPort 2 } Line { SrcBlock "Constant" SrcPort 1 DstBlock "Mux" DstPort 3 } Line { SrcBlock "RdAddr_14b" SrcPort 1 DstBlock "Shared Memory" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical" DstPort 2 } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "Inverter" DstPort 1 } Line { SrcBlock "En" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Rst" SrcPort 1 DstBlock "Logical" DstPort 1 } Line { SrcBlock "Convert" SrcPort 1 Points [160, 0; 0, 95] DstBlock "Mux" DstPort 1 } Line { SrcBlock "Logical" SrcPort 1 DstBlock "Convert" DstPort 1 } } } Block { BlockType SubSystem Name "Radio 3 Inputs" Ports [2, 2] Position [905, 310, 1080, 370] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Radio 3 Inputs" Location [2, 74, 1014, 726] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "DebugRxBuffers" Position [180, 248, 210, 262] IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Inport Name "MGCAGC_AGCDCO_SEL" Position [185, 328, 215, 342] Port "2" IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType SubSystem Name "ADC I" Ports [2, 2] Position [410, 245, 565, 285] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "ADC I" Location [37, 74, 1049, 726] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Debug" Position [645, 13, 675, 27] IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Inport Name "MGCAGC_AGCDCO_SEL" Position [125, 203, 155, 217] Port "2" IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Constant Name "Constant1" Position [15, 280, 45, 310] ShowName off Value "0" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Reference Name "Counter" Ports [0, 1] Position [480, 300, 540, 360] SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited counter is implemented by combining a counter with a comparator." cnt_type "Free Running" cnt_to "Inf" operation "Down" start_count "2^14-1" cnt_by_val "1" arith_type "Unsigned" n_bits "14" bin_pt "0" load_pin off rst off en off explicit_period "on" period "1" dbl_ovrd off use_behavioral_HDL off use_rpm off implementation "Fabric" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,619" block_type "counter" block_version "10.1.3" sg_icon_stat "60,60,1,1,white,blue,0,a170c862,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([14 4 18 4 14 30 34 38 55 42 29 20 35 20 29 42 55 38 34 30 14 ],[6 16 30 44 54 54 50 54 54 41 54 45 30 15 6 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'out');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "FromAGC_Radio3_I" Ports [1, 1] Position [110, 385, 175, 405] SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, double and fixed point to Xilinx fixed point type.

Hardware notes: In hardware these blocks become top level input ports." arith_type "Signed (2's comp)" n_bits "14" bin_pt "13" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,406" block_type "gatewayin" block_version "10.1.3" sg_icon_stat "65,20,1,1,white,yellow,0,bc55d28f,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([27 24 29 24 27 32 33 34 40 36 32 29 34 29 32 36 40 34 33 32 27 ],[2 5 10 15 18 18 17 18 18 14 18 15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Mux" Ports [3, 1] Position [780, 48, 825, 152] SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "1" bin_pt "0" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,303" block_type "mux" block_version "10.1.3" sg_icon_stat "45,104,1,1,white,blue,3,613f58e1,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 ],[0 14.8571 89.1429 104 ],[0.77 0.82 0.91]);\npatch([10 3 14 3 10 22 25 28 41 31 21 14 25 14 21 31 41 28 25 22 10 ],[34 41 52 63 70 70 67 70 70 60 70 63 52 41 34 44 34 34 37 34 34 ],[0.98 0.96 0.92]);\nplot([0 45 45 0 0 ],[0 14.8571 89.1429 104 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('input',3,'d1');\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Mux1" Ports [3, 1] Position [780, 243, 825, 347] SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "1" bin_pt "0" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,303" block_type "mux" block_version "10.1.3" sg_icon_stat "45,104,1,1,white,blue,3,613f58e1,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 ],[0 14.8571 89.1429 104 ],[0.77 0.82 0.91]);\npatch([10 3 14 3 10 22 25 28 41 31 21 14 25 14 21 31 41 28 25 22 10 ],[34 41 52 63 70 70 67 70 70 60 70 63 52 41 34 44 34 34 37 34 34 ],[0.98 0.96 0.92]);\nplot([0 45 45 0 0 ],[0 14.8571 89.1429 104 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('input',3,'d1');\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Mux2" Ports [3, 1] Position [270, 243, 315, 347] SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "1" bin_pt "0" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,303" block_type "mux" block_version "10.1.3" sg_icon_stat "45,104,1,1,white,blue,3,613f58e1,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 ],[0 14.8571 89.1429 104 ],[0.77 0.82 0.91]);\npatch([10 3 14 3 10 22 25 28 41 31 21 14 25 14 21 31 41 28 25 22 10 ],[34 41 52 63 70 70 67 70 70 60 70 63 52 41 34 44 34 34 37 34 34 ],[0.98 0.96 0.92]);\nplot([0 45 45 0 0 ],[0 14.8571 89.1429 104 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('input',3,'d1');\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Radio 3 ADC I" Ports [1, 1] Position [80, 274, 175, 316] LinkData { BlockName "radio3_adc_I" DialogParameters { sg_icon_stat "65,20,1,1,white,yellow,0,bc55d28f,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([27 24 29 24 27 32 33 34 40 36 32 29 34 29 32 36 40 34 33 32 27 ],[2 5 10 15 18 18 17 18 18 14 18 15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end icon text');\n" } } SourceBlock "WARP_Blockset/WARP Radio Board ADC//DACs/Radio 3 ADC I" SourceType "" ShowPortLabels "FromPortIcon" SystemSampleTime "-1" FunctionWithSeparateData off RTWMemSecFuncInitTerm "Inherit from model" RTWMemSecFuncExecute "Inherit from model" RTWMemSecDataConstants "Inherit from model" RTWMemSecDataInternal "Inherit from model" RTWMemSecDataParameters "Inherit from model" samp_period "1" } Block { BlockType Reference Name "Register" Ports [1, 1] Position [405, 281, 440, 309] ShowName off SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "8.2" sg_icon_stat "35,28,1,1,white,blue,0,ac6b57db,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('\\bf{z^{-1}}','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Reinterpret" Ports [1, 1] Position [625, 314, 675, 346] SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can changed the signal between signed and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothing.

Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsigned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111000 in binary)." force_arith_type on arith_type "Signed (2's comp)" force_bin_pt on bin_pt "13" has_advanced_control "0" sggui_pos "20,20,336,312" block_type "reinterpret" block_version "10.1.3" sg_icon_stat "50,32,1,1,white,blue,0,8982c1db,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 ],[0 0 32 32 ],[0.77 0.82 0.91]);\npatch([16 11 18 11 16 24 26 28 37 30 23 18 25 18 23 30 37 28 26 24 16 ],[3 8 15 22 27 27 25 27 27 20 27 22 15 8 3 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 50 50 0 0 ],[0 0 32 32 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('reinterpret');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Slice" Ports [1, 1] Position [630, 120, 690, 150] SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,376" block_type "slice" block_version "10.1.3" sg_icon_stat "60,30,1,1,white,blue,0,b1026674,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "radio3_ADC_I_OTR" Ports [1, 1] Position [400, 94, 455, 106] NamePlacement "alternate" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, double and fixed point to Xilinx fixed point type.

Hardware notes: In hardware these blocks become top level input ports." arith_type "Unsigned" n_bits "1" bin_pt "0" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,356,432" block_type "gatewayin" block_version "VER_STRING_GOES_HERE" sg_icon_stat "55,12,1,1,white,yellow,0,bc55d28f,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([27 24 29 24 27 32 33 34 40 36 32 29 34 29 32 36 40 34 33 32 27 ],[2 5 10 15 18 18 17 18 18 14 18 15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Outport Name "OTR I" Position [885, 93, 915, 107] IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Outport Name "ADC I" Position [885, 288, 915, 302] Port "2" IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Line { SrcBlock "Constant1" SrcPort 1 Points [20, 0] Branch { DstBlock "Radio 3 ADC I" DstPort 1 } Branch { Points [-10, 0] Branch { Points [0, -195] DstBlock "radio3_ADC_I_OTR" DstPort 1 } Branch { Points [0, 100] DstBlock "FromAGC_Radio3_I" DstPort 1 } } } Line { SrcBlock "Mux" SrcPort 1 DstBlock "OTR I" DstPort 1 } Line { SrcBlock "Debug" SrcPort 1 Points [40, 0; 0, 45] Branch { DstBlock "Mux" DstPort 1 } Branch { Points [0, 195] DstBlock "Mux1" DstPort 1 } } Line { SrcBlock "radio3_ADC_I_OTR" SrcPort 1 DstBlock "Mux" DstPort 2 } Line { SrcBlock "Slice" SrcPort 1 DstBlock "Mux" DstPort 3 } Line { SrcBlock "Mux1" SrcPort 1 DstBlock "ADC I" DstPort 1 } Line { SrcBlock "Register" SrcPort 1 DstBlock "Mux1" DstPort 2 } Line { SrcBlock "Reinterpret" SrcPort 1 DstBlock "Mux1" DstPort 3 } Line { SrcBlock "Counter" SrcPort 1 Points [25, 0] Branch { DstBlock "Reinterpret" DstPort 1 } Branch { Points [0, -195] DstBlock "Slice" DstPort 1 } } Line { SrcBlock "MGCAGC_AGCDCO_SEL" SrcPort 1 Points [70, 0; 0, 50] DstBlock "Mux2" DstPort 1 } Line { SrcBlock "FromAGC_Radio3_I" SrcPort 1 Points [50, 0; 0, -65] DstBlock "Mux2" DstPort 3 } Line { SrcBlock "Mux2" SrcPort 1 DstBlock "Register" DstPort 1 } Line { SrcBlock "Radio 3 ADC I" SrcPort 1 DstBlock "Mux2" DstPort 2 } } } Block { BlockType SubSystem Name "ADC Q" Ports [2, 2] Position [410, 305, 565, 345] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "ADC Q" Location [2, 74, 1014, 726] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Debug" Position [695, 13, 725, 27] IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Inport Name "MGCAGC_AGCDCO_SEL" Position [165, 203, 195, 217] Port "2" IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Constant Name "Constant1" Position [15, 280, 45, 310] ShowName off Value "0" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Reference Name "Counter" Ports [0, 1] Position [525, 300, 585, 360] SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited counter is implemented by combining a counter with a comparator." cnt_type "Free Running" cnt_to "Inf" operation "Up" start_count "0" cnt_by_val "1" arith_type "Unsigned" n_bits "14" bin_pt "0" load_pin off rst off en off explicit_period "on" period "1" dbl_ovrd off use_behavioral_HDL off use_rpm off implementation "Fabric" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,619" block_type "counter" block_version "10.1.3" sg_icon_stat "60,60,1,1,white,blue,0,a170c862,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([14 4 18 4 14 30 34 38 55 42 29 20 35 20 29 42 55 38 34 30 14 ],[6 16 30 44 54 54 50 54 54 41 54 45 30 15 6 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'out');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "FromAGC_Radio3_Q" Ports [1, 1] Position [150, 385, 215, 405] SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, double and fixed point to Xilinx fixed point type.

Hardware notes: In hardware these blocks become top level input ports." arith_type "Signed (2's comp)" n_bits "14" bin_pt "13" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,406" block_type "gatewayin" block_version "10.1.3" sg_icon_stat "65,20,1,1,white,yellow,0,bc55d28f,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([27 24 29 24 27 32 33 34 40 36 32 29 34 29 32 36 40 34 33 32 27 ],[2 5 10 15 18 18 17 18 18 14 18 15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Mux" Ports [3, 1] Position [830, 48, 875, 152] SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "1" bin_pt "0" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,303" block_type "mux" block_version "10.1.3" sg_icon_stat "45,104,1,1,white,blue,3,613f58e1,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 ],[0 14.8571 89.1429 104 ],[0.77 0.82 0.91]);\npatch([10 3 14 3 10 22 25 28 41 31 21 14 25 14 21 31 41 28 25 22 10 ],[34 41 52 63 70 70 67 70 70 60 70 63 52 41 34 44 34 34 37 34 34 ],[0.98 0.96 0.92]);\nplot([0 45 45 0 0 ],[0 14.8571 89.1429 104 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('input',3,'d1');\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Mux1" Ports [3, 1] Position [830, 243, 875, 347] SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "1" bin_pt "0" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,303" block_type "mux" block_version "10.1.3" sg_icon_stat "45,104,1,1,white,blue,3,613f58e1,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 ],[0 14.8571 89.1429 104 ],[0.77 0.82 0.91]);\npatch([10 3 14 3 10 22 25 28 41 31 21 14 25 14 21 31 41 28 25 22 10 ],[34 41 52 63 70 70 67 70 70 60 70 63 52 41 34 44 34 34 37 34 34 ],[0.98 0.96 0.92]);\nplot([0 45 45 0 0 ],[0 14.8571 89.1429 104 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('input',3,'d1');\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Mux2" Ports [3, 1] Position [310, 243, 355, 347] SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "1" bin_pt "0" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,303" block_type "mux" block_version "10.1.3" sg_icon_stat "45,104,1,1,white,blue,3,613f58e1,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 ],[0 14.8571 89.1429 104 ],[0.77 0.82 0.91]);\npatch([10 3 14 3 10 22 25 28 41 31 21 14 25 14 21 31 41 28 25 22 10 ],[34 41 52 63 70 70 67 70 70 60 70 63 52 41 34 44 34 34 37 34 34 ],[0.98 0.96 0.92]);\nplot([0 45 45 0 0 ],[0 14.8571 89.1429 104 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('input',3,'d1');\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Radio 3 ADC Q" Ports [1, 1] Position [85, 274, 180, 316] LinkData { BlockName "radio3_adc_Q" DialogParameters { sg_icon_stat "65,20,1,1,white,yellow,0,bc55d28f,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([27 24 29 24 27 32 33 34 40 36 32 29 34 29 32 36 40 34 33 32 27 ],[2 5 10 15 18 18 17 18 18 14 18 15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end icon text');\n" } } SourceBlock "WARP_Blockset/WARP Radio Board ADC//DACs/Radio 3 ADC Q" SourceType "" ShowPortLabels "FromPortIcon" SystemSampleTime "-1" FunctionWithSeparateData off RTWMemSecFuncInitTerm "Inherit from model" RTWMemSecFuncExecute "Inherit from model" RTWMemSecDataConstants "Inherit from model" RTWMemSecDataInternal "Inherit from model" RTWMemSecDataParameters "Inherit from model" samp_period "1" } Block { BlockType Reference Name "Register" Ports [1, 1] Position [455, 281, 490, 309] ShowName off SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "8.2" sg_icon_stat "35,28,1,1,white,blue,0,ac6b57db,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('\\bf{z^{-1}}','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Reinterpret" Ports [1, 1] Position [675, 314, 725, 346] SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can changed the signal between signed and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothing.

Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsigned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111000 in binary)." force_arith_type on arith_type "Signed (2's comp)" force_bin_pt on bin_pt "13" has_advanced_control "0" sggui_pos "20,20,336,312" block_type "reinterpret" block_version "10.1.3" sg_icon_stat "50,32,1,1,white,blue,0,8982c1db,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 ],[0 0 32 32 ],[0.77 0.82 0.91]);\npatch([16 11 18 11 16 24 26 28 37 30 23 18 25 18 23 30 37 28 26 24 16 ],[3 8 15 22 27 27 25 27 27 20 27 22 15 8 3 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 50 50 0 0 ],[0 0 32 32 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('reinterpret');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Slice" Ports [1, 1] Position [680, 120, 740, 150] SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,376" block_type "slice" block_version "10.1.3" sg_icon_stat "60,30,1,1,white,blue,0,b1026674,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "radio3_ADC_Q_OTR" Ports [1, 1] Position [115, 94, 170, 106] SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, double and fixed point to Xilinx fixed point type.

Hardware notes: In hardware these blocks become top level input ports." arith_type "Unsigned" n_bits "1" bin_pt "0" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,356,432" block_type "gatewayin" block_version "VER_STRING_GOES_HERE" sg_icon_stat "55,12,1,1,white,yellow,0,bc55d28f,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([27 24 29 24 27 32 33 34 40 36 32 29 34 29 32 36 40 34 33 32 27 ],[2 5 10 15 18 18 17 18 18 14 18 15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Outport Name "OTR Q" Position [975, 93, 1005, 107] IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Outport Name "ADC Q" Position [970, 288, 1000, 302] Port "2" IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Line { SrcBlock "Constant1" SrcPort 1 Points [10, 0] Branch { Points [0, -195] DstBlock "radio3_ADC_Q_OTR" DstPort 1 } Branch { Points [0, 100] DstBlock "FromAGC_Radio3_Q" DstPort 1 } Branch { DstBlock "Radio 3 ADC Q" DstPort 1 } } Line { SrcBlock "Mux" SrcPort 1 DstBlock "OTR Q" DstPort 1 } Line { SrcBlock "Debug" SrcPort 1 Points [40, 0; 0, 45] Branch { DstBlock "Mux" DstPort 1 } Branch { Points [0, 195] DstBlock "Mux1" DstPort 1 } } Line { SrcBlock "radio3_ADC_Q_OTR" SrcPort 1 DstBlock "Mux" DstPort 2 } Line { SrcBlock "Slice" SrcPort 1 DstBlock "Mux" DstPort 3 } Line { SrcBlock "Mux1" SrcPort 1 DstBlock "ADC Q" DstPort 1 } Line { SrcBlock "Register" SrcPort 1 DstBlock "Mux1" DstPort 2 } Line { SrcBlock "Reinterpret" SrcPort 1 DstBlock "Mux1" DstPort 3 } Line { SrcBlock "Counter" SrcPort 1 Points [30, 0] Branch { DstBlock "Reinterpret" DstPort 1 } Branch { Points [0, -195] DstBlock "Slice" DstPort 1 } } Line { SrcBlock "MGCAGC_AGCDCO_SEL" SrcPort 1 Points [70, 0; 0, 50] DstBlock "Mux2" DstPort 1 } Line { SrcBlock "FromAGC_Radio3_Q" SrcPort 1 Points [50, 0; 0, -65] DstBlock "Mux2" DstPort 3 } Line { SrcBlock "Radio 3 ADC Q" SrcPort 1 DstBlock "Mux2" DstPort 2 } Line { SrcBlock "Mux2" SrcPort 1 DstBlock "Register" DstPort 1 } } } Block { BlockType SubSystem Name "Concatenates_1" Ports [4, 1] Position [695, 218, 740, 372] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Concatenates_1" Location [2, 74, 1270, 726] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "OTR_I" Position [395, 43, 425, 57] IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Inport Name "ADC_I" Position [330, 93, 360, 107] Port "2" IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Inport Name "OTR_Q" Position [390, 163, 420, 177] Port "3" IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Inport Name "ADC_Q" Position [330, 213, 360, 227] Port "4" IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Reference Name "Concat1" Ports [2, 1] Position [490, 191, 520, 229] ShowName off SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point at zero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" block_version "8.2" sg_icon_stat "30,38,1,1,white,blue,0,df1e5aba,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([14 4 18 4 14 30 34 38 55 42 29 20 35 20 29 42 55 38 34 30 14 ],[6 16 30 44 54 54 50 54 54 41 54 45 30 15 6 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'hi');\ncolor('black');port_label('input',2,'lo');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Concat2" Ports [2, 1] Position [490, 71, 520, 109] ShowName off SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point at zero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" block_version "8.2" sg_icon_stat "30,38,1,1,white,blue,0,df1e5aba,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([14 4 18 4 14 30 34 38 55 42 29 20 35 20 29 42 55 38 34 30 14 ],[6 16 30 44 54 54 50 54 54 41 54 45 30 15 6 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'hi');\ncolor('black');port_label('input',2,'lo');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Concat3" Ports [2, 1] Position [550, 150, 575, 230] ShowName off SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point at zero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" block_version "8.2" sg_icon_stat "25,80,1,1,white,blue,0,df1e5aba,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([14 4 18 4 14 30 34 38 55 42 29 20 35 20 29 42 55 38 34 30 14 ],[6 16 30 44 54 54 50 54 54 41 54 45 30 15 6 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'hi');\ncolor('black');port_label('input',2,'lo');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Concat4" Ports [2, 1] Position [550, 30, 575, 110] ShowName off SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point at zero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" block_version "8.2" sg_icon_stat "25,80,1,1,white,blue,0,df1e5aba,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([14 4 18 4 14 30 34 38 55 42 29 20 35 20 29 42 55 38 34 30 14 ],[6 16 30 44 54 54 50 54 54 41 54 45 30 15 6 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'hi');\ncolor('black');port_label('input',2,'lo');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Concat5" Ports [2, 1] Position [635, 50, 660, 130] ShowName off SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point at zero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" block_version "8.2" sg_icon_stat "25,80,1,1,white,blue,0,df1e5aba,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([14 4 18 4 14 30 34 38 55 42 29 20 35 20 29 42 55 38 34 30 14 ],[6 16 30 44 54 54 50 54 54 41 54 45 30 15 6 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'hi');\ncolor('black');port_label('input',2,'lo');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Reinterpret" Ports [1, 1] Position [385, 90, 420, 110] ShowName off SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can changed the signal between signed and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothing.

Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsigned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111000 in binary)." force_arith_type on arith_type "Unsigned" force_bin_pt on bin_pt "0" has_advanced_control "0" sggui_pos "20,20,356,309" block_type "reinterpret" block_version "8.2" sg_icon_stat "35,20,1,1,white,blue,0,8982c1db,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 ],[0 0 32 32 ],[0.77 0.82 0.91]);\npatch([16 11 18 11 16 24 26 28 37 30 23 18 25 18 23 30 37 28 26 24 16 ],[3 8 15 22 27 27 25 27 27 20 27 22 15 8 3 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 50 50 0 0 ],[0 0 32 32 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('reinterpret');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Reinterpret1" Ports [1, 1] Position [390, 210, 425, 230] ShowName off SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can changed the signal between signed and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothing.

Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsigned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111000 in binary)." force_arith_type on arith_type "Unsigned" force_bin_pt on bin_pt "0" has_advanced_control "0" sggui_pos "20,20,356,309" block_type "reinterpret" block_version "8.2" sg_icon_stat "35,20,1,1,white,blue,0,8982c1db,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 ],[0 0 32 32 ],[0.77 0.82 0.91]);\npatch([16 11 18 11 16 24 26 28 37 30 23 18 25 18 23 30 37 28 26 24 16 ],[3 8 15 22 27 27 25 27 27 20 27 22 15 8 3 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 50 50 0 0 ],[0 0 32 32 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('reinterpret');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "zero" Ports [0, 1] Position [440, 191, 460, 209] ShowName off SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" arith_type "Unsigned" const "0" n_bits "1" bin_pt "0" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "20,18,1,1,white,blue,0,72d575a1,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 26 26 ],[0.77 0.82 0.91]);\npatch([20 16 22 16 20 27 29 31 38 32 26 22 28 22 26 32 38 31 29 27 20 ],[3 7 13 19 23 23 21 23 23 17 23 19 13 7 3 9 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 26 26 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'0');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "zero1" Ports [0, 1] Position [440, 71, 460, 89] ShowName off SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" arith_type "Unsigned" const "0" n_bits "1" bin_pt "0" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "20,18,1,1,white,blue,0,72d575a1,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 26 26 ],[0.77 0.82 0.91]);\npatch([20 16 22 16 20 27 29 31 38 32 26 22 28 22 26 32 38 31 29 27 20 ],[3 7 13 19 23 23 21 23 23 17 23 19 13 7 3 9 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 26 26 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'0');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Outport Name "32b" Position [840, 83, 870, 97] IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Line { SrcBlock "Reinterpret1" SrcPort 1 DstBlock "Concat1" DstPort 2 } Line { SrcBlock "Reinterpret" SrcPort 1 DstBlock "Concat2" DstPort 2 } Line { SrcBlock "ADC_Q" SrcPort 1 DstBlock "Reinterpret1" DstPort 1 } Line { SrcBlock "OTR_Q" SrcPort 1 DstBlock "Concat3" DstPort 1 } Line { SrcBlock "ADC_I" SrcPort 1 DstBlock "Reinterpret" DstPort 1 } Line { SrcBlock "Concat5" SrcPort 1 DstBlock "32b" DstPort 1 } Line { SrcBlock "OTR_I" SrcPort 1 DstBlock "Concat4" DstPort 1 } Line { SrcBlock "Concat3" SrcPort 1 Points [25, 0; 0, -80] DstBlock "Concat5" DstPort 2 } Line { SrcBlock "Concat4" SrcPort 1 DstBlock "Concat5" DstPort 1 } Line { SrcBlock "Concat2" SrcPort 1 Points [0, 0] DstBlock "Concat4" DstPort 2 } Line { SrcBlock "zero1" SrcPort 1 DstBlock "Concat2" DstPort 1 } Line { SrcBlock "Concat1" SrcPort 1 DstBlock "Concat3" DstPort 2 } Line { SrcBlock "zero" SrcPort 1 DstBlock "Concat1" DstPort 1 } } } Block { BlockType Reference Name "Gateway Out1" Ports [1, 1] Position [725, 135, 755, 145] ShowName off SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, double, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarded, depending on how they are configured." hdl_port off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,336,386" block_type "gatewayout" block_version "10.1.2" sg_icon_stat "30,10,1,1,white,grey,0,b3a044a9,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 ],[0 0 10 10 ],[0.88 0.88 0.88]);\npatch([13 11 13 11 13 16 17 18 21 19 17 15 17 15 17 19 21 18 17 16 13 ],[1 3 5 7 9 9 8 9 9 7 9 7 5 3 1 3 1 1 2 1 1 ],[0.98 0.96 0.92]);\nplot([0 30 30 0 0 ],[0 0 10 10 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Gateway Out4" Ports [1, 1] Position [725, 120, 755, 130] ShowName off SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, double, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarded, depending on how they are configured." hdl_port off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,336,386" block_type "gatewayout" block_version "10.1.2" sg_icon_stat "30,10,1,1,white,grey,0,b3a044a9,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 ],[0 0 10 10 ],[0.88 0.88 0.88]);\npatch([13 11 13 11 13 16 17 18 21 19 17 15 17 15 17 19 21 18 17 16 13 ],[1 3 5 7 9 9 8 9 9 7 9 7 5 3 1 3 1 1 2 1 1 ],[0.98 0.96 0.92]);\nplot([0 30 30 0 0 ],[0 0 10 10 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType SubSystem Name "RSSI" Ports [1, 1] Position [495, 397, 565, 433] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "RSSI" Location [2, 74, 1184, 726] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Debug" Position [465, 28, 495, 42] IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Constant Name "Constant1" Position [160, 100, 190, 130] ShowName off Value "0" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Reference Name "Counter" Ports [0, 1] Position [380, 120, 440, 180] SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited counter is implemented by combining a counter with a comparator." cnt_type "Free Running" cnt_to "Inf" operation "Up" start_count "0" cnt_by_val "1" arith_type "Unsigned" n_bits "10" bin_pt "0" load_pin off rst off en off explicit_period "on" period "1" dbl_ovrd off use_behavioral_HDL off use_rpm off implementation "Fabric" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,619" block_type "counter" block_version "10.1.3" sg_icon_stat "60,60,1,1,white,blue,0,a170c862,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([14 4 18 4 14 30 34 38 55 42 29 20 35 20 29 42 55 38 34 30 14 ],[6 16 30 44 54 54 50 54 54 41 54 45 30 15 6 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'out');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Mux" Ports [3, 1] Position [600, 63, 645, 167] SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "1" bin_pt "0" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,303" block_type "mux" block_version "10.1.3" sg_icon_stat "45,104,1,1,white,blue,3,613f58e1,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 ],[0 14.8571 89.1429 104 ],[0.77 0.82 0.91]);\npatch([10 3 14 3 10 22 25 28 41 31 21 14 25 14 21 31 41 28 25 22 10 ],[34 41 52 63 70 70 67 70 70 60 70 63 52 41 34 44 34 34 37 34 34 ],[0.98 0.96 0.92]);\nplot([0 45 45 0 0 ],[0 14.8571 89.1429 104 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('input',3,'d1');\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "radio3_RSSI" Ports [1, 1] Position [280, 109, 335, 121] NamePlacement "alternate" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, double and fixed point to Xilinx fixed point type.

Hardware notes: In hardware these blocks become top level input ports." arith_type "Unsigned" n_bits "10" bin_pt "0" quantization "Truncate" overflow "Wrap" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,356,432" block_type "gatewayin" block_version "VER_STRING_GOES_HERE" sg_icon_stat "55,12,1,1,white,yellow,0,bc55d28f,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([27 24 29 24 27 32 33 34 40 36 32 29 34 29 32 36 40 34 33 32 27 ],[2 5 10 15 18 18 17 18 18 14 18 15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Outport Name "RSSI" Position [740, 108, 770, 122] IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "radio3_RSSI" DstPort 1 } Line { SrcBlock "Debug" SrcPort 1 Points [40, 0; 0, 45] DstBlock "Mux" DstPort 1 } Line { SrcBlock "radio3_RSSI" SrcPort 1 DstBlock "Mux" DstPort 2 } Line { SrcBlock "Counter" SrcPort 1 DstBlock "Mux" DstPort 3 } Line { SrcBlock "Mux" SrcPort 1 DstBlock "RSSI" DstPort 1 } } } Block { BlockType Scope Name "Scope" Ports [2] Position [800, 111, 830, 164] Floating off Location [5, 34, 1285, 912] Open off NumInputPorts "2" List { ListType AxesTitles axes1 "%" axes2 "%" } YMin "-5~-5" YMax "5~5" DataFormat "StructureWithTime" SampleTime "0" } Block { BlockType Outport Name "Radio 3 RSSI" Position [645, 408, 675, 422] IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Outport Name "Radio 3 I/Q" Position [865, 288, 895, 302] Port "2" IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Line { SrcBlock "ADC Q" SrcPort 2 Points [65, 0; 0, 20; 30, 0] Branch { DstBlock "Concatenates_1" DstPort 4 } Branch { Points [0, -215] DstBlock "Gateway Out1" DstPort 1 } } Line { SrcBlock "ADC Q" SrcPort 1 DstBlock "Concatenates_1" DstPort 3 } Line { SrcBlock "ADC I" SrcPort 2 Points [85, 0] Branch { DstBlock "Concatenates_1" DstPort 2 } Branch { Points [0, -150] DstBlock "Gateway Out4" DstPort 1 } } Line { SrcBlock "ADC I" SrcPort 1 Points [0, -20] DstBlock "Concatenates_1" DstPort 1 } Line { SrcBlock "Concatenates_1" SrcPort 1 Points [0, 0] DstBlock "Radio 3 I/Q" DstPort 1 } Line { SrcBlock "Gateway Out4" SrcPort 1 DstBlock "Scope" DstPort 1 } Line { SrcBlock "Gateway Out1" SrcPort 1 Points [25, 0] DstBlock "Scope" DstPort 2 } Line { SrcBlock "DebugRxBuffers" SrcPort 1 Points [145, 0] Branch { DstBlock "ADC I" DstPort 1 } Branch { Points [0, 60] Branch { DstBlock "ADC Q" DstPort 1 } Branch { Points [0, 100] DstBlock "RSSI" DstPort 1 } } } Line { SrcBlock "RSSI" SrcPort 1 DstBlock "Radio 3 RSSI" DstPort 1 } Line { SrcBlock "MGCAGC_AGCDCO_SEL" SrcPort 1 Points [95, 0] Branch { DstBlock "ADC Q" DstPort 2 } Branch { Points [0, -60] DstBlock "ADC I" DstPort 2 } } Annotation { Position [518, 257] } } } Block { BlockType SubSystem Name "Radio 3 Outputs" Ports [1] Position [1180, 858, 1225, 902] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Radio 3 Outputs" Location [60, 247, 880, 529] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "32b" Position [145, 148, 175, 162] IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Reference Name "16LSB" Ports [1, 1] Position [305, 147, 340, 163] SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardware notes: In hardware this block costs nothing." nbits "16" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "593,46,442,407" block_type "slice" block_version "9.1.01" sg_icon_stat "35,16,1,1,white,blue,0,b1026674,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "16MSB" Ports [1, 1] Position [305, 82, 345, 98] SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardware notes: In hardware this block costs nothing." nbits "16" boolean_output off mode "Upper Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "593,46,442,407" block_type "slice" block_version "9.1.01" sg_icon_stat "40,16,1,1,white,blue,0,b1026674,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Radio 3 DAC I" Ports [1, 1] Position [560, 69, 655, 111] LinkData { BlockName "Convert" DialogParameters { sg_icon_stat "45,30,1,1,white,blue,0,74901e60,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([15 10 17 10 15 23 25 27 35 28 22 17 23 17 22 28 35 27 25 23 15 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'cast');\nfprintf('','COMMENT: end icon text');\n" } BlockName "radio3_dac_I" DialogParameters { sg_icon_stat "60,20,1,1,white,yellow,0,38220381,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([24 21 26 21 24 29 30 31 37 33 29 26 31 26 29 33 37 31 30 29 24 ],[2 5 10 15 18 18 17 18 18 14 18 15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } } SourceBlock "WARP_Blockset/WARP Radio Board ADC//DACs/Radio 3 DAC I" SourceType "" ShowPortLabels "FromPortIcon" SystemSampleTime "-1" FunctionWithSeparateData off RTWMemSecFuncInitTerm "Inherit from model" RTWMemSecFuncExecute "Inherit from model" RTWMemSecDataConstants "Inherit from model" RTWMemSecDataInternal "Inherit from model" RTWMemSecDataParameters "Inherit from model" } Block { BlockType Reference Name "Radio 3 DAC Q" Ports [1, 1] Position [560, 134, 655, 176] LinkData { BlockName "Convert" DialogParameters { sg_icon_stat "45,30,1,1,white,blue,0,74901e60,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([15 10 17 10 15 23 25 27 35 28 22 17 23 17 22 28 35 27 25 23 15 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'cast');\nfprintf('','COMMENT: end icon text');\n" } BlockName "radio3_dac_Q" DialogParameters { sg_icon_stat "60,20,1,1,white,yellow,0,38220381,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([24 21 26 21 24 29 30 31 37 33 29 26 31 26 29 33 37 31 30 29 24 ],[2 5 10 15 18 18 17 18 18 14 18 15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } } SourceBlock "WARP_Blockset/WARP Radio Board ADC//DACs/Radio 3 DAC Q" SourceType "" ShowPortLabels "FromPortIcon" SystemSampleTime "-1" FunctionWithSeparateData off RTWMemSecFuncInitTerm "Inherit from model" RTWMemSecFuncExecute "Inherit from model" RTWMemSecDataConstants "Inherit from model" RTWMemSecDataInternal "Inherit from model" RTWMemSecDataParameters "Inherit from model" } Block { BlockType Reference Name "Register" Ports [1, 1] Position [475, 79, 520, 101] ShowName off SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "568,185,356,193" block_type "register" block_version "9.1.01" sg_icon_stat "45,22,1,1,white,blue,0,ac6b57db,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('\\bf{z^{-1}}','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Register1" Ports [1, 1] Position [475, 144, 520, 166] ShowName off SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "568,185,356,193" block_type "register" block_version "9.1.01" sg_icon_stat "45,22,1,1,white,blue,0,ac6b57db,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('\\bf{z^{-1}}','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Reinterpret" Ports [1, 1] Position [380, 81, 440, 99] ShowName off SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can changed the signal between signed and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothing.

Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsigned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111000 in binary)." force_arith_type on arith_type "Signed (2's comp)" force_bin_pt on bin_pt "15" has_advanced_control "0" sggui_pos "436,54,356,309" block_type "reinterpret" block_version "9.1.01" sg_icon_stat "60,18,1,1,white,blue,0,8982c1db,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 ],[0 0 32 32 ],[0.77 0.82 0.91]);\npatch([16 11 18 11 16 24 26 28 37 30 23 18 25 18 23 30 37 28 26 24 16 ],[3 8 15 22 27 27 25 27 27 20 27 22 15 8 3 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 50 50 0 0 ],[0 0 32 32 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('reinterpret');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Reinterpret1" Ports [1, 1] Position [380, 146, 440, 164] ShowName off SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can changed the signal between signed and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothing.

Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsigned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111000 in binary)." force_arith_type on arith_type "Signed (2's comp)" force_bin_pt on bin_pt "15" has_advanced_control "0" sggui_pos "436,54,356,309" block_type "reinterpret" block_version "9.1.01" sg_icon_stat "60,18,1,1,white,blue,0,8982c1db,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 ],[0 0 32 32 ],[0.77 0.82 0.91]);\npatch([16 11 18 11 16 24 26 28 37 30 23 18 25 18 23 30 37 28 26 24 16 ],[3 8 15 22 27 27 25 27 27 20 27 22 15 8 3 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 50 50 0 0 ],[0 0 32 32 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('reinterpret');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Terminator Name "Terminator" Position [680, 80, 700, 100] ShowName off } Block { BlockType Terminator Name "Terminator1" Position [685, 145, 705, 165] ShowName off } Line { SrcBlock "32b" SrcPort 1 Points [85, 0] Branch { DstBlock "16LSB" DstPort 1 } Branch { Points [0, -65] DstBlock "16MSB" DstPort 1 } } Line { SrcBlock "16MSB" SrcPort 1 DstBlock "Reinterpret" DstPort 1 } Line { SrcBlock "16LSB" SrcPort 1 DstBlock "Reinterpret1" DstPort 1 } Line { SrcBlock "Reinterpret" SrcPort 1 DstBlock "Register" DstPort 1 } Line { SrcBlock "Reinterpret1" SrcPort 1 DstBlock "Register1" DstPort 1 } Line { SrcBlock "Register" SrcPort 1 DstBlock "Radio 3 DAC I" DstPort 1 } Line { SrcBlock "Register1" SrcPort 1 DstBlock "Radio 3 DAC Q" DstPort 1 } Line { SrcBlock "Radio 3 DAC I" SrcPort 1 DstBlock "Terminator" DstPort 1 } Line { SrcBlock "Radio 3 DAC Q" SrcPort 1 DstBlock "Terminator1" DstPort 1 } } } Block { BlockType SubSystem Name "Radio 4\nRx Buffers" Ports [5] Position [1175, 465, 1240, 565] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Radio 4\nRx Buffers" Location [2, 74, 1270, 726] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "RSSI" Position [450, 313, 480, 327] IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Inport Name "I/Q" Position [545, 163, 575, 177] Port "2" IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Inport Name "Addr" Position [325, 128, 355, 142] Port "3" IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Inport Name "WE" Position [110, 183, 140, 197] Port "4" IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Inport Name "EN" Position [110, 213, 140, 227] Port "5" IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Reference Name "Convert1" Ports [1, 1] Position [185, 212, 210, 228] ShowName off SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." arith_type "Boolean" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,374,375" block_type "convert" block_version "8.2" sg_icon_stat "25,16,1,1,white,blue,0,74901e60,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([15 10 17 10 15 23 25 27 35 28 22 17 23 17 22 28 35 27 25 23 15 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'cast');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Gateway Out" Ports [1, 1] Position [500, 30, 530, 40] ShowName off SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, double, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarded, depending on how they are configured." hdl_port off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,336,386" block_type "gatewayout" block_version "10.1.2" sg_icon_stat "30,10,1,1,white,grey,0,b3a044a9,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 ],[0 0 10 10 ],[0.88 0.88 0.88]);\npatch([13 11 13 11 13 16 17 18 21 19 17 15 17 15 17 19 21 18 17 16 13 ],[1 3 5 7 9 9 8 9 9 7 9 7 5 3 1 3 1 1 2 1 1 ],[0.98 0.96 0.92]);\nplot([0 30 30 0 0 ],[0 0 10 10 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Gateway Out1" Ports [1, 1] Position [500, 70, 530, 80] ShowName off SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, double, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarded, depending on how they are configured." hdl_port off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,336,386" block_type "gatewayout" block_version "10.1.2" sg_icon_stat "30,10,1,1,white,grey,0,b3a044a9,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 ],[0 0 10 10 ],[0.88 0.88 0.88]);\npatch([13 11 13 11 13 16 17 18 21 19 17 15 17 15 17 19 21 18 17 16 13 ],[1 3 5 7 9 9 8 9 9 7 9 7 5 3 1 3 1 1 2 1 1 ],[0.98 0.96 0.92]);\nplot([0 30 30 0 0 ],[0 0 10 10 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Logical" Ports [2, 1] Position [255, 175, 310, 235] SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "9.1.01" sg_icon_stat "55,60,1,1,white,blue,0,087b5522,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[8 17 30 43 52 52 48 52 52 40 52 43 30 17 8 20 8 8 12 8 8 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newlineand\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType SubSystem Name "Radio 4\nRSSI Buffer" Ports [3] Position [650, 264, 705, 376] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Radio 4\nRSSI Buffer" Location [2, 70, 1918, 1150] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Addr_14b" Position [325, 348, 355, 362] NamePlacement "alternate" IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Inport Name "RSSI" Position [95, 383, 125, 397] Port "2" IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Inport Name "WE" Position [720, 478, 750, 492] Port "3" IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Reference Name "11MSB" Ports [1, 1] Position [430, 346, 470, 364] NamePlacement "alternate" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardware notes: In hardware this block costs nothing." nbits "11" boolean_output off mode "Upper Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,407" block_type "slice" block_version "8.2" sg_icon_stat "40,18,1,1,white,blue,0,b1026674,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "BIT[2]" Ports [1, 1] Position [430, 401, 470, 419] SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "2" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,407" block_type "slice" block_version "8.2" sg_icon_stat "40,18,1,1,white,blue,0,b1026674,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Concat" Ports [2, 1] Position [685, 381, 725, 459] ShowName off SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point at zero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" block_version "10.1.2" sg_icon_stat "40,78,1,1,white,blue,0,df1e5aba,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([14 4 18 4 14 30 34 38 55 42 29 20 35 20 29 42 55 38 34 30 14 ],[6 16 30 44 54 54 50 54 54 41 54 45 30 15 6 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'hi');\ncolor('black');port_label('input',2,'lo');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Convert" Ports [1, 1] Position [285, 382, 320, 398] ShowName off SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." arith_type "Unsigned" n_bits "16" bin_pt "0" quantization "Truncate" overflow "Wrap" latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,461,375" block_type "convert" block_version "8.2" sg_icon_stat "35,16,1,1,white,blue,0,74901e60,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([15 10 17 10 15 23 25 27 35 28 22 17 23 17 22 28 35 27 25 23 15 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'cast');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Inverter" Ports [1, 1] Position [510, 402, 540, 418] ShowName off SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,251" block_type "inv" block_version "10.1.2" sg_icon_stat "30,16,1,1,white,blue,0,1ab4a85f,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 58 58 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[7 16 29 42 51 51 47 51 51 39 51 42 29 16 7 19 7 7 11 7 7 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Register" Ports [2, 1] Position [580, 378, 625, 422] ShowName off SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "10.1.2" sg_icon_stat "45,44,1,1,white,blue,0,cc3303a0,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('\\bf{z^{-1}}','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Reinterpret1" Ports [1, 1] Position [180, 382, 215, 398] ShowName off SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can changed the signal between signed and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothing.

Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsigned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111000 in binary)." force_arith_type on arith_type "Unsigned" force_bin_pt on bin_pt "0" has_advanced_control "0" sggui_pos "436,54,356,312" block_type "reinterpret" block_version "9.1.01" sg_icon_stat "35,16,1,1,white,blue,0,8982c1db,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 ],[0 0 32 32 ],[0.77 0.82 0.91]);\npatch([16 11 18 11 16 24 26 28 37 30 23 18 25 18 23 30 37 28 26 24 16 ],[3 8 15 22 27 27 25 27 27 20 27 22 15 8 3 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 50 50 0 0 ],[0 0 32 32 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('reinterpret');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Shared Memory" Ports [3, 1] Position [800, 323, 880, 517] AttributesFormatString "<< % >>" SourceBlock "xbsIndex_r4/Shared Memory" SourceType "Xilinx Shared Memory Random Access Memory Block" shared_memory_name "'RSSIBuff_Radio4'" depth "2^11" ownership "Locally Owned and Initialized" initVector "0" mutex "Unprotected" mode "Read and Write" write_mode "Read After Write" time_out "0" latency "1" explicit_data_type on arith_type "Unsigned" n_bits "32" bin_pt "0" xl_use_area off xl_area "[0,0,0,0,0,0,0]" implementation "Block RAM" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,384,381" block_type "shmem" block_version "10.1.2" sg_icon_stat "80,194,1,1,white,blue,0,e2c38f9a,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 80 80 0 ],[0 0 90 90 ],[0.77 0.82 0.91]);\npatch([18 5 24 5 18 39 45 51 74 56 39 27 46 27 39 56 74 51 45 39 18 ],[14 27 46 65 78 78 72 78 78 60 77 65 46 27 15 32 14 14 20 14 14 ],[0.98 0.96 0.92]);\nplot([0 80 80 0 0 ],[0 0 90 90 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'addr');\ncolor('black');port_label('input',2,'din');\ncolor('black');port_label('input',3,'we');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Terminator Name "Terminator2" Position [945, 410, 965, 430] ShowName off } Line { SrcBlock "RSSI" SrcPort 1 DstBlock "Reinterpret1" DstPort 1 } Line { SrcBlock "Convert" SrcPort 1 Points [35, 0] Branch { DstBlock "Register" DstPort 1 } Branch { Points [0, 50] DstBlock "Concat" DstPort 2 } } Line { SrcBlock "Addr_14b" SrcPort 1 Points [40, 0] Branch { DstBlock "11MSB" DstPort 1 } Branch { Points [0, 55] DstBlock "BIT[2]" DstPort 1 } } Line { SrcBlock "WE" SrcPort 1 DstBlock "Shared Memory" DstPort 3 } Line { SrcBlock "Reinterpret1" SrcPort 1 DstBlock "Convert" DstPort 1 } Line { SrcBlock "Concat" SrcPort 1 DstBlock "Shared Memory" DstPort 2 } Line { SrcBlock "BIT[2]" SrcPort 1 DstBlock "Inverter" DstPort 1 } Line { SrcBlock "11MSB" SrcPort 1 DstBlock "Shared Memory" DstPort 1 } Line { SrcBlock "Shared Memory" SrcPort 1 DstBlock "Terminator2" DstPort 1 } Line { SrcBlock "Register" SrcPort 1 DstBlock "Concat" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Register" DstPort 2 } } } Block { BlockType SubSystem Name "Radio 4 I/Q\nBuffer" Ports [3] Position [650, 116, 705, 224] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Radio 4 I/Q\nBuffer" Location [2, 74, 1270, 726] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Addr_14b" Position [205, 68, 235, 82] IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Inport Name "I/Q_32b" Position [205, 98, 235, 112] Port "2" IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Inport Name "WE" Position [205, 128, 235, 142] Port "3" IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Reference Name "Shared Memory" Ports [3, 1] Position [320, 60, 400, 150] AttributesFormatString "<< % >>" SourceBlock "xbsIndex_r4/Shared Memory" SourceType "Xilinx Shared Memory Random Access Memory Block" shared_memory_name "'RxBuff_Radio4'" depth "2^14" ownership "Locally Owned and Initialized" initVector "0" mutex "Unprotected" mode "Read and Write" write_mode "Read After Write" time_out "0" latency "1" explicit_data_type on arith_type "Unsigned" n_bits "32" bin_pt "0" xl_use_area off xl_area "[0,0,0,0,0,0,0]" implementation "Block RAM" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,384,381" block_type "shmem" block_version "10.1.2" sg_icon_stat "80,90,1,1,white,blue,0,e2c38f9a,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 80 80 0 ],[0 0 90 90 ],[0.77 0.82 0.91]);\npatch([18 5 24 5 18 39 45 51 74 56 39 27 46 27 39 56 74 51 45 39 18 ],[14 27 46 65 78 78 72 78 78 60 77 65 46 27 15 32 14 14 20 14 14 ],[0.98 0.96 0.92]);\nplot([0 80 80 0 0 ],[0 0 90 90 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'addr');\ncolor('black');port_label('input',2,'din');\ncolor('black');port_label('input',3,'we');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Terminator Name "Terminator" Position [450, 95, 470, 115] ShowName off } Line { SrcBlock "Shared Memory" SrcPort 1 DstBlock "Terminator" DstPort 1 } Line { SrcBlock "WE" SrcPort 1 DstBlock "Shared Memory" DstPort 3 } Line { SrcBlock "I/Q_32b" SrcPort 1 DstBlock "Shared Memory" DstPort 2 } Line { SrcBlock "Addr_14b" SrcPort 1 DstBlock "Shared Memory" DstPort 1 } } } Block { BlockType Scope Name "Scope" Ports [2] Position [585, 14, 625, 96] Floating off Location [5, 49, 1285, 757] Open off NumInputPorts "2" ZoomMode "yonly" List { ListType AxesTitles axes1 "%" axes2 "%" } YMin "-5~-5" YMax "5~5" SaveName "ScopeData2" DataFormat "StructureWithTime" MaxDataPoints "40000" SampleTime "0" } Line { SrcBlock "Gateway Out1" SrcPort 1 DstBlock "Scope" DstPort 2 } Line { SrcBlock "Gateway Out" SrcPort 1 DstBlock "Scope" DstPort 1 } Line { SrcBlock "I/Q" SrcPort 1 DstBlock "Radio 4 I/Q\nBuffer" DstPort 2 } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "Logical" DstPort 2 } Line { SrcBlock "EN" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "WE" SrcPort 1 DstBlock "Logical" DstPort 1 } Line { SrcBlock "Addr" SrcPort 1 Points [75, 0] Branch { Points [0, -100] DstBlock "Gateway Out" DstPort 1 } Branch { Labels [0, 0] DstBlock "Radio 4 I/Q\nBuffer" DstPort 1 } Branch { Points [0, 150] DstBlock "Radio 4\nRSSI Buffer" DstPort 1 } } Line { SrcBlock "Logical" SrcPort 1 Points [65, 0] Branch { Points [85, 0] Branch { Points [0, -130] DstBlock "Gateway Out1" DstPort 1 } Branch { Labels [0, 0] DstBlock "Radio 4 I/Q\nBuffer" DstPort 3 } } Branch { Points [0, 150] DstBlock "Radio 4\nRSSI Buffer" DstPort 3 } } Line { SrcBlock "RSSI" SrcPort 1 DstBlock "Radio 4\nRSSI Buffer" DstPort 2 } } } Block { BlockType SubSystem Name "Radio 4\nTx Buffer" Ports [3, 1] Position [1015, 952, 1095, 1008] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Radio 4\nTx Buffer" Location [2, 74, 1270, 726] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "RdAddr_14b" Position [350, 288, 380, 302] NamePlacement "alternate" IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Inport Name "Rst" Position [30, 173, 60, 187] Port "2" IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Inport Name "En" Position [30, 203, 60, 217] Port "3" IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Reference Name "Constant" Ports [0, 1] Position [630, 350, 655, 370] ShowName off SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" arith_type "Unsigned" const "0" n_bits "32" bin_pt "0" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,400,346" block_type "constant" block_version "10.1.2" sg_icon_stat "25,20,1,1,white,blue,0,72d575a1,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 26 26 ],[0.77 0.82 0.91]);\npatch([20 16 22 16 20 27 29 31 38 32 26 22 28 22 26 32 38 31 29 27 20 ],[3 7 13 19 23 23 21 23 23 17 23 19 13 7 3 9 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 26 26 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'0');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Constant1" Ports [0, 1] Position [355, 345, 380, 365] ShowName off SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" arith_type "Boolean" const "0" n_bits "32" bin_pt "0" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,400,346" block_type "constant" block_version "10.1.2" sg_icon_stat "25,20,1,1,white,blue,0,72d575a1,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 26 26 ],[0.77 0.82 0.91]);\npatch([20 16 22 16 20 27 29 31 38 32 26 22 28 22 26 32 38 31 29 27 20 ],[3 7 13 19 23 23 21 23 23 17 23 19 13 7 3 9 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 26 26 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'0');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Constant2" Ports [0, 1] Position [355, 315, 380, 335] ShowName off SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" arith_type "Unsigned" const "0" n_bits "32" bin_pt "0" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,400,346" block_type "constant" block_version "10.1.2" sg_icon_stat "25,20,1,1,white,blue,0,72d575a1,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 26 26 ],[0.77 0.82 0.91]);\npatch([20 16 22 16 20 27 29 31 38 32 26 22 28 22 26 32 38 31 29 27 20 ],[3 7 13 19 23 23 21 23 23 17 23 19 13 7 3 9 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 26 26 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'0');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Convert" Ports [1, 1] Position [350, 188, 375, 202] ShowName off SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." arith_type "Boolean" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,374,375" block_type "convert" block_version "8.2" sg_icon_stat "25,14,1,1,white,blue,0,74901e60,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([15 10 17 10 15 23 25 27 35 28 22 17 23 17 22 28 35 27 25 23 15 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'cast');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Convert1" Ports [1, 1] Position [100, 203, 120, 217] ShowName off SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." arith_type "Boolean" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,374,375" block_type "convert" block_version "8.2" sg_icon_stat "20,14,1,1,white,blue,0,74901e60,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([15 10 17 10 15 23 25 27 35 28 22 17 23 17 22 28 35 27 25 23 15 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'cast');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Inverter" Ports [1, 1] Position [150, 201, 180, 219] SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "9.1.01" sg_icon_stat "30,18,1,1,white,blue,0,1ab4a85f,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 58 58 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[7 16 29 42 51 51 47 51 51 39 51 42 29 16 7 19 7 7 11 7 7 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Logical" Ports [2, 1] Position [215, 165, 270, 225] SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "9.1.01" sg_icon_stat "55,60,1,1,white,blue,0,f4a65842,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[8 17 30 43 52 52 48 52 52 40 52 43 30 17 8 20 8 8 12 8 8 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newlineor\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Mux" Ports [3, 1] Position [750, 273, 795, 377] SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,303" block_type "mux" block_version "10.1.2" sg_icon_stat "45,104,1,1,white,blue,3,613f58e1,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 ],[0 14.8571 89.1429 104 ],[0.77 0.82 0.91]);\npatch([10 3 14 3 10 22 25 28 41 31 21 14 25 14 21 31 41 28 25 22 10 ],[34 41 52 63 70 70 67 70 70 60 70 63 52 41 34 44 34 34 37 34 34 ],[0.98 0.96 0.92]);\nplot([0 45 45 0 0 ],[0 14.8571 89.1429 104 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('input',3,'d1');\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Shared Memory" Ports [3, 1] Position [445, 280, 525, 370] AttributesFormatString "<< % >>" SourceBlock "xbsIndex_r4/Shared Memory" SourceType "Xilinx Shared Memory Random Access Memory Block" shared_memory_name "'TxBuff_Radio4'" depth "2^14" ownership "Locally Owned and Initialized" initVector "0" mutex "Unprotected" mode "Read and Write" write_mode "Read After Write" time_out "0" latency "1" explicit_data_type on arith_type "Unsigned" n_bits "32" bin_pt "0" xl_use_area off xl_area "[0,0,0,0,0,0,0]" implementation "Block RAM" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,384,381" block_type "shmem" block_version "10.1.2" sg_icon_stat "80,90,1,1,white,blue,0,e2c38f9a,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 80 80 0 ],[0 0 90 90 ],[0.77 0.82 0.91]);\npatch([18 5 24 5 18 39 45 51 74 56 39 27 46 27 39 56 74 51 45 39 18 ],[14 27 46 65 78 78 72 78 78 60 77 65 46 27 15 32 14 14 20 14 14 ],[0.98 0.96 0.92]);\nplot([0 80 80 0 0 ],[0 0 90 90 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'addr');\ncolor('black');port_label('input',2,'din');\ncolor('black');port_label('input',3,'we');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Outport Name "IQ_32b" Position [885, 318, 915, 332] IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Line { SrcBlock "Mux" SrcPort 1 DstBlock "IQ_32b" DstPort 1 } Line { SrcBlock "Constant2" SrcPort 1 DstBlock "Shared Memory" DstPort 2 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Shared Memory" DstPort 3 } Line { SrcBlock "Shared Memory" SrcPort 1 DstBlock "Mux" DstPort 2 } Line { SrcBlock "Constant" SrcPort 1 DstBlock "Mux" DstPort 3 } Line { SrcBlock "RdAddr_14b" SrcPort 1 DstBlock "Shared Memory" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical" DstPort 2 } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "Inverter" DstPort 1 } Line { SrcBlock "En" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Rst" SrcPort 1 DstBlock "Logical" DstPort 1 } Line { SrcBlock "Convert" SrcPort 1 Points [160, 0; 0, 95] DstBlock "Mux" DstPort 1 } Line { SrcBlock "Logical" SrcPort 1 DstBlock "Convert" DstPort 1 } } } Block { BlockType SubSystem Name "Radio 4 Inputs" Ports [2, 2] Position [910, 450, 1080, 510] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Radio 4 Inputs" Location [2, 74, 1014, 726] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "DebugRxBuffers" Position [180, 228, 210, 242] IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Inport Name "MGCAGC_AGCDCO_SEL" Position [180, 323, 210, 337] Port "2" IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType SubSystem Name "ADC I" Ports [2, 2] Position [430, 223, 580, 267] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "ADC I" Location [37, 74, 1049, 726] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Debug" Position [685, 13, 715, 27] IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Inport Name "MGCAGC_AGCDCO_SEL" Position [135, 203, 165, 217] Port "2" IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Constant Name "Constant1" Position [15, 280, 45, 310] ShowName off Value "0" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Reference Name "Counter" Ports [0, 1] Position [520, 300, 580, 360] SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited counter is implemented by combining a counter with a comparator." cnt_type "Free Running" cnt_to "Inf" operation "Down" start_count "2^14-1" cnt_by_val "1" arith_type "Unsigned" n_bits "14" bin_pt "0" load_pin off rst off en off explicit_period "on" period "1" dbl_ovrd off use_behavioral_HDL off use_rpm off implementation "Fabric" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,619" block_type "counter" block_version "10.1.3" sg_icon_stat "60,60,1,1,white,blue,0,a170c862,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([14 4 18 4 14 30 34 38 55 42 29 20 35 20 29 42 55 38 34 30 14 ],[6 16 30 44 54 54 50 54 54 41 54 45 30 15 6 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'out');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "FromAGC_Radio4_I" Ports [1, 1] Position [120, 385, 185, 405] SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, double and fixed point to Xilinx fixed point type.

Hardware notes: In hardware these blocks become top level input ports." arith_type "Signed (2's comp)" n_bits "14" bin_pt "13" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,406" block_type "gatewayin" block_version "10.1.3" sg_icon_stat "65,20,1,1,white,yellow,0,bc55d28f,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([27 24 29 24 27 32 33 34 40 36 32 29 34 29 32 36 40 34 33 32 27 ],[2 5 10 15 18 18 17 18 18 14 18 15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Mux" Ports [3, 1] Position [820, 48, 865, 152] SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "1" bin_pt "0" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,303" block_type "mux" block_version "10.1.3" sg_icon_stat "45,104,1,1,white,blue,3,613f58e1,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 ],[0 14.8571 89.1429 104 ],[0.77 0.82 0.91]);\npatch([10 3 14 3 10 22 25 28 41 31 21 14 25 14 21 31 41 28 25 22 10 ],[34 41 52 63 70 70 67 70 70 60 70 63 52 41 34 44 34 34 37 34 34 ],[0.98 0.96 0.92]);\nplot([0 45 45 0 0 ],[0 14.8571 89.1429 104 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('input',3,'d1');\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Mux1" Ports [3, 1] Position [820, 243, 865, 347] SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "1" bin_pt "0" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,303" block_type "mux" block_version "10.1.3" sg_icon_stat "45,104,1,1,white,blue,3,613f58e1,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 ],[0 14.8571 89.1429 104 ],[0.77 0.82 0.91]);\npatch([10 3 14 3 10 22 25 28 41 31 21 14 25 14 21 31 41 28 25 22 10 ],[34 41 52 63 70 70 67 70 70 60 70 63 52 41 34 44 34 34 37 34 34 ],[0.98 0.96 0.92]);\nplot([0 45 45 0 0 ],[0 14.8571 89.1429 104 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('input',3,'d1');\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Mux2" Ports [3, 1] Position [280, 243, 325, 347] SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "1" bin_pt "0" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,303" block_type "mux" block_version "10.1.3" sg_icon_stat "45,104,1,1,white,blue,3,613f58e1,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 ],[0 14.8571 89.1429 104 ],[0.77 0.82 0.91]);\npatch([10 3 14 3 10 22 25 28 41 31 21 14 25 14 21 31 41 28 25 22 10 ],[34 41 52 63 70 70 67 70 70 60 70 63 52 41 34 44 34 34 37 34 34 ],[0.98 0.96 0.92]);\nplot([0 45 45 0 0 ],[0 14.8571 89.1429 104 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('input',3,'d1');\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Radio 4 ADC I" Ports [1, 1] Position [85, 274, 180, 316] LinkData { BlockName "radio4_adc_I" DialogParameters { sg_icon_stat "65,20,1,1,white,yellow,0,bc55d28f,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([27 24 29 24 27 32 33 34 40 36 32 29 34 29 32 36 40 34 33 32 27 ],[2 5 10 15 18 18 17 18 18 14 18 15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end icon text');\n" } } SourceBlock "WARP_Blockset/WARP Radio Board ADC//DACs/Radio 4 ADC I" SourceType "" ShowPortLabels "FromPortIcon" SystemSampleTime "-1" FunctionWithSeparateData off RTWMemSecFuncInitTerm "Inherit from model" RTWMemSecFuncExecute "Inherit from model" RTWMemSecDataConstants "Inherit from model" RTWMemSecDataInternal "Inherit from model" RTWMemSecDataParameters "Inherit from model" samp_period "1" } Block { BlockType Reference Name "Register" Ports [1, 1] Position [445, 281, 480, 309] ShowName off SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "8.2" sg_icon_stat "35,28,1,1,white,blue,0,ac6b57db,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('\\bf{z^{-1}}','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Reinterpret" Ports [1, 1] Position [665, 314, 715, 346] SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can changed the signal between signed and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothing.

Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsigned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111000 in binary)." force_arith_type on arith_type "Signed (2's comp)" force_bin_pt on bin_pt "13" has_advanced_control "0" sggui_pos "20,20,336,312" block_type "reinterpret" block_version "10.1.3" sg_icon_stat "50,32,1,1,white,blue,0,8982c1db,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 ],[0 0 32 32 ],[0.77 0.82 0.91]);\npatch([16 11 18 11 16 24 26 28 37 30 23 18 25 18 23 30 37 28 26 24 16 ],[3 8 15 22 27 27 25 27 27 20 27 22 15 8 3 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 50 50 0 0 ],[0 0 32 32 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('reinterpret');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Slice" Ports [1, 1] Position [670, 120, 730, 150] SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,376" block_type "slice" block_version "10.1.3" sg_icon_stat "60,30,1,1,white,blue,0,b1026674,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "radio4_ADC_I_OTR" Ports [1, 1] Position [440, 94, 495, 106] NamePlacement "alternate" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, double and fixed point to Xilinx fixed point type.

Hardware notes: In hardware these blocks become top level input ports." arith_type "Unsigned" n_bits "1" bin_pt "0" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,356,432" block_type "gatewayin" block_version "VER_STRING_GOES_HERE" sg_icon_stat "55,12,1,1,white,yellow,0,bc55d28f,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([27 24 29 24 27 32 33 34 40 36 32 29 34 29 32 36 40 34 33 32 27 ],[2 5 10 15 18 18 17 18 18 14 18 15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Outport Name "OTR I" Position [925, 93, 955, 107] IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Outport Name "ADC I" Position [925, 288, 955, 302] Port "2" IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Line { SrcBlock "Constant1" SrcPort 1 Points [10, 0] Branch { Points [0, -195] DstBlock "radio4_ADC_I_OTR" DstPort 1 } Branch { DstBlock "Radio 4 ADC I" DstPort 1 } Branch { Points [0, 100] DstBlock "FromAGC_Radio4_I" DstPort 1 } } Line { SrcBlock "Mux" SrcPort 1 DstBlock "OTR I" DstPort 1 } Line { SrcBlock "Debug" SrcPort 1 Points [40, 0; 0, 45] Branch { DstBlock "Mux" DstPort 1 } Branch { Points [0, 195] DstBlock "Mux1" DstPort 1 } } Line { SrcBlock "radio4_ADC_I_OTR" SrcPort 1 DstBlock "Mux" DstPort 2 } Line { SrcBlock "Slice" SrcPort 1 DstBlock "Mux" DstPort 3 } Line { SrcBlock "Mux1" SrcPort 1 DstBlock "ADC I" DstPort 1 } Line { SrcBlock "Register" SrcPort 1 DstBlock "Mux1" DstPort 2 } Line { SrcBlock "Reinterpret" SrcPort 1 DstBlock "Mux1" DstPort 3 } Line { SrcBlock "Counter" SrcPort 1 Points [25, 0] Branch { DstBlock "Reinterpret" DstPort 1 } Branch { Points [0, -195] DstBlock "Slice" DstPort 1 } } Line { SrcBlock "MGCAGC_AGCDCO_SEL" SrcPort 1 Points [70, 0; 0, 50] DstBlock "Mux2" DstPort 1 } Line { SrcBlock "FromAGC_Radio4_I" SrcPort 1 Points [50, 0; 0, -65] DstBlock "Mux2" DstPort 3 } Line { SrcBlock "Radio 4 ADC I" SrcPort 1 DstBlock "Mux2" DstPort 2 } Line { SrcBlock "Mux2" SrcPort 1 DstBlock "Register" DstPort 1 } } } Block { BlockType SubSystem Name "ADC Q" Ports [2, 2] Position [430, 298, 580, 342] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "ADC Q" Location [22, 84, 1034, 736] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Debug" Position [675, 13, 705, 27] IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Inport Name "MGCAGC_AGCDCO_SEL" Position [120, 203, 150, 217] Port "2" IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Constant Name "Constant1" Position [15, 280, 45, 310] ShowName off Value "0" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Reference Name "Counter" Ports [0, 1] Position [505, 300, 565, 360] SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited counter is implemented by combining a counter with a comparator." cnt_type "Free Running" cnt_to "Inf" operation "Up" start_count "0" cnt_by_val "1" arith_type "Unsigned" n_bits "14" bin_pt "0" load_pin off rst off en off explicit_period "on" period "1" dbl_ovrd off use_behavioral_HDL off use_rpm off implementation "Fabric" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,619" block_type "counter" block_version "10.1.3" sg_icon_stat "60,60,1,1,white,blue,0,a170c862,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([14 4 18 4 14 30 34 38 55 42 29 20 35 20 29 42 55 38 34 30 14 ],[6 16 30 44 54 54 50 54 54 41 54 45 30 15 6 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'out');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "FromAGC_Radio4_Q" Ports [1, 1] Position [105, 385, 170, 405] SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, double and fixed point to Xilinx fixed point type.

Hardware notes: In hardware these blocks become top level input ports." arith_type "Signed (2's comp)" n_bits "14" bin_pt "13" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,406" block_type "gatewayin" block_version "10.1.3" sg_icon_stat "65,20,1,1,white,yellow,0,bc55d28f,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([27 24 29 24 27 32 33 34 40 36 32 29 34 29 32 36 40 34 33 32 27 ],[2 5 10 15 18 18 17 18 18 14 18 15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Mux" Ports [3, 1] Position [810, 48, 855, 152] SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "1" bin_pt "0" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,303" block_type "mux" block_version "10.1.3" sg_icon_stat "45,104,1,1,white,blue,3,613f58e1,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 ],[0 14.8571 89.1429 104 ],[0.77 0.82 0.91]);\npatch([10 3 14 3 10 22 25 28 41 31 21 14 25 14 21 31 41 28 25 22 10 ],[34 41 52 63 70 70 67 70 70 60 70 63 52 41 34 44 34 34 37 34 34 ],[0.98 0.96 0.92]);\nplot([0 45 45 0 0 ],[0 14.8571 89.1429 104 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('input',3,'d1');\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Mux1" Ports [3, 1] Position [810, 243, 855, 347] SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "1" bin_pt "0" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,303" block_type "mux" block_version "10.1.3" sg_icon_stat "45,104,1,1,white,blue,3,613f58e1,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 ],[0 14.8571 89.1429 104 ],[0.77 0.82 0.91]);\npatch([10 3 14 3 10 22 25 28 41 31 21 14 25 14 21 31 41 28 25 22 10 ],[34 41 52 63 70 70 67 70 70 60 70 63 52 41 34 44 34 34 37 34 34 ],[0.98 0.96 0.92]);\nplot([0 45 45 0 0 ],[0 14.8571 89.1429 104 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('input',3,'d1');\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Mux2" Ports [3, 1] Position [265, 243, 310, 347] SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "1" bin_pt "0" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,303" block_type "mux" block_version "10.1.3" sg_icon_stat "45,104,1,1,white,blue,3,613f58e1,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 ],[0 14.8571 89.1429 104 ],[0.77 0.82 0.91]);\npatch([10 3 14 3 10 22 25 28 41 31 21 14 25 14 21 31 41 28 25 22 10 ],[34 41 52 63 70 70 67 70 70 60 70 63 52 41 34 44 34 34 37 34 34 ],[0.98 0.96 0.92]);\nplot([0 45 45 0 0 ],[0 14.8571 89.1429 104 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('input',3,'d1');\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Radio 4 ADC Q" Ports [1, 1] Position [85, 274, 180, 316] LinkData { BlockName "radio4_adc_Q" DialogParameters { sg_icon_stat "65,20,1,1,white,yellow,0,bc55d28f,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([27 24 29 24 27 32 33 34 40 36 32 29 34 29 32 36 40 34 33 32 27 ],[2 5 10 15 18 18 17 18 18 14 18 15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end icon text');\n" } } SourceBlock "WARP_Blockset/WARP Radio Board ADC//DACs/Radio 4 ADC Q" SourceType "" ShowPortLabels "FromPortIcon" SystemSampleTime "-1" FunctionWithSeparateData off RTWMemSecFuncInitTerm "Inherit from model" RTWMemSecFuncExecute "Inherit from model" RTWMemSecDataConstants "Inherit from model" RTWMemSecDataInternal "Inherit from model" RTWMemSecDataParameters "Inherit from model" samp_period "1" } Block { BlockType Reference Name "Register" Ports [1, 1] Position [385, 281, 420, 309] ShowName off SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "8.2" sg_icon_stat "35,28,1,1,white,blue,0,ac6b57db,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('\\bf{z^{-1}}','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Reinterpret" Ports [1, 1] Position [655, 314, 705, 346] SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can changed the signal between signed and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothing.

Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsigned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111000 in binary)." force_arith_type on arith_type "Signed (2's comp)" force_bin_pt on bin_pt "13" has_advanced_control "0" sggui_pos "20,20,336,312" block_type "reinterpret" block_version "10.1.3" sg_icon_stat "50,32,1,1,white,blue,0,8982c1db,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 ],[0 0 32 32 ],[0.77 0.82 0.91]);\npatch([16 11 18 11 16 24 26 28 37 30 23 18 25 18 23 30 37 28 26 24 16 ],[3 8 15 22 27 27 25 27 27 20 27 22 15 8 3 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 50 50 0 0 ],[0 0 32 32 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('reinterpret');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Slice" Ports [1, 1] Position [660, 120, 720, 150] SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,376" block_type "slice" block_version "10.1.3" sg_icon_stat "60,30,1,1,white,blue,0,b1026674,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "radio4_ADC_Q_OTR" Ports [1, 1] Position [115, 94, 170, 106] SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, double and fixed point to Xilinx fixed point type.

Hardware notes: In hardware these blocks become top level input ports." arith_type "Unsigned" n_bits "1" bin_pt "0" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,356,432" block_type "gatewayin" block_version "VER_STRING_GOES_HERE" sg_icon_stat "55,12,1,1,white,yellow,0,bc55d28f,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([27 24 29 24 27 32 33 34 40 36 32 29 34 29 32 36 40 34 33 32 27 ],[2 5 10 15 18 18 17 18 18 14 18 15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Outport Name "OTR Q" Position [955, 93, 985, 107] IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Outport Name "ADC Q" Position [950, 288, 980, 302] Port "2" IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Line { SrcBlock "Constant1" SrcPort 1 Points [10, 0] Branch { Points [0, -195] DstBlock "radio4_ADC_Q_OTR" DstPort 1 } Branch { DstBlock "Radio 4 ADC Q" DstPort 1 } Branch { Points [0, 100] DstBlock "FromAGC_Radio4_Q" DstPort 1 } } Line { SrcBlock "Mux" SrcPort 1 DstBlock "OTR Q" DstPort 1 } Line { SrcBlock "Debug" SrcPort 1 Points [40, 0; 0, 45] Branch { DstBlock "Mux" DstPort 1 } Branch { Points [0, 195] DstBlock "Mux1" DstPort 1 } } Line { SrcBlock "radio4_ADC_Q_OTR" SrcPort 1 DstBlock "Mux" DstPort 2 } Line { SrcBlock "Slice" SrcPort 1 DstBlock "Mux" DstPort 3 } Line { SrcBlock "Mux1" SrcPort 1 DstBlock "ADC Q" DstPort 1 } Line { SrcBlock "Register" SrcPort 1 DstBlock "Mux1" DstPort 2 } Line { SrcBlock "Reinterpret" SrcPort 1 DstBlock "Mux1" DstPort 3 } Line { SrcBlock "Counter" SrcPort 1 Points [30, 0] Branch { DstBlock "Reinterpret" DstPort 1 } Branch { Points [0, -195] DstBlock "Slice" DstPort 1 } } Line { SrcBlock "MGCAGC_AGCDCO_SEL" SrcPort 1 Points [70, 0; 0, 50] DstBlock "Mux2" DstPort 1 } Line { SrcBlock "FromAGC_Radio4_Q" SrcPort 1 Points [50, 0; 0, -65] DstBlock "Mux2" DstPort 3 } Line { SrcBlock "Radio 4 ADC Q" SrcPort 1 DstBlock "Mux2" DstPort 2 } Line { SrcBlock "Mux2" SrcPort 1 DstBlock "Register" DstPort 1 } } } Block { BlockType SubSystem Name "Concatenates_1" Ports [4, 1] Position [695, 218, 740, 372] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Concatenates_1" Location [2, 74, 1270, 726] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "OTR_I" Position [395, 43, 425, 57] IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Inport Name "ADC_I" Position [330, 93, 360, 107] Port "2" IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Inport Name "OTR_Q" Position [390, 163, 420, 177] Port "3" IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Inport Name "ADC_Q" Position [330, 213, 360, 227] Port "4" IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Reference Name "Concat1" Ports [2, 1] Position [490, 191, 520, 229] ShowName off SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point at zero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" block_version "8.2" sg_icon_stat "30,38,1,1,white,blue,0,df1e5aba,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([14 4 18 4 14 30 34 38 55 42 29 20 35 20 29 42 55 38 34 30 14 ],[6 16 30 44 54 54 50 54 54 41 54 45 30 15 6 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'hi');\ncolor('black');port_label('input',2,'lo');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Concat2" Ports [2, 1] Position [490, 71, 520, 109] ShowName off SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point at zero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" block_version "8.2" sg_icon_stat "30,38,1,1,white,blue,0,df1e5aba,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([14 4 18 4 14 30 34 38 55 42 29 20 35 20 29 42 55 38 34 30 14 ],[6 16 30 44 54 54 50 54 54 41 54 45 30 15 6 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'hi');\ncolor('black');port_label('input',2,'lo');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Concat3" Ports [2, 1] Position [550, 150, 575, 230] ShowName off SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point at zero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" block_version "8.2" sg_icon_stat "25,80,1,1,white,blue,0,df1e5aba,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([14 4 18 4 14 30 34 38 55 42 29 20 35 20 29 42 55 38 34 30 14 ],[6 16 30 44 54 54 50 54 54 41 54 45 30 15 6 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'hi');\ncolor('black');port_label('input',2,'lo');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Concat4" Ports [2, 1] Position [550, 30, 575, 110] ShowName off SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point at zero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" block_version "8.2" sg_icon_stat "25,80,1,1,white,blue,0,df1e5aba,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([14 4 18 4 14 30 34 38 55 42 29 20 35 20 29 42 55 38 34 30 14 ],[6 16 30 44 54 54 50 54 54 41 54 45 30 15 6 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'hi');\ncolor('black');port_label('input',2,'lo');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Concat5" Ports [2, 1] Position [635, 50, 660, 130] ShowName off SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary point at zero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" block_version "8.2" sg_icon_stat "25,80,1,1,white,blue,0,df1e5aba,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([14 4 18 4 14 30 34 38 55 42 29 20 35 20 29 42 55 38 34 30 14 ],[6 16 30 44 54 54 50 54 54 41 54 45 30 15 6 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'hi');\ncolor('black');port_label('input',2,'lo');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Reinterpret" Ports [1, 1] Position [385, 90, 420, 110] ShowName off SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can changed the signal between signed and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothing.

Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsigned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111000 in binary)." force_arith_type on arith_type "Unsigned" force_bin_pt on bin_pt "0" has_advanced_control "0" sggui_pos "20,20,356,309" block_type "reinterpret" block_version "8.2" sg_icon_stat "35,20,1,1,white,blue,0,8982c1db,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 ],[0 0 32 32 ],[0.77 0.82 0.91]);\npatch([16 11 18 11 16 24 26 28 37 30 23 18 25 18 23 30 37 28 26 24 16 ],[3 8 15 22 27 27 25 27 27 20 27 22 15 8 3 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 50 50 0 0 ],[0 0 32 32 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('reinterpret');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Reinterpret1" Ports [1, 1] Position [390, 210, 425, 230] ShowName off SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can changed the signal between signed and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothing.

Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsigned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111000 in binary)." force_arith_type on arith_type "Unsigned" force_bin_pt on bin_pt "0" has_advanced_control "0" sggui_pos "20,20,356,309" block_type "reinterpret" block_version "8.2" sg_icon_stat "35,20,1,1,white,blue,0,8982c1db,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 ],[0 0 32 32 ],[0.77 0.82 0.91]);\npatch([16 11 18 11 16 24 26 28 37 30 23 18 25 18 23 30 37 28 26 24 16 ],[3 8 15 22 27 27 25 27 27 20 27 22 15 8 3 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 50 50 0 0 ],[0 0 32 32 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('reinterpret');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "zero" Ports [0, 1] Position [440, 191, 460, 209] ShowName off SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" arith_type "Unsigned" const "0" n_bits "1" bin_pt "0" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "20,18,1,1,white,blue,0,72d575a1,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 26 26 ],[0.77 0.82 0.91]);\npatch([20 16 22 16 20 27 29 31 38 32 26 22 28 22 26 32 38 31 29 27 20 ],[3 7 13 19 23 23 21 23 23 17 23 19 13 7 3 9 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 26 26 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'0');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "zero1" Ports [0, 1] Position [440, 71, 460, 89] ShowName off SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" arith_type "Unsigned" const "0" n_bits "1" bin_pt "0" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "20,18,1,1,white,blue,0,72d575a1,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 26 26 ],[0.77 0.82 0.91]);\npatch([20 16 22 16 20 27 29 31 38 32 26 22 28 22 26 32 38 31 29 27 20 ],[3 7 13 19 23 23 21 23 23 17 23 19 13 7 3 9 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 26 26 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'0');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Outport Name "32b" Position [840, 83, 870, 97] IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Line { SrcBlock "Reinterpret1" SrcPort 1 DstBlock "Concat1" DstPort 2 } Line { SrcBlock "Reinterpret" SrcPort 1 DstBlock "Concat2" DstPort 2 } Line { SrcBlock "ADC_Q" SrcPort 1 DstBlock "Reinterpret1" DstPort 1 } Line { SrcBlock "OTR_Q" SrcPort 1 DstBlock "Concat3" DstPort 1 } Line { SrcBlock "ADC_I" SrcPort 1 DstBlock "Reinterpret" DstPort 1 } Line { SrcBlock "Concat5" SrcPort 1 DstBlock "32b" DstPort 1 } Line { SrcBlock "OTR_I" SrcPort 1 DstBlock "Concat4" DstPort 1 } Line { SrcBlock "Concat3" SrcPort 1 Points [25, 0; 0, -80] DstBlock "Concat5" DstPort 2 } Line { SrcBlock "Concat4" SrcPort 1 DstBlock "Concat5" DstPort 1 } Line { SrcBlock "Concat2" SrcPort 1 Points [0, 0] DstBlock "Concat4" DstPort 2 } Line { SrcBlock "zero1" SrcPort 1 DstBlock "Concat2" DstPort 1 } Line { SrcBlock "Concat1" SrcPort 1 DstBlock "Concat3" DstPort 2 } Line { SrcBlock "zero" SrcPort 1 DstBlock "Concat1" DstPort 1 } } } Block { BlockType Reference Name "Gateway Out1" Ports [1, 1] Position [725, 135, 755, 145] ShowName off SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, double, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarded, depending on how they are configured." hdl_port off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,336,386" block_type "gatewayout" block_version "10.1.2" sg_icon_stat "30,10,1,1,white,grey,0,b3a044a9,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 ],[0 0 10 10 ],[0.88 0.88 0.88]);\npatch([13 11 13 11 13 16 17 18 21 19 17 15 17 15 17 19 21 18 17 16 13 ],[1 3 5 7 9 9 8 9 9 7 9 7 5 3 1 3 1 1 2 1 1 ],[0.98 0.96 0.92]);\nplot([0 30 30 0 0 ],[0 0 10 10 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Gateway Out4" Ports [1, 1] Position [725, 120, 755, 130] ShowName off SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, double, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarded, depending on how they are configured." hdl_port off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,336,386" block_type "gatewayout" block_version "10.1.2" sg_icon_stat "30,10,1,1,white,grey,0,b3a044a9,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 ],[0 0 10 10 ],[0.88 0.88 0.88]);\npatch([13 11 13 11 13 16 17 18 21 19 17 15 17 15 17 19 21 18 17 16 13 ],[1 3 5 7 9 9 8 9 9 7 9 7 5 3 1 3 1 1 2 1 1 ],[0.98 0.96 0.92]);\nplot([0 30 30 0 0 ],[0 0 10 10 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType SubSystem Name "RSSI" Ports [1, 1] Position [500, 407, 570, 443] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "RSSI" Location [2, 74, 1184, 726] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Debug" Position [465, 28, 495, 42] IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Constant Name "Constant1" Position [160, 100, 190, 130] ShowName off Value "0" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Reference Name "Counter" Ports [0, 1] Position [380, 120, 440, 180] SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited counter is implemented by combining a counter with a comparator." cnt_type "Free Running" cnt_to "Inf" operation "Up" start_count "0" cnt_by_val "1" arith_type "Unsigned" n_bits "10" bin_pt "0" load_pin off rst off en off explicit_period "on" period "1" dbl_ovrd off use_behavioral_HDL off use_rpm off implementation "Fabric" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,619" block_type "counter" block_version "10.1.3" sg_icon_stat "60,60,1,1,white,blue,0,a170c862,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([14 4 18 4 14 30 34 38 55 42 29 20 35 20 29 42 55 38 34 30 14 ],[6 16 30 44 54 54 50 54 54 41 54 45 30 15 6 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'out');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Mux" Ports [3, 1] Position [600, 63, 645, 167] SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "1" bin_pt "0" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,303" block_type "mux" block_version "10.1.3" sg_icon_stat "45,104,1,1,white,blue,3,613f58e1,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 ],[0 14.8571 89.1429 104 ],[0.77 0.82 0.91]);\npatch([10 3 14 3 10 22 25 28 41 31 21 14 25 14 21 31 41 28 25 22 10 ],[34 41 52 63 70 70 67 70 70 60 70 63 52 41 34 44 34 34 37 34 34 ],[0.98 0.96 0.92]);\nplot([0 45 45 0 0 ],[0 14.8571 89.1429 104 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('input',3,'d1');\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "radio4_RSSI" Ports [1, 1] Position [280, 109, 335, 121] NamePlacement "alternate" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, double and fixed point to Xilinx fixed point type.

Hardware notes: In hardware these blocks become top level input ports." arith_type "Unsigned" n_bits "10" bin_pt "0" quantization "Truncate" overflow "Wrap" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,356,432" block_type "gatewayin" block_version "VER_STRING_GOES_HERE" sg_icon_stat "55,12,1,1,white,yellow,0,bc55d28f,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([27 24 29 24 27 32 33 34 40 36 32 29 34 29 32 36 40 34 33 32 27 ],[2 5 10 15 18 18 17 18 18 14 18 15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Outport Name "RSSI" Position [740, 108, 770, 122] IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "radio4_RSSI" DstPort 1 } Line { SrcBlock "Debug" SrcPort 1 Points [40, 0; 0, 45] DstBlock "Mux" DstPort 1 } Line { SrcBlock "radio4_RSSI" SrcPort 1 DstBlock "Mux" DstPort 2 } Line { SrcBlock "Counter" SrcPort 1 DstBlock "Mux" DstPort 3 } Line { SrcBlock "Mux" SrcPort 1 DstBlock "RSSI" DstPort 1 } } } Block { BlockType Scope Name "Scope" Ports [2] Position [800, 111, 830, 164] Floating off Location [5, 34, 1285, 912] Open off NumInputPorts "2" List { ListType AxesTitles axes1 "%" axes2 "%" } YMin "-5~-5" YMax "5~5" DataFormat "StructureWithTime" SampleTime "0" } Block { BlockType Outport Name "Radio 4 RSSI" Position [650, 418, 680, 432] IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Outport Name "Radio 4 I/Q" Position [865, 288, 895, 302] Port "2" IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Line { SrcBlock "ADC Q" SrcPort 2 Points [50, 0; 0, 25; 30, 0] Branch { DstBlock "Concatenates_1" DstPort 4 } Branch { Points [0, -215] DstBlock "Gateway Out1" DstPort 1 } } Line { SrcBlock "ADC Q" SrcPort 1 Points [0, 5] DstBlock "Concatenates_1" DstPort 3 } Line { SrcBlock "ADC I" SrcPort 2 Points [0, 20; 70, 0] Branch { DstBlock "Concatenates_1" DstPort 2 } Branch { Points [0, -150] DstBlock "Gateway Out4" DstPort 1 } } Line { SrcBlock "ADC I" SrcPort 1 DstBlock "Concatenates_1" DstPort 1 } Line { SrcBlock "Concatenates_1" SrcPort 1 Points [0, 0] DstBlock "Radio 4 I/Q" DstPort 1 } Line { SrcBlock "Gateway Out4" SrcPort 1 DstBlock "Scope" DstPort 1 } Line { SrcBlock "Gateway Out1" SrcPort 1 Points [25, 0] DstBlock "Scope" DstPort 2 } Line { SrcBlock "DebugRxBuffers" SrcPort 1 Points [150, 0] Branch { DstBlock "ADC I" DstPort 1 } Branch { Points [0, 75] Branch { DstBlock "ADC Q" DstPort 1 } Branch { Points [0, 115] DstBlock "RSSI" DstPort 1 } } } Line { SrcBlock "RSSI" SrcPort 1 DstBlock "Radio 4 RSSI" DstPort 1 } Line { SrcBlock "MGCAGC_AGCDCO_SEL" SrcPort 1 Points [115, 0] Branch { DstBlock "ADC Q" DstPort 2 } Branch { Points [0, -75] DstBlock "ADC I" DstPort 2 } } Annotation { Position [518, 257] } } } Block { BlockType SubSystem Name "Radio 4 Outputs" Ports [1] Position [1180, 958, 1225, 1002] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Radio 4 Outputs" Location [60, 247, 880, 529] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "32b" Position [145, 148, 175, 162] IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Reference Name "16LSB" Ports [1, 1] Position [305, 147, 340, 163] SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardware notes: In hardware this block costs nothing." nbits "16" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "593,46,442,407" block_type "slice" block_version "9.1.01" sg_icon_stat "35,16,1,1,white,blue,0,b1026674,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "16MSB" Ports [1, 1] Position [305, 82, 345, 98] SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardware notes: In hardware this block costs nothing." nbits "16" boolean_output off mode "Upper Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "593,46,442,407" block_type "slice" block_version "9.1.01" sg_icon_stat "40,16,1,1,white,blue,0,b1026674,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([22 17 24 17 22 30 32 34 42 35 29 24 30 24 29 35 42 34 32 30 22 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Radio 4 DAC I" Ports [1, 1] Position [560, 69, 655, 111] LinkData { BlockName "Convert" DialogParameters { sg_icon_stat "45,30,1,1,white,blue,0,74901e60,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([15 10 17 10 15 23 25 27 35 28 22 17 23 17 22 28 35 27 25 23 15 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'cast');\nfprintf('','COMMENT: end icon text');\n" } BlockName "radio4_dac_I" DialogParameters { sg_icon_stat "60,20,1,1,white,yellow,0,38220381,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([24 21 26 21 24 29 30 31 37 33 29 26 31 26 29 33 37 31 30 29 24 ],[2 5 10 15 18 18 17 18 18 14 18 15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } } SourceBlock "WARP_Blockset/WARP Radio Board ADC//DACs/Radio 4 DAC I" SourceType "" ShowPortLabels "FromPortIcon" SystemSampleTime "-1" FunctionWithSeparateData off RTWMemSecFuncInitTerm "Inherit from model" RTWMemSecFuncExecute "Inherit from model" RTWMemSecDataConstants "Inherit from model" RTWMemSecDataInternal "Inherit from model" RTWMemSecDataParameters "Inherit from model" } Block { BlockType Reference Name "Radio 4 DAC Q" Ports [1, 1] Position [560, 134, 655, 176] LinkData { BlockName "Convert" DialogParameters { sg_icon_stat "45,30,1,1,white,blue,0,74901e60,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([15 10 17 10 15 23 25 27 35 28 22 17 23 17 22 28 35 27 25 23 15 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'cast');\nfprintf('','COMMENT: end icon text');\n" } BlockName "radio4_dac_Q" DialogParameters { sg_icon_stat "60,20,1,1,white,yellow,0,38220381,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([24 21 26 21 24 29 30 31 37 33 29 26 31 26 29 33 37 31 30 29 24 ],[2 5 10 15 18 18 17 18 18 14 18 15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } } SourceBlock "WARP_Blockset/WARP Radio Board ADC//DACs/Radio 4 DAC Q" SourceType "" ShowPortLabels "FromPortIcon" SystemSampleTime "-1" FunctionWithSeparateData off RTWMemSecFuncInitTerm "Inherit from model" RTWMemSecFuncExecute "Inherit from model" RTWMemSecDataConstants "Inherit from model" RTWMemSecDataInternal "Inherit from model" RTWMemSecDataParameters "Inherit from model" } Block { BlockType Reference Name "Register" Ports [1, 1] Position [475, 79, 520, 101] ShowName off SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "568,185,356,193" block_type "register" block_version "9.1.01" sg_icon_stat "45,22,1,1,white,blue,0,ac6b57db,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('\\bf{z^{-1}}','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Register1" Ports [1, 1] Position [475, 144, 520, 166] ShowName off SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "568,185,356,193" block_type "register" block_version "9.1.01" sg_icon_stat "45,22,1,1,white,blue,0,ac6b57db,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('\\bf{z^{-1}}','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Reinterpret" Ports [1, 1] Position [380, 81, 440, 99] ShowName off SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can changed the signal between signed and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothing.

Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsigned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111000 in binary)." force_arith_type on arith_type "Signed (2's comp)" force_bin_pt on bin_pt "15" has_advanced_control "0" sggui_pos "436,54,356,309" block_type "reinterpret" block_version "9.1.01" sg_icon_stat "60,18,1,1,white,blue,0,8982c1db,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 ],[0 0 32 32 ],[0.77 0.82 0.91]);\npatch([16 11 18 11 16 24 26 28 37 30 23 18 25 18 23 30 37 28 26 24 16 ],[3 8 15 22 27 27 25 27 27 20 27 22 15 8 3 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 50 50 0 0 ],[0 0 32 32 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('reinterpret');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Reinterpret1" Ports [1, 1] Position [380, 146, 440, 164] ShowName off SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can changed the signal between signed and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothing.

Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsigned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111000 in binary)." force_arith_type on arith_type "Signed (2's comp)" force_bin_pt on bin_pt "15" has_advanced_control "0" sggui_pos "436,54,356,309" block_type "reinterpret" block_version "9.1.01" sg_icon_stat "60,18,1,1,white,blue,0,8982c1db,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 ],[0 0 32 32 ],[0.77 0.82 0.91]);\npatch([16 11 18 11 16 24 26 28 37 30 23 18 25 18 23 30 37 28 26 24 16 ],[3 8 15 22 27 27 25 27 27 20 27 22 15 8 3 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 50 50 0 0 ],[0 0 32 32 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('reinterpret');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Terminator Name "Terminator" Position [680, 80, 700, 100] ShowName off } Block { BlockType Terminator Name "Terminator1" Position [685, 145, 705, 165] ShowName off } Line { SrcBlock "32b" SrcPort 1 Points [85, 0] Branch { DstBlock "16LSB" DstPort 1 } Branch { Points [0, -65] DstBlock "16MSB" DstPort 1 } } Line { SrcBlock "16MSB" SrcPort 1 DstBlock "Reinterpret" DstPort 1 } Line { SrcBlock "16LSB" SrcPort 1 DstBlock "Reinterpret1" DstPort 1 } Line { SrcBlock "Reinterpret" SrcPort 1 DstBlock "Register" DstPort 1 } Line { SrcBlock "Reinterpret1" SrcPort 1 DstBlock "Register1" DstPort 1 } Line { SrcBlock "Register" SrcPort 1 DstBlock "Radio 4 DAC I" DstPort 1 } Line { SrcBlock "Register1" SrcPort 1 DstBlock "Radio 4 DAC Q" DstPort 1 } Line { SrcBlock "Radio 4 DAC I" SrcPort 1 DstBlock "Terminator" DstPort 1 } Line { SrcBlock "Radio 4 DAC Q" SrcPort 1 DstBlock "Terminator1" DstPort 1 } } } Block { BlockType Reference Name "Register" Ports [1, 1] Position [250, 1006, 285, 1034] ShowName off SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "8.2" sg_icon_stat "35,28,1,1,white,blue,0,ac6b57db,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('\\bf{z^{-1}}','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType SubSystem Name "Rx Control" Ports [1, 2] Position [415, 224, 510, 266] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Rx Control" Location [2, 74, 1270, 710] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "159" Block { BlockType Inport Name "Start" Position [15, 298, 45, 312] IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Reference Name "Convert" Ports [1, 1] Position [635, 162, 665, 178] ShowName off SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." arith_type "Unsigned" n_bits "1" bin_pt "0" quantization "Truncate" overflow "Wrap" latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,461,334" block_type "convert" block_version "10.1.2" sg_icon_stat "30,16,1,1,white,blue,0,74901e60,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([15 10 17 10 15 23 25 27 35 28 22 17 23 17 22 28 35 27 25 23 15 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'cast');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Gateway Out1" Ports [1, 1] Position [585, 25, 615, 35] ShowName off SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, double, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarded, depending on how they are configured." hdl_port off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,336,386" block_type "gatewayout" block_version "10.1.2" sg_icon_stat "30,10,1,1,white,grey,0,b3a044a9,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 ],[0 0 10 10 ],[0.88 0.88 0.88]);\npatch([13 11 13 11 13 16 17 18 21 19 17 15 17 15 17 19 21 18 17 16 13 ],[1 3 5 7 9 9 8 9 9 7 9 7 5 3 1 3 1 1 2 1 1 ],[0.98 0.96 0.92]);\nplot([0 30 30 0 0 ],[0 0 10 10 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Gateway Out2" Ports [1, 1] Position [585, 40, 615, 50] ShowName off SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, double, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarded, depending on how they are configured." hdl_port off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,336,386" block_type "gatewayout" block_version "10.1.2" sg_icon_stat "30,10,1,1,white,grey,0,b3a044a9,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 ],[0 0 10 10 ],[0.88 0.88 0.88]);\npatch([13 11 13 11 13 16 17 18 21 19 17 15 17 15 17 19 21 18 17 16 13 ],[1 3 5 7 9 9 8 9 9 7 9 7 5 3 1 3 1 1 2 1 1 ],[0.98 0.96 0.92]);\nplot([0 30 30 0 0 ],[0 0 10 10 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Gateway Out3" Ports [1, 1] Position [585, 55, 615, 65] ShowName off SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, double, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarded, depending on how they are configured." hdl_port off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,336,386" block_type "gatewayout" block_version "10.1.2" sg_icon_stat "30,10,1,1,white,grey,0,b3a044a9,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 ],[0 0 10 10 ],[0.88 0.88 0.88]);\npatch([13 11 13 11 13 16 17 18 21 19 17 15 17 15 17 19 21 18 17 16 13 ],[1 3 5 7 9 9 8 9 9 7 9 7 5 3 1 3 1 1 2 1 1 ],[0.98 0.96 0.92]);\nplot([0 30 30 0 0 ],[0 0 10 10 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Gateway Out4" Ports [1, 1] Position [585, 70, 615, 80] ShowName off SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, double, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarded, depending on how they are configured." hdl_port off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,336,386" block_type "gatewayout" block_version "10.1.2" sg_icon_stat "30,10,1,1,white,grey,0,b3a044a9,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 ],[0 0 10 10 ],[0.88 0.88 0.88]);\npatch([13 11 13 11 13 16 17 18 21 19 17 15 17 15 17 19 21 18 17 16 13 ],[1 3 5 7 9 9 8 9 9 7 9 7 5 3 1 3 1 1 2 1 1 ],[0.98 0.96 0.92]);\nplot([0 30 30 0 0 ],[0 0 10 10 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Gateway Out5" Ports [1, 1] Position [585, 85, 615, 95] ShowName off SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, double, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarded, depending on how they are configured." hdl_port off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,336,386" block_type "gatewayout" block_version "10.1.2" sg_icon_stat "30,10,1,1,white,grey,0,b3a044a9,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 ],[0 0 10 10 ],[0.88 0.88 0.88]);\npatch([13 11 13 11 13 16 17 18 21 19 17 15 17 15 17 19 21 18 17 16 13 ],[1 3 5 7 9 9 8 9 9 7 9 7 5 3 1 3 1 1 2 1 1 ],[0.98 0.96 0.92]);\nplot([0 30 30 0 0 ],[0 0 10 10 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Goto Name "Goto2" Position [695, 160, 825, 180] ShowName off GotoTag "CAPTURE_IS_DONE" TagVisibility "global" } Block { BlockType Reference Name "Inverter1" Ports [1, 1] Position [360, 281, 385, 299] ShowName off SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "8.2" sg_icon_stat "25,18,1,1,white,blue,0,1ab4a85f,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 58 58 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[7 16 29 42 51 51 47 51 51 39 51 42 29 16 7 19 7 7 11 7 7 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Inverter2" Ports [1, 1] Position [570, 161, 595, 179] ShowName off SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "8.2" sg_icon_stat "25,18,1,1,white,blue,0,1ab4a85f,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 58 58 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[7 16 29 42 51 51 47 51 51 39 51 42 29 16 7 19 7 7 11 7 7 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Relational1" Ports [2, 1] Position [425, 354, 470, 401] Orientation "left" NamePlacement "alternate" ShowName off SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a>=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "relational" block_version "8.2" sg_icon_stat "45,47,1,1,white,blue,0,6d6ac162,left" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[6 15 28 41 50 50 46 50 50 38 50 41 28 15 6 18 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');disp('\\newline\\bf{a>=b}\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Rx Addr Counter1" Ports [2, 1] Position [425, 276, 465, 329] NamePlacement "alternate" SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited counter is implemented by combining a counter with a comparator." cnt_type "Free Running" cnt_to "Inf" operation "Up" start_count "0" cnt_by_val "1" arith_type "Unsigned" n_bits "14" bin_pt "0" load_pin off rst on en on explicit_period "off" period "1" dbl_ovrd off use_behavioral_HDL off use_rpm off implementation "Fabric" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,356,630" block_type "counter" block_version "8.2" sg_icon_stat "40,53,1,1,white,blue,0,46c73e85,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 ],[0 0 53 53 ],[0.77 0.82 0.91]);\npatch([10 3 12 3 10 21 24 27 38 29 20 14 24 14 20 29 38 27 24 21 10 ],[11 18 27 36 43 43 40 43 43 34 43 37 27 17 11 20 11 11 14 11 11 ],[0.98 0.96 0.92]);\nplot([0 40 40 0 0 ],[0 0 53 53 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'rst');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'out');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Scope Name "Rx Control" Ports [5] Position [665, 22, 695, 98] Floating off Location [5, 34, 1285, 742] Open off NumInputPorts "5" ZoomMode "yonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" } TimeRange "70000" YMin "0~0~0~0~0" YMax "1~1~1~1~20000" SaveName "ScopeData1" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType SubSystem Name "S-R Latch1" Ports [2, 1] Position [225, 297, 265, 333] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "S-R Latch1" Location [2, 74, 1184, 1000] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "S" Position [125, 198, 155, 212] IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Inport Name "R" Position [125, 178, 155, 192] NamePlacement "alternate" Port "2" IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Reference Name "Convert" Ports [1, 1] Position [200, 178, 230, 192] ShowName off SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." arith_type "Boolean" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,374,375" block_type "convert" block_version "8.2" sg_icon_stat "30,14,1,1,white,blue,0,74901e60,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([15 10 17 10 15 23 25 27 35 28 22 17 23 17 22 28 35 27 25 23 15 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'cast');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Convert1" Ports [1, 1] Position [200, 198, 230, 212] ShowName off SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." arith_type "Boolean" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,374,375" block_type "convert" block_version "8.2" sg_icon_stat "30,14,1,1,white,blue,0,74901e60,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([15 10 17 10 15 23 25 27 35 28 22 17 23 17 22 28 35 27 25 23 15 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'cast');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Register" Ports [3, 1] Position [280, 153, 330, 217] NamePlacement "alternate" ShowName off SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "8.2" sg_icon_stat "50,64,1,1,white,blue,0,923c1847,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('\\bf{z^{-1}}','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "zero3" Ports [0, 1] Position [215, 156, 235, 174] ShowName off SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" arith_type "Boolean" const "1" n_bits "1" bin_pt "0" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "20,18,1,1,white,blue,0,06094819,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 26 26 ],[0.77 0.82 0.91]);\npatch([20 16 22 16 20 27 29 31 38 32 26 22 28 22 26 32 38 31 29 27 20 ],[3 7 13 19 23 23 21 23 23 17 23 19 13 7 3 9 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 26 26 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Outport Name "Q" Position [395, 178, 425, 192] IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "Register" DstPort 3 } Line { SrcBlock "Convert" SrcPort 1 DstBlock "Register" DstPort 2 } Line { SrcBlock "Register" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "S" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "R" SrcPort 1 DstBlock "Convert" DstPort 1 } Line { SrcBlock "zero3" SrcPort 1 DstBlock "Register" DstPort 1 } } } Block { BlockType Reference Name "zero3" Ports [0, 1] Position [510, 380, 565, 400] Orientation "left" NamePlacement "alternate" ShowName off SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" arith_type "Unsigned" const "2^14-1" n_bits "14" bin_pt "0" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,400,346" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "55,20,1,1,white,blue,0,63905735,left" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 26 26 ],[0.77 0.82 0.91]);\npatch([20 16 22 16 20 27 29 31 38 32 26 22 28 22 26 32 38 31 29 27 20 ],[3 7 13 19 23 23 21 23 23 17 23 19 13 7 3 9 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 26 26 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'16383');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Outport Name "WrAddr" Position [730, 298, 760, 312] IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Outport Name "WrEn" Position [730, 233, 760, 247] Port "2" IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Line { SrcBlock "Start" SrcPort 1 Points [145, 0] Branch { DstBlock "S-R Latch1" DstPort 1 } Branch { Points [0, -275] DstBlock "Gateway Out1" DstPort 1 } } Line { SrcBlock "S-R Latch1" SrcPort 1 Points [60, 0] Branch { DstBlock "Rx Addr Counter1" DstPort 2 } Branch { Points [0, -25] Branch { DstBlock "Inverter1" DstPort 1 } Branch { Points [0, -50] Branch { Points [200, 0] Branch { DstBlock "WrEn" DstPort 1 } Branch { Points [0, -70] DstBlock "Inverter2" DstPort 1 } } Branch { Points [0, -180] DstBlock "Gateway Out3" DstPort 1 } } } } Line { SrcBlock "Inverter1" SrcPort 1 Points [15, 0] Branch { DstBlock "Rx Addr Counter1" DstPort 1 } Branch { Points [0, -215] DstBlock "Gateway Out4" DstPort 1 } } Line { SrcBlock "Rx Addr Counter1" SrcPort 1 Points [45, 0] Branch { Points [0, 60] DstBlock "Relational1" DstPort 1 } Branch { DstBlock "WrAddr" DstPort 1 } Branch { Points [0, -215] DstBlock "Gateway Out5" DstPort 1 } } Line { SrcBlock "Gateway Out5" SrcPort 1 DstBlock "Rx Control" DstPort 5 } Line { SrcBlock "Gateway Out4" SrcPort 1 DstBlock "Rx Control" DstPort 4 } Line { SrcBlock "Gateway Out3" SrcPort 1 DstBlock "Rx Control" DstPort 3 } Line { SrcBlock "Gateway Out2" SrcPort 1 DstBlock "Rx Control" DstPort 2 } Line { SrcBlock "Gateway Out1" SrcPort 1 DstBlock "Rx Control" DstPort 1 } Line { SrcBlock "zero3" SrcPort 1 DstBlock "Relational1" DstPort 2 } Line { SrcBlock "Relational1" SrcPort 1 Points [-220, 0; 0, -55] Branch { DstBlock "S-R Latch1" DstPort 2 } Branch { Points [0, -280] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "Inverter2" SrcPort 1 DstBlock "Convert" DstPort 1 } Line { SrcBlock "Convert" SrcPort 1 DstBlock "Goto2" DstPort 1 } } } Block { BlockType Reference Name "StartCapture" Ports [1, 1] Position [120, 214, 175, 226] NamePlacement "alternate" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, double and fixed point to Xilinx fixed point type.

Hardware notes: In hardware these blocks become top level input ports." arith_type "Unsigned" n_bits "1" bin_pt "0" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,356,432" block_type "gatewayin" block_version "VER_STRING_GOES_HERE" sg_icon_stat "55,12,1,1,white,yellow,0,bc55d28f,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([27 24 29 24 27 32 33 34 40 36 32 29 34 29 32 36 40 34 33 32 27 ],[2 5 10 15 18 18 17 18 18 14 18 15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "StartTx" Ports [1, 1] Position [160, 654, 215, 666] NamePlacement "alternate" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, double and fixed point to Xilinx fixed point type.

Hardware notes: In hardware these blocks become top level input ports." arith_type "Unsigned" n_bits "1" bin_pt "0" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,356,432" block_type "gatewayin" block_version "VER_STRING_GOES_HERE" sg_icon_stat "55,12,1,1,white,yellow,0,bc55d28f,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([27 24 29 24 27 32 33 34 40 36 32 29 34 29 32 36 40 34 33 32 27 ],[2 5 10 15 18 18 17 18 18 14 18 15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "StopTx" Ports [1, 1] Position [160, 739, 215, 751] NamePlacement "alternate" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, double and fixed point to Xilinx fixed point type.

Hardware notes: In hardware these blocks become top level input ports." arith_type "Unsigned" n_bits "1" bin_pt "0" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,356,432" block_type "gatewayin" block_version "VER_STRING_GOES_HERE" sg_icon_stat "55,12,1,1,white,yellow,0,bc55d28f,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 ],[0 0 20 20 ],[0.95 0.93 0.65]);\npatch([27 24 29 24 27 32 33 34 40 36 32 29 34 29 32 36 40 34 33 32 27 ],[2 5 10 15 18 18 17 18 18 14 18 15 10 5 2 6 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Terminator Name "Terminator" Position [260, 945, 280, 965] ShowName off } Block { BlockType SubSystem Name "Tx Control" Ports [4, 2] Position [570, 650, 680, 715] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Tx Control" Location [2, 74, 1254, 710] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "StartTx" Position [390, 368, 420, 382] NamePlacement "alternate" IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Inport Name "StopTx" Position [145, 423, 175, 437] Port "2" IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Inport Name "ContinuousTx" Position [150, 353, 180, 367] Port "3" IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Inport Name "TxDelay" Position [750, 413, 780, 427] Port "4" IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Reference Name "Convert1" Ports [1, 1] Position [470, 366, 500, 384] NamePlacement "alternate" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." arith_type "Boolean" n_bits "1" bin_pt "0" quantization "Truncate" overflow "Wrap" latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,461,375" block_type "convert" block_version "9.1.01" sg_icon_stat "30,18,1,1,white,blue,0,74901e60,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([15 10 17 10 15 23 25 27 35 28 22 17 23 17 22 28 35 27 25 23 15 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'cast');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Convert2" Ports [1, 1] Position [230, 421, 260, 439] SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." arith_type "Boolean" n_bits "1" bin_pt "0" quantization "Truncate" overflow "Wrap" latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,461,375" block_type "convert" block_version "9.1.01" sg_icon_stat "30,18,1,1,white,blue,0,74901e60,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([15 10 17 10 15 23 25 27 35 28 22 17 23 17 22 28 35 27 25 23 15 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'cast');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "From Register4" Ports [0, 1] Position [1230, 220, 1275, 250] Orientation "left" NamePlacement "alternate" ShowName off AttributesFormatString "TxLength\\n<< % >>" SourceBlock "xbsIndex_r4/From Register" SourceType "Xilinx Shared Memory Based From Register Block" infoedit "Register block that reads data to a shared memory register. Delay of one sample period." shared_memory_name "'TxLength'" init "2^14-1" period "1" ownership "Locally owned and initialized" arith_type "Unsigned" n_bits "14" bin_pt "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,381,246" block_type "fromreg" block_version "8.2" sg_icon_stat "45,30,1,1,white,blue,0,4b212927,left" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Gateway Out1" Ports [1, 1] Position [1295, 620, 1325, 630] ShowName off SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, double, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarded, depending on how they are configured." hdl_port off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,336,386" block_type "gatewayout" block_version "10.1.2" sg_icon_stat "30,10,1,1,white,grey,0,b3a044a9,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 ],[0 0 10 10 ],[0.88 0.88 0.88]);\npatch([13 11 13 11 13 16 17 18 21 19 17 15 17 15 17 19 21 18 17 16 13 ],[1 3 5 7 9 9 8 9 9 7 9 7 5 3 1 3 1 1 2 1 1 ],[0.98 0.96 0.92]);\nplot([0 30 30 0 0 ],[0 0 10 10 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Gateway Out2" Ports [1, 1] Position [1295, 635, 1325, 645] ShowName off SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, double, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarded, depending on how they are configured." hdl_port off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,336,386" block_type "gatewayout" block_version "10.1.2" sg_icon_stat "30,10,1,1,white,grey,0,b3a044a9,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 ],[0 0 10 10 ],[0.88 0.88 0.88]);\npatch([13 11 13 11 13 16 17 18 21 19 17 15 17 15 17 19 21 18 17 16 13 ],[1 3 5 7 9 9 8 9 9 7 9 7 5 3 1 3 1 1 2 1 1 ],[0.98 0.96 0.92]);\nplot([0 30 30 0 0 ],[0 0 10 10 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Gateway Out3" Ports [1, 1] Position [1295, 650, 1325, 660] ShowName off SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, double, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarded, depending on how they are configured." hdl_port off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,336,386" block_type "gatewayout" block_version "10.1.2" sg_icon_stat "30,10,1,1,white,grey,0,b3a044a9,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 ],[0 0 10 10 ],[0.88 0.88 0.88]);\npatch([13 11 13 11 13 16 17 18 21 19 17 15 17 15 17 19 21 18 17 16 13 ],[1 3 5 7 9 9 8 9 9 7 9 7 5 3 1 3 1 1 2 1 1 ],[0.98 0.96 0.92]);\nplot([0 30 30 0 0 ],[0 0 10 10 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Gateway Out4" Ports [1, 1] Position [1295, 665, 1325, 675] ShowName off SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, double, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarded, depending on how they are configured." hdl_port off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,336,386" block_type "gatewayout" block_version "10.1.2" sg_icon_stat "30,10,1,1,white,grey,0,b3a044a9,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 ],[0 0 10 10 ],[0.88 0.88 0.88]);\npatch([13 11 13 11 13 16 17 18 21 19 17 15 17 15 17 19 21 18 17 16 13 ],[1 3 5 7 9 9 8 9 9 7 9 7 5 3 1 3 1 1 2 1 1 ],[0.98 0.96 0.92]);\nplot([0 30 30 0 0 ],[0 0 10 10 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Gateway Out5" Ports [1, 1] Position [1295, 680, 1325, 690] ShowName off SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, double, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarded, depending on how they are configured." hdl_port off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,336,386" block_type "gatewayout" block_version "10.1.2" sg_icon_stat "30,10,1,1,white,grey,0,b3a044a9,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 ],[0 0 10 10 ],[0.88 0.88 0.88]);\npatch([13 11 13 11 13 16 17 18 21 19 17 15 17 15 17 19 21 18 17 16 13 ],[1 3 5 7 9 9 8 9 9 7 9 7 5 3 1 3 1 1 2 1 1 ],[0.98 0.96 0.92]);\nplot([0 30 30 0 0 ],[0 0 10 10 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Gateway Out6" Ports [1, 1] Position [1295, 695, 1325, 705] ShowName off SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, double, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarded, depending on how they are configured." hdl_port off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,336,386" block_type "gatewayout" block_version "10.1.2" sg_icon_stat "30,10,1,1,white,grey,0,b3a044a9,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 ],[0 0 10 10 ],[0.88 0.88 0.88]);\npatch([13 11 13 11 13 16 17 18 21 19 17 15 17 15 17 19 21 18 17 16 13 ],[1 3 5 7 9 9 8 9 9 7 9 7 5 3 1 3 1 1 2 1 1 ],[0.98 0.96 0.92]);\nplot([0 30 30 0 0 ],[0 0 10 10 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Gateway Out7" Ports [1, 1] Position [1295, 710, 1325, 720] ShowName off SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, double, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarded, depending on how they are configured." hdl_port off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,336,386" block_type "gatewayout" block_version "10.1.2" sg_icon_stat "30,10,1,1,white,grey,0,b3a044a9,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 ],[0 0 10 10 ],[0.88 0.88 0.88]);\npatch([13 11 13 11 13 16 17 18 21 19 17 15 17 15 17 19 21 18 17 16 13 ],[1 3 5 7 9 9 8 9 9 7 9 7 5 3 1 3 1 1 2 1 1 ],[0.98 0.96 0.92]);\nplot([0 30 30 0 0 ],[0 0 10 10 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Gateway Out8" Ports [1, 1] Position [1295, 725, 1325, 735] ShowName off SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, double, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarded, depending on how they are configured." hdl_port off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,336,386" block_type "gatewayout" block_version "10.1.2" sg_icon_stat "30,10,1,1,white,grey,0,b3a044a9,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 ],[0 0 10 10 ],[0.88 0.88 0.88]);\npatch([13 11 13 11 13 16 17 18 21 19 17 15 17 15 17 19 21 18 17 16 13 ],[1 3 5 7 9 9 8 9 9 7 9 7 5 3 1 3 1 1 2 1 1 ],[0.98 0.96 0.92]);\nplot([0 30 30 0 0 ],[0 0 10 10 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Inverter" Ports [1, 1] Position [765, 476, 790, 494] Orientation "left" NamePlacement "alternate" ShowName off SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "8.2" sg_icon_stat "25,18,1,1,white,blue,0,1ab4a85f,left" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 58 58 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[7 16 29 42 51 51 47 51 51 39 51 42 29 16 7 19 7 7 11 7 7 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Logical" Ports [2, 1] Position [665, 376, 700, 409] ShowName off SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,261" block_type "logical" block_version "8.2" sg_icon_stat "35,33,1,1,white,blue,0,087b5522,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[8 17 30 43 52 52 48 52 52 40 52 43 30 17 8 20 8 8 12 8 8 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newlineand\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Logical1" Ports [2, 1] Position [970, 326, 1005, 359] ShowName off SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,261" block_type "logical" block_version "8.2" sg_icon_stat "35,33,1,1,white,blue,0,087b5522,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[8 17 30 43 52 52 48 52 52 40 52 43 30 17 8 20 8 8 12 8 8 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newlineand\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Logical2" Ports [2, 1] Position [645, 216, 680, 249] ShowName off SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,261" block_type "logical" block_version "8.2" sg_icon_stat "35,33,1,1,white,blue,0,f4a65842,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[8 17 30 43 52 52 48 52 52 40 52 43 30 17 8 20 8 8 12 8 8 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newlineor\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType SubSystem Name "Posedge2" Ports [1, 1] Position [570, 233, 605, 247] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Posedge2" Location [132, 719, 452, 817] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" Position [25, 33, 55, 47] IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Reference Name "Delay" Ports [1, 1] Position [145, 45, 175, 75] ShowName off SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. If register retiming is enabled, the delay line is a chain of flip-flops." en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "8.2" sg_icon_stat "30,30,1,1,white,blue,0,fc531c0e,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Inverter" Ports [1, 1] Position [90, 47, 120, 73] ShowName off SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,251" block_type "inv" block_version "8.2" sg_icon_stat "30,26,1,1,white,blue,0,1ab4a85f,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 58 58 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[7 16 29 42 51 51 47 51 51 39 51 42 29 16 7 19 7 7 11 7 7 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 58 58 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Logical" Ports [2, 1] Position [205, 29, 240, 71] ShowName off SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,261" block_type "logical" block_version "8.2" sg_icon_stat "35,42,1,1,white,blue,0,087b5522,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 60 60 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[8 17 30 43 52 52 48 52 52 40 52 43 30 17 8 20 8 8 12 8 8 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');disp('\\newlineand\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Outport Name "Q" Position [265, 43, 295, 57] IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Line { SrcBlock "Logical" SrcPort 1 Points [0, 0] DstBlock "Q" DstPort 1 } Line { SrcBlock "Delay" SrcPort 1 Points [0, 0] DstBlock "Logical" DstPort 2 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Delay" DstPort 1 } Line { SrcBlock "D" SrcPort 1 Points [0, 0; 15, 0] Branch { DstBlock "Logical" DstPort 1 } Branch { DstBlock "Inverter" DstPort 1 } } } } Block { BlockType Reference Name "Relational" Ports [2, 1] Position [1085, 223, 1130, 272] Orientation "left" ShowName off SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a<=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "relational" block_version "8.2" sg_icon_stat "45,49,1,1,white,blue,0,07808d72,left" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[6 15 28 41 50 50 46 50 50 38 50 41 28 15 6 18 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');disp('\\newline\\bf{a<=b}\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Relational1" Ports [2, 1] Position [845, 367, 890, 438] ShowName off SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a>=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "relational" block_version "8.2" sg_icon_stat "45,71,1,1,white,blue,0,6d6ac162,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([13 4 17 4 13 28 32 36 52 40 28 19 32 19 28 40 52 36 32 28 13 ],[6 15 28 41 50 50 46 50 50 38 50 41 28 15 6 18 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');disp('\\newline\\bf{a>=b}\\newlinez^{-0}','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType SubSystem Name "S-R Latch" Ports [2, 1] Position [555, 367, 595, 403] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "S-R Latch" Location [2, 74, 1184, 726] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "S" Position [125, 198, 155, 212] IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Inport Name "R" Position [125, 178, 155, 192] NamePlacement "alternate" Port "2" IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Reference Name "Convert" Ports [1, 1] Position [200, 178, 230, 192] ShowName off SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." arith_type "Boolean" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,374,375" block_type "convert" block_version "8.2" sg_icon_stat "30,14,1,1,white,blue,0,74901e60,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([15 10 17 10 15 23 25 27 35 28 22 17 23 17 22 28 35 27 25 23 15 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'cast');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Convert1" Ports [1, 1] Position [200, 198, 230, 212] ShowName off SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." arith_type "Boolean" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,374,375" block_type "convert" block_version "8.2" sg_icon_stat "30,14,1,1,white,blue,0,74901e60,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 ],[0 0 30 30 ],[0.77 0.82 0.91]);\npatch([15 10 17 10 15 23 25 27 35 28 22 17 23 17 22 28 35 27 25 23 15 ],[3 8 15 22 27 27 25 27 27 20 26 21 15 9 4 10 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'cast');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Register" Ports [3, 1] Position [280, 153, 330, 217] NamePlacement "alternate" ShowName off SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "8.2" sg_icon_stat "50,64,1,1,white,blue,0,923c1847,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 ],[0 0 56 56 ],[0.77 0.82 0.91]);\npatch([15 6 19 6 15 30 34 38 54 41 29 20 32 20 29 41 54 38 34 30 15 ],[6 15 28 41 50 50 46 50 50 37 49 40 28 16 7 19 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');port_label('input',3,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('\\bf{z^{-1}}','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "zero3" Ports [0, 1] Position [215, 156, 235, 174] ShowName off SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" arith_type "Boolean" const "1" n_bits "1" bin_pt "0" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "20,18,1,1,white,blue,0,06094819,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 ],[0 0 26 26 ],[0.77 0.82 0.91]);\npatch([20 16 22 16 20 27 29 31 38 32 26 22 28 22 26 32 38 31 29 27 20 ],[3 7 13 19 23 23 21 23 23 17 23 19 13 7 3 9 3 3 5 3 3 ],[0.98 0.96 0.92]);\nplot([0 55 55 0 0 ],[0 0 26 26 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Outport Name "Q" Position [395, 178, 425, 192] IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "Register" DstPort 3 } Line { SrcBlock "Convert" SrcPort 1 DstBlock "Register" DstPort 2 } Line { SrcBlock "Register" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "S" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "R" SrcPort 1 DstBlock "Convert" DstPort 1 } Line { SrcBlock "zero3" SrcPort 1 DstBlock "Register" DstPort 1 } } } Block { BlockType Reference Name "Transmisson\nMode Selector" Ports [3, 1] Position [315, 343, 350, 447] SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" block_version "9.1.01" sg_icon_stat "35,104,1,1,white,blue,3,613f58e1,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 ],[0 14.8571 89.1429 104 ],[0.77 0.82 0.91]);\npatch([10 3 14 3 10 22 25 28 41 31 21 14 25 14 21 31 41 28 25 22 10 ],[34 41 52 63 70 70 67 70 70 60 70 63 52 41 34 44 34 34 37 34 34 ],[0.98 0.96 0.92]);\nplot([0 45 45 0 0 ],[0 14.8571 89.1429 104 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('input',3,'d1');\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "Tx Addr Counter" Ports [2, 1] Position [1085, 308, 1130, 357] NamePlacement "alternate" SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited counter is implemented by combining a counter with a comparator." cnt_type "Free Running" cnt_to "Inf" operation "Up" start_count "0" cnt_by_val "1" arith_type "Unsigned" n_bits "14" bin_pt "0" load_pin off rst on en on explicit_period "off" period "1" dbl_ovrd off use_behavioral_HDL off use_rpm off implementation "Fabric" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,356,630" block_type "counter" block_version "8.2" sg_icon_stat "45,49,1,1,white,blue,0,46c73e85,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 ],[0 0 49 49 ],[0.77 0.82 0.91]);\npatch([10 3 14 3 10 22 25 28 41 31 21 14 25 14 21 31 41 28 25 22 10 ],[7 14 25 36 43 43 40 43 43 33 43 36 25 14 7 17 7 7 10 7 7 ],[0.98 0.96 0.92]);\nplot([0 45 45 0 0 ],[0 0 49 49 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'rst');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'out');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Scope Name "Tx Control" Ports [8] Position [1375, 624, 1405, 731] Floating off Location [1, 45, 1281, 719] Open off NumInputPorts "8" ZoomMode "yonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" axes8 "%" } TimeRange "70000" YMin "0~0~0~0~0~0~0~0" YMax "2~1~1~1~1~100~1~20000" SaveName "ScopeData3" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType Reference Name "Tx Delay Counter" Ports [2, 1] Position [745, 356, 785, 409] NamePlacement "alternate" SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited counter is implemented by combining a counter with a comparator." cnt_type "Free Running" cnt_to "Inf" operation "Up" start_count "0" cnt_by_val "1" arith_type "Unsigned" n_bits "14" bin_pt "0" load_pin off rst on en on explicit_period "off" period "1" dbl_ovrd off use_behavioral_HDL off use_rpm off implementation "Fabric" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,356,630" block_type "counter" block_version "8.2" sg_icon_stat "40,53,1,1,white,blue,0,46c73e85,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 ],[0 0 53 53 ],[0.77 0.82 0.91]);\npatch([10 3 12 3 10 21 24 27 38 29 20 14 24 14 20 29 38 27 24 21 10 ],[11 18 27 36 43 43 40 43 43 34 43 37 27 17 11 20 11 11 14 11 11 ],[0.98 0.96 0.92]);\nplot([0 40 40 0 0 ],[0 0 53 53 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'rst');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'out');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Outport Name "Addr" Position [1315, 328, 1345, 342] IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Block { BlockType Outport Name "Vout" Position [1160, 418, 1190, 432] Port "2" IconDisplay "Port number" OutDataType "sfix(16)" OutScaling "2^0" } Line { SrcBlock "Transmisson\nMode Selector" SrcPort 1 Points [20, 0] Branch { DstBlock "S-R Latch" DstPort 2 } Branch { Points [0, -170] DstBlock "Logical2" DstPort 1 } } Line { SrcBlock "Tx Delay Counter" SrcPort 1 Points [25, 0] Branch { DstBlock "Relational1" DstPort 1 } Branch { Points [0, 315] DstBlock "Gateway Out6" DstPort 1 } } Line { SrcBlock "TxDelay" SrcPort 1 DstBlock "Relational1" DstPort 2 } Line { SrcBlock "ContinuousTx" SrcPort 1 Points [105, 0] Branch { DstBlock "Transmisson\nMode Selector" DstPort 1 } Branch { Points [0, 265] DstBlock "Gateway Out1" DstPort 1 } } Line { SrcBlock "StartTx" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "StopTx" SrcPort 1 DstBlock "Convert2" DstPort 1 } Line { SrcBlock "Logical" SrcPort 1 DstBlock "Tx Delay Counter" DstPort 2 } Line { SrcBlock "S-R Latch" SrcPort 1 Points [20, 0] Branch { Points [0, 0] Branch { DstBlock "Logical" DstPort 1 } Branch { Points [0, 0; 0, -50] DstBlock "Logical1" DstPort 1 } } Branch { Points [0, 300] DstBlock "Gateway Out5" DstPort 1 } } Line { SrcBlock "Relational1" SrcPort 1 Points [50, 0] Branch { Points [0, 80] DstBlock "Inverter" DstPort 1 } Branch { Points [0, -55] DstBlock "Logical1" DstPort 2 } } Line { SrcBlock "Inverter" SrcPort 1 Points [-130, 0; 0, -85] DstBlock "Logical" DstPort 2 } Line { SrcBlock "Logical1" SrcPort 1 Points [30, 0] Branch { DstBlock "Tx Addr Counter" DstPort 2 } Branch { Points [0, 80] Branch { DstBlock "Vout" DstPort 1 } Branch { Points [0, 290] DstBlock "Gateway Out7" DstPort 1 } } } Line { SrcBlock "Tx Addr Counter" SrcPort 1 Points [65, 0] Branch { DstBlock "Addr" DstPort 1 } Branch { Points [0, -75] DstBlock "Relational" DstPort 2 } Branch { Points [0, 395] DstBlock "Gateway Out8" DstPort 1 } } Line { SrcBlock "From Register4" SrcPort 1 DstBlock "Relational" DstPort 1 } Line { SrcBlock "Posedge2" SrcPort 1 DstBlock "Logical2" DstPort 2 } Line { SrcBlock "Relational" SrcPort 1 Points [-90, 0; 0, -60; -710, 0; 0, 205] Branch { DstBlock "Transmisson\nMode Selector" DstPort 2 } Branch { Points [0, 245] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "Logical2" SrcPort 1 Points [20, 0] Branch { Points [240, 0; 0, 85] DstBlock "Tx Addr Counter" DstPort 1 } Branch { Points [0, 135] DstBlock "Tx Delay Counter" DstPort 1 } } Line { SrcBlock "Convert1" SrcPort 1 Points [25, 0] Branch { DstBlock "S-R Latch" DstPort 1 } Branch { Points [0, -135] DstBlock "Posedge2" DstPort 1 } Branch { Points [0, 295] DstBlock "Gateway Out4" DstPort 1 } } Line { SrcBlock "Convert2" SrcPort 1 Points [5, 0] Branch { DstBlock "Transmisson\nMode Selector" DstPort 3 } Branch { Points [0, 225] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "Gateway Out5" SrcPort 1 DstBlock "Tx Control" DstPort 5 } Line { SrcBlock "Gateway Out4" SrcPort 1 DstBlock "Tx Control" DstPort 4 } Line { SrcBlock "Gateway Out3" SrcPort 1 DstBlock "Tx Control" DstPort 3 } Line { SrcBlock "Gateway Out2" SrcPort 1 DstBlock "Tx Control" DstPort 2 } Line { SrcBlock "Gateway Out1" SrcPort 1 DstBlock "Tx Control" DstPort 1 } Line { SrcBlock "Gateway Out6" SrcPort 1 DstBlock "Tx Control" DstPort 6 } Line { SrcBlock "Gateway Out7" SrcPort 1 DstBlock "Tx Control" DstPort 7 } Line { SrcBlock "Gateway Out8" SrcPort 1 DstBlock "Tx Control" DstPort 8 } } } Block { BlockType Reference Name "debug_AGC_Done" Ports [1, 1] Position [270, 1088, 310, 1102] SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, double, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarded, depending on how they are configured." hdl_port on timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "8.2" sg_icon_stat "40,14,1,1,white,yellow,0,38220381,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 ],[0 0 14 14 ],[0.95 0.93 0.65]);\npatch([16 14 17 14 16 20 21 22 26 23 20 18 21 18 20 23 26 22 21 20 16 ],[2 4 7 10 12 12 11 12 12 9 12 10 7 4 2 5 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "debug_Capturing" Ports [1, 1] Position [580, 528, 620, 542] Orientation "left" NamePlacement "alternate" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, double, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarded, depending on how they are configured." hdl_port on timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "8.2" sg_icon_stat "40,14,1,1,white,yellow,0,38220381,left" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 ],[0 0 14 14 ],[0.95 0.93 0.65]);\npatch([16 14 17 14 16 20 21 22 26 23 20 18 21 18 20 23 26 22 21 20 16 ],[2 4 7 10 12 12 11 12 12 9 12 10 7 4 2 5 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name "debug_Transmitting" Ports [1, 1] Position [755, 763, 795, 777] SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, double, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarded, depending on how they are configured." hdl_port on timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "8.2" sg_icon_stat "40,14,1,1,white,yellow,0,38220381,right" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 ],[0 0 14 14 ],[0.95 0.93 0.65]);\npatch([16 14 17 14 16 20 21 22 26 23 20 18 21 18 20 23 26 22 21 20 16 ],[2 4 7 10 12 12 11 12 12 9 12 10 7 4 2 5 2 2 3 2 2 ],[0.98 0.96 0.92]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end icon text');\n" } Line { SrcBlock "Pulse\nGenerator" SrcPort 1 DstBlock "StartCapture" DstPort 1 } Line { SrcBlock "From9" SrcPort 1 DstBlock "Logical" DstPort 2 } Line { SrcBlock "Logical" SrcPort 1 DstBlock "Posedge" DstPort 1 } Line { SrcBlock "StartCapture" SrcPort 1 DstBlock "Logical" DstPort 1 } Line { SrcBlock "Radio 3 Inputs" SrcPort 2 DstBlock "Radio 3\nRx Buffers" DstPort 2 } Line { SrcBlock "From12" SrcPort 1 DstBlock "Radio 3\nRx Buffers" DstPort 5 } Line { SrcBlock "Radio 2 Inputs" SrcPort 2 DstBlock "Radio 2\nRx Buffers" DstPort 2 } Line { SrcBlock "From11" SrcPort 1 DstBlock "Radio 2\nRx Buffers" DstPort 5 } Line { SrcBlock "Posedge" SrcPort 1 DstBlock "Rx Control" DstPort 1 } Line { SrcBlock "From15" SrcPort 1 DstBlock "Radio 2 Inputs" DstPort 1 } Line { SrcBlock "From16" SrcPort 1 DstBlock "Radio 3 Inputs" DstPort 1 } Line { SrcBlock "Radio 1 Inputs" SrcPort 2 DstBlock "Radio 1\nRx Buffers" DstPort 2 } Line { SrcBlock "From10" SrcPort 1 DstBlock "Radio 1\nRx Buffers" DstPort 5 } Line { SrcBlock "From14" SrcPort 1 DstBlock "Radio 1 Inputs" DstPort 1 } Line { SrcBlock "Radio 4 Inputs" SrcPort 2 DstBlock "Radio 4\nRx Buffers" DstPort 2 } Line { SrcBlock "From13" SrcPort 1 DstBlock "Radio 4\nRx Buffers" DstPort 5 } Line { SrcBlock "From17" SrcPort 1 DstBlock "Radio 4 Inputs" DstPort 1 } Line { SrcBlock "Rx Control" SrcPort 1 Points [25, 0] Branch { Points [130, 0] Branch { DstBlock "Radio 2\nRx Buffers" DstPort 3 } Branch { Points [0, -145] DstBlock "Radio 1\nRx Buffers" DstPort 3 } Branch { Points [0, 140] Branch { DstBlock "Radio 3\nRx Buffers" DstPort 3 } Branch { Points [0, 140] DstBlock "Radio 4\nRx Buffers" DstPort 3 } } } Branch { DstBlock "Goto1" DstPort 1 } } Line { SrcBlock "Rx Control" SrcPort 2 Points [180, 0] Branch { Labels [1, 0] DstBlock "Radio 2\nRx Buffers" DstPort 4 } Branch { Points [0, 140] Branch { DstBlock "Radio 3\nRx Buffers" DstPort 4 } Branch { Points [0, 140] Branch { DstBlock "Radio 4\nRx Buffers" DstPort 4 } Branch { DstBlock "debug_Capturing" DstPort 1 } } } Branch { Points [0, -145] DstBlock "Radio 1\nRx Buffers" DstPort 4 } } Line { SrcBlock "Radio 2\nTx Buffer" SrcPort 1 DstBlock "Radio 2 Outputs" DstPort 1 } Line { SrcBlock "Posedge1" SrcPort 1 DstBlock "Tx Control" DstPort 1 } Line { SrcBlock "From2" SrcPort 1 Points [75, 0; 0, -140] DstBlock "Tx Control" DstPort 3 } Line { SrcBlock "Posedge2" SrcPort 1 Points [60, 0; 0, -85] DstBlock "Tx Control" DstPort 2 } Line { SrcBlock " 1" SrcPort 1 DstBlock "Posedge2" DstPort 1 } Line { SrcBlock "StopTx" SrcPort 1 DstBlock " 1" DstPort 1 } Line { SrcBlock "Pulse\nGenerator2" SrcPort 1 DstBlock "StopTx" DstPort 1 } Line { SrcBlock " " SrcPort 1 DstBlock "Posedge1" DstPort 1 } Line { SrcBlock "Pulse\nGenerator1" SrcPort 1 DstBlock "StartTx" DstPort 1 } Line { SrcBlock "From6" SrcPort 1 DstBlock "Radio 2\nTx Buffer" DstPort 3 } Line { SrcBlock "From4" SrcPort 1 Points [105, 0; 0, -200] DstBlock "Tx Control" DstPort 4 } Line { SrcBlock "Tx Control" SrcPort 2 Points [25, 0] Branch { Points [0, 70] DstBlock "debug_Transmitting" DstPort 1 } Branch { DstBlock "Inverter" DstPort 1 } } Line { SrcBlock "Radio 3\nTx Buffer" SrcPort 1 DstBlock "Radio 3 Outputs" DstPort 1 } Line { SrcBlock "From7" SrcPort 1 DstBlock "Radio 3\nTx Buffer" DstPort 3 } Line { SrcBlock "Radio 1\nTx Buffer" SrcPort 1 DstBlock "Radio 1 Outputs" DstPort 1 } Line { SrcBlock "From5" SrcPort 1 DstBlock "Radio 1\nTx Buffer" DstPort 3 } Line { SrcBlock "Radio 4\nTx Buffer" SrcPort 1 DstBlock "Radio 4 Outputs" DstPort 1 } Line { SrcBlock "From8" SrcPort 1 DstBlock "Radio 4\nTx Buffer" DstPort 3 } Line { SrcBlock "Tx Control" SrcPort 1 Points [155, 0] Branch { DstBlock "Radio 1\nTx Buffer" DstPort 1 } Branch { Points [0, 95] Branch { DstBlock "Radio 2\nTx Buffer" DstPort 1 } Branch { Points [0, 95] Branch { DstBlock "Radio 3\nTx Buffer" DstPort 1 } Branch { Points [0, 100] DstBlock "Radio 4\nTx Buffer" DstPort 1 } } } } Line { SrcBlock "Inverter" SrcPort 1 Points [55, 0] Branch { Points [0, -10] DstBlock "Radio 1\nTx Buffer" DstPort 2 } Branch { Points [0, 85] Branch { DstBlock "Radio 2\nTx Buffer" DstPort 2 } Branch { Points [0, 95] Branch { DstBlock "Radio 3\nTx Buffer" DstPort 2 } Branch { Points [0, 100] DstBlock "Radio 4\nTx Buffer" DstPort 2 } } } } Line { SrcBlock "From1" SrcPort 1 DstBlock " 1" DstPort 2 } Line { SrcBlock "Radio 1 Inputs" SrcPort 1 Points [15, 0] Branch { Points [0, -15] DstBlock "Goto2" DstPort 1 } Branch { Points [0, 5] DstBlock "Radio 1\nRx Buffers" DstPort 1 } } Line { SrcBlock "Radio 2 Inputs" SrcPort 1 Points [25, 0] Branch { Points [0, -15] DstBlock "Goto4" DstPort 1 } Branch { Points [0, 5] DstBlock "Radio 2\nRx Buffers" DstPort 1 } } Line { SrcBlock "Radio 3 Inputs" SrcPort 1 Points [35, 0] Branch { Points [0, -15] DstBlock "Goto5" DstPort 1 } Branch { Points [0, 10] DstBlock "Radio 3\nRx Buffers" DstPort 1 } } Line { SrcBlock "Radio 4 Inputs" SrcPort 1 Points [15, 0] Branch { Points [0, -15] DstBlock "Goto6" DstPort 1 } Branch { Points [0, 10] DstBlock "Radio 4\nRx Buffers" DstPort 1 } } Line { SrcBlock "From18" SrcPort 1 Points [15, 0; 0, -65] Branch { DstBlock "Radio 4 Inputs" DstPort 2 } Branch { Points [0, -140] Branch { DstBlock "Radio 3 Inputs" DstPort 2 } Branch { Points [0, -140] Branch { DstBlock "Radio 2 Inputs" DstPort 2 } Branch { Points [0, -145] DstBlock "Radio 1 Inputs" DstPort 2 } } } } Line { SrcBlock "From19" SrcPort 1 Points [15, 0] Branch { Points [0, 165] DstBlock " " DstPort 1 } Branch { Points [0, -205] DstBlock "Logical" DstPort 3 } } Line { SrcBlock "StartTx" SrcPort 1 DstBlock " " DstPort 2 } Line { SrcBlock "From3" SrcPort 1 DstBlock " " DstPort 3 } Line { SrcBlock "RSSI Clock\nGenerator" SrcPort 1 DstBlock "RSSI_ADC_CLK" DstPort 1 } Line { SrcBlock "RSSI_ADC_CLK" SrcPort 1 DstBlock "Terminator" DstPort 1 } Line { SrcBlock "AGC_Done" SrcPort 1 Points [15, 0] Branch { Points [0, 75] DstBlock "debug_AGC_Done" DstPort 1 } Branch { DstBlock "Register" DstPort 1 } } Line { SrcBlock "Pulse\nGenerator3" SrcPort 1 DstBlock "AGC_Done" DstPort 1 } Line { SrcBlock "Register" SrcPort 1 DstBlock "Posedge3" DstPort 1 } Line { SrcBlock "Posedge3" SrcPort 1 DstBlock "Convert2" DstPort 1 } Line { SrcBlock "Convert2" SrcPort 1 DstBlock "Goto3" DstPort 1 } Annotation { Position [348, 1029] } } } MatData { NumRecords 1 DataRecord { Tag DataTag0 Data " %)30 . Z'D 8 ( @ % \" $ ! 0 % 0 !@ $ , 0 . . 8 ( ! % \" $ ' 0 0 !P '1A7, !V86QU97, . & $ 8 ( 0 % \" $ # 0 . 0 8 ( ! % \" $ + 0 0 \"P $A$3\"!.971L:7-T . 2 8 ( ! % \" $ 8 0 0 & $5X<&]R=\"!A7=H97)E(&EN(%-U8E-Y&EL:6YX9F%M:6QY <&%R= #0 #@ #@ & \" 0 !0 @ ! \" $ $ @ !X8S1V'0G*3L*9G!R:6YT9B@G)RPG0T]-345.5#H@96YD(&EC;VX@=&5X=\"&EL:6YX9F%M:6QY <&%R= &QE9&MS971T:6YG7-T96T@1V5N97)A=&]R X X !@ @ $ 4 ( 0 @ ! ! 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