Model { Name "w2_warplab_buffers" Version 7.7 MdlSubVersion 0 GraphicalInterface { NumRootInports 0 NumRootOutports 0 ParameterArgumentNames "" ComputedModelVersion "1.184" NumModelReferences 0 NumTestPointedSignals 0 } SavedCharacterEncoding "windows-1252" SaveDefaultBlockParams on ScopeRefreshTime 0.035000 OverrideScopeRefreshTime on DisableAllScopes off DataTypeOverride "UseLocalSettings" DataTypeOverrideAppliesTo "AllNumericTypes" MinMaxOverflowLogging "UseLocalSettings" MinMaxOverflowArchiveMode "Overwrite" MaxMDLFileLineLength 120 Created "Wed Jan 07 15:32:06 2009" Creator "mduarte" UpdateHistory "UpdateHistoryNever" ModifiedByFormat "%" LastModifiedBy "chunter" ModifiedDateFormat "%" LastModifiedDate "Wed Aug 29 13:55:41 2012" RTWModifiedTimeStamp 268149340 ModelVersionFormat "1.%" ConfigurationManager "None" SampleTimeColors off SampleTimeAnnotations off LibraryLinkDisplay "none" WideLines off ShowLineDimensions off ShowPortDataTypes off ShowLoopsOnError on IgnoreBidirectionalLines off ShowStorageClass off ShowTestPointIcons on ShowSignalResolutionIcons on ShowViewerIcons on SortedOrder off ExecutionContextIcon off ShowLinearizationAnnotations on BlockNameDataTip off BlockParametersDataTip off BlockDescriptionStringDataTip off ToolBar on StatusBar on BrowserShowLibraryLinks off BrowserLookUnderMasks off SimulationMode "normal" LinearizationMsg "none" Profile off ParamWorkspaceSource "MATLABWorkspace" AccelSystemTargetFile "accel.tlc" AccelTemplateMakefile "accel_default_tmf" AccelMakeCommand "make_rtw" TryForcingSFcnDF off RecordCoverage off CovPath "/" CovSaveName "covdata" CovMetricSettings "dw" CovNameIncrementing off CovHtmlReporting on CovForceBlockReductionOff on covSaveCumulativeToWorkspaceVar on CovSaveSingleToWorkspaceVar on CovCumulativeVarName "covCumulativeData" CovCumulativeReport off CovReportOnPause on CovModelRefEnable "Off" CovExternalEMLEnable off ExtModeBatchMode off ExtModeEnableFloating on ExtModeTrigType "manual" ExtModeTrigMode "normal" ExtModeTrigPort "1" ExtModeTrigElement "any" ExtModeTrigDuration 1000 ExtModeTrigDurationFloating "auto" ExtModeTrigHoldOff 0 ExtModeTrigDelay 0 ExtModeTrigDirection "rising" ExtModeTrigLevel 0 ExtModeArchiveMode "off" ExtModeAutoIncOneShot off ExtModeIncDirWhenArm off ExtModeAddSuffixToVar off ExtModeWriteAllDataToWs off ExtModeArmWhenConnect on ExtModeSkipDownloadWhenConnect off ExtModeLogAll on ExtModeAutoUpdateStatusClock on BufferReuse on ShowModelReferenceBlockVersion off ShowModelReferenceBlockIO off Array { Type "Handle" Dimension 1 Simulink.ConfigSet { $ObjectID 1 Version "1.11.0" Array { Type "Handle" Dimension 8 Simulink.SolverCC { $ObjectID 2 Version "1.11.0" StartTime "0.0" StopTime "50000" AbsTol "auto" FixedStep "auto" InitialStep "auto" MaxNumMinSteps "-1" MaxOrder 5 ZcThreshold "auto" ConsecutiveZCsStepRelTol "10*128*eps" MaxConsecutiveZCs "1000" ExtrapolationOrder 4 NumberNewtonIterations 1 MaxStep "auto" MinStep "auto" MaxConsecutiveMinStep "1" RelTol "1e-3" SolverMode "Auto" ConcurrentTasks off Solver "ode45" SolverName "ode45" SolverJacobianMethodControl "auto" ShapePreserveControl "DisableAll" ZeroCrossControl "UseLocalSettings" ZeroCrossAlgorithm "Nonadaptive" AlgebraicLoopSolver "TrustRegion" SolverResetMethod "Fast" PositivePriorityOrder off AutoInsertRateTranBlk off SampleTimeConstraint "Unconstrained" InsertRTBMode "Whenever possible" } Simulink.DataIOCC { $ObjectID 3 Version "1.11.0" Decimation "1" ExternalInput "[t, u]" FinalStateName "xFinal" InitialState "xInitial" LimitDataPoints on MaxDataPoints "1000" LoadExternalInput off LoadInitialState off SaveFinalState off SaveCompleteFinalSimState off SaveFormat "Array" SignalLoggingSaveFormat "ModelDataLogs" SaveOutput on SaveState off SignalLogging on DSMLogging on InspectSignalLogs off SaveTime on ReturnWorkspaceOutputs off StateSaveName "xout" TimeSaveName "tout" OutputSaveName "yout" SignalLoggingName "logsout" DSMLoggingName "dsmout" OutputOption "RefineOutputTimes" OutputTimes "[]" ReturnWorkspaceOutputsName "out" Refine "1" } Simulink.OptimizationCC { $ObjectID 4 Version "1.11.0" Array { Type "Cell" Dimension 4 Cell "ZeroExternalMemoryAtStartup" Cell "ZeroInternalMemoryAtStartup" Cell "NoFixptDivByZeroProtection" Cell "OptimizeModelRefInitCode" PropName "DisabledProps" } BlockReduction on BooleanDataType on ConditionallyExecuteInputs on InlineParams off UseIntDivNetSlope off UseSpecifiedMinMax off InlineInvariantSignals off OptimizeBlockIOStorage on BufferReuse on EnhancedBackFolding off StrengthReduction off ExpressionFolding on BooleansAsBitfields off BitfieldContainerType "uint_T" EnableMemcpy on MemcpyThreshold 64 PassReuseOutputArgsAs "Structure reference" ExpressionDepthLimit 2147483647 FoldNonRolledExpr on LocalBlockOutputs on RollThreshold 5 SystemCodeInlineAuto off StateBitsets off DataBitsets off UseTempVars off ZeroExternalMemoryAtStartup on ZeroInternalMemoryAtStartup on InitFltsAndDblsToZero on NoFixptDivByZeroProtection off EfficientFloat2IntCast off EfficientMapNaN2IntZero on OptimizeModelRefInitCode off LifeSpan "inf" MaxStackSize "Inherit from target" BufferReusableBoundary on SimCompilerOptimization "Off" AccelVerboseBuild off AccelParallelForEachSubsystem on } Simulink.DebuggingCC { $ObjectID 5 Version "1.11.0" RTPrefix "error" ConsistencyChecking "none" ArrayBoundsChecking "none" SignalInfNanChecking "none" SignalRangeChecking "none" ReadBeforeWriteMsg "UseLocalSettings" WriteAfterWriteMsg "UseLocalSettings" WriteAfterReadMsg "UseLocalSettings" AlgebraicLoopMsg "warning" ArtificialAlgebraicLoopMsg "warning" SaveWithDisabledLinksMsg "warning" SaveWithParameterizedLinksMsg "none" CheckSSInitialOutputMsg on UnderspecifiedInitializationDetection "Classic" MergeDetectMultiDrivingBlocksExec "none" CheckExecutionContextPreStartOutputMsg off CheckExecutionContextRuntimeOutputMsg off SignalResolutionControl "UseLocalSettings" BlockPriorityViolationMsg "warning" MinStepSizeMsg "warning" TimeAdjustmentMsg "none" MaxConsecutiveZCsMsg "error" MaskedZcDiagnostic "warning" IgnoredZcDiagnostic "warning" SolverPrmCheckMsg "warning" InheritedTsInSrcMsg "warning" DiscreteInheritContinuousMsg "warning" MultiTaskDSMMsg "error" MultiTaskCondExecSysMsg "error" MultiTaskRateTransMsg "error" SingleTaskRateTransMsg "none" TasksWithSamePriorityMsg "warning" SigSpecEnsureSampleTimeMsg "warning" CheckMatrixSingularityMsg "none" IntegerOverflowMsg "warning" Int32ToFloatConvMsg "warning" ParameterDowncastMsg "error" ParameterOverflowMsg "error" ParameterUnderflowMsg "none" ParameterPrecisionLossMsg "warning" ParameterTunabilityLossMsg "warning" FixptConstUnderflowMsg "none" FixptConstOverflowMsg "none" FixptConstPrecisionLossMsg "none" UnderSpecifiedDataTypeMsg "none" UnnecessaryDatatypeConvMsg "none" VectorMatrixConversionMsg "none" InvalidFcnCallConnMsg "error" FcnCallInpInsideContextMsg "Use local settings" SignalLabelMismatchMsg "none" UnconnectedInputMsg "warning" UnconnectedOutputMsg "warning" UnconnectedLineMsg "warning" SFcnCompatibilityMsg "none" UniqueDataStoreMsg "none" BusObjectLabelMismatch "warning" RootOutportRequireBusObject "warning" AssertControl "UseLocalSettings" EnableOverflowDetection off ModelReferenceIOMsg "none" ModelReferenceMultiInstanceNormalModeStructChecksumCheck "error" ModelReferenceVersionMismatchMessage "none" ModelReferenceIOMismatchMessage "none" ModelReferenceCSMismatchMessage "none" UnknownTsInhSupMsg "warning" ModelReferenceDataLoggingMessage "warning" ModelReferenceSymbolNameMessage "warning" ModelReferenceExtraNoncontSigs "error" StateNameClashWarn "warning" SimStateInterfaceChecksumMismatchMsg "warning" SimStateOlderReleaseMsg "error" InitInArrayFormatMsg "warning" StrictBusMsg "Warning" BusNameAdapt "WarnAndRepair" NonBusSignalsTreatedAsBus "none" LoggingUnavailableSignals "error" BlockIODiagnostic "none" SFUnusedDataAndEventsDiag "warning" SFUnexpectedBacktrackingDiag "warning" SFInvalidInputDataAccessInChartInitDiag "warning" SFNoUnconditionalDefaultTransitionDiag "warning" SFTransitionOutsideNaturalParentDiag "warning" } Simulink.HardwareCC { $ObjectID 6 Version "1.11.0" ProdBitPerChar 8 ProdBitPerShort 16 ProdBitPerInt 32 ProdBitPerLong 32 ProdBitPerFloat 32 ProdBitPerDouble 64 ProdBitPerPointer 32 ProdLargestAtomicInteger "Char" ProdLargestAtomicFloat "None" ProdIntDivRoundTo "Undefined" ProdEndianess "Unspecified" ProdWordSize 32 ProdShiftRightIntArith on ProdHWDeviceType "32-bit Generic" TargetBitPerChar 8 TargetBitPerShort 16 TargetBitPerInt 32 TargetBitPerLong 32 TargetBitPerFloat 32 TargetBitPerDouble 64 TargetBitPerPointer 32 TargetLargestAtomicInteger "Char" TargetLargestAtomicFloat "None" TargetShiftRightIntArith on TargetIntDivRoundTo "Undefined" TargetEndianess "Unspecified" TargetWordSize 32 TargetTypeEmulationWarnSuppressLevel 0 TargetPreprocMaxBitsSint 32 TargetPreprocMaxBitsUint 32 TargetHWDeviceType "Specified" TargetUnknown off ProdEqTarget on } Simulink.ModelReferenceCC { $ObjectID 7 Version "1.11.0" UpdateModelReferenceTargets "IfOutOfDateOrStructuralChange" CheckModelReferenceTargetMessage "error" EnableParallelModelReferenceBuilds off ParallelModelReferenceErrorOnInvalidPool on ParallelModelReferenceMATLABWorkerInit "None" ModelReferenceNumInstancesAllowed "Multi" PropagateVarSize "Infer from blocks in model" ModelReferencePassRootInputsByReference on ModelReferenceMinAlgLoopOccurrences off PropagateSignalLabelsOutOfModel off SupportModelReferenceSimTargetCustomCode off } Simulink.SFSimCC { $ObjectID 8 Version "1.11.0" SFSimEnableDebug on SFSimOverflowDetection on SFSimEcho on SimBlas on SimCtrlC on SimExtrinsic on SimIntegrity on SimUseLocalCustomCode off SimParseCustomCode on SimBuildMode "sf_incremental_build" } Simulink.RTWCC { $BackupClass "Simulink.RTWCC" $ObjectID 9 Version "1.11.0" Array { Type "Cell" Dimension 1 Cell "IncludeHyperlinkInReport" PropName "DisabledProps" } SystemTargetFile "grt.tlc" GenCodeOnly off MakeCommand "make_rtw" GenerateMakefile on TemplateMakefile "grt_default_tmf" GenerateReport off SaveLog off RTWVerbose on RetainRTWFile off ProfileTLC off TLCDebug off TLCCoverage off TLCAssert off ProcessScriptMode "Default" ConfigurationMode "Optimized" ConfigAtBuild off RTWUseLocalCustomCode off RTWUseSimCustomCode off IncludeHyperlinkInReport off LaunchReport off TargetLang "C" IncludeBusHierarchyInRTWFileBlockHierarchyMap off IncludeERTFirstTime off GenerateTraceInfo off GenerateTraceReport off GenerateTraceReportSl off GenerateTraceReportSf off GenerateTraceReportEml off GenerateCodeInfo off GenerateSLWebview off GenerateCodeMetricsReport off RTWCompilerOptimization "Off" CheckMdlBeforeBuild "Off" CustomRebuildMode "OnUpdate" Array { Type "Handle" Dimension 2 Simulink.CodeAppCC { $ObjectID 10 Version "1.11.0" Array { Type "Cell" Dimension 16 Cell "IgnoreCustomStorageClasses" Cell "InsertBlockDesc" Cell "SFDataObjDesc" Cell "SimulinkDataObjDesc" Cell "DefineNamingRule" Cell "SignalNamingRule" Cell "ParamNamingRule" Cell "InlinedPrmAccess" Cell "CustomSymbolStr" Cell "CustomSymbolStrGlobalVar" Cell "CustomSymbolStrType" Cell "CustomSymbolStrField" Cell "CustomSymbolStrFcn" Cell "CustomSymbolStrBlkIO" Cell "CustomSymbolStrTmpVar" Cell "CustomSymbolStrMacro" PropName "DisabledProps" } ForceParamTrailComments off GenerateComments on IgnoreCustomStorageClasses on IgnoreTestpoints off IncHierarchyInIds off MaxIdLength 31 PreserveName off PreserveNameWithParent off ShowEliminatedStatement off IncAutoGenComments off SimulinkDataObjDesc off SFDataObjDesc off MATLABFcnDesc off IncDataTypeInIds off MangleLength 1 CustomSymbolStrGlobalVar "$R$N$M" CustomSymbolStrType "$N$R$M" CustomSymbolStrField "$N$M" CustomSymbolStrFcn "$R$N$M$F" CustomSymbolStrFcnArg "rt$I$N$M" CustomSymbolStrBlkIO "rtb_$N$M" CustomSymbolStrTmpVar "$N$M" CustomSymbolStrMacro "$R$N$M" DefineNamingRule "None" ParamNamingRule "None" SignalNamingRule "None" InsertBlockDesc off InsertPolySpaceComments off SimulinkBlockComments on MATLABSourceComments off EnableCustomComments off InlinedPrmAccess "Literals" ReqsInCode off UseSimReservedNames off } Simulink.GRTTargetCC { $BackupClass "Simulink.TargetCC" $ObjectID 11 Version "1.11.0" Array { Type "Cell" Dimension 14 Cell "IncludeMdlTerminateFcn" Cell "CombineOutputUpdateFcns" Cell "SuppressErrorStatus" Cell "ERTCustomFileBanners" Cell "GenerateSampleERTMain" Cell "GenerateTestInterfaces" Cell "ModelStepFunctionPrototypeControlCompliant" Cell "MultiInstanceERTCode" Cell "PurelyIntegerCode" Cell "PortableWordSizes" Cell "SupportComplex" Cell "SupportAbsoluteTime" Cell "SupportContinuousTime" Cell "SupportNonInlinedSFcns" PropName "DisabledProps" } TargetFcnLib "ansi_tfl_tmw.mat" TargetLibSuffix "" TargetPreCompLibLocation "" TargetFunctionLibrary "ANSI_C" UtilityFuncGeneration "Auto" ERTMultiwordTypeDef "System defined" FunctionExecutionProfile off CodeExecutionProfiling off ERTCodeCoverageTool "None" ERTMultiwordLength 256 MultiwordLength 2048 GenerateFullHeader on GenerateSampleERTMain off GenerateTestInterfaces off IsPILTarget off ModelReferenceCompliant on ParMdlRefBuildCompliant on CompOptLevelCompliant on IncludeMdlTerminateFcn on GeneratePreprocessorConditionals "Disable all" CombineOutputUpdateFcns off CombineSignalStateStructs off SuppressErrorStatus off ERTFirstTimeCompliant off IncludeFileDelimiter "Auto" ERTCustomFileBanners off SupportAbsoluteTime on LogVarNameModifier "rt_" MatFileLogging on MultiInstanceERTCode off SupportNonFinite on SupportComplex on PurelyIntegerCode off SupportContinuousTime on SupportNonInlinedSFcns on SupportVariableSizeSignals off EnableShiftOperators on ParenthesesLevel "Nominal" PortableWordSizes off ModelStepFunctionPrototypeControlCompliant off CPPClassGenCompliant off AutosarCompliant off UseMalloc off ExtMode off ExtModeStaticAlloc off ExtModeTesting off ExtModeStaticAllocSize 1000000 ExtModeTransport 0 ExtModeMexFile "ext_comm" ExtModeIntrfLevel "Level1" RTWCAPISignals off RTWCAPIParams off RTWCAPIStates off RTWCAPIRootIO off GenerateASAP2 off } PropName "Components" } } PropName "Components" } Name "Configuration" CurrentDlgPage "Solver" ConfigPrmDlgPosition [ 840, 405, 1720, 1035 ] } PropName "ConfigurationSets" } Simulink.ConfigSet { $PropName "ActiveConfigurationSet" $ObjectID 1 } BlockDefaults { ForegroundColor "black" BackgroundColor "white" DropShadow off NamePlacement "normal" FontName "Arial" FontSize 10 FontWeight "normal" FontAngle "normal" ShowName on BlockRotation 0 BlockMirror off } AnnotationDefaults { HorizontalAlignment "center" VerticalAlignment "middle" ForegroundColor "black" BackgroundColor "white" DropShadow off FontName "Arial" FontSize 10 FontWeight "normal" FontAngle "normal" UseDisplayTextAsClickCallback off } LineDefaults { FontName "Arial" FontSize 9 FontWeight "normal" FontAngle "normal" } BlockParameterDefaults { Block { BlockType Constant Value "1" VectorParams1D on SamplingMode "Sample based" OutMin "[]" OutMax "[]" OutDataTypeStr "Inherit: Inherit from 'Constant value'" LockScale off SampleTime "inf" FramePeriod "inf" PreserveConstantTs off } Block { BlockType DiscretePulseGenerator PulseType "Sample based" TimeSource "Use simulation time" Amplitude "1" Period "2" PulseWidth "1" PhaseDelay "0" SampleTime "1" VectorParams1D on } Block { BlockType From IconDisplay "Tag" TagVisibility "local" } Block { BlockType Goto IconDisplay "Tag" } Block { BlockType Inport Port "1" OutputFunctionCall off OutMin "[]" OutMax "[]" OutDataTypeStr "Inherit: auto" LockScale off BusOutputAsStruct off PortDimensions "-1" VarSizeSig "Inherit" SampleTime "-1" SignalType "auto" SamplingMode "auto" LatchByDelayingOutsideSignal off LatchInputForFeedbackSignals off Interpolate on } Block { BlockType Outport Port "1" OutMin "[]" OutMax "[]" OutDataTypeStr "Inherit: auto" LockScale off BusOutputAsStruct off PortDimensions "-1" VarSizeSig "Inherit" SampleTime "-1" SignalType "auto" SamplingMode "auto" SourceOfInitialOutputValue "Dialog" OutputWhenDisabled "held" InitialOutput "[]" } Block { BlockType Scope ModelBased off TickLabels "OneTimeTick" ZoomMode "on" Grid "on" TimeRange "auto" YMin "-5" YMax "5" SaveToWorkspace off SaveName "ScopeData" LimitDataPoints on MaxDataPoints "5000" Decimation "1" SampleInput off SampleTime "-1" } Block { BlockType SubSystem ShowPortLabels "FromPortIcon" Permissions "ReadWrite" PermitHierarchicalResolution "All" TreatAsAtomicUnit off CheckFcnCallInpInsideContextMsg off SystemSampleTime "-1" RTWFcnNameOpts "Auto" RTWFileNameOpts "Auto" RTWMemSecFuncInitTerm "Inherit from model" RTWMemSecFuncExecute "Inherit from model" RTWMemSecDataConstants "Inherit from model" RTWMemSecDataInternal "Inherit from model" RTWMemSecDataParameters "Inherit from model" SimViewingDevice off DataTypeOverride "UseLocalSettings" DataTypeOverrideAppliesTo "AllNumericTypes" MinMaxOverflowLogging "UseLocalSettings" Variant off GeneratePreprocessorConditionals off } Block { BlockType Terminator } } System { Name "w2_warplab_buffers" Location [2, 74, 1894, 1154] Open on ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" ReportName "simulink-default.rpt" SIDHighWatermark "668" Block { BlockType Reference Name " " SID "1" Ports [3, 1] Position [270, 627, 310, 693] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "3" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,261" block_type "logical" block_version "9.1.01" sg_icon_stat "40,66,3,1,white,blue,0,a2abe52d,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 66 66 0 ],[0.77 0." "82 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 66 66 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[38.55 3" "8.55 43.55 38.55 43.55 43.55 43.55 38.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[33.55 33.55 38.55" " 38.55 33.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[28.55 28.55 33.55 33.55 28.55 ],[1" " 1 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[23.55 23.55 28.55 23.55 28.55 28.55 23.55 ],[0.931 0" ".946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n\ncolo" "r('black');disp('or');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Reference Name " 1" SID "2" Ports [2, 1] Position [270, 732, 310, 788] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "9.1.01" sg_icon_stat "40,56,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 56 56 0 ],[0.77 0." "82 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 56 56 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[33.55 3" "3.55 38.55 33.55 38.55 38.55 38.55 33.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[28.55 28.55 33.55" " 33.55 28.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[23.55 23.55 28.55 28.55 23.55 ],[1" " 1 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[18.55 18.55 23.55 18.55 23.55 23.55 18.55 ],[0.931 0" ".946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor(" "'black');disp('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name " System Generator" SID "3" Tag "genX" Ports [] Position [34, 24, 85, 74] ShowName off AttributesFormatString "System\\nGenerator" LibraryVersion "1.2" UserDataPersistent on UserData "DataTag0" SourceBlock "xbsIndex_r4/ System Generator" SourceType "Xilinx System Generator Block" ShowPortLabels "FromPortIcon" SystemSampleTime "-1" FunctionWithSeparateData off RTWMemSecFuncInitTerm "Inherit from model" RTWMemSecFuncExecute "Inherit from model" RTWMemSecDataConstants "Inherit from model" RTWMemSecDataInternal "Inherit from model" RTWMemSecDataParameters "Inherit from model" GeneratePreprocessorConditionals off infoedit " System Generator" xilinxfamily "virtex4" part "xc4vfx100" speed "-11" package "ff1517" synthesis_tool "XST" clock_wrapper "Clock Enables" directory "./w2_netlist" proj_type "Project Navigator" Synth_file "XST Defaults" Impl_file "ISE Defaults" testbench off simulink_period "1" sysclk_period "10" dcm_input_clock_period "100" incr_netlist off trim_vbits "Everywhere in SubSystem" dbl_ovrd "According to Block Masks" core_generation "According to Block Masks" run_coregen off deprecated_control off eval_field "0" has_advanced_control "0" sggui_pos "326,241,464,470" block_type "sysgen" block_version "10.1.3" sg_icon_stat "51,50,0,0,token,white,0,58c5b5770fe5f7c311f53dbc6e73f0f6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 51 51 0 0 ],[0 0 50 50 0 ],[1 1 1 ]" ");\npatch([1.6375 16.81 27.31 37.81 48.31 27.31 12.1375 1.6375 ],[36.655 36.655 47.155 36.655 47.155 47.155 47.1" "55 36.655 ],[0.933333 0.203922 0.141176 ]);\npatch([12.1375 27.31 16.81 1.6375 12.1375 ],[26.155 26.155 36.655 3" "6.655 26.155 ],[0.698039 0.0313725 0.219608 ]);\npatch([1.6375 16.81 27.31 12.1375 1.6375 ],[15.655 15.655 26.15" "5 26.155 15.655 ],[0.933333 0.203922 0.141176 ]);\npatch([12.1375 48.31 37.81 27.31 16.81 1.6375 12.1375 ],[5.15" "5 5.155 15.655 5.155 15.655 15.655 5.155 ],[0.698039 0.0313725 0.219608 ]);\nfprintf('','COMMENT: end icon graph" "ics');\nfprintf('','COMMENT: begin icon text');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "AGC_Done" SID "4" Ports [1, 1] Position [130, 1014, 185, 1026] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, double and fixed point to Xilinx " "fixed point type.

Hardware notes: In hardware these blocks become top level input ports." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off UseAsADC off ADCChannel "'1'" hdl_port "on" has_advanced_control "0" sggui_pos "20,20,356,432" block_type "gatewayin" block_version "VER_STRING_GOES_HERE" sg_icon_stat "55,12,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 12 12 0 ],[0.95 0." "93 0.65 ]);\nplot([0 55 55 0 0 ],[0 0 12 12 0 ]);\npatch([24.775 26.22 27.22 28.22 29.22 27.22 25.775 24.775 ],[" "7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([25.775 27.22 26.22 24.775 25.775 ],[6.11 6.11 7.11 " "7.11 6.11 ],[0.985 0.979 0.895 ]);\npatch([24.775 26.22 27.22 25.775 24.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1" " ]);\npatch([25.775 29.22 28.22 27.22 26.22 24.775 25.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.985 0.979 0" ".895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');por" "t_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprin" "tf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert2" SID "5" Ports [1, 1] Position [420, 1011, 455, 1029] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do " "not." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "16" bin_pt "14" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,461,375" block_type "convert" block_version "8.2" sg_icon_stat "35,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 18 18 0 ],[0.77 0." "82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 18 18 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[11." "22 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[9.22 9.22 11." "22 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 " "1 ]);\npatch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.9" "73 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');por" "t_label('output',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "EDK Processor" SID "6" Ports [] Position [146, 23, 208, 87] CopyFcn "xlProcBlockCopyCallback(gcbh);xlBlockMoveCallback(gcbh);" DeleteFcn "xlDestroyGui(gcbh);" LoadFcn "xlBlockLoadCallback(gcbh);" ModelCloseFcn "xlDestroyGui(gcbh);" PreSaveFcn "xlBlockPreSaveCallback(gcbh);" PostSaveFcn "xlBlockPostSaveCallback(gcbh);" DestroyFcn "xlDestroyGui(gcbh);" OpenFcn "bh=gcbh;xlProcBlockCallbacks('populatesharedmemorylistbox',bh);xlOpenGui(bh, 'edkprocessor_gui.x" "ml', @xlProcBlockEnablement, @xlProcBlockAction)" CloseFcn "xlDestroyGui(gcbh);" MoveFcn "xlBlockMoveCallback(gcbh);" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskType "Xilinx EDK Processor Block" MaskDescription "Xilinx EDK Processor" MaskHelp "eval('');xlDoc('-book','sysgen','-topic','EDK_Processor');" MaskPromptString "Configure Processor for|EDK Project| |Available Memories| | |Bus Type|Base Address| |Loc" "k| |Dual Clocks| |Register Read-Back|Constraint file| |Inherit Device Type| | | | | | | | | | | | | | | | " MaskStyleString "popup(EDK pcore generation|HDL netlisting),edit,edit,popup(),edit,edit,popup(PLB|F" "SL),edit,edit,checkbox,edit,checkbox,edit,checkbox,edit,edit,checkbox,edit,edit,edit,edit,edit,edit,edit,edit,ed" "it,edit,edit,edit,edit,edit,edit,edit" MaskVariables "mode=&1;xmp=&2;MemVisToProc=&3;AvailableMemories=&4;portInterfaceTable=&5;bus_type_sgadvanc" "ed=&6;bus_type=@7;baseaddr=&8;baseaddr_lock_sgadvanced=&9;baseaddr_lock=@10;dual_clock_sgadvanced=&11;dual_clock" "=@12;reg_readback_sgadvanced=&13;reg_readback=@14;ucf_file=&15;inheritDeviceType_sgadvanced=&16;inheritDeviceTyp" "e=@17;clock_name=&18;internalPortList=&19;resetPolarity=&20;memxtable=&21;procinfo=&22;memmapdirty=&23;blockname" "=&24;xpsintstyle=&25;has_advanced_control=@26;sggui_pos=&27;block_type=&28;block_version=&29;sg_icon_stat=&30;sg" "_mask_display=&31;sg_list_contents=&32;sg_blockgui_xml=&33;" MaskTunableValueString "on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on," "on,on,on,on" MaskCallbackString "||||||||||||||||||||||||||||||||" MaskEnableString "on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,o" "n,on,on,on" MaskVisibilityString "on,on,off,on,on,off,on,on,off,on,off,on,off,on,on,off,on,off,off,off,off,off,off,off,of" "f,off,off,off,off,off,off,off,off" MaskToolTipString "on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on,on," "on,on,on,on" MaskInitialization "try\n tmp_gcb = gcb;\n tmp_gcbh = gcbh;\n if (strcmp('SysGenIndex',get_param(bdroot(" "tmp_gcbh),'tag')) && ~isempty(regexp(bdroot(tmp_gcb), '^xbs', 'once')))\n return;\n end;\n xlMungeMaskParam" "s;\n\nblock_type='edkprocessor';\n serialized_declarations = '{,''block_type''=>''String''}';\n xledkprocessor" "_init();\n ptable_ = xlblockprep(get_param(tmp_gcb, 'MaskWSVariables'));\ncatch\n global dbgsysgen;\n if(~ise" "mpty(dbgsysgen) && dbgsysgen)\n e = regexprep(lasterr, '\\n', '\\nError: ');\n disp(['Error: While running" " MaskInit code on block ' tmp_gcb ': ' e]);\n error(e);\n end\nend\n" MaskSelfModifiable on MaskDisplay "fprintf('','COMMENT: begin icon graphics');\npatch([0 62 62 0 0 ],[0 0 64 64 0 ],[0.77 0.82 0" ".91 ]);\nplot([0 62 62 0 0 ],[0 0 64 64 0 ]);\npatch([13.2 24.76 32.76 40.76 48.76 32.76 21.2 13.2 ],[40.88 40.8" "8 48.88 40.88 48.88 48.88 48.88 40.88 ],[1 1 1 ]);\npatch([21.2 32.76 24.76 13.2 21.2 ],[32.88 32.88 40.88 40.88" " 32.88 ],[0.931 0.946 0.973 ]);\npatch([13.2 24.76 32.76 21.2 13.2 ],[24.88 24.88 32.88 32.88 24.88 ],[1 1 1 ]);" "\npatch([21.2 48.76 40.76 32.76 24.76 13.2 21.2 ],[16.88 16.88 24.88 16.88 24.88 24.88 16.88 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ndisp('');\n\nfprintf(" "'','COMMENT: end icon text');" MaskIconFrame off MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" MaskValueString "EDK pcore generation||

<<AGCDoneAddr>>
<<CaptureDone>>
<<DCO_EN_SEL>>
<<DebugRx1Buffers>>
<<DebugRx2Buffers>>
<" "img src=\"C:/Xilinx/13.4/ISE_DS/ISE/sysgen/data/images/registerplus.gif\"> <<DebugRx3Buffers>>
<<DebugRx4Buffers>" ">
<<MGC_AGC_S" "EL>>
<<RAD" "IO1RXBUFF_RXEN>>
" " <<RADIO1TXBUFF_TXEN>>
<<RADIO2RXBUFF_RXEN>>
<<RADIO2TXBUFF_TXEN>>
<<RADIO3RXBUFF_RXEN>>
<<RADIO3TXBUFF_TXEN>>
<<RADIO4RXBUFF_RXEN>>
<<RADIO4TXBUFF_TXEN>>
<<Radio1AGCDoneRSSI&g" "t;>
<<Radio2A" "GCDoneRSSI>>
<" ";<Radio3AGCDoneRSSI>>
<<Radio4AGCDoneRSSI>>
<<StartCapture>>
<<StartTx>>
<<StopTx>>
<<TransMode>>
<<TxDelay>>
<<TxLength>>
<<StartTxRx>>
<<RxBuff_Radio1>>
<<RxBuff_Radio2>>
<<RxBuff_Radio3>>
<<RxBuff_Radio4>>
<<TxBuff_Radio1>>
<<TxBuff_Radio2>>
<" "div> <<TxBuff_Radio3>>
<" "/div>
<<TxBuff_Radio4>>" ";
<<RSSIBuff_Radio" "1>>
<<RSSIBu" "ff_Radio2>>
<&l" "t;RSSIBuff_Radio3>>
<<RSSIBuff_Radio4>>
||{'exposed'=>[],'portdir'=>[],'portname'=>[],'shortname'" "=>[]}||PLB|0x80000000||off||on||on|||off|plb|{}|0|{'mladdr'=>[0.00000000000000000,1.00000000000000000,0.00000000" "000000000,1.00000000000000000,2.00000000000000000,3.00000000000000000,4.00000000000000000,5.00000000000000000,6." "00000000000000000,7.00000000000000000,8.00000000000000000,9.00000000000000000,10.00000000000000000,11.0000000000" "0000000,12.00000000000000000,13.00000000000000000,2.00000000000000000,3.00000000000000000,4.00000000000000000,5." "00000000000000000,14.00000000000000000,15.00000000000000000,16.00000000000000000,17.00000000000000000,18.0000000" "0000000000,19.00000000000000000,20.00000000000000000,-1.00000000000000000,-1.00000000000000000,-1.00000000000000" "000,-1.00000000000000000,-1.00000000000000000,-1.00000000000000000,-1.00000000000000000,-1.00000000000000000,-1." "00000000000000000,-1.00000000000000000,-1.00000000000000000,-1.00000000000000000],'mlist'=>['w2_warplab_buffers/" "Memmory-mapped Registers/AGCDoneAddr','w2_warplab_buffers/Memmory-mapped Registers/To Register','w2_warplab_buff" "ers/Memmory-mapped Registers/From Register14','w2_warplab_buffers/Memmory-mapped Registers/DebugRx1Buffers','w2_" "warplab_buffers/Memmory-mapped Registers/DebugRx2Buffers','w2_warplab_buffers/Memmory-mapped Registers/DebugRx3B" "uffers','w2_warplab_buffers/Memmory-mapped Registers/DebugRx4Buffers','w2_warplab_buffers/Memmory-mapped Registe" "rs/From Register13','w2_warplab_buffers/Memmory-mapped Registers/From Register1','w2_warplab_buffers/Memmory-map" "ped Registers/From Register6','w2_warplab_buffers/Memmory-mapped Registers/From Register5','w2_warplab_buffers/M" "emmory-mapped Registers/From Register9','w2_warplab_buffers/Memmory-mapped Registers/From Register11','w2_warpla" "b_buffers/Memmory-mapped Registers/From Register10','w2_warplab_buffers/Memmory-mapped Registers/From Register3'" ",'w2_warplab_buffers/Memmory-mapped Registers/From Register12','w2_warplab_buffers/Memmory-mapped Registers/Radi" "o1AGCDoneRSSI','w2_warplab_buffers/Memmory-mapped Registers/Radio2AGCDoneRSSI','w2_warplab_buffers/Memmory-mappe" "d Registers/Radio3AGCDoneRSSI','w2_warplab_buffers/Memmory-mapped Registers/Radio4AGCDoneRSSI','w2_warplab_buffe" "rs/Memmory-mapped Registers/From Register2','w2_warplab_buffers/Memmory-mapped Registers/From Register4','w2_war" "plab_buffers/Memmory-mapped Registers/From Register7','w2_warplab_buffers/Memmory-mapped Registers/From Register" "8','w2_warplab_buffers/Memmory-mapped Registers/TxDelay','w2_warplab_buffers/Tx Control/From Register4','w2_warp" "lab_buffers/Memmory-mapped Registers/From Register15','w2_warplab_buffers/Radio 1\nRx Buffers/Radio 1 I//Q\nBuff" "er/Shared Memory','w2_warplab_buffers/Radio 2\nRx Buffers/Radio 2 I//Q\nBuffer/Shared Memory','w2_warplab_buffer" "s/Radio 3\nRx Buffers/Radio 3 I//Q\nBuffer/Shared Memory','w2_warplab_buffers/Radio 4\nRx Buffers/Radio 4 I//Q\n" "Buffer/Shared Memory','w2_warplab_buffers/Radio 1\nTx Buffer/Shared Memory','w2_warplab_buffers/Radio 2\nTx Buff" "er/Shared Memory','w2_warplab_buffers/Radio 3\nTx Buffer/Shared Memory','w2_warplab_buffers/Radio 4\nTx Buffer/S" "hared Memory','w2_warplab_buffers/Radio 1\nRx Buffers/Radio 1\nRSSI Buffer/Shared Memory','w2_warplab_buffers/Ra" "dio 2\nRx Buffers/Radio 2\nRSSI Buffer/Shared Memory','w2_warplab_buffers/Radio 3\nRx Buffers/Radio 3\nRSSI Buff" "er/Shared Memory','w2_warplab_buffers/Radio 4\nRx Buffers/Radio 4\nRSSI Buffer/Shared Memory'],'mlname'=>['\\\\'" "AGCDoneAddr\\\\'','\\\\'CaptureDone\\\\'','\\\\'DCO_EN_SEL\\\\'','\\\\'DebugRx1Buffers\\\\'','\\\\'DebugRx2Buffe" "rs\\\\'','\\\\'DebugRx3Buffers\\\\'','\\\\'DebugRx4Buffers\\\\'','\\\\'MGC_AGC_SEL\\\\'','\\\\'RADIO1RXBUFF_RXEN" "\\\\'','\\\\'RADIO1TXBUFF_TXEN\\\\'','\\\\'RADIO2RXBUFF_RXEN\\\\'','\\\\'RADIO2TXBUFF_TXEN\\\\'','\\\\'RADIO3RXB" "UFF_RXEN\\\\'','\\\\'RADIO3TXBUFF_TXEN\\\\'','\\\\'RADIO4RXBUFF_RXEN\\\\'','\\\\'RADIO4TXBUFF_TXEN\\\\'','\\\\'R" "adio1AGCDoneRSSI\\\\'','\\\\'Radio2AGCDoneRSSI\\\\'','\\\\'Radio3AGCDoneRSSI\\\\'','\\\\'Radio4AGCDoneRSSI\\\\''" ",'\\\\'StartCapture\\\\'','\\\\'StartTx\\\\'','\\\\'StopTx\\\\'','\\\\'TransMode\\\\'','\\\\'TxDelay\\\\'','\\\\" "'TxLength\\\\'','\\\\'StartTxRx\\\\'','\\\\'RxBuff_Radio1\\\\'','\\\\'RxBuff_Radio2\\\\'','\\\\'RxBuff_Radio3\\\\" "'','\\\\'RxBuff_Radio4\\\\'','\\\\'TxBuff_Radio1\\\\'','\\\\'TxBuff_Radio2\\\\'','\\\\'TxBuff_Radio3\\\\'','\\\\" "'TxBuff_Radio4\\\\'','\\\\'RSSIBuff_Radio1\\\\'','\\\\'RSSIBuff_Radio2\\\\'','\\\\'RSSIBuff_Radio3\\\\'','\\\\'R" "SSIBuff_Radio4\\\\''],'mlstate'=>[0.00000000000000000,0.00000000000000000,0.00000000000000000,0.0000000000000000" "0,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000" "000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0." "00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.000000000000" "00000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.0000" "0000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.0000000000000000" "0,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000000000000,0.00000000" "000000000,0.00000000000000000]}|{'xmliface'=>'Xilinx//microblaze//iface.xml'}|off||default|0|55,59,383,441|edkpr" "ocessor|2.5|62,64,-1,-1,white,blue,0,07734,right|fprintf('','COMMENT: begin icon graphics');\npatch([0 62 62 0 ]" ",[0 0 64 64 ],[0.77 0.82 0.91]);\npatch([14 4 19 4 14 30 34 38 56 42 29 19 33 19 29 42 56 38 34 30 14 ],[8 18 33" " 48 58 58 54 58 58 44 57 47 33 19 9 22 8 8 12 8 8 ],[0.98 0.96 0.92]);\nplot([0 62 62 0 0 ],[0 0 64 64 0 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\nfprintf('','COMMENT: end icon " "text');\n|{'table'=>{'AvailableMemories'=>'popup()'}}|" System { Name "EDK Processor" Location [514, 91, 900, 269] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" SIDHighWatermark "136" Block { BlockType Constant Name "Constant" SID "6:83" Position [40, 565, 60, 585] ShowName off } Block { BlockType Constant Name "Constant1" SID "6:85" Position [40, 625, 60, 645] ShowName off } Block { BlockType Constant Name "Constant2" SID "6:87" Position [40, 680, 60, 700] ShowName off } Block { BlockType Constant Name "Constant3" SID "6:89" Position [40, 740, 60, 760] ShowName off } Block { BlockType Constant Name "Constant4" SID "6:91" Position [40, 800, 60, 820] ShowName off } Block { BlockType Reference Name "Constant5" SID "6:93" Ports [0, 1] Position [20, 492, 75, 518] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period on period "xlGetNormalizedPeriod()" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" sg_icon_stat "55,26,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 55 55 0 0 ],[0 0 26 26 0 ]);\npatch([20.325 24.66 27.66 30.66 33.66 27.66 23.325 20.325 ],[16.33 16.3" "3 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([23.325 27.66 24.66 20.325 23.325 ],[13.33 13.33 16.33 16" ".33 13.33 ],[0.931 0.946 0.973 ]);\npatch([20.325 24.66 27.66 23.325 20.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1" " 1 ]);\npatch([23.325 33.66 30.66 27.66 24.66 20.325 23.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946" " 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port" "_label('output',1,'0');\nfprintf('','COMMENT: end icon text');" Port { PortNumber 1 Name "Sl_wait" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Constant Name "Constant6" SID "6:94" Position [40, 915, 60, 935] ShowName off } Block { BlockType Reference Name "From Register" SID "6:97" Ports [0, 1] Position [260, 1467, 320, 1523] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/From Register" SourceType "Xilinx Shared Memory Based From Register Block" infoedit "Register block that reads data to a shared memory register. Delay of one sample period." shared_memory_name "'AGCDoneAddr'" init "0" period "xlGetNormalizedPeriod()" ownership "Owned and initialized elsewhere" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "14" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "fromreg" sg_icon_stat "60,56,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.91" " ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36.88 44.8" "8 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36.88 28.88 ]," "[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]);\npatch([20." "2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0.973 ]);\nfprintf(" "'','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'d" "out');\nfprintf('','COMMENT: end icon text');" Port { PortNumber 1 Name "AGCDoneAddr_dout" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "From Register1" SID "6:98" Ports [0, 1] Position [260, 1552, 320, 1608] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/From Register" SourceType "Xilinx Shared Memory Based From Register Block" infoedit "Register block that reads data to a shared memory register. Delay of one sample period." shared_memory_name "'CaptureDone'" init "0" period "xlGetNormalizedPeriod()" ownership "Owned and initialized elsewhere" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "fromreg" sg_icon_stat "60,56,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.91" " ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36.88 44.8" "8 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36.88 28.88 ]," "[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]);\npatch([20." "2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0.973 ]);\nfprintf(" "'','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'d" "out');\nfprintf('','COMMENT: end icon text');" Port { PortNumber 1 Name "CaptureDone_dout" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "From Register2" SID "6:99" Ports [0, 1] Position [260, 1637, 320, 1693] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/From Register" SourceType "Xilinx Shared Memory Based From Register Block" infoedit "Register block that reads data to a shared memory register. Delay of one sample period." shared_memory_name "'Radio1AGCDoneRSSI'" init "0" period "xlGetNormalizedPeriod()" ownership "Owned and initialized elsewhere" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "10" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "fromreg" sg_icon_stat "60,56,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.91" " ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36.88 44.8" "8 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36.88 28.88 ]," "[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]);\npatch([20." "2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0.973 ]);\nfprintf(" "'','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'d" "out');\nfprintf('','COMMENT: end icon text');" Port { PortNumber 1 Name "Radio1AGCDoneRSSI_dout" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "From Register3" SID "6:100" Ports [0, 1] Position [260, 1727, 320, 1783] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/From Register" SourceType "Xilinx Shared Memory Based From Register Block" infoedit "Register block that reads data to a shared memory register. Delay of one sample period." shared_memory_name "'Radio2AGCDoneRSSI'" init "0" period "xlGetNormalizedPeriod()" ownership "Owned and initialized elsewhere" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "10" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "fromreg" sg_icon_stat "60,56,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.91" " ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36.88 44.8" "8 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36.88 28.88 ]," "[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]);\npatch([20." "2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0.973 ]);\nfprintf(" "'','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'d" "out');\nfprintf('','COMMENT: end icon text');" Port { PortNumber 1 Name "Radio2AGCDoneRSSI_dout" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "From Register4" SID "6:101" Ports [0, 1] Position [260, 1812, 320, 1868] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/From Register" SourceType "Xilinx Shared Memory Based From Register Block" infoedit "Register block that reads data to a shared memory register. Delay of one sample period." shared_memory_name "'Radio3AGCDoneRSSI'" init "0" period "xlGetNormalizedPeriod()" ownership "Owned and initialized elsewhere" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "10" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "fromreg" sg_icon_stat "60,56,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.91" " ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36.88 44.8" "8 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36.88 28.88 ]," "[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]);\npatch([20." "2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0.973 ]);\nfprintf(" "'','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'d" "out');\nfprintf('','COMMENT: end icon text');" Port { PortNumber 1 Name "Radio3AGCDoneRSSI_dout" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "From Register5" SID "6:102" Ports [0, 1] Position [260, 1897, 320, 1953] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/From Register" SourceType "Xilinx Shared Memory Based From Register Block" infoedit "Register block that reads data to a shared memory register. Delay of one sample period." shared_memory_name "'Radio4AGCDoneRSSI'" init "0" period "xlGetNormalizedPeriod()" ownership "Owned and initialized elsewhere" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "10" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "fromreg" sg_icon_stat "60,56,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.91" " ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36.88 44.8" "8 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36.88 28.88 ]," "[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]);\npatch([20." "2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0.973 ]);\nfprintf(" "'','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'d" "out');\nfprintf('','COMMENT: end icon text');" Port { PortNumber 1 Name "Radio4AGCDoneRSSI_dout" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "PLB_ABus" SID "6:86" Ports [1, 1] Position [110, 625, 175, 645] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed point to Xilinx" " fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top level input p" "orts." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "xlGetNormalizedPeriod()" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off UseAsADC off ADCChannel "'1'" hdl_port "on" sginterface "{'Xilinx'=>{'jtaghwcosim'=>{'non_memory_mapped_port'=>'PLB_ABus'}},'iopad'=>{'constraint'=>'#'}}" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" "\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end ic" "on text');" Port { PortNumber 1 Name "PLB_ABus" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "PLB_PAValid" SID "6:88" Ports [1, 1] Position [110, 680, 175, 700] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed point to Xilinx" " fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top level input p" "orts." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "xlGetNormalizedPeriod()" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off UseAsADC off ADCChannel "'1'" hdl_port "on" sginterface "{'Xilinx'=>{'jtaghwcosim'=>{'non_memory_mapped_port'=>'PLB_PAValid'}},'iopad'=>{'constraint'=>'#'}}" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" "\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end ic" "on text');" Port { PortNumber 1 Name "PLB_PAValid" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "PLB_RNW" SID "6:90" Ports [1, 1] Position [110, 740, 175, 760] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed point to Xilinx" " fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top level input p" "orts." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "xlGetNormalizedPeriod()" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off UseAsADC off ADCChannel "'1'" hdl_port "on" sginterface "{'Xilinx'=>{'jtaghwcosim'=>{'non_memory_mapped_port'=>'PLB_RNW'}},'iopad'=>{'constraint'=>'#'}}" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" "\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end ic" "on text');" Port { PortNumber 1 Name "PLB_RNW" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "PLB_wrDBus" SID "6:92" Ports [1, 1] Position [110, 800, 175, 820] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed point to Xilinx" " fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top level input p" "orts." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "xlGetNormalizedPeriod()" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off UseAsADC off ADCChannel "'1'" hdl_port "on" sginterface "{'Xilinx'=>{'jtaghwcosim'=>{'non_memory_mapped_port'=>'PLB_wrDBus'}},'iopad'=>{'constraint'=>'#'}}" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" "\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end ic" "on text');" Port { PortNumber 1 Name "PLB_wrDBus" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "SPLB_Rst" SID "6:84" Ports [1, 1] Position [110, 565, 175, 585] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed point to Xilinx" " fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top level input p" "orts." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "xlGetNormalizedPeriod()" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off UseAsADC off ADCChannel "'1'" hdl_port "on" sginterface "{'Xilinx'=>{'jtaghwcosim'=>{'non_memory_mapped_port'=>'SPLB_Rst'}},'iopad'=>{'constraint'=>'#'}}" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" "\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end ic" "on text');" Port { PortNumber 1 Name "SPLB_Rst" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Shared Memory" SID "6:124" Ports [3, 1] Position [605, 2145, 685, 2235] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Shared Memory" SourceType "Xilinx Shared Memory Random Access Memory Block" shared_memory_name "'RxBuff_Radio1'" depth "16384" ownership "Owned and Initialized Elsewhere" initVector "sin(pi*(0:15)/16)" en off mutex "Unprotected" mode "Read and Write" write_mode "Read Before Write" time_out "0" latency "1" explicit_data_type off gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" xl_use_area off xl_area "[0,0,0,0,0,0,0]" implementation "Block RAM" use_rpm "off" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "shmem" sg_icon_stat "80,90,3,1,white,blue,0,bf435243,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 80 80 0 0 ],[0 0 90 90 0 ],[0.77 0.82 0.91" " ]);\nplot([0 80 80 0 0 ],[0 0 90 90 0 ]);\npatch([15.525 31.42 42.42 53.42 64.42 42.42 26.525 15.525 ],[57.21 57.2" "1 68.21 57.21 68.21 68.21 68.21 57.21 ],[1 1 1 ]);\npatch([26.525 42.42 31.42 15.525 26.525 ],[46.21 46.21 57.21 57" ".21 46.21 ],[0.931 0.946 0.973 ]);\npatch([15.525 31.42 42.42 26.525 15.525 ],[35.21 35.21 46.21 46.21 35.21 ],[1 1" " 1 ]);\npatch([26.525 64.42 53.42 42.42 31.42 15.525 26.525 ],[24.21 24.21 35.21 24.21 35.21 35.21 24.21 ],[0.931 0" ".946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');" "port_label('input',1,'addr');\ncolor('black');port_label('input',2,'din');\ncolor('black');port_label('input',3,'we" "');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');" Port { PortNumber 1 Name "RxBuff_Radio1_dout" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Shared Memory1" SID "6:125" Ports [3, 1] Position [605, 2269, 685, 2361] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Shared Memory" SourceType "Xilinx Shared Memory Random Access Memory Block" shared_memory_name "'RxBuff_Radio2'" depth "16384" ownership "Owned and Initialized Elsewhere" initVector "sin(pi*(0:15)/16)" en off mutex "Unprotected" mode "Read and Write" write_mode "Read Before Write" time_out "0" latency "1" explicit_data_type off gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" xl_use_area off xl_area "[0,0,0,0,0,0,0]" implementation "Block RAM" use_rpm "off" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "shmem" sg_icon_stat "80,92,3,1,white,blue,0,bf435243,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 80 80 0 0 ],[0 0 92 92 0 ],[0.77 0.82 0.91" " ]);\nplot([0 80 80 0 0 ],[0 0 92 92 0 ]);\npatch([15.525 31.42 42.42 53.42 64.42 42.42 26.525 15.525 ],[58.21 58.2" "1 69.21 58.21 69.21 69.21 69.21 58.21 ],[1 1 1 ]);\npatch([26.525 42.42 31.42 15.525 26.525 ],[47.21 47.21 58.21 58" ".21 47.21 ],[0.931 0.946 0.973 ]);\npatch([15.525 31.42 42.42 26.525 15.525 ],[36.21 36.21 47.21 47.21 36.21 ],[1 1" " 1 ]);\npatch([26.525 64.42 53.42 42.42 31.42 15.525 26.525 ],[25.21 25.21 36.21 25.21 36.21 36.21 25.21 ],[0.931 0" ".946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');" "port_label('input',1,'addr');\ncolor('black');port_label('input',2,'din');\ncolor('black');port_label('input',3,'we" "');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');" Port { PortNumber 1 Name "RxBuff_Radio2_dout" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Shared Memory10" SID "6:134" Ports [3, 1] Position [605, 3359, 685, 3451] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Shared Memory" SourceType "Xilinx Shared Memory Random Access Memory Block" shared_memory_name "'RSSIBuff_Radio3'" depth "2048" ownership "Owned and Initialized Elsewhere" initVector "sin(pi*(0:15)/16)" en off mutex "Unprotected" mode "Read and Write" write_mode "Read Before Write" time_out "0" latency "1" explicit_data_type off gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" xl_use_area off xl_area "[0,0,0,0,0,0,0]" implementation "Block RAM" use_rpm "off" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "shmem" sg_icon_stat "80,92,3,1,white,blue,0,bf435243,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 80 80 0 0 ],[0 0 92 92 0 ],[0.77 0.82 0.91" " ]);\nplot([0 80 80 0 0 ],[0 0 92 92 0 ]);\npatch([15.525 31.42 42.42 53.42 64.42 42.42 26.525 15.525 ],[58.21 58.2" "1 69.21 58.21 69.21 69.21 69.21 58.21 ],[1 1 1 ]);\npatch([26.525 42.42 31.42 15.525 26.525 ],[47.21 47.21 58.21 58" ".21 47.21 ],[0.931 0.946 0.973 ]);\npatch([15.525 31.42 42.42 26.525 15.525 ],[36.21 36.21 47.21 47.21 36.21 ],[1 1" " 1 ]);\npatch([26.525 64.42 53.42 42.42 31.42 15.525 26.525 ],[25.21 25.21 36.21 25.21 36.21 36.21 25.21 ],[0.931 0" ".946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');" "port_label('input',1,'addr');\ncolor('black');port_label('input',2,'din');\ncolor('black');port_label('input',3,'we" "');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');" Port { PortNumber 1 Name "RSSIBuff_Radio3_dout" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Shared Memory11" SID "6:135" Ports [3, 1] Position [605, 3479, 685, 3571] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Shared Memory" SourceType "Xilinx Shared Memory Random Access Memory Block" shared_memory_name "'RSSIBuff_Radio4'" depth "2048" ownership "Owned and Initialized Elsewhere" initVector "sin(pi*(0:15)/16)" en off mutex "Unprotected" mode "Read and Write" write_mode "Read Before Write" time_out "0" latency "1" explicit_data_type off gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" xl_use_area off xl_area "[0,0,0,0,0,0,0]" implementation "Block RAM" use_rpm "off" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "shmem" sg_icon_stat "80,92,3,1,white,blue,0,bf435243,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 80 80 0 0 ],[0 0 92 92 0 ],[0.77 0.82 0.91" " ]);\nplot([0 80 80 0 0 ],[0 0 92 92 0 ]);\npatch([15.525 31.42 42.42 53.42 64.42 42.42 26.525 15.525 ],[58.21 58.2" "1 69.21 58.21 69.21 69.21 69.21 58.21 ],[1 1 1 ]);\npatch([26.525 42.42 31.42 15.525 26.525 ],[47.21 47.21 58.21 58" ".21 47.21 ],[0.931 0.946 0.973 ]);\npatch([15.525 31.42 42.42 26.525 15.525 ],[36.21 36.21 47.21 47.21 36.21 ],[1 1" " 1 ]);\npatch([26.525 64.42 53.42 42.42 31.42 15.525 26.525 ],[25.21 25.21 36.21 25.21 36.21 36.21 25.21 ],[0.931 0" ".946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');" "port_label('input',1,'addr');\ncolor('black');port_label('input',2,'din');\ncolor('black');port_label('input',3,'we" "');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');" Port { PortNumber 1 Name "RSSIBuff_Radio4_dout" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Shared Memory2" SID "6:126" Ports [3, 1] Position [605, 2389, 685, 2481] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Shared Memory" SourceType "Xilinx Shared Memory Random Access Memory Block" shared_memory_name "'RxBuff_Radio3'" depth "16384" ownership "Owned and Initialized Elsewhere" initVector "sin(pi*(0:15)/16)" en off mutex "Unprotected" mode "Read and Write" write_mode "Read Before Write" time_out "0" latency "1" explicit_data_type off gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" xl_use_area off xl_area "[0,0,0,0,0,0,0]" implementation "Block RAM" use_rpm "off" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "shmem" sg_icon_stat "80,92,3,1,white,blue,0,bf435243,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 80 80 0 0 ],[0 0 92 92 0 ],[0.77 0.82 0.91" " ]);\nplot([0 80 80 0 0 ],[0 0 92 92 0 ]);\npatch([15.525 31.42 42.42 53.42 64.42 42.42 26.525 15.525 ],[58.21 58.2" "1 69.21 58.21 69.21 69.21 69.21 58.21 ],[1 1 1 ]);\npatch([26.525 42.42 31.42 15.525 26.525 ],[47.21 47.21 58.21 58" ".21 47.21 ],[0.931 0.946 0.973 ]);\npatch([15.525 31.42 42.42 26.525 15.525 ],[36.21 36.21 47.21 47.21 36.21 ],[1 1" " 1 ]);\npatch([26.525 64.42 53.42 42.42 31.42 15.525 26.525 ],[25.21 25.21 36.21 25.21 36.21 36.21 25.21 ],[0.931 0" ".946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');" "port_label('input',1,'addr');\ncolor('black');port_label('input',2,'din');\ncolor('black');port_label('input',3,'we" "');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');" Port { PortNumber 1 Name "RxBuff_Radio3_dout" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Shared Memory3" SID "6:127" Ports [3, 1] Position [605, 2510, 685, 2600] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Shared Memory" SourceType "Xilinx Shared Memory Random Access Memory Block" shared_memory_name "'RxBuff_Radio4'" depth "16384" ownership "Owned and Initialized Elsewhere" initVector "sin(pi*(0:15)/16)" en off mutex "Unprotected" mode "Read and Write" write_mode "Read Before Write" time_out "0" latency "1" explicit_data_type off gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" xl_use_area off xl_area "[0,0,0,0,0,0,0]" implementation "Block RAM" use_rpm "off" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "shmem" sg_icon_stat "80,90,3,1,white,blue,0,bf435243,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 80 80 0 0 ],[0 0 90 90 0 ],[0.77 0.82 0.91" " ]);\nplot([0 80 80 0 0 ],[0 0 90 90 0 ]);\npatch([15.525 31.42 42.42 53.42 64.42 42.42 26.525 15.525 ],[57.21 57.2" "1 68.21 57.21 68.21 68.21 68.21 57.21 ],[1 1 1 ]);\npatch([26.525 42.42 31.42 15.525 26.525 ],[46.21 46.21 57.21 57" ".21 46.21 ],[0.931 0.946 0.973 ]);\npatch([15.525 31.42 42.42 26.525 15.525 ],[35.21 35.21 46.21 46.21 35.21 ],[1 1" " 1 ]);\npatch([26.525 64.42 53.42 42.42 31.42 15.525 26.525 ],[24.21 24.21 35.21 24.21 35.21 35.21 24.21 ],[0.931 0" ".946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');" "port_label('input',1,'addr');\ncolor('black');port_label('input',2,'din');\ncolor('black');port_label('input',3,'we" "');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');" Port { PortNumber 1 Name "RxBuff_Radio4_dout" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Shared Memory4" SID "6:128" Ports [3, 1] Position [605, 2634, 685, 2726] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Shared Memory" SourceType "Xilinx Shared Memory Random Access Memory Block" shared_memory_name "'TxBuff_Radio1'" depth "16384" ownership "Owned and Initialized Elsewhere" initVector "sin(pi*(0:15)/16)" en off mutex "Unprotected" mode "Read and Write" write_mode "Read Before Write" time_out "0" latency "1" explicit_data_type off gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" xl_use_area off xl_area "[0,0,0,0,0,0,0]" implementation "Block RAM" use_rpm "off" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "shmem" sg_icon_stat "80,92,3,1,white,blue,0,bf435243,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 80 80 0 0 ],[0 0 92 92 0 ],[0.77 0.82 0.91" " ]);\nplot([0 80 80 0 0 ],[0 0 92 92 0 ]);\npatch([15.525 31.42 42.42 53.42 64.42 42.42 26.525 15.525 ],[58.21 58.2" "1 69.21 58.21 69.21 69.21 69.21 58.21 ],[1 1 1 ]);\npatch([26.525 42.42 31.42 15.525 26.525 ],[47.21 47.21 58.21 58" ".21 47.21 ],[0.931 0.946 0.973 ]);\npatch([15.525 31.42 42.42 26.525 15.525 ],[36.21 36.21 47.21 47.21 36.21 ],[1 1" " 1 ]);\npatch([26.525 64.42 53.42 42.42 31.42 15.525 26.525 ],[25.21 25.21 36.21 25.21 36.21 36.21 25.21 ],[0.931 0" ".946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');" "port_label('input',1,'addr');\ncolor('black');port_label('input',2,'din');\ncolor('black');port_label('input',3,'we" "');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');" Port { PortNumber 1 Name "TxBuff_Radio1_dout" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Shared Memory5" SID "6:129" Ports [3, 1] Position [605, 2754, 685, 2846] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Shared Memory" SourceType "Xilinx Shared Memory Random Access Memory Block" shared_memory_name "'TxBuff_Radio2'" depth "16384" ownership "Owned and Initialized Elsewhere" initVector "sin(pi*(0:15)/16)" en off mutex "Unprotected" mode "Read and Write" write_mode "Read Before Write" time_out "0" latency "1" explicit_data_type off gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" xl_use_area off xl_area "[0,0,0,0,0,0,0]" implementation "Block RAM" use_rpm "off" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "shmem" sg_icon_stat "80,92,3,1,white,blue,0,bf435243,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 80 80 0 0 ],[0 0 92 92 0 ],[0.77 0.82 0.91" " ]);\nplot([0 80 80 0 0 ],[0 0 92 92 0 ]);\npatch([15.525 31.42 42.42 53.42 64.42 42.42 26.525 15.525 ],[58.21 58.2" "1 69.21 58.21 69.21 69.21 69.21 58.21 ],[1 1 1 ]);\npatch([26.525 42.42 31.42 15.525 26.525 ],[47.21 47.21 58.21 58" ".21 47.21 ],[0.931 0.946 0.973 ]);\npatch([15.525 31.42 42.42 26.525 15.525 ],[36.21 36.21 47.21 47.21 36.21 ],[1 1" " 1 ]);\npatch([26.525 64.42 53.42 42.42 31.42 15.525 26.525 ],[25.21 25.21 36.21 25.21 36.21 36.21 25.21 ],[0.931 0" ".946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');" "port_label('input',1,'addr');\ncolor('black');port_label('input',2,'din');\ncolor('black');port_label('input',3,'we" "');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');" Port { PortNumber 1 Name "TxBuff_Radio2_dout" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Shared Memory6" SID "6:130" Ports [3, 1] Position [605, 2875, 685, 2965] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Shared Memory" SourceType "Xilinx Shared Memory Random Access Memory Block" shared_memory_name "'TxBuff_Radio3'" depth "16384" ownership "Owned and Initialized Elsewhere" initVector "sin(pi*(0:15)/16)" en off mutex "Unprotected" mode "Read and Write" write_mode "Read Before Write" time_out "0" latency "1" explicit_data_type off gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" xl_use_area off xl_area "[0,0,0,0,0,0,0]" implementation "Block RAM" use_rpm "off" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "shmem" sg_icon_stat "80,90,3,1,white,blue,0,bf435243,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 80 80 0 0 ],[0 0 90 90 0 ],[0.77 0.82 0.91" " ]);\nplot([0 80 80 0 0 ],[0 0 90 90 0 ]);\npatch([15.525 31.42 42.42 53.42 64.42 42.42 26.525 15.525 ],[57.21 57.2" "1 68.21 57.21 68.21 68.21 68.21 57.21 ],[1 1 1 ]);\npatch([26.525 42.42 31.42 15.525 26.525 ],[46.21 46.21 57.21 57" ".21 46.21 ],[0.931 0.946 0.973 ]);\npatch([15.525 31.42 42.42 26.525 15.525 ],[35.21 35.21 46.21 46.21 35.21 ],[1 1" " 1 ]);\npatch([26.525 64.42 53.42 42.42 31.42 15.525 26.525 ],[24.21 24.21 35.21 24.21 35.21 35.21 24.21 ],[0.931 0" ".946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');" "port_label('input',1,'addr');\ncolor('black');port_label('input',2,'din');\ncolor('black');port_label('input',3,'we" "');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');" Port { PortNumber 1 Name "TxBuff_Radio3_dout" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Shared Memory7" SID "6:131" Ports [3, 1] Position [605, 2994, 685, 3086] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Shared Memory" SourceType "Xilinx Shared Memory Random Access Memory Block" shared_memory_name "'TxBuff_Radio4'" depth "16384" ownership "Owned and Initialized Elsewhere" initVector "sin(pi*(0:15)/16)" en off mutex "Unprotected" mode "Read and Write" write_mode "Read Before Write" time_out "0" latency "1" explicit_data_type off gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" xl_use_area off xl_area "[0,0,0,0,0,0,0]" implementation "Block RAM" use_rpm "off" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "shmem" sg_icon_stat "80,92,3,1,white,blue,0,bf435243,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 80 80 0 0 ],[0 0 92 92 0 ],[0.77 0.82 0.91" " ]);\nplot([0 80 80 0 0 ],[0 0 92 92 0 ]);\npatch([15.525 31.42 42.42 53.42 64.42 42.42 26.525 15.525 ],[58.21 58.2" "1 69.21 58.21 69.21 69.21 69.21 58.21 ],[1 1 1 ]);\npatch([26.525 42.42 31.42 15.525 26.525 ],[47.21 47.21 58.21 58" ".21 47.21 ],[0.931 0.946 0.973 ]);\npatch([15.525 31.42 42.42 26.525 15.525 ],[36.21 36.21 47.21 47.21 36.21 ],[1 1" " 1 ]);\npatch([26.525 64.42 53.42 42.42 31.42 15.525 26.525 ],[25.21 25.21 36.21 25.21 36.21 36.21 25.21 ],[0.931 0" ".946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');" "port_label('input',1,'addr');\ncolor('black');port_label('input',2,'din');\ncolor('black');port_label('input',3,'we" "');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');" Port { PortNumber 1 Name "TxBuff_Radio4_dout" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Shared Memory8" SID "6:132" Ports [3, 1] Position [605, 3119, 685, 3211] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Shared Memory" SourceType "Xilinx Shared Memory Random Access Memory Block" shared_memory_name "'RSSIBuff_Radio1'" depth "2048" ownership "Owned and Initialized Elsewhere" initVector "sin(pi*(0:15)/16)" en off mutex "Unprotected" mode "Read and Write" write_mode "Read Before Write" time_out "0" latency "1" explicit_data_type off gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" xl_use_area off xl_area "[0,0,0,0,0,0,0]" implementation "Block RAM" use_rpm "off" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "shmem" sg_icon_stat "80,92,3,1,white,blue,0,bf435243,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 80 80 0 0 ],[0 0 92 92 0 ],[0.77 0.82 0.91" " ]);\nplot([0 80 80 0 0 ],[0 0 92 92 0 ]);\npatch([15.525 31.42 42.42 53.42 64.42 42.42 26.525 15.525 ],[58.21 58.2" "1 69.21 58.21 69.21 69.21 69.21 58.21 ],[1 1 1 ]);\npatch([26.525 42.42 31.42 15.525 26.525 ],[47.21 47.21 58.21 58" ".21 47.21 ],[0.931 0.946 0.973 ]);\npatch([15.525 31.42 42.42 26.525 15.525 ],[36.21 36.21 47.21 47.21 36.21 ],[1 1" " 1 ]);\npatch([26.525 64.42 53.42 42.42 31.42 15.525 26.525 ],[25.21 25.21 36.21 25.21 36.21 36.21 25.21 ],[0.931 0" ".946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');" "port_label('input',1,'addr');\ncolor('black');port_label('input',2,'din');\ncolor('black');port_label('input',3,'we" "');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');" Port { PortNumber 1 Name "RSSIBuff_Radio1_dout" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Shared Memory9" SID "6:133" Ports [3, 1] Position [605, 3240, 685, 3330] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Shared Memory" SourceType "Xilinx Shared Memory Random Access Memory Block" shared_memory_name "'RSSIBuff_Radio2'" depth "2048" ownership "Owned and Initialized Elsewhere" initVector "sin(pi*(0:15)/16)" en off mutex "Unprotected" mode "Read and Write" write_mode "Read Before Write" time_out "0" latency "1" explicit_data_type off gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" xl_use_area off xl_area "[0,0,0,0,0,0,0]" implementation "Block RAM" use_rpm "off" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "shmem" sg_icon_stat "80,90,3,1,white,blue,0,bf435243,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 80 80 0 0 ],[0 0 90 90 0 ],[0.77 0.82 0.91" " ]);\nplot([0 80 80 0 0 ],[0 0 90 90 0 ]);\npatch([15.525 31.42 42.42 53.42 64.42 42.42 26.525 15.525 ],[57.21 57.2" "1 68.21 57.21 68.21 68.21 68.21 57.21 ],[1 1 1 ]);\npatch([26.525 42.42 31.42 15.525 26.525 ],[46.21 46.21 57.21 57" ".21 46.21 ],[0.931 0.946 0.973 ]);\npatch([15.525 31.42 42.42 26.525 15.525 ],[35.21 35.21 46.21 46.21 35.21 ],[1 1" " 1 ]);\npatch([26.525 64.42 53.42 42.42 31.42 15.525 26.525 ],[24.21 24.21 35.21 24.21 35.21 35.21 24.21 ],[0.931 0" ".946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');" "port_label('input',1,'addr');\ncolor('black');port_label('input',2,'din');\ncolor('black');port_label('input',3,'we" "');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');" Port { PortNumber 1 Name "RSSIBuff_Radio2_dout" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Sl_addrAck" SID "6:70" Ports [1, 1] Position [460, 100, 520, 120] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" UseAsDAC off DACChannel "'1'" sginterface "{'Xilinx'=>{'jtaghwcosim'=>{'non_memory_mapped_port'=>'Sl_addrAck'}},'iopad'=>{'constraint'=>'#'}}" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" " ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "Sl_rdComp" SID "6:72" Ports [1, 1] Position [460, 210, 520, 230] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" UseAsDAC off DACChannel "'1'" sginterface "{'Xilinx'=>{'jtaghwcosim'=>{'non_memory_mapped_port'=>'Sl_rdComp'}},'iopad'=>{'constraint'=>'#'}}" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" " ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "Sl_rdDAck" SID "6:74" Ports [1, 1] Position [460, 755, 520, 775] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" UseAsDAC off DACChannel "'1'" sginterface "{'Xilinx'=>{'jtaghwcosim'=>{'non_memory_mapped_port'=>'Sl_rdDAck'}},'iopad'=>{'constraint'=>'#'}}" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" " ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "Sl_rdDBus" SID "6:76" Ports [1, 1] Position [460, 840, 520, 860] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" UseAsDAC off DACChannel "'1'" sginterface "{'Xilinx'=>{'jtaghwcosim'=>{'non_memory_mapped_port'=>'Sl_rdDBus'}},'iopad'=>{'constraint'=>'#'}}" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" " ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "Sl_wait" SID "6:78" Ports [1, 1] Position [110, 495, 170, 515] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" UseAsDAC off DACChannel "'1'" sginterface "{'Xilinx'=>{'jtaghwcosim'=>{'non_memory_mapped_port'=>'Sl_wait'}},'iopad'=>{'constraint'=>'#'}}" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" " ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "Sl_wrComp" SID "6:82" Ports [1, 1] Position [460, 665, 520, 685] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" UseAsDAC off DACChannel "'1'" sginterface "{'Xilinx'=>{'jtaghwcosim'=>{'non_memory_mapped_port'=>'Sl_wrComp'}},'iopad'=>{'constraint'=>'#'}}" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" " ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Reference Name "Sl_wrDAck" SID "6:80" Ports [1, 1] Position [460, 380, 520, 400] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed-point or floating-point type inputs into ouputs of type Simu" "link integer, single, double, or fixed point.

Hardware notes: In hardware these blocks become top level out" "put ports or are discarded, depending on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" UseAsDAC off DACChannel "'1'" sginterface "{'Xilinx'=>{'jtaghwcosim'=>{'non_memory_mapped_port'=>'Sl_wrDAck'}},'iopad'=>{'constraint'=>'#'}}" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" sg_icon_stat "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" " ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','COMMENT: end i" "con text');" } Block { BlockType Terminator Name "Terminator" SID "6:69" Position [635, 30, 655, 50] ShowName off } Block { BlockType Terminator Name "Terminator1" SID "6:71" Position [635, 80, 655, 100] ShowName off } Block { BlockType Terminator Name "Terminator2" SID "6:73" Position [635, 225, 655, 245] ShowName off } Block { BlockType Terminator Name "Terminator3" SID "6:75" Position [635, 275, 655, 295] ShowName off } Block { BlockType Terminator Name "Terminator4" SID "6:77" Position [280, 495, 300, 515] ShowName off } Block { BlockType Terminator Name "Terminator5" SID "6:79" Position [635, 130, 655, 150] ShowName off } Block { BlockType Terminator Name "Terminator6" SID "6:81" Position [635, 180, 655, 200] ShowName off } Block { BlockType Reference Name "To Register" SID "6:103" Ports [2, 1] Position [615, 327, 675, 383] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/To Register" SourceType "Xilinx Shared Memory Based To Register Block" infoedit "Register block that writes data to a shared memory register. Delay of one sample period." shared_memory_name "'DCO_EN_SEL'" init "0" ownership "Owned and initialized elsewhere" explicit_data_type on gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "toreg" sg_icon_stat "60,56,2,1,white,blue,0,10ab453e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.91" " ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36.88 44.8" "8 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36.88 28.88 ]," "[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]);\npatch([20." "2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0.973 ]);\nfprintf(" "'','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'di" "n');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMEN" "T: end icon text');" Port { PortNumber 1 Name "DCO_EN_SEL_dout" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "To Register1" SID "6:104" Ports [2, 1] Position [615, 412, 675, 468] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/To Register" SourceType "Xilinx Shared Memory Based To Register Block" infoedit "Register block that writes data to a shared memory register. Delay of one sample period." shared_memory_name "'DebugRx1Buffers'" init "0" ownership "Owned and initialized elsewhere" explicit_data_type on gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "toreg" sg_icon_stat "60,56,2,1,white,blue,0,10ab453e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.91" " ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36.88 44.8" "8 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36.88 28.88 ]," "[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]);\npatch([20." "2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0.973 ]);\nfprintf(" "'','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'di" "n');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMEN" "T: end icon text');" Port { PortNumber 1 Name "DebugRx1Buffers_dout" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "To Register10" SID "6:113" Ports [2, 1] Position [615, 1192, 675, 1248] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/To Register" SourceType "Xilinx Shared Memory Based To Register Block" infoedit "Register block that writes data to a shared memory register. Delay of one sample period." shared_memory_name "'RADIO3RXBUFF_RXEN'" init "0" ownership "Owned and initialized elsewhere" explicit_data_type on gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "toreg" sg_icon_stat "60,56,2,1,white,blue,0,10ab453e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.91" " ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36.88 44.8" "8 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36.88 28.88 ]," "[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]);\npatch([20." "2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0.973 ]);\nfprintf(" "'','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'di" "n');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMEN" "T: end icon text');" Port { PortNumber 1 Name "RADIO3RXBUFF_RXEN_dout" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "To Register11" SID "6:114" Ports [2, 1] Position [615, 1282, 675, 1338] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/To Register" SourceType "Xilinx Shared Memory Based To Register Block" infoedit "Register block that writes data to a shared memory register. Delay of one sample period." shared_memory_name "'RADIO3TXBUFF_TXEN'" init "0" ownership "Owned and initialized elsewhere" explicit_data_type on gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "toreg" sg_icon_stat "60,56,2,1,white,blue,0,10ab453e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.91" " ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36.88 44.8" "8 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36.88 28.88 ]," "[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]);\npatch([20." "2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0.973 ]);\nfprintf(" "'','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'di" "n');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMEN" "T: end icon text');" Port { PortNumber 1 Name "RADIO3TXBUFF_TXEN_dout" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "To Register12" SID "6:115" Ports [2, 1] Position [615, 1367, 675, 1423] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/To Register" SourceType "Xilinx Shared Memory Based To Register Block" infoedit "Register block that writes data to a shared memory register. Delay of one sample period." shared_memory_name "'RADIO4RXBUFF_RXEN'" init "0" ownership "Owned and initialized elsewhere" explicit_data_type on gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "toreg" sg_icon_stat "60,56,2,1,white,blue,0,10ab453e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.91" " ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36.88 44.8" "8 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36.88 28.88 ]," "[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]);\npatch([20." "2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0.973 ]);\nfprintf(" "'','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'di" "n');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMEN" "T: end icon text');" Port { PortNumber 1 Name "RADIO4RXBUFF_RXEN_dout" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "To Register13" SID "6:116" Ports [2, 1] Position [615, 1452, 675, 1508] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/To Register" SourceType "Xilinx Shared Memory Based To Register Block" infoedit "Register block that writes data to a shared memory register. Delay of one sample period." shared_memory_name "'RADIO4TXBUFF_TXEN'" init "0" ownership "Owned and initialized elsewhere" explicit_data_type on gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "toreg" sg_icon_stat "60,56,2,1,white,blue,0,10ab453e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.91" " ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36.88 44.8" "8 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36.88 28.88 ]," "[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]);\npatch([20." "2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0.973 ]);\nfprintf(" "'','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'di" "n');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMEN" "T: end icon text');" Port { PortNumber 1 Name "RADIO4TXBUFF_TXEN_dout" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "To Register14" SID "6:117" Ports [2, 1] Position [615, 1542, 675, 1598] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/To Register" SourceType "Xilinx Shared Memory Based To Register Block" infoedit "Register block that writes data to a shared memory register. Delay of one sample period." shared_memory_name "'StartCapture'" init "0" ownership "Owned and initialized elsewhere" explicit_data_type on gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "toreg" sg_icon_stat "60,56,2,1,white,blue,0,10ab453e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.91" " ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36.88 44.8" "8 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36.88 28.88 ]," "[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]);\npatch([20." "2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0.973 ]);\nfprintf(" "'','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'di" "n');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMEN" "T: end icon text');" Port { PortNumber 1 Name "StartCapture_dout" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "To Register15" SID "6:118" Ports [2, 1] Position [615, 1627, 675, 1683] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/To Register" SourceType "Xilinx Shared Memory Based To Register Block" infoedit "Register block that writes data to a shared memory register. Delay of one sample period." shared_memory_name "'StartTx'" init "0" ownership "Owned and initialized elsewhere" explicit_data_type on gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "toreg" sg_icon_stat "60,56,2,1,white,blue,0,10ab453e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.91" " ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36.88 44.8" "8 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36.88 28.88 ]," "[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]);\npatch([20." "2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0.973 ]);\nfprintf(" "'','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'di" "n');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMEN" "T: end icon text');" Port { PortNumber 1 Name "StartTx_dout" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "To Register16" SID "6:119" Ports [2, 1] Position [615, 1712, 675, 1768] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/To Register" SourceType "Xilinx Shared Memory Based To Register Block" infoedit "Register block that writes data to a shared memory register. Delay of one sample period." shared_memory_name "'StopTx'" init "0" ownership "Owned and initialized elsewhere" explicit_data_type on gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "toreg" sg_icon_stat "60,56,2,1,white,blue,0,10ab453e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.91" " ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36.88 44.8" "8 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36.88 28.88 ]," "[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]);\npatch([20." "2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0.973 ]);\nfprintf(" "'','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'di" "n');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMEN" "T: end icon text');" Port { PortNumber 1 Name "StopTx_dout" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "To Register17" SID "6:120" Ports [2, 1] Position [615, 1802, 675, 1858] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/To Register" SourceType "Xilinx Shared Memory Based To Register Block" infoedit "Register block that writes data to a shared memory register. Delay of one sample period." shared_memory_name "'TransMode'" init "0" ownership "Owned and initialized elsewhere" explicit_data_type on gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "toreg" sg_icon_stat "60,56,2,1,white,blue,0,10ab453e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.91" " ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36.88 44.8" "8 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36.88 28.88 ]," "[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]);\npatch([20." "2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0.973 ]);\nfprintf(" "'','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'di" "n');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMEN" "T: end icon text');" Port { PortNumber 1 Name "TransMode_dout" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "To Register18" SID "6:121" Ports [2, 1] Position [615, 1887, 675, 1943] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/To Register" SourceType "Xilinx Shared Memory Based To Register Block" infoedit "Register block that writes data to a shared memory register. Delay of one sample period." shared_memory_name "'TxDelay'" init "0" ownership "Owned and initialized elsewhere" explicit_data_type on gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "14" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "toreg" sg_icon_stat "60,56,2,1,white,blue,0,10ab453e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.91" " ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36.88 44.8" "8 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36.88 28.88 ]," "[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]);\npatch([20." "2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0.973 ]);\nfprintf(" "'','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'di" "n');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMEN" "T: end icon text');" Port { PortNumber 1 Name "TxDelay_dout" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "To Register19" SID "6:122" Ports [2, 1] Position [615, 1972, 675, 2028] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/To Register" SourceType "Xilinx Shared Memory Based To Register Block" infoedit "Register block that writes data to a shared memory register. Delay of one sample period." shared_memory_name "'TxLength'" init "0" ownership "Owned and initialized elsewhere" explicit_data_type on gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "14" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "toreg" sg_icon_stat "60,56,2,1,white,blue,0,10ab453e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.91" " ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36.88 44.8" "8 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36.88 28.88 ]," "[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]);\npatch([20." "2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0.973 ]);\nfprintf(" "'','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'di" "n');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMEN" "T: end icon text');" Port { PortNumber 1 Name "TxLength_dout" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "To Register2" SID "6:105" Ports [2, 1] Position [615, 502, 675, 558] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/To Register" SourceType "Xilinx Shared Memory Based To Register Block" infoedit "Register block that writes data to a shared memory register. Delay of one sample period." shared_memory_name "'DebugRx2Buffers'" init "0" ownership "Owned and initialized elsewhere" explicit_data_type on gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "toreg" sg_icon_stat "60,56,2,1,white,blue,0,10ab453e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.91" " ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36.88 44.8" "8 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36.88 28.88 ]," "[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]);\npatch([20." "2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0.973 ]);\nfprintf(" "'','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'di" "n');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMEN" "T: end icon text');" Port { PortNumber 1 Name "DebugRx2Buffers_dout" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "To Register20" SID "6:123" Ports [2, 1] Position [615, 2062, 675, 2118] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/To Register" SourceType "Xilinx Shared Memory Based To Register Block" infoedit "Register block that writes data to a shared memory register. Delay of one sample period." shared_memory_name "'StartTxRx'" init "0" ownership "Owned and initialized elsewhere" explicit_data_type on gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "toreg" sg_icon_stat "60,56,2,1,white,blue,0,10ab453e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.91" " ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36.88 44.8" "8 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36.88 28.88 ]," "[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]);\npatch([20." "2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0.973 ]);\nfprintf(" "'','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'di" "n');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMEN" "T: end icon text');" Port { PortNumber 1 Name "StartTxRx_dout" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "To Register3" SID "6:106" Ports [2, 1] Position [615, 587, 675, 643] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/To Register" SourceType "Xilinx Shared Memory Based To Register Block" infoedit "Register block that writes data to a shared memory register. Delay of one sample period." shared_memory_name "'DebugRx3Buffers'" init "0" ownership "Owned and initialized elsewhere" explicit_data_type on gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "toreg" sg_icon_stat "60,56,2,1,white,blue,0,10ab453e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.91" " ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36.88 44.8" "8 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36.88 28.88 ]," "[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]);\npatch([20." "2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0.973 ]);\nfprintf(" "'','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'di" "n');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMEN" "T: end icon text');" Port { PortNumber 1 Name "DebugRx3Buffers_dout" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "To Register4" SID "6:107" Ports [2, 1] Position [615, 672, 675, 728] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/To Register" SourceType "Xilinx Shared Memory Based To Register Block" infoedit "Register block that writes data to a shared memory register. Delay of one sample period." shared_memory_name "'DebugRx4Buffers'" init "0" ownership "Owned and initialized elsewhere" explicit_data_type on gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "toreg" sg_icon_stat "60,56,2,1,white,blue,0,10ab453e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.91" " ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36.88 44.8" "8 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36.88 28.88 ]," "[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]);\npatch([20." "2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0.973 ]);\nfprintf(" "'','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'di" "n');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMEN" "T: end icon text');" Port { PortNumber 1 Name "DebugRx4Buffers_dout" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "To Register5" SID "6:108" Ports [2, 1] Position [615, 762, 675, 818] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/To Register" SourceType "Xilinx Shared Memory Based To Register Block" infoedit "Register block that writes data to a shared memory register. Delay of one sample period." shared_memory_name "'MGC_AGC_SEL'" init "0" ownership "Owned and initialized elsewhere" explicit_data_type on gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "toreg" sg_icon_stat "60,56,2,1,white,blue,0,10ab453e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.91" " ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36.88 44.8" "8 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36.88 28.88 ]," "[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]);\npatch([20." "2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0.973 ]);\nfprintf(" "'','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'di" "n');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMEN" "T: end icon text');" Port { PortNumber 1 Name "MGC_AGC_SEL_dout" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "To Register6" SID "6:109" Ports [2, 1] Position [615, 847, 675, 903] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/To Register" SourceType "Xilinx Shared Memory Based To Register Block" infoedit "Register block that writes data to a shared memory register. Delay of one sample period." shared_memory_name "'RADIO1RXBUFF_RXEN'" init "0" ownership "Owned and initialized elsewhere" explicit_data_type on gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "toreg" sg_icon_stat "60,56,2,1,white,blue,0,10ab453e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.91" " ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36.88 44.8" "8 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36.88 28.88 ]," "[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]);\npatch([20." "2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0.973 ]);\nfprintf(" "'','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'di" "n');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMEN" "T: end icon text');" Port { PortNumber 1 Name "RADIO1RXBUFF_RXEN_dout" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "To Register7" SID "6:110" Ports [2, 1] Position [615, 932, 675, 988] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/To Register" SourceType "Xilinx Shared Memory Based To Register Block" infoedit "Register block that writes data to a shared memory register. Delay of one sample period." shared_memory_name "'RADIO1TXBUFF_TXEN'" init "0" ownership "Owned and initialized elsewhere" explicit_data_type on gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "toreg" sg_icon_stat "60,56,2,1,white,blue,0,10ab453e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.91" " ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36.88 44.8" "8 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36.88 28.88 ]," "[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]);\npatch([20." "2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0.973 ]);\nfprintf(" "'','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'di" "n');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMEN" "T: end icon text');" Port { PortNumber 1 Name "RADIO1TXBUFF_TXEN_dout" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "To Register8" SID "6:111" Ports [2, 1] Position [615, 1022, 675, 1078] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/To Register" SourceType "Xilinx Shared Memory Based To Register Block" infoedit "Register block that writes data to a shared memory register. Delay of one sample period." shared_memory_name "'RADIO2RXBUFF_RXEN'" init "0" ownership "Owned and initialized elsewhere" explicit_data_type on gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "toreg" sg_icon_stat "60,56,2,1,white,blue,0,10ab453e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.91" " ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36.88 44.8" "8 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36.88 28.88 ]," "[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]);\npatch([20." "2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0.973 ]);\nfprintf(" "'','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'di" "n');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMEN" "T: end icon text');" Port { PortNumber 1 Name "RADIO2RXBUFF_RXEN_dout" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "To Register9" SID "6:112" Ports [2, 1] Position [615, 1107, 675, 1163] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/To Register" SourceType "Xilinx Shared Memory Based To Register Block" infoedit "Register block that writes data to a shared memory register. Delay of one sample period." shared_memory_name "'RADIO2TXBUFF_TXEN'" init "0" ownership "Owned and initialized elsewhere" explicit_data_type on gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "toreg" sg_icon_stat "60,56,2,1,white,blue,0,10ab453e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.91" " ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36.88 44.8" "8 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36.88 28.88 ]," "[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]);\npatch([20." "2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0.973 ]);\nfprintf(" "'','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'di" "n');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMEN" "T: end icon text');" Port { PortNumber 1 Name "RADIO2TXBUFF_TXEN_dout" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "plb_decode" SID "6:96" Ports [7, 9] Position [205, 544, 375, 956] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/MCode" SourceType "Xilinx MCode Block Block" infoedit "Pass input values to a MATLAB function for evaluation in Xilinx fixed-point type. The input ports of t" "he block are input arguments of the function. The output ports of the block are output arguments of the function." mfname "xlmax" explicit_period off period "1" dbl_ovrd off enable_stdout off enable_debug off xl_use_area off xl_area "[0,0,0,0,0,0,0]" mfilecontent "function [wrDBusReg, addrAck, rdComp, wrDAck, bankAddr, RNWReg, rdDAck, rdDBus, linearAddr] = plb_" "bus_decode(plbRst, plbABus, plbPAValid, plbRNW, plbWrDBus, rdData, addrPref)\n\n% constant variables (TODO: should " "pass from outside)\nADDRPREF_LEN = 10;\nBANKADDR_LEN = 2;\nLINEARADDR_LEN = 18;\nABUS_LEN = 32;\nDBUS_LEN = 32;\n\n" "% declare and initialize persistent variables\n% register input bus signals\npersistent plbRstReg_, plbRstReg_ = xl" "_state(0, {xlBoolean});\npersistent plbABusReg_, plbABusReg_ = xl_state(0, {xlUnsigned, ABUS_LEN, 0});\npersistent " "plbPAValidReg_, plbPAValidReg_ = xl_state(0, {xlBoolean});\npersistent plbRNWReg_, plbRNWReg_ = xl_state(0, {xlUnsi" "gned, 1, 0});\npersistent plbWrDBusReg_, plbWrDBusReg_ = xl_state(0, {xlUnsigned, DBUS_LEN, 0});\n\n% ===== rest of" " the outputs =====\n\nbankAddr = xl_slice(plbABusReg_, 2+BANKADDR_LEN+LINEARADDR_LEN-1, 2+LINEARADDR_LEN);\nlinea" "rAddr = xl_slice(plbABusReg_, 2+LINEARADDR_LEN-1, 2);\nRNWReg = plbRNWReg_;\nwrDBusReg = plbWrDBusReg_;\n\n% ===== " "p_select =====\n\n% register PAValid\npersistent aValidReg, aValidReg = xl_state(0, {xlBoolean});\naValidReg = plbP" "AValidReg_;\n\n% extract and register the address prefix\naddrPref_in = xl_slice(plbABusReg_, xl_nbits(plbABusReg_)" "-1, xl_nbits(plbABusReg_)-ADDRPREF_LEN);\nif addrPref_in == addrPref\n ps1 = true;\nelse \n ps1 = false;\nend" " \n\npersistent ps1Reg, ps1Reg = xl_state(0, ps1);\nps1Reg = ps1;\n\nps = xl_and(ps1Reg, aValidReg);\n\n% ===== add" "rAck =====\n\n% register ps\npersistent psReg, psReg = xl_state(0, ps);\n\naddrAck = xfix({xlUnsigned, 1, 0}, xl_an" "d(xl_not(plbRstReg_), ps, xl_not(psReg)));\n\npsReg = ps;\n\n% ===== rdComp, rd/wr DAck =====\n \nrdComp1 = xfix({x" "lUnsigned, 1, 0}, xl_and(addrAck, RNWReg));\n\nNUM_rdCompDelay = 3;\npersistent rdCompDelay, rdCompDelay = xl_state" "(zeros(1, NUM_rdCompDelay), rdComp1, NUM_rdCompDelay);\nrdComp2 = rdCompDelay.back;\nrdCompDelay.push_front_pop_bac" "k(rdComp1);\n\npersistent rdCompReg, rdCompReg = xl_state(0, rdComp1);\nrdComp = rdCompReg;\nrdCompReg = rdComp2;\n" "\npersistent rdDAckReg, rdDAckReg = xl_state(0, rdComp1);\nrdDAck = rdDAckReg;\nrdDAckReg = rdComp;\n\npersistent w" "rDAckReg, wrDAckReg = xl_state(0, addrAck);\nwrDAck = wrDAckReg;\nwrDAckReg = xl_and(addrAck, xl_not(RNWReg));\n\n%" " ===== rdDBus =====\n\nrdSel = xl_or(rdComp2, rdComp);\n\nif rdSel == 1\n rdDBus1 = rdData;\nelse\n rdDBus1 =" " 0;\nend % if\n\npersistent rdDBusReg, rdDBusReg = xl_state(0, rdDBus1);\nrdDBus = rdDBusReg;\nrdDBusReg = rdDBus1;" "\n\n% rdDBus = xl_concat(rdDBus32, rdDBus32);\n% rdDBus = rdDBus32;\n\n% ===== update the persistent variables ====" "=\n\nplbRstReg_ = plbRst;\nplbABusReg_ = plbABus;\nplbPAValidReg_ = plbPAValid;\nplbRNWReg_ = plbRNW;\nplbWrDBusReg" "_ = xl_slice(plbWrDBus, DBUS_LEN-1, 0);\n" suppress_output "on" defparams "{}" hide_port_list "{}" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mcode" sg_icon_stat "170,412,7,9,white,blue,0,43a237d5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 170 170 0 0 ],[0 0 412 412 0 ],[0.77 0.82 " "0.91 ]);\nplot([0 170 170 0 0 ],[0 0 412 412 0 ]);\npatch([31.6 66.28 90.28 114.28 138.28 90.28 55.6 31.6 ],[232.64" " 232.64 256.64 232.64 256.64 256.64 256.64 232.64 ],[1 1 1 ]);\npatch([55.6 90.28 66.28 31.6 55.6 ],[208.64 208.64 " "232.64 232.64 208.64 ],[0.931 0.946 0.973 ]);\npatch([31.6 66.28 90.28 55.6 31.6 ],[184.64 184.64 208.64 208.64 184" ".64 ],[1 1 1 ]);\npatch([55.6 138.28 114.28 90.28 66.28 31.6 55.6 ],[160.64 160.64 184.64 160.64 184.64 184.64 160." "64 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\nco" "lor('black');port_label('input',1,'plbRst');\ncolor('black');port_label('input',2,'plbABus');\ncolor('black');port_" "label('input',3,'plbPAValid');\ncolor('black');port_label('input',4,'plbRNW');\ncolor('black');port_label('input',5" ",'plbWrDBus');\ncolor('black');port_label('input',6,'rdData');\ncolor('black');port_label('input',7,'addrPref');\nc" "olor('black');port_label('output',1,'wrDBusReg');\ncolor('black');port_label('output',2,'addrAck');\ncolor('black')" ";port_label('output',3,'rdComp');\ncolor('black');port_label('output',4,'wrDAck');\ncolor('black');port_label('outp" "ut',5,'bankAddr');\ncolor('black');port_label('output',6,'RNWReg');\ncolor('black');port_label('output',7,'rdDAck')" ";\ncolor('black');port_label('output',8,'rdDBus');\ncolor('black');port_label('output',9,'linearAddr');\ncolor('bla" "ck');disp('\\bf{xlmax}','texmode','on');\nfprintf('','COMMENT: end icon text');" Port { PortNumber 1 Name "wrDBusReg" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 2 Name "Sl_addrAck" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 3 Name "Sl_rdComp" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 4 Name "Sl_wrDAck" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 5 Name "bankAddr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 6 Name "RNWReg" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 7 Name "Sl_rdDAck" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 8 Name "Sl_rdDBus" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 9 Name "linearAddr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "plb_memmap" SID "6:136" Ports [44, 79] Position [405, 1639, 575, 2031] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/MCode" SourceType "Xilinx MCode Block Block" infoedit "Pass input values to a MATLAB function for evaluation in Xilinx fixed-point type. The input ports of t" "he block are input arguments of the function. The output ports of the block are output arguments of the function." mfname "xlmax" explicit_period off period "1" dbl_ovrd off enable_stdout off enable_debug off xl_use_area off xl_area "[0,0,0,0,0,0,0]" mfilecontent "function [read_bank_out, sm_DCO_EN_SEL_din, sm_DCO_EN_SEL_en, sm_DebugRx1Buffers_din, sm_DebugRx1B" "uffers_en, sm_DebugRx2Buffers_din, sm_DebugRx2Buffers_en, sm_DebugRx3Buffers_din, sm_DebugRx3Buffers_en, sm_DebugRx" "4Buffers_din, sm_DebugRx4Buffers_en, sm_MGC_AGC_SEL_din, sm_MGC_AGC_SEL_en, sm_RADIO1RXBUFF_RXEN_din, sm_RADIO1RXBU" "FF_RXEN_en, sm_RADIO1TXBUFF_TXEN_din, sm_RADIO1TXBUFF_TXEN_en, sm_RADIO2RXBUFF_RXEN_din, sm_RADIO2RXBUFF_RXEN_en, s" "m_RADIO2TXBUFF_TXEN_din, sm_RADIO2TXBUFF_TXEN_en, sm_RADIO3RXBUFF_RXEN_din, sm_RADIO3RXBUFF_RXEN_en, sm_RADIO3TXBUF" "F_TXEN_din, sm_RADIO3TXBUFF_TXEN_en, sm_RADIO4RXBUFF_RXEN_din, sm_RADIO4RXBUFF_RXEN_en, sm_RADIO4TXBUFF_TXEN_din, s" "m_RADIO4TXBUFF_TXEN_en, sm_StartCapture_din, sm_StartCapture_en, sm_StartTx_din, sm_StartTx_en, sm_StopTx_din, sm_S" "topTx_en, sm_TransMode_din, sm_TransMode_en, sm_TxDelay_din, sm_TxDelay_en, sm_TxLength_din, sm_TxLength_en, sm_Sta" "rtTxRx_din, sm_StartTxRx_en, sm_RxBuff_Radio1_addr, sm_RxBuff_Radio1_din, sm_RxBuff_Radio1_we, sm_RxBuff_Radio2_add" "r, sm_RxBuff_Radio2_din, sm_RxBuff_Radio2_we, sm_RxBuff_Radio3_addr, sm_RxBuff_Radio3_din, sm_RxBuff_Radio3_we, sm_" "RxBuff_Radio4_addr, sm_RxBuff_Radio4_din, sm_RxBuff_Radio4_we, sm_TxBuff_Radio1_addr, sm_TxBuff_Radio1_din, sm_TxBu" "ff_Radio1_we, sm_TxBuff_Radio2_addr, sm_TxBuff_Radio2_din, sm_TxBuff_Radio2_we, sm_TxBuff_Radio3_addr, sm_TxBuff_Ra" "dio3_din, sm_TxBuff_Radio3_we, sm_TxBuff_Radio4_addr, sm_TxBuff_Radio4_din, sm_TxBuff_Radio4_we, sm_RSSIBuff_Radio1" "_addr, sm_RSSIBuff_Radio1_din, sm_RSSIBuff_Radio1_we, sm_RSSIBuff_Radio2_addr, sm_RSSIBuff_Radio2_din, sm_RSSIBuff_" "Radio2_we, sm_RSSIBuff_Radio3_addr, sm_RSSIBuff_Radio3_din, sm_RSSIBuff_Radio3_we, sm_RSSIBuff_Radio4_addr, sm_RSSI" "Buff_Radio4_din, sm_RSSIBuff_Radio4_we] = plb_memmap(wrDBus, bankAddr, linearAddr, RNWReg, addrAck, sm_AGCDoneAddr," " sm_CaptureDone, sm_Radio1AGCDoneRSSI, sm_Radio2AGCDoneRSSI, sm_Radio3AGCDoneRSSI, sm_Radio4AGCDoneRSSI, sm_DCO_EN_" "SEL, sm_DebugRx1Buffers, sm_DebugRx2Buffers, sm_DebugRx3Buffers, sm_DebugRx4Buffers, sm_MGC_AGC_SEL, sm_RADIO1RXBUF" "F_RXEN, sm_RADIO1TXBUFF_TXEN, sm_RADIO2RXBUFF_RXEN, sm_RADIO2TXBUFF_TXEN, sm_RADIO3RXBUFF_RXEN, sm_RADIO3TXBUFF_TXE" "N, sm_RADIO4RXBUFF_RXEN, sm_RADIO4TXBUFF_TXEN, sm_StartCapture, sm_StartTx, sm_StopTx, sm_TransMode, sm_TxDelay, sm" "_TxLength, sm_StartTxRx, sm_RxBuff_Radio1, sm_RxBuff_Radio2, sm_RxBuff_Radio3, sm_RxBuff_Radio4, sm_TxBuff_Radio1, " "sm_TxBuff_Radio2, sm_TxBuff_Radio3, sm_TxBuff_Radio4, sm_RSSIBuff_Radio1, sm_RSSIBuff_Radio2, sm_RSSIBuff_Radio3, s" "m_RSSIBuff_Radio4)\n\n\n% connvert the input data to UFix_32_0 (the bus data type)\n% 'From Register' blocks\n% sm_" "AGCDoneAddr_bus = xfix({xlUnsigned, 32, 0}, 0);\nsm_AGCDoneAddr_bus = xl_force(sm_AGCDoneAddr, xlUnsigned, 0);\n\n%" " sm_CaptureDone_bus = xfix({xlUnsigned, 32, 0}, 0);\nsm_CaptureDone_bus = xl_force(sm_CaptureDone, xlUnsigned, 0);\n" "\n% sm_Radio1AGCDoneRSSI_bus = xfix({xlUnsigned, 32, 0}, 0);\nsm_Radio1AGCDoneRSSI_bus = xl_force(sm_Radio1AGCDoneR" "SSI, xlUnsigned, 0);\n\n% sm_Radio2AGCDoneRSSI_bus = xfix({xlUnsigned, 32, 0}, 0);\nsm_Radio2AGCDoneRSSI_bus = xl_f" "orce(sm_Radio2AGCDoneRSSI, xlUnsigned, 0);\n\n% sm_Radio3AGCDoneRSSI_bus = xfix({xlUnsigned, 32, 0}, 0);\nsm_Radio3" "AGCDoneRSSI_bus = xl_force(sm_Radio3AGCDoneRSSI, xlUnsigned, 0);\n\n% sm_Radio4AGCDoneRSSI_bus = xfix({xlUnsigned, " "32, 0}, 0);\nsm_Radio4AGCDoneRSSI_bus = xl_force(sm_Radio4AGCDoneRSSI, xlUnsigned, 0);\n\n% 'To Register' blocks\n\n" "% sm_DCO_EN_SEL_dout = xfix({xlUnsigned, 32, 0}, 0);\nsm_DCO_EN_SEL_dout = xl_force(sm_DCO_EN_SEL, xlUnsigned, 0);\n" "\n% sm_DebugRx1Buffers_dout = xfix({xlUnsigned, 32, 0}, 0);\nsm_DebugRx1Buffers_dout = xl_force(sm_DebugRx1Buffers," " xlUnsigned, 0);\n\n% sm_DebugRx2Buffers_dout = xfix({xlUnsigned, 32, 0}, 0);\nsm_DebugRx2Buffers_dout = xl_force(s" "m_DebugRx2Buffers, xlUnsigned, 0);\n\n% sm_DebugRx3Buffers_dout = xfix({xlUnsigned, 32, 0}, 0);\nsm_DebugRx3Buffers" "_dout = xl_force(sm_DebugRx3Buffers, xlUnsigned, 0);\n\n% sm_DebugRx4Buffers_dout = xfix({xlUnsigned, 32, 0}, 0);\n" "sm_DebugRx4Buffers_dout = xl_force(sm_DebugRx4Buffers, xlUnsigned, 0);\n\n% sm_MGC_AGC_SEL_dout = xfix({xlUnsigned," " 32, 0}, 0);\nsm_MGC_AGC_SEL_dout = xl_force(sm_MGC_AGC_SEL, xlUnsigned, 0);\n\n% sm_RADIO1RXBUFF_RXEN_dout = xfix(" "{xlUnsigned, 32, 0}, 0);\nsm_RADIO1RXBUFF_RXEN_dout = xl_force(sm_RADIO1RXBUFF_RXEN, xlUnsigned, 0);\n\n% sm_RADIO1" "TXBUFF_TXEN_dout = xfix({xlUnsigned, 32, 0}, 0);\nsm_RADIO1TXBUFF_TXEN_dout = xl_force(sm_RADIO1TXBUFF_TXEN, xlUnsi" "gned, 0);\n\n% sm_RADIO2RXBUFF_RXEN_dout = xfix({xlUnsigned, 32, 0}, 0);\nsm_RADIO2RXBUFF_RXEN_dout = xl_force(sm_R" "ADIO2RXBUFF_RXEN, xlUnsigned, 0);\n\n% sm_RADIO2TXBUFF_TXEN_dout = xfix({xlUnsigned, 32, 0}, 0);\nsm_RADIO2TXBUFF_T" "XEN_dout = xl_force(sm_RADIO2TXBUFF_TXEN, xlUnsigned, 0);\n\n% sm_RADIO3RXBUFF_RXEN_dout = xfix({xlUnsigned, 32, 0}" ", 0);\nsm_RADIO3RXBUFF_RXEN_dout = xl_force(sm_RADIO3RXBUFF_RXEN, xlUnsigned, 0);\n\n% sm_RADIO3TXBUFF_TXEN_dout = " "xfix({xlUnsigned, 32, 0}, 0);\nsm_RADIO3TXBUFF_TXEN_dout = xl_force(sm_RADIO3TXBUFF_TXEN, xlUnsigned, 0);\n\n% sm_R" "ADIO4RXBUFF_RXEN_dout = xfix({xlUnsigned, 32, 0}, 0);\nsm_RADIO4RXBUFF_RXEN_dout = xl_force(sm_RADIO4RXBUFF_RXEN, x" "lUnsigned, 0);\n\n% sm_RADIO4TXBUFF_TXEN_dout = xfix({xlUnsigned, 32, 0}, 0);\nsm_RADIO4TXBUFF_TXEN_dout = xl_force" "(sm_RADIO4TXBUFF_TXEN, xlUnsigned, 0);\n\n% sm_StartCapture_dout = xfix({xlUnsigned, 32, 0}, 0);\nsm_StartCapture_d" "out = xl_force(sm_StartCapture, xlUnsigned, 0);\n\n% sm_StartTx_dout = xfix({xlUnsigned, 32, 0}, 0);\nsm_StartTx_do" "ut = xl_force(sm_StartTx, xlUnsigned, 0);\n\n% sm_StopTx_dout = xfix({xlUnsigned, 32, 0}, 0);\nsm_StopTx_dout = xl_" "force(sm_StopTx, xlUnsigned, 0);\n\n% sm_TransMode_dout = xfix({xlUnsigned, 32, 0}, 0);\nsm_TransMode_dout = xl_for" "ce(sm_TransMode, xlUnsigned, 0);\n\n% sm_TxDelay_dout = xfix({xlUnsigned, 32, 0}, 0);\nsm_TxDelay_dout = xl_force(s" "m_TxDelay, xlUnsigned, 0);\n\n% sm_TxLength_dout = xfix({xlUnsigned, 32, 0}, 0);\nsm_TxLength_dout = xl_force(sm_Tx" "Length, xlUnsigned, 0);\n\n% sm_StartTxRx_dout = xfix({xlUnsigned, 32, 0}, 0);\nsm_StartTxRx_dout = xl_force(sm_Sta" "rtTxRx, xlUnsigned, 0);\n\n\n% 'From FIFO' blocks\n% 'To FIFO' blocks\n% 'Shared Memory' blocks\n% RxBuff_Radio1_bu" "s = xfix({xlUnsigned, 32, 0}, 0);\nsm_RxBuff_Radio1_bus = xl_force(sm_RxBuff_Radio1, xlUnsigned, 0);\n\n% RxBuff_Ra" "dio2_bus = xfix({xlUnsigned, 32, 0}, 0);\nsm_RxBuff_Radio2_bus = xl_force(sm_RxBuff_Radio2, xlUnsigned, 0);\n\n% Rx" "Buff_Radio3_bus = xfix({xlUnsigned, 32, 0}, 0);\nsm_RxBuff_Radio3_bus = xl_force(sm_RxBuff_Radio3, xlUnsigned, 0);\n" "\n% RxBuff_Radio4_bus = xfix({xlUnsigned, 32, 0}, 0);\nsm_RxBuff_Radio4_bus = xl_force(sm_RxBuff_Radio4, xlUnsigned" ", 0);\n\n% TxBuff_Radio1_bus = xfix({xlUnsigned, 32, 0}, 0);\nsm_TxBuff_Radio1_bus = xl_force(sm_TxBuff_Radio1, xlU" "nsigned, 0);\n\n% TxBuff_Radio2_bus = xfix({xlUnsigned, 32, 0}, 0);\nsm_TxBuff_Radio2_bus = xl_force(sm_TxBuff_Radi" "o2, xlUnsigned, 0);\n\n% TxBuff_Radio3_bus = xfix({xlUnsigned, 32, 0}, 0);\nsm_TxBuff_Radio3_bus = xl_force(sm_TxBu" "ff_Radio3, xlUnsigned, 0);\n\n% TxBuff_Radio4_bus = xfix({xlUnsigned, 32, 0}, 0);\nsm_TxBuff_Radio4_bus = xl_force(" "sm_TxBuff_Radio4, xlUnsigned, 0);\n\n% RSSIBuff_Radio1_bus = xfix({xlUnsigned, 32, 0}, 0);\nsm_RSSIBuff_Radio1_bus " "= xl_force(sm_RSSIBuff_Radio1, xlUnsigned, 0);\n\n% RSSIBuff_Radio2_bus = xfix({xlUnsigned, 32, 0}, 0);\nsm_RSSIBuf" "f_Radio2_bus = xl_force(sm_RSSIBuff_Radio2, xlUnsigned, 0);\n\n% RSSIBuff_Radio3_bus = xfix({xlUnsigned, 32, 0}, 0)" ";\nsm_RSSIBuff_Radio3_bus = xl_force(sm_RSSIBuff_Radio3, xlUnsigned, 0);\n\n% RSSIBuff_Radio4_bus = xfix({xlUnsigne" "d, 32, 0}, 0);\nsm_RSSIBuff_Radio4_bus = xl_force(sm_RSSIBuff_Radio4, xlUnsigned, 0);\n\n\n% 'dout' ports of 'From " "Register' blocks\n\n% registered register mux output\npersistent reg_bank_out_reg; reg_bank_out_reg = xl_state(0, {" "xlUnsigned, 32, 0});\nreg_bank_out = reg_bank_out_reg;\n\nif linearAddr == 21\n reg_bank_out_reg = sm_AGCDoneAdd" "r_bus;\nelseif linearAddr == 22\n reg_bank_out_reg = sm_CaptureDone_bus;\nelseif linearAddr == 23\n reg_bank_" "out_reg = sm_Radio1AGCDoneRSSI_bus;\nelseif linearAddr == 24\n reg_bank_out_reg = sm_Radio2AGCDoneRSSI_bus;\nels" "eif linearAddr == 25\n reg_bank_out_reg = sm_Radio3AGCDoneRSSI_bus;\nelseif linearAddr == 26\n reg_bank_out_r" "eg = sm_Radio4AGCDoneRSSI_bus;\nelseif linearAddr == 0\n reg_bank_out_reg = sm_DCO_EN_SEL_dout;\nelseif linearAd" "dr == 1\n reg_bank_out_reg = sm_DebugRx1Buffers_dout;\nelseif linearAddr == 2\n reg_bank_out_reg = sm_DebugRx" "2Buffers_dout;\nelseif linearAddr == 3\n reg_bank_out_reg = sm_DebugRx3Buffers_dout;\nelseif linearAddr == 4\n " " reg_bank_out_reg = sm_DebugRx4Buffers_dout;\nelseif linearAddr == 5\n reg_bank_out_reg = sm_MGC_AGC_SEL_dout;\n" "elseif linearAddr == 6\n reg_bank_out_reg = sm_RADIO1RXBUFF_RXEN_dout;\nelseif linearAddr == 7\n reg_bank_out" "_reg = sm_RADIO1TXBUFF_TXEN_dout;\nelseif linearAddr == 8\n reg_bank_out_reg = sm_RADIO2RXBUFF_RXEN_dout;\nelsei" "f linearAddr == 9\n reg_bank_out_reg = sm_RADIO2TXBUFF_TXEN_dout;\nelseif linearAddr == 10\n reg_bank_out_reg" " = sm_RADIO3RXBUFF_RXEN_dout;\nelseif linearAddr == 11\n reg_bank_out_reg = sm_RADIO3TXBUFF_TXEN_dout;\nelseif l" "inearAddr == 12\n reg_bank_out_reg = sm_RADIO4RXBUFF_RXEN_dout;\nelseif linearAddr == 13\n reg_bank_out_reg =" " sm_RADIO4TXBUFF_TXEN_dout;\nelseif linearAddr == 14\n reg_bank_out_reg = sm_StartCapture_dout;\nelseif linearAd" "dr == 15\n reg_bank_out_reg = sm_StartTx_dout;\nelseif linearAddr == 16\n reg_bank_out_reg = sm_StopTx_dout;\n" "elseif linearAddr == 17\n reg_bank_out_reg = sm_TransMode_dout;\nelseif linearAddr == 18\n reg_bank_out_reg =" " sm_TxDelay_dout;\nelseif linearAddr == 19\n reg_bank_out_reg = sm_TxLength_dout;\nelseif linearAddr == 20\n " "reg_bank_out_reg = sm_StartTxRx_dout;\n\nend\n\n\n% 'From FIFO' and 'To FIFO' blocks\n\n\n\n\n\nopCode = xl_concat(" "addrAck, RNWReg, bankAddr, linearAddr);\n\n% 'Shared Memory' blocks\n\nsm_RxBuff_Radio1_sel_value = xl_concat(xl_sl" "ice(linearAddr, ...\n xl_nbits(linearAddr) - 1, ...\n " " 14) ...\n );\nif sm_RxBuff_Radio1_sel_value == xfix({xlUnsigned" ", ...\n xl_nbits(linearAddr) - 14, ...\n " " 0}, ...\n 0);\n sm_RxBuff_Radio1_sel = true;\nelse\n sm_RxBuff_Rad" "io1_sel = false;\nend\nsm_RxBuff_Radio2_sel_value = xl_concat(xl_slice(linearAddr, ...\n " " xl_nbits(linearAddr) - 1, ...\n 14) ...\n " " );\nif sm_RxBuff_Radio2_sel_value == xfix({xlUnsigned, ...\n x" "l_nbits(linearAddr) - 14, ...\n 0}, ...\n " " 1);\n sm_RxBuff_Radio2_sel = true;\nelse\n sm_RxBuff_Radio2_sel = false;\nend\nsm_RxBuff_Radio3_sel_valu" "e = xl_concat(xl_slice(linearAddr, ...\n xl_nbits(linearAddr) - 1, ...\n " " 14) ...\n );\nif sm_RxBuff_Radio3_sel_value " "== xfix({xlUnsigned, ...\n xl_nbits(linearAddr) - 14, ...\n " " 0}, ...\n 2);\n sm_RxBuff_Radio3_sel = true;\nelse" "\n sm_RxBuff_Radio3_sel = false;\nend\nsm_RxBuff_Radio4_sel_value = xl_concat(xl_slice(linearAddr, ...\n " " xl_nbits(linearAddr) - 1, ...\n 14) ...\n " " );\nif sm_RxBuff_Radio4_sel_value == xfix({xlUnsigned, ...\n " " xl_nbits(linearAddr) - 14, ...\n 0}, ...\n " " 3);\n sm_RxBuff_Radio4_sel = true;\nelse\n sm_RxBuff_Radio4_sel = false;\nend\nsm_TxB" "uff_Radio1_sel_value = xl_concat(xl_slice(linearAddr, ...\n xl_nbits(linearA" "ddr) - 1, ...\n 14) ...\n );\nif sm_TxBuf" "f_Radio1_sel_value == xfix({xlUnsigned, ...\n xl_nbits(linearAddr) - 14, ..." "\n 0}, ...\n 4);\n sm_TxBuff_Radio" "1_sel = true;\nelse\n sm_TxBuff_Radio1_sel = false;\nend\nsm_TxBuff_Radio2_sel_value = xl_concat(xl_slice(linear" "Addr, ...\n xl_nbits(linearAddr) - 1, ...\n " " 14) ...\n );\nif sm_TxBuff_Radio2_sel_value == xfix({xlUnsigned, ...\n " " xl_nbits(linearAddr) - 14, ...\n 0}, .." ".\n 5);\n sm_TxBuff_Radio2_sel = true;\nelse\n sm_TxBuff_Radio2_sel = " "false;\nend\nsm_TxBuff_Radio3_sel_value = xl_concat(xl_slice(linearAddr, ...\n " " xl_nbits(linearAddr) - 1, ...\n 14) ...\n " " );\nif sm_TxBuff_Radio3_sel_value == xfix({xlUnsigned, ...\n xl_nbits(li" "nearAddr) - 14, ...\n 0}, ...\n 6);\n" " sm_TxBuff_Radio3_sel = true;\nelse\n sm_TxBuff_Radio3_sel = false;\nend\nsm_TxBuff_Radio4_sel_value = xl_con" "cat(xl_slice(linearAddr, ...\n xl_nbits(linearAddr) - 1, ...\n " " 14) ...\n );\nif sm_TxBuff_Radio4_sel_value == xfix({x" "lUnsigned, ...\n xl_nbits(linearAddr) - 14, ...\n " " 0}, ...\n 7);\n sm_TxBuff_Radio4_sel = true;\nelse\n sm_T" "xBuff_Radio4_sel = false;\nend\nsm_RSSIBuff_Radio1_sel_value = xl_concat(xl_slice(linearAddr, ...\n " " xl_nbits(linearAddr) - 1, ...\n 11) ...\n " " );\nif sm_RSSIBuff_Radio1_sel_value == xfix({xlUnsigned, ...\n " " xl_nbits(linearAddr) - 11, ...\n 0}, ...\n " " 64);\n sm_RSSIBuff_Radio1_sel = true;\nelse\n sm_RSSIBuff_Radio1_sel = false;\nend\nsm_RSSI" "Buff_Radio2_sel_value = xl_concat(xl_slice(linearAddr, ...\n xl_nbits(linear" "Addr) - 1, ...\n 11) ...\n );\nif sm_RSSI" "Buff_Radio2_sel_value == xfix({xlUnsigned, ...\n xl_nbits(linearAddr) - 11, " "...\n 0}, ...\n 65);\n sm_RSSIBuff" "_Radio2_sel = true;\nelse\n sm_RSSIBuff_Radio2_sel = false;\nend\nsm_RSSIBuff_Radio3_sel_value = xl_concat(xl_sl" "ice(linearAddr, ...\n xl_nbits(linearAddr) - 1, ...\n " " 11) ...\n );\nif sm_RSSIBuff_Radio3_sel_value == xfix({xlUnsign" "ed, ...\n xl_nbits(linearAddr) - 11, ...\n " " 0}, ...\n 66);\n sm_RSSIBuff_Radio3_sel = true;\nelse\n sm_RSSIB" "uff_Radio3_sel = false;\nend\nsm_RSSIBuff_Radio4_sel_value = xl_concat(xl_slice(linearAddr, ...\n " " xl_nbits(linearAddr) - 1, ...\n 11) ...\n " " );\nif sm_RSSIBuff_Radio4_sel_value == xfix({xlUnsigned, ...\n " " xl_nbits(linearAddr) - 11, ...\n 0}, ...\n " " 67);\n sm_RSSIBuff_Radio4_sel = true;\nelse\n sm_RSSIBuff_Radio4_sel = false;\nend\n\n\n% reg" "istered Shared Memory mux output\npersistent ram_bank_out_reg; ram_bank_out_reg = xl_state(0, {xlUnsigned, 32, 0});" "\nram_bank_out = ram_bank_out_reg;\nif sm_RxBuff_Radio1_sel\n ram_bank_out_reg = sm_RxBuff_Radio1_bus;\nelseif s" "m_RxBuff_Radio2_sel\n ram_bank_out_reg = sm_RxBuff_Radio2_bus;\nelseif sm_RxBuff_Radio3_sel\n ram_bank_out_re" "g = sm_RxBuff_Radio3_bus;\nelseif sm_RxBuff_Radio4_sel\n ram_bank_out_reg = sm_RxBuff_Radio4_bus;\nelseif sm_TxB" "uff_Radio1_sel\n ram_bank_out_reg = sm_TxBuff_Radio1_bus;\nelseif sm_TxBuff_Radio2_sel\n ram_bank_out_reg = s" "m_TxBuff_Radio2_bus;\nelseif sm_TxBuff_Radio3_sel\n ram_bank_out_reg = sm_TxBuff_Radio3_bus;\nelseif sm_TxBuff_R" "adio4_sel\n ram_bank_out_reg = sm_TxBuff_Radio4_bus;\nelseif sm_RSSIBuff_Radio1_sel\n ram_bank_out_reg = sm_R" "SSIBuff_Radio1_bus;\nelseif sm_RSSIBuff_Radio2_sel\n ram_bank_out_reg = sm_RSSIBuff_Radio2_bus;\nelseif sm_RSSIB" "uff_Radio3_sel\n ram_bank_out_reg = sm_RSSIBuff_Radio3_bus;\nelseif sm_RSSIBuff_Radio4_sel\n ram_bank_out_reg" " = sm_RSSIBuff_Radio4_bus;\nend\n\n% 'din' ports of 'Shared Memory' blocks\nsm_RxBuff_Radio1_din = xl_force(xl_slic" "e(wrDBus, 32 - 1, 0), ...\n xlUnsigned, ...\n 0);\n" "sm_RxBuff_Radio2_din = xl_force(xl_slice(wrDBus, 32 - 1, 0), ...\n xlUnsigned, ...\n" " 0);\nsm_RxBuff_Radio3_din = xl_force(xl_slice(wrDBus, 32 - 1, 0), ...\n " " xlUnsigned, ...\n 0);\nsm_RxBuff_Radio4_din = xl_force(xl_sli" "ce(wrDBus, 32 - 1, 0), ...\n xlUnsigned, ...\n 0);\n" "sm_TxBuff_Radio1_din = xl_force(xl_slice(wrDBus, 32 - 1, 0), ...\n xlUnsigned, ...\n" " 0);\nsm_TxBuff_Radio2_din = xl_force(xl_slice(wrDBus, 32 - 1, 0), ...\n " " xlUnsigned, ...\n 0);\nsm_TxBuff_Radio3_din = xl_force(xl_sli" "ce(wrDBus, 32 - 1, 0), ...\n xlUnsigned, ...\n 0);\n" "sm_TxBuff_Radio4_din = xl_force(xl_slice(wrDBus, 32 - 1, 0), ...\n xlUnsigned, ...\n" " 0);\nsm_RSSIBuff_Radio1_din = xl_force(xl_slice(wrDBus, 32 - 1, 0), ...\n " " xlUnsigned, ...\n 0);\nsm_RSSIBuff_Radio2_din = xl_force(xl" "_slice(wrDBus, 32 - 1, 0), ...\n xlUnsigned, ...\n " "0);\nsm_RSSIBuff_Radio3_din = xl_force(xl_slice(wrDBus, 32 - 1, 0), ...\n xlUnsigne" "d, ...\n 0);\nsm_RSSIBuff_Radio4_din = xl_force(xl_slice(wrDBus, 32 - 1, 0), ...\n " " xlUnsigned, ...\n 0);\n\n\n% 'we' ports of 'Shared " "Memory' blocks\npersistent sm_RxBuff_Radio1_we_reg; sm_RxBuff_Radio1_we_reg = xl_state(false, {xlBoolean});\nsm_RxB" "uff_Radio1_we = sm_RxBuff_Radio1_we_reg;\nopCode_sm_RxBuff_Radio1 = xl_concat(addrAck, ...\n " " RNWReg, ...\n bankAddr, ...\n " " xl_slice(linearAddr, ...\n xl_nbits(linearAddr) - 1, ...\n " " 14) ...\n );\nif opCode_sm_RxBuff_Radio1 == x" "l_concat(xfix({xlUnsigned, 4, 0}, 8), ...\n xfix({xlUnsigned, ...\n " " xl_nbits(linearAddr) - 14, ...\n " " 0}, ...\n 0) ...\n );\n " "sm_RxBuff_Radio1_we_reg = true;\nelse\n sm_RxBuff_Radio1_we_reg = false;\nend\npersistent sm_RxBuff_Radio2_we_re" "g; sm_RxBuff_Radio2_we_reg = xl_state(false, {xlBoolean});\nsm_RxBuff_Radio2_we = sm_RxBuff_Radio2_we_reg;\nopCode_" "sm_RxBuff_Radio2 = xl_concat(addrAck, ...\n RNWReg, ...\n " " bankAddr, ...\n xl_slice(linearAddr, ...\n " " xl_nbits(linearAddr) - 1, ...\n 14) ...\n " " );\nif opCode_sm_RxBuff_Radio2 == xl_concat(xfix({xlUnsigned, 4, 0}, 8), ...\n " " xfix({xlUnsigned, ...\n xl_nbits(l" "inearAddr) - 14, ...\n 0}, ...\n " " 1) ...\n );\n sm_RxBuff_Radio2_we_reg = true;\nelse\n sm_RxB" "uff_Radio2_we_reg = false;\nend\npersistent sm_RxBuff_Radio3_we_reg; sm_RxBuff_Radio3_we_reg = xl_state(false, {xlB" "oolean});\nsm_RxBuff_Radio3_we = sm_RxBuff_Radio3_we_reg;\nopCode_sm_RxBuff_Radio3 = xl_concat(addrAck, ...\n " " RNWReg, ...\n bankAddr, ...\n " " xl_slice(linearAddr, ...\n xl_nbits(linearAddr) - 1," " ...\n 14) ...\n );\nif opCode_sm_R" "xBuff_Radio3 == xl_concat(xfix({xlUnsigned, 4, 0}, 8), ...\n xfix({xlUnsign" "ed, ...\n xl_nbits(linearAddr) - 14, ...\n " " 0}, ...\n 2) ...\n " " );\n sm_RxBuff_Radio3_we_reg = true;\nelse\n sm_RxBuff_Radio3_we_reg = false;\nend\npersistent sm_Rx" "Buff_Radio4_we_reg; sm_RxBuff_Radio4_we_reg = xl_state(false, {xlBoolean});\nsm_RxBuff_Radio4_we = sm_RxBuff_Radio4" "_we_reg;\nopCode_sm_RxBuff_Radio4 = xl_concat(addrAck, ...\n RNWReg, ...\n " " bankAddr, ...\n xl_slice(linearAddr, ...\n " " xl_nbits(linearAddr) - 1, ...\n " " 14) ...\n );\nif opCode_sm_RxBuff_Radio4 == xl_concat(xfix({xlUnsigned, 4, 0}" ", 8), ...\n xfix({xlUnsigned, ...\n " " xl_nbits(linearAddr) - 14, ...\n 0}, ...\n " " 3) ...\n );\n sm_RxBuff_Radio4_we_reg = true;\n" "else\n sm_RxBuff_Radio4_we_reg = false;\nend\npersistent sm_TxBuff_Radio1_we_reg; sm_TxBuff_Radio1_we_reg = xl_s" "tate(false, {xlBoolean});\nsm_TxBuff_Radio1_we = sm_TxBuff_Radio1_we_reg;\nopCode_sm_TxBuff_Radio1 = xl_concat(addr" "Ack, ...\n RNWReg, ...\n bankAddr, ...\n " " xl_slice(linearAddr, ...\n xl_nbits(" "linearAddr) - 1, ...\n 14) ...\n );" "\nif opCode_sm_TxBuff_Radio1 == xl_concat(xfix({xlUnsigned, 4, 0}, 8), ...\n " " xfix({xlUnsigned, ...\n xl_nbits(linearAddr) - 14, ...\n " " 0}, ...\n 4) ...\n " " );\n sm_TxBuff_Radio1_we_reg = true;\nelse\n sm_TxBuff_Radio1_we_reg = false;\nend\n" "persistent sm_TxBuff_Radio2_we_reg; sm_TxBuff_Radio2_we_reg = xl_state(false, {xlBoolean});\nsm_TxBuff_Radio2_we = " "sm_TxBuff_Radio2_we_reg;\nopCode_sm_TxBuff_Radio2 = xl_concat(addrAck, ...\n RN" "WReg, ...\n bankAddr, ...\n xl_slice(linear" "Addr, ...\n xl_nbits(linearAddr) - 1, ...\n " " 14) ...\n );\nif opCode_sm_TxBuff_Radio2 == xl_concat(xfix({x" "lUnsigned, 4, 0}, 8), ...\n xfix({xlUnsigned, ...\n " " xl_nbits(linearAddr) - 14, ...\n 0}, ...\n " " 5) ...\n );\n sm_TxBuff_Radio2" "_we_reg = true;\nelse\n sm_TxBuff_Radio2_we_reg = false;\nend\npersistent sm_TxBuff_Radio3_we_reg; sm_TxBuff_Rad" "io3_we_reg = xl_state(false, {xlBoolean});\nsm_TxBuff_Radio3_we = sm_TxBuff_Radio3_we_reg;\nopCode_sm_TxBuff_Radio3" " = xl_concat(addrAck, ...\n RNWReg, ...\n b" "ankAddr, ...\n xl_slice(linearAddr, ...\n " " xl_nbits(linearAddr) - 1, ...\n 14) ...\n " " );\nif opCode_sm_TxBuff_Radio3 == xl_concat(xfix({xlUnsigned, 4, 0}, 8), ...\n " " xfix({xlUnsigned, ...\n xl_nbits(linearAddr) - 14," " ...\n 0}, ...\n 6) ..." "\n );\n sm_TxBuff_Radio3_we_reg = true;\nelse\n sm_TxBuff_Radio3_we_re" "g = false;\nend\npersistent sm_TxBuff_Radio4_we_reg; sm_TxBuff_Radio4_we_reg = xl_state(false, {xlBoolean});\nsm_Tx" "Buff_Radio4_we = sm_TxBuff_Radio4_we_reg;\nopCode_sm_TxBuff_Radio4 = xl_concat(addrAck, ...\n " " RNWReg, ...\n bankAddr, ...\n " " xl_slice(linearAddr, ...\n xl_nbits(linearAddr) - 1, ...\n " " 14) ...\n );\nif opCode_sm_TxBuff_Radio4 == " "xl_concat(xfix({xlUnsigned, 4, 0}, 8), ...\n xfix({xlUnsigned, ...\n " " xl_nbits(linearAddr) - 14, ...\n " " 0}, ...\n 7) ...\n );\n " " sm_TxBuff_Radio4_we_reg = true;\nelse\n sm_TxBuff_Radio4_we_reg = false;\nend\npersistent sm_RSSIBuff_Radio1_we" "_reg; sm_RSSIBuff_Radio1_we_reg = xl_state(false, {xlBoolean});\nsm_RSSIBuff_Radio1_we = sm_RSSIBuff_Radio1_we_reg;" "\nopCode_sm_RSSIBuff_Radio1 = xl_concat(addrAck, ...\n RNWReg, ...\n " " bankAddr, ...\n xl_slice(linearAddr, ...\n " " xl_nbits(linearAddr) - 1, ...\n 11)" " ...\n );\nif opCode_sm_RSSIBuff_Radio1 == xl_concat(xfix({xlUnsigned, 4, 0}, 8)" ", ...\n xfix({xlUnsigned, ...\n " " xl_nbits(linearAddr) - 11, ...\n 0}, ...\n " " 64) ...\n );\n sm_RSSIBuff_Radio1_we_reg = true;\n" "else\n sm_RSSIBuff_Radio1_we_reg = false;\nend\npersistent sm_RSSIBuff_Radio2_we_reg; sm_RSSIBuff_Radio2_we_reg " "= xl_state(false, {xlBoolean});\nsm_RSSIBuff_Radio2_we = sm_RSSIBuff_Radio2_we_reg;\nopCode_sm_RSSIBuff_Radio2 = xl" "_concat(addrAck, ...\n RNWReg, ...\n bankAd" "dr, ...\n xl_slice(linearAddr, ...\n " " xl_nbits(linearAddr) - 1, ...\n 11) ...\n " " );\nif opCode_sm_RSSIBuff_Radio2 == xl_concat(xfix({xlUnsigned, 4, 0}, 8), ...\n " " xfix({xlUnsigned, ...\n xl_nbits(linearAddr) - 11, .." ".\n 0}, ...\n 65) ...\n" " );\n sm_RSSIBuff_Radio2_we_reg = true;\nelse\n sm_RSSIBuff_Radio2_we_" "reg = false;\nend\npersistent sm_RSSIBuff_Radio3_we_reg; sm_RSSIBuff_Radio3_we_reg = xl_state(false, {xlBoolean});\n" "sm_RSSIBuff_Radio3_we = sm_RSSIBuff_Radio3_we_reg;\nopCode_sm_RSSIBuff_Radio3 = xl_concat(addrAck, ...\n " " RNWReg, ...\n bankAddr, ...\n " " xl_slice(linearAddr, ...\n xl_nbits(linearAddr) - 1, ...\n" " 11) ...\n );\nif opCode_sm_RSSIBuf" "f_Radio3 == xl_concat(xfix({xlUnsigned, 4, 0}, 8), ...\n xfix({xlUnsigned, " "...\n xl_nbits(linearAddr) - 11, ...\n " " 0}, ...\n 66) ...\n " " );\n sm_RSSIBuff_Radio3_we_reg = true;\nelse\n sm_RSSIBuff_Radio3_we_reg = false;\nend\npersistent sm_R" "SSIBuff_Radio4_we_reg; sm_RSSIBuff_Radio4_we_reg = xl_state(false, {xlBoolean});\nsm_RSSIBuff_Radio4_we = sm_RSSIBu" "ff_Radio4_we_reg;\nopCode_sm_RSSIBuff_Radio4 = xl_concat(addrAck, ...\n RNWReg," " ...\n bankAddr, ...\n xl_slice(linearAddr," " ...\n xl_nbits(linearAddr) - 1, ...\n " " 11) ...\n );\nif opCode_sm_RSSIBuff_Radio4 == xl_concat(xfix({xlUn" "signed, 4, 0}, 8), ...\n xfix({xlUnsigned, ...\n " " xl_nbits(linearAddr) - 11, ...\n 0}, ...\n " " 67) ...\n );\n sm_RSSIBuff_Radio4" "_we_reg = true;\nelse\n sm_RSSIBuff_Radio4_we_reg = false;\nend\n\n\n% 'addr' ports of 'Shared Memory' blocks\np" "ersistent sm_RxBuff_Radio1_addr_reg; \nsm_RxBuff_Radio1_addr_reg = xl_state(0, {xlUnsigned, 14, 0});\nsm_RxBuff_Rad" "io1_addr = sm_RxBuff_Radio1_addr_reg;\nif addrAck == 1\n sm_RxBuff_Radio1_addr_reg = xl_slice(linearAddr, 14, 0)" ";\nelse\n sm_RxBuff_Radio1_addr_reg = sm_RxBuff_Radio1_addr_reg;\nend\npersistent sm_RxBuff_Radio2_addr_reg; \ns" "m_RxBuff_Radio2_addr_reg = xl_state(0, {xlUnsigned, 14, 0});\nsm_RxBuff_Radio2_addr = sm_RxBuff_Radio2_addr_reg;\ni" "f addrAck == 1\n sm_RxBuff_Radio2_addr_reg = xl_slice(linearAddr, 14, 0);\nelse\n sm_RxBuff_Radio2_addr_reg =" " sm_RxBuff_Radio2_addr_reg;\nend\npersistent sm_RxBuff_Radio3_addr_reg; \nsm_RxBuff_Radio3_addr_reg = xl_state(0, {" "xlUnsigned, 14, 0});\nsm_RxBuff_Radio3_addr = sm_RxBuff_Radio3_addr_reg;\nif addrAck == 1\n sm_RxBuff_Radio3_add" "r_reg = xl_slice(linearAddr, 14, 0);\nelse\n sm_RxBuff_Radio3_addr_reg = sm_RxBuff_Radio3_addr_reg;\nend\npersis" "tent sm_RxBuff_Radio4_addr_reg; \nsm_RxBuff_Radio4_addr_reg = xl_state(0, {xlUnsigned, 14, 0});\nsm_RxBuff_Radio4_a" "ddr = sm_RxBuff_Radio4_addr_reg;\nif addrAck == 1\n sm_RxBuff_Radio4_addr_reg = xl_slice(linearAddr, 14, 0);\nel" "se\n sm_RxBuff_Radio4_addr_reg = sm_RxBuff_Radio4_addr_reg;\nend\npersistent sm_TxBuff_Radio1_addr_reg; \nsm_TxB" "uff_Radio1_addr_reg = xl_state(0, {xlUnsigned, 14, 0});\nsm_TxBuff_Radio1_addr = sm_TxBuff_Radio1_addr_reg;\nif add" "rAck == 1\n sm_TxBuff_Radio1_addr_reg = xl_slice(linearAddr, 14, 0);\nelse\n sm_TxBuff_Radio1_addr_reg = sm_T" "xBuff_Radio1_addr_reg;\nend\npersistent sm_TxBuff_Radio2_addr_reg; \nsm_TxBuff_Radio2_addr_reg = xl_state(0, {xlUns" "igned, 14, 0});\nsm_TxBuff_Radio2_addr = sm_TxBuff_Radio2_addr_reg;\nif addrAck == 1\n sm_TxBuff_Radio2_addr_reg" " = xl_slice(linearAddr, 14, 0);\nelse\n sm_TxBuff_Radio2_addr_reg = sm_TxBuff_Radio2_addr_reg;\nend\npersistent " "sm_TxBuff_Radio3_addr_reg; \nsm_TxBuff_Radio3_addr_reg = xl_state(0, {xlUnsigned, 14, 0});\nsm_TxBuff_Radio3_addr =" " sm_TxBuff_Radio3_addr_reg;\nif addrAck == 1\n sm_TxBuff_Radio3_addr_reg = xl_slice(linearAddr, 14, 0);\nelse\n " " sm_TxBuff_Radio3_addr_reg = sm_TxBuff_Radio3_addr_reg;\nend\npersistent sm_TxBuff_Radio4_addr_reg; \nsm_TxBuff_R" "adio4_addr_reg = xl_state(0, {xlUnsigned, 14, 0});\nsm_TxBuff_Radio4_addr = sm_TxBuff_Radio4_addr_reg;\nif addrAck " "== 1\n sm_TxBuff_Radio4_addr_reg = xl_slice(linearAddr, 14, 0);\nelse\n sm_TxBuff_Radio4_addr_reg = sm_TxBuff" "_Radio4_addr_reg;\nend\npersistent sm_RSSIBuff_Radio1_addr_reg; \nsm_RSSIBuff_Radio1_addr_reg = xl_state(0, {xlUnsi" "gned, 11, 0});\nsm_RSSIBuff_Radio1_addr = sm_RSSIBuff_Radio1_addr_reg;\nif addrAck == 1\n sm_RSSIBuff_Radio1_add" "r_reg = xl_slice(linearAddr, 11, 0);\nelse\n sm_RSSIBuff_Radio1_addr_reg = sm_RSSIBuff_Radio1_addr_reg;\nend\npe" "rsistent sm_RSSIBuff_Radio2_addr_reg; \nsm_RSSIBuff_Radio2_addr_reg = xl_state(0, {xlUnsigned, 11, 0});\nsm_RSSIBuf" "f_Radio2_addr = sm_RSSIBuff_Radio2_addr_reg;\nif addrAck == 1\n sm_RSSIBuff_Radio2_addr_reg = xl_slice(linearAdd" "r, 11, 0);\nelse\n sm_RSSIBuff_Radio2_addr_reg = sm_RSSIBuff_Radio2_addr_reg;\nend\npersistent sm_RSSIBuff_Radio" "3_addr_reg; \nsm_RSSIBuff_Radio3_addr_reg = xl_state(0, {xlUnsigned, 11, 0});\nsm_RSSIBuff_Radio3_addr = sm_RSSIBuf" "f_Radio3_addr_reg;\nif addrAck == 1\n sm_RSSIBuff_Radio3_addr_reg = xl_slice(linearAddr, 11, 0);\nelse\n sm_R" "SSIBuff_Radio3_addr_reg = sm_RSSIBuff_Radio3_addr_reg;\nend\npersistent sm_RSSIBuff_Radio4_addr_reg; \nsm_RSSIBuff_" "Radio4_addr_reg = xl_state(0, {xlUnsigned, 11, 0});\nsm_RSSIBuff_Radio4_addr = sm_RSSIBuff_Radio4_addr_reg;\nif add" "rAck == 1\n sm_RSSIBuff_Radio4_addr_reg = xl_slice(linearAddr, 11, 0);\nelse\n sm_RSSIBuff_Radio4_addr_reg = " "sm_RSSIBuff_Radio4_addr_reg;\nend\n\n\n% 're' ports of 'From FIFO' blocks\n\n\n% 'en' ports of 'To Register' blocks" "\nif opCode == xl_concat(xfix({xlUnsigned, 4, 0}, 10), ...\n xfix({xlUnsigned, xl_nbits(linea" "rAddr), 0}, 0))\n sm_DCO_EN_SEL_en = true;\nelse\n sm_DCO_EN_SEL_en = false;\nend\nif opCode == xl_concat(xfi" "x({xlUnsigned, 4, 0}, 10), ...\n xfix({xlUnsigned, xl_nbits(linearAddr), 0}, 1))\n sm_Debu" "gRx1Buffers_en = true;\nelse\n sm_DebugRx1Buffers_en = false;\nend\nif opCode == xl_concat(xfix({xlUnsigned, 4, " "0}, 10), ...\n xfix({xlUnsigned, xl_nbits(linearAddr), 0}, 2))\n sm_DebugRx2Buffers_en = t" "rue;\nelse\n sm_DebugRx2Buffers_en = false;\nend\nif opCode == xl_concat(xfix({xlUnsigned, 4, 0}, 10), ...\n " " xfix({xlUnsigned, xl_nbits(linearAddr), 0}, 3))\n sm_DebugRx3Buffers_en = true;\nelse\n sm" "_DebugRx3Buffers_en = false;\nend\nif opCode == xl_concat(xfix({xlUnsigned, 4, 0}, 10), ...\n " " xfix({xlUnsigned, xl_nbits(linearAddr), 0}, 4))\n sm_DebugRx4Buffers_en = true;\nelse\n sm_DebugRx4Buffers_e" "n = false;\nend\nif opCode == xl_concat(xfix({xlUnsigned, 4, 0}, 10), ...\n xfix({xlUnsigned," " xl_nbits(linearAddr), 0}, 5))\n sm_MGC_AGC_SEL_en = true;\nelse\n sm_MGC_AGC_SEL_en = false;\nend\nif opCode" " == xl_concat(xfix({xlUnsigned, 4, 0}, 10), ...\n xfix({xlUnsigned, xl_nbits(linearAddr), 0}," " 6))\n sm_RADIO1RXBUFF_RXEN_en = true;\nelse\n sm_RADIO1RXBUFF_RXEN_en = false;\nend\nif opCode == xl_concat(" "xfix({xlUnsigned, 4, 0}, 10), ...\n xfix({xlUnsigned, xl_nbits(linearAddr), 0}, 7))\n sm_R" "ADIO1TXBUFF_TXEN_en = true;\nelse\n sm_RADIO1TXBUFF_TXEN_en = false;\nend\nif opCode == xl_concat(xfix({xlUnsign" "ed, 4, 0}, 10), ...\n xfix({xlUnsigned, xl_nbits(linearAddr), 0}, 8))\n sm_RADIO2RXBUFF_RX" "EN_en = true;\nelse\n sm_RADIO2RXBUFF_RXEN_en = false;\nend\nif opCode == xl_concat(xfix({xlUnsigned, 4, 0}, 10)" ", ...\n xfix({xlUnsigned, xl_nbits(linearAddr), 0}, 9))\n sm_RADIO2TXBUFF_TXEN_en = true;\n" "else\n sm_RADIO2TXBUFF_TXEN_en = false;\nend\nif opCode == xl_concat(xfix({xlUnsigned, 4, 0}, 10), ...\n " " xfix({xlUnsigned, xl_nbits(linearAddr), 0}, 10))\n sm_RADIO3RXBUFF_RXEN_en = true;\nelse\n sm_" "RADIO3RXBUFF_RXEN_en = false;\nend\nif opCode == xl_concat(xfix({xlUnsigned, 4, 0}, 10), ...\n " " xfix({xlUnsigned, xl_nbits(linearAddr), 0}, 11))\n sm_RADIO3TXBUFF_TXEN_en = true;\nelse\n sm_RADIO3TXBUFF_" "TXEN_en = false;\nend\nif opCode == xl_concat(xfix({xlUnsigned, 4, 0}, 10), ...\n xfix({xlUns" "igned, xl_nbits(linearAddr), 0}, 12))\n sm_RADIO4RXBUFF_RXEN_en = true;\nelse\n sm_RADIO4RXBUFF_RXEN_en = fal" "se;\nend\nif opCode == xl_concat(xfix({xlUnsigned, 4, 0}, 10), ...\n xfix({xlUnsigned, xl_nbi" "ts(linearAddr), 0}, 13))\n sm_RADIO4TXBUFF_TXEN_en = true;\nelse\n sm_RADIO4TXBUFF_TXEN_en = false;\nend\nif " "opCode == xl_concat(xfix({xlUnsigned, 4, 0}, 10), ...\n xfix({xlUnsigned, xl_nbits(linearAddr" "), 0}, 14))\n sm_StartCapture_en = true;\nelse\n sm_StartCapture_en = false;\nend\nif opCode == xl_concat(xfi" "x({xlUnsigned, 4, 0}, 10), ...\n xfix({xlUnsigned, xl_nbits(linearAddr), 0}, 15))\n sm_Sta" "rtTx_en = true;\nelse\n sm_StartTx_en = false;\nend\nif opCode == xl_concat(xfix({xlUnsigned, 4, 0}, 10), ...\n " " xfix({xlUnsigned, xl_nbits(linearAddr), 0}, 16))\n sm_StopTx_en = true;\nelse\n sm_Stop" "Tx_en = false;\nend\nif opCode == xl_concat(xfix({xlUnsigned, 4, 0}, 10), ...\n xfix({xlUnsig" "ned, xl_nbits(linearAddr), 0}, 17))\n sm_TransMode_en = true;\nelse\n sm_TransMode_en = false;\nend\nif opCod" "e == xl_concat(xfix({xlUnsigned, 4, 0}, 10), ...\n xfix({xlUnsigned, xl_nbits(linearAddr), 0}" ", 18))\n sm_TxDelay_en = true;\nelse\n sm_TxDelay_en = false;\nend\nif opCode == xl_concat(xfix({xlUnsigned, " "4, 0}, 10), ...\n xfix({xlUnsigned, xl_nbits(linearAddr), 0}, 19))\n sm_TxLength_en = true" ";\nelse\n sm_TxLength_en = false;\nend\nif opCode == xl_concat(xfix({xlUnsigned, 4, 0}, 10), ...\n " " xfix({xlUnsigned, xl_nbits(linearAddr), 0}, 20))\n sm_StartTxRx_en = true;\nelse\n sm_StartTxRx_en =" " false;\nend\n\n\n% 'din' ports of 'To FIFO' blocks\n\n\n% 'we' ports of 'To FIFO' blocks\n\n\n% 'din' ports of 'To" " Register' blocks\nsm_DCO_EN_SEL_din = xl_force(xl_slice(wrDBus, 1 - 1, 0), ...\n x" "lUnsigned, ...\n 0);\nsm_DebugRx1Buffers_din = xl_force(xl_slice(wrDBus, 1 - 1, 0)," " ...\n xlUnsigned, ...\n 0);\nsm_DebugRx2Buffers_di" "n = xl_force(xl_slice(wrDBus, 1 - 1, 0), ...\n xlUnsigned, ...\n " " 0);\nsm_DebugRx3Buffers_din = xl_force(xl_slice(wrDBus, 1 - 1, 0), ...\n " " xlUnsigned, ...\n 0);\nsm_DebugRx4Buffers_din = xl_force(xl_slice(wrDBus, 1 - 1" ", 0), ...\n xlUnsigned, ...\n 0);\nsm_MGC_AGC_SEL_d" "in = xl_force(xl_slice(wrDBus, 1 - 1, 0), ...\n xlUnsigned, ...\n " " 0);\nsm_RADIO1RXBUFF_RXEN_din = xl_force(xl_slice(wrDBus, 1 - 1, 0), ...\n " " xlUnsigned, ...\n 0);\nsm_RADIO1TXBUFF_TXEN_din = xl_force(xl_slice(wrDBus, " "1 - 1, 0), ...\n xlUnsigned, ...\n 0);\nsm_RADIO2RX" "BUFF_RXEN_din = xl_force(xl_slice(wrDBus, 1 - 1, 0), ...\n xlUnsigned, ...\n " " 0);\nsm_RADIO2TXBUFF_TXEN_din = xl_force(xl_slice(wrDBus, 1 - 1, 0), ...\n " " xlUnsigned, ...\n 0);\nsm_RADIO3RXBUFF_RXEN_din = xl_force(xl_sli" "ce(wrDBus, 1 - 1, 0), ...\n xlUnsigned, ...\n 0);\n" "sm_RADIO3TXBUFF_TXEN_din = xl_force(xl_slice(wrDBus, 1 - 1, 0), ...\n xlUnsigned, ." "..\n 0);\nsm_RADIO4RXBUFF_RXEN_din = xl_force(xl_slice(wrDBus, 1 - 1, 0), ...\n " " xlUnsigned, ...\n 0);\nsm_RADIO4TXBUFF_TXEN_din = xl_f" "orce(xl_slice(wrDBus, 1 - 1, 0), ...\n xlUnsigned, ...\n " " 0);\nsm_StartCapture_din = xl_force(xl_slice(wrDBus, 1 - 1, 0), ...\n xlUnsig" "ned, ...\n 0);\nsm_StartTx_din = xl_force(xl_slice(wrDBus, 1 - 1, 0), ...\n " " xlUnsigned, ...\n 0);\nsm_StopTx_din = xl_force(xl_slice(w" "rDBus, 1 - 1, 0), ...\n xlUnsigned, ...\n 0);\nsm_T" "ransMode_din = xl_force(xl_slice(wrDBus, 1 - 1, 0), ...\n xlUnsigned, ...\n " " 0);\nsm_TxDelay_din = xl_force(xl_slice(wrDBus, 14 - 1, 0), ...\n " " xlUnsigned, ...\n 0);\nsm_TxLength_din = xl_force(xl_slice(wrDBus, 14 - 1, " "0), ...\n xlUnsigned, ...\n 0);\nsm_StartTxRx_din =" " xl_force(xl_slice(wrDBus, 1 - 1, 0), ...\n xlUnsigned, ...\n " " 0);\n\n\npersistent read_bank_out_reg; read_bank_out_reg = xl_state(0, {xlUnsigned, 32, 0});\nread_bank_" "out = read_bank_out_reg;\n\npersistent bankAddr_reg; bankAddr_reg = xl_state(0, bankAddr);\n\nif bankAddr_reg == 0\n" " % Bank 0: Shared Memories\n read_bank_out_reg = ram_bank_out;\nelseif bankAddr_reg == 1\n % Bank 1: From/" "To FIFOs\n read_bank_out_reg = 0;\nelseif bankAddr_reg == 2\n % Bank 2: From/To Registers\n read_bank_out" "_reg = reg_bank_out;\nelseif bankAddr_reg == 3\n % Bank 3: Configuration Registers\n read_bank_out_reg = 0;\n" "end\n\nbankAddr_reg = bankAddr;\n" suppress_output "on" defparams "{}" hide_port_list "{}" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mcode" sg_icon_stat "170,392,44,79,white,blue,0,926ade75,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 170 170 0 0 ],[0 0 392 392 0 ],[0.77 0.82 " "0.91 ]);\nplot([0 170 170 0 0 ],[0 0 392 392 0 ]);\npatch([31.6 66.28 90.28 114.28 138.28 90.28 55.6 31.6 ],[222.64" " 222.64 246.64 222.64 246.64 246.64 246.64 222.64 ],[1 1 1 ]);\npatch([55.6 90.28 66.28 31.6 55.6 ],[198.64 198.64 " "222.64 222.64 198.64 ],[0.931 0.946 0.973 ]);\npatch([31.6 66.28 90.28 55.6 31.6 ],[174.64 174.64 198.64 198.64 174" ".64 ],[1 1 1 ]);\npatch([55.6 138.28 114.28 90.28 66.28 31.6 55.6 ],[150.64 150.64 174.64 150.64 174.64 174.64 150." "64 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\nco" "lor('black');port_label('input',1,'wrDBus');\ncolor('black');port_label('input',2,'bankAddr');\ncolor('black');port" "_label('input',3,'linearAddr');\ncolor('black');port_label('input',4,'RNWReg');\ncolor('black');port_label('input'," "5,'addrAck');\ncolor('black');port_label('input',6,'sm_AGCDoneAddr');\ncolor('black');port_label('input',7,'sm_Capt" "ureDone');\ncolor('black');port_label('input',8,'sm_Radio1AGCDoneRSSI');\ncolor('black');port_label('input',9,'sm_R" "adio2AGCDoneRSSI');\ncolor('black');port_label('input',10,'sm_Radio3AGCDoneRSSI');\ncolor('black');port_label('inpu" "t',11,'sm_Radio4AGCDoneRSSI');\ncolor('black');port_label('input',12,'sm_DCO_EN_SEL');\ncolor('black');port_label('" "input',13,'sm_DebugRx1Buffers');\ncolor('black');port_label('input',14,'sm_DebugRx2Buffers');\ncolor('black');port_" "label('input',15,'sm_DebugRx3Buffers');\ncolor('black');port_label('input',16,'sm_DebugRx4Buffers');\ncolor('black'" ");port_label('input',17,'sm_MGC_AGC_SEL');\ncolor('black');port_label('input',18,'sm_RADIO1RXBUFF_RXEN');\ncolor('b" "lack');port_label('input',19,'sm_RADIO1TXBUFF_TXEN');\ncolor('black');port_label('input',20,'sm_RADIO2RXBUFF_RXEN')" ";\ncolor('black');port_label('input',21,'sm_RADIO2TXBUFF_TXEN');\ncolor('black');port_label('input',22,'sm_RADIO3RX" "BUFF_RXEN');\ncolor('black');port_label('input',23,'sm_RADIO3TXBUFF_TXEN');\ncolor('black');port_label('input',24,'" "sm_RADIO4RXBUFF_RXEN');\ncolor('black');port_label('input',25,'sm_RADIO4TXBUFF_TXEN');\ncolor('black');port_label('" "input',26,'sm_StartCapture');\ncolor('black');port_label('input',27,'sm_StartTx');\ncolor('black');port_label('inpu" "t',28,'sm_StopTx');\ncolor('black');port_label('input',29,'sm_TransMode');\ncolor('black');port_label('input',30,'s" "m_TxDelay');\ncolor('black');port_label('input',31,'sm_TxLength');\ncolor('black');port_label('input',32,'sm_StartT" "xRx');\ncolor('black');port_label('input',33,'sm_RxBuff_Radio1');\ncolor('black');port_label('input',34,'sm_RxBuff_" "Radio2');\ncolor('black');port_label('input',35,'sm_RxBuff_Radio3');\ncolor('black');port_label('input',36,'sm_RxBu" "ff_Radio4');\ncolor('black');port_label('input',37,'sm_TxBuff_Radio1');\ncolor('black');port_label('input',38,'sm_T" "xBuff_Radio2');\ncolor('black');port_label('input',39,'sm_TxBuff_Radio3');\ncolor('black');port_label('input',40,'s" "m_TxBuff_Radio4');\ncolor('black');port_label('input',41,'sm_RSSIBuff_Radio1');\ncolor('black');port_label('input'," "42,'sm_RSSIBuff_Radio2');\ncolor('black');port_label('input',43,'sm_RSSIBuff_Radio3');\ncolor('black');port_label('" "input',44,'sm_RSSIBuff_Radio4');\ncolor('black');port_label('output',1,'read_bank_out');\ncolor('black');port_label" "('output',2,'sm_DCO_EN_SEL_din');\ncolor('black');port_label('output',3,'sm_DCO_EN_SEL_en');\ncolor('black');port_l" "abel('output',4,'sm_DebugRx1Buffers_din');\ncolor('black');port_label('output',5,'sm_DebugRx1Buffers_en');\ncolor('" "black');port_label('output',6,'sm_DebugRx2Buffers_din');\ncolor('black');port_label('output',7,'sm_DebugRx2Buffers_" "en');\ncolor('black');port_label('output',8,'sm_DebugRx3Buffers_din');\ncolor('black');port_label('output',9,'sm_De" "bugRx3Buffers_en');\ncolor('black');port_label('output',10,'sm_DebugRx4Buffers_din');\ncolor('black');port_label('o" "utput',11,'sm_DebugRx4Buffers_en');\ncolor('black');port_label('output',12,'sm_MGC_AGC_SEL_din');\ncolor('black');p" "ort_label('output',13,'sm_MGC_AGC_SEL_en');\ncolor('black');port_label('output',14,'sm_RADIO1RXBUFF_RXEN_din');\nco" "lor('black');port_label('output',15,'sm_RADIO1RXBUFF_RXEN_en');\ncolor('black');port_label('output',16,'sm_RADIO1TX" "BUFF_TXEN_din');\ncolor('black');port_label('output',17,'sm_RADIO1TXBUFF_TXEN_en');\ncolor('black');port_label('out" "put',18,'sm_RADIO2RXBUFF_RXEN_din');\ncolor('black');port_label('output',19,'sm_RADIO2RXBUFF_RXEN_en');\ncolor('bla" "ck');port_label('output',20,'sm_RADIO2TXBUFF_TXEN_din');\ncolor('black');port_label('output',21,'sm_RADIO2TXBUFF_TX" "EN_en');\ncolor('black');port_label('output',22,'sm_RADIO3RXBUFF_RXEN_din');\ncolor('black');port_label('output',23" ",'sm_RADIO3RXBUFF_RXEN_en');\ncolor('black');port_label('output',24,'sm_RADIO3TXBUFF_TXEN_din');\ncolor('black');po" "rt_label('output',25,'sm_RADIO3TXBUFF_TXEN_en');\ncolor('black');port_label('output',26,'sm_RADIO4RXBUFF_RXEN_din')" ";\ncolor('black');port_label('output',27,'sm_RADIO4RXBUFF_RXEN_en');\ncolor('black');port_label('output',28,'sm_RAD" "IO4TXBUFF_TXEN_din');\ncolor('black');port_label('output',29,'sm_RADIO4TXBUFF_TXEN_en');\ncolor('black');port_label" "('output',30,'sm_StartCapture_din');\ncolor('black');port_label('output',31,'sm_StartCapture_en');\ncolor('black');" "port_label('output',32,'sm_StartTx_din');\ncolor('black');port_label('output',33,'sm_StartTx_en');\ncolor('black');" "port_label('output',34,'sm_StopTx_din');\ncolor('black');port_label('output',35,'sm_StopTx_en');\ncolor('black');po" "rt_label('output',36,'sm_TransMode_din');\ncolor('black');port_label('output',37,'sm_TransMode_en');\ncolor('black'" ");port_label('output',38,'sm_TxDelay_din');\ncolor('black');port_label('output',39,'sm_TxDelay_en');\ncolor('black'" ");port_label('output',40,'sm_TxLength_din');\ncolor('black');port_label('output',41,'sm_TxLength_en');\ncolor('blac" "k');port_label('output',42,'sm_StartTxRx_din');\ncolor('black');port_label('output',43,'sm_StartTxRx_en');\ncolor('" "black');port_label('output',44,'sm_RxBuff_Radio1_addr');\ncolor('black');port_label('output',45,'sm_RxBuff_Radio1_d" "in');\ncolor('black');port_label('output',46,'sm_RxBuff_Radio1_we');\ncolor('black');port_label('output',47,'sm_RxB" "uff_Radio2_addr');\ncolor('black');port_label('output',48,'sm_RxBuff_Radio2_din');\ncolor('black');port_label('outp" "ut',49,'sm_RxBuff_Radio2_we');\ncolor('black');port_label('output',50,'sm_RxBuff_Radio3_addr');\ncolor('black');por" "t_label('output',51,'sm_RxBuff_Radio3_din');\ncolor('black');port_label('output',52,'sm_RxBuff_Radio3_we');\ncolor(" "'black');port_label('output',53,'sm_RxBuff_Radio4_addr');\ncolor('black');port_label('output',54,'sm_RxBuff_Radio4_" "din');\ncolor('black');port_label('output',55,'sm_RxBuff_Radio4_we');\ncolor('black');port_label('output',56,'sm_Tx" "Buff_Radio1_addr');\ncolor('black');port_label('output',57,'sm_TxBuff_Radio1_din');\ncolor('black');port_label('out" "put',58,'sm_TxBuff_Radio1_we');\ncolor('black');port_label('output',59,'sm_TxBuff_Radio2_addr');\ncolor('black');po" "rt_label('output',60,'sm_TxBuff_Radio2_din');\ncolor('black');port_label('output',61,'sm_TxBuff_Radio2_we');\ncolor" "('black');port_label('output',62,'sm_TxBuff_Radio3_addr');\ncolor('black');port_label('output',63,'sm_TxBuff_Radio3" "_din');\ncolor('black');port_label('output',64,'sm_TxBuff_Radio3_we');\ncolor('black');port_label('output',65,'sm_T" "xBuff_Radio4_addr');\ncolor('black');port_label('output',66,'sm_TxBuff_Radio4_din');\ncolor('black');port_label('ou" "tput',67,'sm_TxBuff_Radio4_we');\ncolor('black');port_label('output',68,'sm_RSSIBuff_Radio1_addr');\ncolor('black')" ";port_label('output',69,'sm_RSSIBuff_Radio1_din');\ncolor('black');port_label('output',70,'sm_RSSIBuff_Radio1_we');" "\ncolor('black');port_label('output',71,'sm_RSSIBuff_Radio2_addr');\ncolor('black');port_label('output',72,'sm_RSSI" "Buff_Radio2_din');\ncolor('black');port_label('output',73,'sm_RSSIBuff_Radio2_we');\ncolor('black');port_label('out" "put',74,'sm_RSSIBuff_Radio3_addr');\ncolor('black');port_label('output',75,'sm_RSSIBuff_Radio3_din');\ncolor('black" "');port_label('output',76,'sm_RSSIBuff_Radio3_we');\ncolor('black');port_label('output',77,'sm_RSSIBuff_Radio4_addr" "');\ncolor('black');port_label('output',78,'sm_RSSIBuff_Radio4_din');\ncolor('black');port_label('output',79,'sm_RS" "SIBuff_Radio4_we');\ncolor('black');disp('\\bf{xlmax}','texmode','on');\nfprintf('','COMMENT: end icon text');" Port { PortNumber 1 Name "rdData" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 2 Name "DCO_EN_SEL_din" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 3 Name "DCO_EN_SEL_en" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 4 Name "DebugRx1Buffers_din" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 5 Name "DebugRx1Buffers_en" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 6 Name "DebugRx2Buffers_din" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 7 Name "DebugRx2Buffers_en" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 8 Name "DebugRx3Buffers_din" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 9 Name "DebugRx3Buffers_en" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 10 Name "DebugRx4Buffers_din" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 11 Name "DebugRx4Buffers_en" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 12 Name "MGC_AGC_SEL_din" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 13 Name "MGC_AGC_SEL_en" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 14 Name "RADIO1RXBUFF_RXEN_din" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 15 Name "RADIO1RXBUFF_RXEN_en" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 16 Name "RADIO1TXBUFF_TXEN_din" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 17 Name "RADIO1TXBUFF_TXEN_en" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 18 Name "RADIO2RXBUFF_RXEN_din" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 19 Name "RADIO2RXBUFF_RXEN_en" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 20 Name "RADIO2TXBUFF_TXEN_din" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 21 Name "RADIO2TXBUFF_TXEN_en" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 22 Name "RADIO3RXBUFF_RXEN_din" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 23 Name "RADIO3RXBUFF_RXEN_en" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 24 Name "RADIO3TXBUFF_TXEN_din" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 25 Name "RADIO3TXBUFF_TXEN_en" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 26 Name "RADIO4RXBUFF_RXEN_din" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 27 Name "RADIO4RXBUFF_RXEN_en" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 28 Name "RADIO4TXBUFF_TXEN_din" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 29 Name "RADIO4TXBUFF_TXEN_en" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 30 Name "StartCapture_din" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 31 Name "StartCapture_en" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 32 Name "StartTx_din" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 33 Name "StartTx_en" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 34 Name "StopTx_din" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 35 Name "StopTx_en" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 36 Name "TransMode_din" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 37 Name "TransMode_en" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 38 Name "TxDelay_din" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 39 Name "TxDelay_en" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 40 Name "TxLength_din" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 41 Name "TxLength_en" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 42 Name "StartTxRx_din" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 43 Name "StartTxRx_en" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 44 Name "RxBuff_Radio1_addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 45 Name "RxBuff_Radio1_din" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 46 Name "RxBuff_Radio1_we" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 47 Name "RxBuff_Radio2_addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 48 Name "RxBuff_Radio2_din" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 49 Name "RxBuff_Radio2_we" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 50 Name "RxBuff_Radio3_addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 51 Name "RxBuff_Radio3_din" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 52 Name "RxBuff_Radio3_we" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 53 Name "RxBuff_Radio4_addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 54 Name "RxBuff_Radio4_din" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 55 Name "RxBuff_Radio4_we" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 56 Name "TxBuff_Radio1_addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 57 Name "TxBuff_Radio1_din" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 58 Name "TxBuff_Radio1_we" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 59 Name "TxBuff_Radio2_addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 60 Name "TxBuff_Radio2_din" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 61 Name "TxBuff_Radio2_we" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 62 Name "TxBuff_Radio3_addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 63 Name "TxBuff_Radio3_din" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 64 Name "TxBuff_Radio3_we" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 65 Name "TxBuff_Radio4_addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 66 Name "TxBuff_Radio4_din" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 67 Name "TxBuff_Radio4_we" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 68 Name "RSSIBuff_Radio1_addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 69 Name "RSSIBuff_Radio1_din" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 70 Name "RSSIBuff_Radio1_we" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 71 Name "RSSIBuff_Radio2_addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 72 Name "RSSIBuff_Radio2_din" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 73 Name "RSSIBuff_Radio2_we" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 74 Name "RSSIBuff_Radio3_addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 75 Name "RSSIBuff_Radio3_din" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 76 Name "RSSIBuff_Radio3_we" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 77 Name "RSSIBuff_Radio4_addr" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 78 Name "RSSIBuff_Radio4_din" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 79 Name "RSSIBuff_Radio4_we" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "sg_plb_addrpref" SID "6:95" Ports [1, 1] Position [110, 915, 175, 935] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, single, double and fixed point to Xilinx" " fixed-point or floating-point data type.

Hardware notes: In hardware these blocks become top level input p" "orts." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "10" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "xlGetNormalizedPeriod()" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off UseAsADC off ADCChannel "'1'" hdl_port "on" sginterface "{'Xilinx'=>{'jtaghwcosim'=>{'non_memory_mapped_port'=>'sg_plb_addrpref'}},'iopad'=>{'constraint'=>'" "#'}}" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayin" sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.65" " ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'" "\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT: end ic" "on text');" Port { PortNumber 1 Name "addrPref" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Line { Name "Sl_addrAck" SrcBlock "plb_decode" SrcPort 2 Points [0, 0] Branch { Labels [1, 0] Points [5, 0; 0, 1135] DstBlock "plb_memmap" DstPort 5 } Branch { Labels [0, 0] Points [30, 0; 0, -505] DstBlock "Sl_addrAck" DstPort 1 } } Line { Name "Sl_wrDAck" SrcBlock "plb_decode" SrcPort 4 Points [0, 0] Branch { Labels [1, 0] Points [30, 0; 0, -315] DstBlock "Sl_wrDAck" DstPort 1 } Branch { Labels [0, 0] Points [30, 0; 0, -30] DstBlock "Sl_wrComp" DstPort 1 } } Line { Name "RSSIBuff_Radio4_we" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 79 Points [5, 0; 0, 1525] DstBlock "Shared Memory11" DstPort 3 } Line { Name "RSSIBuff_Radio4_din" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 78 Points [5, 0; 0, 1500] DstBlock "Shared Memory11" DstPort 2 } Line { Name "RSSIBuff_Radio4_addr" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 77 Points [5, 0; 0, 1475] DstBlock "Shared Memory11" DstPort 1 } Line { Name "RSSIBuff_Radio3_we" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 76 Points [5, 0; 0, 1420] DstBlock "Shared Memory10" DstPort 3 } Line { Name "RSSIBuff_Radio3_din" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 75 Points [5, 0; 0, 1395] DstBlock "Shared Memory10" DstPort 2 } Line { Name "RSSIBuff_Radio3_addr" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 74 Points [5, 0; 0, 1370] DstBlock "Shared Memory10" DstPort 1 } Line { Name "RSSIBuff_Radio2_we" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 73 Points [5, 0; 0, 1315] DstBlock "Shared Memory9" DstPort 3 } Line { Name "RSSIBuff_Radio2_din" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 72 Points [5, 0; 0, 1290] DstBlock "Shared Memory9" DstPort 2 } Line { Name "RSSIBuff_Radio2_addr" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 71 Points [5, 0; 0, 1265] DstBlock "Shared Memory9" DstPort 1 } Line { Name "RSSIBuff_Radio1_we" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 70 Points [5, 0; 0, 1210] DstBlock "Shared Memory8" DstPort 3 } Line { Name "RSSIBuff_Radio1_din" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 69 Points [5, 0; 0, 1185] DstBlock "Shared Memory8" DstPort 2 } Line { Name "RSSIBuff_Radio1_addr" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 68 Points [5, 0; 0, 1160] DstBlock "Shared Memory8" DstPort 1 } Line { Name "TxBuff_Radio4_we" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 67 Points [5, 0; 0, 1100] DstBlock "Shared Memory7" DstPort 3 } Line { Name "TxBuff_Radio4_din" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 66 Points [5, 0; 0, 1075] DstBlock "Shared Memory7" DstPort 2 } Line { Name "TxBuff_Radio4_addr" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 65 Points [5, 0; 0, 1050] DstBlock "Shared Memory7" DstPort 1 } Line { Name "TxBuff_Radio3_we" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 64 Points [5, 0; 0, 995] DstBlock "Shared Memory6" DstPort 3 } Line { Name "TxBuff_Radio3_din" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 63 Points [5, 0; 0, 970] DstBlock "Shared Memory6" DstPort 2 } Line { Name "TxBuff_Radio3_addr" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 62 Points [5, 0; 0, 945] DstBlock "Shared Memory6" DstPort 1 } Line { Name "TxBuff_Radio2_we" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 61 Points [5, 0; 0, 890] DstBlock "Shared Memory5" DstPort 3 } Line { Name "TxBuff_Radio2_din" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 60 Points [5, 0; 0, 865] DstBlock "Shared Memory5" DstPort 2 } Line { Name "TxBuff_Radio2_addr" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 59 Points [5, 0; 0, 840] DstBlock "Shared Memory5" DstPort 1 } Line { Name "TxBuff_Radio1_we" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 58 Points [5, 0; 0, 785] DstBlock "Shared Memory4" DstPort 3 } Line { Name "TxBuff_Radio1_din" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 57 Points [5, 0; 0, 760] DstBlock "Shared Memory4" DstPort 2 } Line { Name "TxBuff_Radio1_addr" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 56 Points [5, 0; 0, 735] DstBlock "Shared Memory4" DstPort 1 } Line { Name "RxBuff_Radio4_we" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 55 Points [5, 0; 0, 675] DstBlock "Shared Memory3" DstPort 3 } Line { Name "RxBuff_Radio4_din" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 54 Points [5, 0; 0, 650] DstBlock "Shared Memory3" DstPort 2 } Line { Name "RxBuff_Radio4_addr" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 53 Points [5, 0; 0, 625] DstBlock "Shared Memory3" DstPort 1 } Line { Name "RxBuff_Radio3_we" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 52 Points [5, 0; 0, 570] DstBlock "Shared Memory2" DstPort 3 } Line { Name "RxBuff_Radio3_din" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 51 Points [5, 0; 0, 545] DstBlock "Shared Memory2" DstPort 2 } Line { Name "RxBuff_Radio3_addr" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 50 Points [5, 0; 0, 520] DstBlock "Shared Memory2" DstPort 1 } Line { Name "RxBuff_Radio2_we" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 49 Points [5, 0; 0, 465] DstBlock "Shared Memory1" DstPort 3 } Line { Name "RxBuff_Radio2_din" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 48 Points [5, 0; 0, 440] DstBlock "Shared Memory1" DstPort 2 } Line { Name "RxBuff_Radio2_addr" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 47 Points [5, 0; 0, 415] DstBlock "Shared Memory1" DstPort 1 } Line { Name "RxBuff_Radio1_we" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 46 Points [5, 0; 0, 355] DstBlock "Shared Memory" DstPort 3 } Line { Name "RxBuff_Radio1_din" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 45 Points [5, 0; 0, 330] DstBlock "Shared Memory" DstPort 2 } Line { Name "RxBuff_Radio1_addr" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 44 Points [10, 0] DstBlock "Shared Memory" DstPort 1 } Line { Name "StartTxRx_en" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 43 Points [15, 0; 0, 255] DstBlock "To Register20" DstPort 2 } Line { Name "StartTxRx_din" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 42 Points [15, 0; 0, 230] DstBlock "To Register20" DstPort 1 } Line { Name "TxLength_en" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 41 Points [15, 0; 0, 175] DstBlock "To Register19" DstPort 2 } Line { Name "TxLength_din" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 40 Points [15, 0; 0, 150] DstBlock "To Register19" DstPort 1 } Line { Name "TxDelay_en" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 39 Points [15, 0; 0, 100] DstBlock "To Register18" DstPort 2 } Line { Name "TxDelay_din" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 38 Points [15, 0; 0, 75] DstBlock "To Register18" DstPort 1 } Line { Name "TransMode_en" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 37 Points [15, 0; 0, 25] DstBlock "To Register17" DstPort 2 } Line { Name "TransMode_din" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 36 DstBlock "To Register17" DstPort 1 } Line { Name "StopTx_en" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 35 Points [15, 0; 0, -55] DstBlock "To Register16" DstPort 2 } Line { Name "StopTx_din" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 34 Points [15, 0; 0, -80] DstBlock "To Register16" DstPort 1 } Line { Name "StartTx_en" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 33 Points [15, 0; 0, -130] DstBlock "To Register15" DstPort 2 } Line { Name "StartTx_din" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 32 Points [15, 0; 0, -155] DstBlock "To Register15" DstPort 1 } Line { Name "StartCapture_en" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 31 Points [15, 0; 0, -205] DstBlock "To Register14" DstPort 2 } Line { Name "StartCapture_din" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 30 Points [15, 0; 0, -230] DstBlock "To Register14" DstPort 1 } Line { Name "RADIO4TXBUFF_TXEN_en" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 29 Points [15, 0; 0, -285] DstBlock "To Register13" DstPort 2 } Line { Name "RADIO4TXBUFF_TXEN_din" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 28 Points [15, 0; 0, -310] DstBlock "To Register13" DstPort 1 } Line { Name "RADIO4RXBUFF_RXEN_en" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 27 Points [15, 0; 0, -360] DstBlock "To Register12" DstPort 2 } Line { Name "RADIO4RXBUFF_RXEN_din" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 26 Points [15, 0; 0, -385] DstBlock "To Register12" DstPort 1 } Line { Name "RADIO3TXBUFF_TXEN_en" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 25 Points [15, 0; 0, -435] DstBlock "To Register11" DstPort 2 } Line { Name "RADIO3TXBUFF_TXEN_din" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 24 Points [15, 0; 0, -460] DstBlock "To Register11" DstPort 1 } Line { Name "RADIO3RXBUFF_RXEN_en" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 23 Points [15, 0; 0, -515] DstBlock "To Register10" DstPort 2 } Line { Name "RADIO3RXBUFF_RXEN_din" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 22 Points [15, 0; 0, -540] DstBlock "To Register10" DstPort 1 } Line { Name "RADIO2TXBUFF_TXEN_en" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 21 Points [15, 0; 0, -590] DstBlock "To Register9" DstPort 2 } Line { Name "RADIO2TXBUFF_TXEN_din" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 20 Points [15, 0; 0, -615] DstBlock "To Register9" DstPort 1 } Line { Name "RADIO2RXBUFF_RXEN_en" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 19 Points [15, 0; 0, -665] DstBlock "To Register8" DstPort 2 } Line { Name "RADIO2RXBUFF_RXEN_din" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 18 Points [15, 0; 0, -690] DstBlock "To Register8" DstPort 1 } Line { Name "RADIO1TXBUFF_TXEN_en" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 17 Points [15, 0; 0, -745] DstBlock "To Register7" DstPort 2 } Line { Name "RADIO1TXBUFF_TXEN_din" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 16 Points [15, 0; 0, -770] DstBlock "To Register7" DstPort 1 } Line { Name "RADIO1RXBUFF_RXEN_en" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 15 Points [15, 0; 0, -820] DstBlock "To Register6" DstPort 2 } Line { Name "RADIO1RXBUFF_RXEN_din" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 14 Points [15, 0; 0, -845] DstBlock "To Register6" DstPort 1 } Line { Name "MGC_AGC_SEL_en" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 13 Points [15, 0; 0, -895] DstBlock "To Register5" DstPort 2 } Line { Name "MGC_AGC_SEL_din" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 12 Points [15, 0; 0, -920] DstBlock "To Register5" DstPort 1 } Line { Name "DebugRx4Buffers_en" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 11 Points [15, 0; 0, -975] DstBlock "To Register4" DstPort 2 } Line { Name "DebugRx4Buffers_din" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 10 Points [15, 0; 0, -1000] DstBlock "To Register4" DstPort 1 } Line { Name "DebugRx3Buffers_en" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 9 Points [15, 0; 0, -1050] DstBlock "To Register3" DstPort 2 } Line { Name "DebugRx3Buffers_din" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 8 Points [15, 0; 0, -1075] DstBlock "To Register3" DstPort 1 } Line { Name "DebugRx2Buffers_en" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 7 Points [15, 0; 0, -1125] DstBlock "To Register2" DstPort 2 } Line { Name "DebugRx2Buffers_din" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 6 Points [15, 0; 0, -1150] DstBlock "To Register2" DstPort 1 } Line { Name "DebugRx1Buffers_en" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 5 Points [15, 0; 0, -1205] DstBlock "To Register1" DstPort 2 } Line { Name "DebugRx1Buffers_din" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 4 Points [15, 0; 0, -1230] DstBlock "To Register1" DstPort 1 } Line { Name "DCO_EN_SEL_en" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 3 Points [15, 0; 0, -1280] DstBlock "To Register" DstPort 2 } Line { Name "DCO_EN_SEL_din" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 2 Points [15, 0; 0, -1305] DstBlock "To Register" DstPort 1 } Line { Name "rdData" Labels [0, 0; 0, 0] SrcBlock "plb_memmap" SrcPort 1 Points [0, -675; -395, 0; 0, -95] DstBlock "plb_decode" DstPort 6 } Line { Name "RSSIBuff_Radio4_dout" Labels [0, 0; 0, 0] SrcBlock "Shared Memory11" SrcPort 1 Points [0, -65; -300, 0] DstBlock "plb_memmap" DstPort 44 } Line { Name "RSSIBuff_Radio3_dout" Labels [0, 0; 0, 0] SrcBlock "Shared Memory10" SrcPort 1 Points [0, -70; -305, 0; 0, -1395] DstBlock "plb_memmap" DstPort 43 } Line { Name "RSSIBuff_Radio2_dout" Labels [0, 0; 0, 0] SrcBlock "Shared Memory9" SrcPort 1 Points [0, -65; -305, 0; 0, -1285] DstBlock "plb_memmap" DstPort 42 } Line { Name "RSSIBuff_Radio1_dout" Labels [0, 0; 0, 0] SrcBlock "Shared Memory8" SrcPort 1 Points [0, -75; -305, 0; 0, -1165] DstBlock "plb_memmap" DstPort 41 } Line { Name "TxBuff_Radio4_dout" Labels [0, 0; 0, 0] SrcBlock "Shared Memory7" SrcPort 1 Points [0, -70; -305, 0; 0, -1045] DstBlock "plb_memmap" DstPort 40 } Line { Name "TxBuff_Radio3_dout" Labels [0, 0; 0, 0] SrcBlock "Shared Memory6" SrcPort 1 Points [0, -65; -305, 0; 0, -935] DstBlock "plb_memmap" DstPort 39 } Line { Name "TxBuff_Radio2_dout" Labels [0, 0; 0, 0] SrcBlock "Shared Memory5" SrcPort 1 Points [0, -65; -305, 0; 0, -820] DstBlock "plb_memmap" DstPort 38 } Line { Name "TxBuff_Radio1_dout" Labels [0, 0; 0, 0] SrcBlock "Shared Memory4" SrcPort 1 Points [0, -80; -305, 0; 0, -695] DstBlock "plb_memmap" DstPort 37 } Line { Name "RxBuff_Radio4_dout" Labels [0, 0; 0, 0] SrcBlock "Shared Memory3" SrcPort 1 Points [0, -65; -305, 0; 0, -585] DstBlock "plb_memmap" DstPort 36 } Line { Name "RxBuff_Radio3_dout" Labels [0, 0; 0, 0] SrcBlock "Shared Memory2" SrcPort 1 Points [0, -65; -305, 0; 0, -470] DstBlock "plb_memmap" DstPort 35 } Line { Name "RxBuff_Radio2_dout" Labels [0, 0; 0, 0] SrcBlock "Shared Memory1" SrcPort 1 Points [0, -75; -305, 0; 0, -345] DstBlock "plb_memmap" DstPort 34 } Line { Name "RxBuff_Radio1_dout" Labels [0, 0; 0, 0] SrcBlock "Shared Memory" SrcPort 1 Points [0, -150; -305, 0; 0, -150] DstBlock "plb_memmap" DstPort 33 } Line { Name "StartTxRx_dout" Labels [0, 0; 0, 0] SrcBlock "To Register20" SrcPort 1 Points [0, -50; -295, 0; 0, -155] DstBlock "plb_memmap" DstPort 32 } Line { Name "TxLength_dout" Labels [0, 0; 0, 0] SrcBlock "To Register19" SrcPort 1 Points [0, 40; -295, 0; 0, -160] DstBlock "plb_memmap" DstPort 31 } Line { Name "TxDelay_dout" Labels [0, 0; 0, 0] SrcBlock "To Register18" SrcPort 1 Points [0, 50; -95, 0; 0, 75; -200, 0; 0, -165] DstBlock "plb_memmap" DstPort 30 } Line { Name "TransMode_dout" Labels [0, 0; 0, 0] SrcBlock "To Register17" SrcPort 1 Points [0, 50; -95, 0; 0, 160; -200, 0; 0, -170] DstBlock "plb_memmap" DstPort 29 } Line { Name "StopTx_dout" Labels [0, 0; 0, 0] SrcBlock "To Register16" SrcPort 1 Points [0, -50; -95, 0; 0, -55; -200, 0; 0, 230] DstBlock "plb_memmap" DstPort 28 } Line { Name "StartTx_dout" Labels [0, 0; 0, 0] SrcBlock "To Register15" SrcPort 1 Points [0, -35; -295, 0; 0, 240] DstBlock "plb_memmap" DstPort 27 } Line { Name "StartCapture_dout" Labels [0, 0; 0, 0] SrcBlock "To Register14" SrcPort 1 Points [0, 50; -295, 0; 0, 235] DstBlock "plb_memmap" DstPort 26 } Line { Name "RADIO4TXBUFF_TXEN_dout" Labels [0, 0; 0, 0] SrcBlock "To Register13" SrcPort 1 Points [0, 55; -295, 0; 0, 315] DstBlock "plb_memmap" DstPort 25 } Line { Name "RADIO4RXBUFF_RXEN_dout" Labels [0, 0; 0, 0] SrcBlock "To Register12" SrcPort 1 Points [0, 50; -295, 0; 0, 400] DstBlock "plb_memmap" DstPort 24 } Line { Name "RADIO3TXBUFF_TXEN_dout" Labels [0, 0; 0, 0] SrcBlock "To Register11" SrcPort 1 Points [0, 50; -295, 0; 0, 480] DstBlock "plb_memmap" DstPort 23 } Line { Name "RADIO3RXBUFF_RXEN_dout" Labels [0, 0; 0, 0] SrcBlock "To Register10" SrcPort 1 Points [0, 55; -295, 0; 0, 560] DstBlock "plb_memmap" DstPort 22 } Line { Name "RADIO2TXBUFF_TXEN_dout" Labels [0, 0; 0, 0] SrcBlock "To Register9" SrcPort 1 Points [0, 50; -295, 0; 0, 645] DstBlock "plb_memmap" DstPort 21 } Line { Name "RADIO2RXBUFF_RXEN_dout" Labels [0, 0; 0, 0] SrcBlock "To Register8" SrcPort 1 Points [0, 50; -295, 0; 0, 725] DstBlock "plb_memmap" DstPort 20 } Line { Name "RADIO1TXBUFF_TXEN_dout" Labels [0, 0; 0, 0] SrcBlock "To Register7" SrcPort 1 Points [0, 55; -295, 0; 0, 805] DstBlock "plb_memmap" DstPort 19 } Line { Name "RADIO1RXBUFF_RXEN_dout" Labels [0, 0; 0, 0] SrcBlock "To Register6" SrcPort 1 Points [0, 50; -295, 0; 0, 890] DstBlock "plb_memmap" DstPort 18 } Line { Name "MGC_AGC_SEL_dout" Labels [0, 0; 0, 0] SrcBlock "To Register5" SrcPort 1 Points [0, 50; -150, 0; 0, 795; -145, 0; 0, 175] DstBlock "plb_memmap" DstPort 17 } Line { Name "DebugRx4Buffers_dout" Labels [0, 0; 0, 0] SrcBlock "To Register4" SrcPort 1 Points [0, 55; -150, 0; 0, 880; -145, 0; 0, 170] DstBlock "plb_memmap" DstPort 16 } Line { Name "DebugRx3Buffers_dout" Labels [0, 0; 0, 0] SrcBlock "To Register3" SrcPort 1 Points [0, 50; -150, 0; 0, 970; -145, 0; 0, 165] DstBlock "plb_memmap" DstPort 15 } Line { Name "DebugRx2Buffers_dout" Labels [0, 0; 0, 0] SrcBlock "To Register2" SrcPort 1 Points [0, 50; -295, 0; 0, 1215] DstBlock "plb_memmap" DstPort 14 } Line { Name "DebugRx1Buffers_dout" Labels [0, 0; 0, 0] SrcBlock "To Register1" SrcPort 1 Points [0, 55; -295, 0; 0, 1295] DstBlock "plb_memmap" DstPort 13 } Line { Name "DCO_EN_SEL_dout" Labels [0, 0; 0, 0] SrcBlock "To Register" SrcPort 1 Points [0, 50; -295, 0; 0, 1380] DstBlock "plb_memmap" DstPort 12 } Line { Name "Radio4AGCDoneRSSI_dout" Labels [0, 0; 0, 0] SrcBlock "From Register5" SrcPort 1 Points [60, 0; 0, -145] DstBlock "plb_memmap" DstPort 11 } Line { Name "Radio3AGCDoneRSSI_dout" Labels [0, 0; 0, 0] SrcBlock "From Register4" SrcPort 1 Points [60, 0; 0, -65] DstBlock "plb_memmap" DstPort 10 } Line { Name "Radio2AGCDoneRSSI_dout" Labels [0, 0; 0, 0] SrcBlock "From Register3" SrcPort 1 Points [60, 0; 0, 15] DstBlock "plb_memmap" DstPort 9 } Line { Name "Radio1AGCDoneRSSI_dout" Labels [0, 0; 0, 0] SrcBlock "From Register2" SrcPort 1 Points [60, 0; 0, 100] DstBlock "plb_memmap" DstPort 8 } Line { Name "CaptureDone_dout" Labels [0, 0; 0, 0] SrcBlock "From Register1" SrcPort 1 Points [60, 0; 0, 180] DstBlock "plb_memmap" DstPort 7 } Line { Name "AGCDoneAddr_dout" Labels [0, 0; 0, 0] SrcBlock "From Register" SrcPort 1 Points [60, 0; 0, 260] DstBlock "plb_memmap" DstPort 6 } Line { Name "RNWReg" Labels [0, 0; 0, 0] SrcBlock "plb_decode" SrcPort 6 Points [5, 0; 0, 950] DstBlock "plb_memmap" DstPort 4 } Line { Name "linearAddr" Labels [0, 0; 0, 0] SrcBlock "plb_decode" SrcPort 9 Points [5, 0; 0, 810] DstBlock "plb_memmap" DstPort 3 } Line { Name "bankAddr" Labels [0, 0; 0, 0] SrcBlock "plb_decode" SrcPort 5 Points [5, 0; 0, 985] DstBlock "plb_memmap" DstPort 2 } Line { Name "wrDBusReg" Labels [0, 0; 0, 0] SrcBlock "plb_decode" SrcPort 1 Points [10, 0] DstBlock "plb_memmap" DstPort 1 } Line { Name "Sl_rdDBus" Labels [0, 0; 0, 0] SrcBlock "plb_decode" SrcPort 8 Points [65, 0] DstBlock "Sl_rdDBus" DstPort 1 } Line { Name "Sl_rdDAck" Labels [0, 0; 0, 0] SrcBlock "plb_decode" SrcPort 7 Points [65, 0] DstBlock "Sl_rdDAck" DstPort 1 } Line { Name "Sl_rdComp" Labels [0, 0; 0, 0] SrcBlock "plb_decode" SrcPort 3 Points [60, 0; 0, -440] DstBlock "Sl_rdComp" DstPort 1 } Line { Name "addrPref" Labels [0, 0; 0, 0] SrcBlock "sg_plb_addrpref" SrcPort 1 Points [10, 0] DstBlock "plb_decode" DstPort 7 } Line { Name "PLB_wrDBus" Labels [0, 0; 0, 0] SrcBlock "PLB_wrDBus" SrcPort 1 DstBlock "plb_decode" DstPort 5 } Line { Name "PLB_RNW" Labels [0, 0; 0, 0] SrcBlock "PLB_RNW" SrcPort 1 DstBlock "plb_decode" DstPort 4 } Line { Name "PLB_PAValid" Labels [0, 0; 0, 0] SrcBlock "PLB_PAValid" SrcPort 1 DstBlock "plb_decode" DstPort 3 } Line { Name "PLB_ABus" Labels [0, 0; 0, 0] SrcBlock "PLB_ABus" SrcPort 1 Points [5, 0; 0, -5] DstBlock "plb_decode" DstPort 2 } Line { Name "SPLB_Rst" Labels [0, 0; 0, 0] SrcBlock "SPLB_Rst" SrcPort 1 Points [5, 0; 0, -5] DstBlock "plb_decode" DstPort 1 } Line { SrcBlock "Constant6" SrcPort 1 DstBlock "sg_plb_addrpref" DstPort 1 } Line { Name "Sl_wait" Labels [0, 0; 0, 0] SrcBlock "Constant5" SrcPort 1 DstBlock "Sl_wait" DstPort 1 } Line { SrcBlock "Constant4" SrcPort 1 DstBlock "PLB_wrDBus" DstPort 1 } Line { SrcBlock "Constant3" SrcPort 1 DstBlock "PLB_RNW" DstPort 1 } Line { SrcBlock "Constant2" SrcPort 1 DstBlock "PLB_PAValid" DstPort 1 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "PLB_ABus" DstPort 1 } Line { SrcBlock "Constant" SrcPort 1 DstBlock "SPLB_Rst" DstPort 1 } Line { SrcBlock "Sl_wrComp" SrcPort 1 Points [70, 0; 0, -485] DstBlock "Terminator6" DstPort 1 } Line { SrcBlock "Sl_wrDAck" SrcPort 1 Points [70, 0; 0, -250] DstBlock "Terminator5" DstPort 1 } Line { SrcBlock "Sl_wait" SrcPort 1 DstBlock "Terminator4" DstPort 1 } Line { SrcBlock "Sl_rdDBus" SrcPort 1 Points [70, 0; 0, -565] DstBlock "Terminator3" DstPort 1 } Line { SrcBlock "Sl_rdDAck" SrcPort 1 Points [70, 0; 0, -530] DstBlock "Terminator2" DstPort 1 } Line { SrcBlock "Sl_rdComp" SrcPort 1 Points [90, 0; 0, -130] DstBlock "Terminator1" DstPort 1 } Line { SrcBlock "Sl_addrAck" SrcPort 1 Points [45, 0; 0, -70] DstBlock "Terminator" DstPort 1 } } } Block { BlockType From Name "From1" SID "7" Position [115, 766, 250, 784] ShowName off CloseFcn "tagdialog Close" GotoTag "StopTx" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType From Name "From10" SID "8" Position [940, 121, 1075, 139] ShowName off CloseFcn "tagdialog Close" GotoTag "RADIO1RXBUFF_RXEN" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType From Name "From11" SID "9" Position [945, 266, 1080, 284] ShowName off CloseFcn "tagdialog Close" GotoTag "RADIO2RXBUFF_RXEN" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType From Name "From12" SID "10" Position [945, 406, 1080, 424] ShowName off CloseFcn "tagdialog Close" GotoTag "RADIO3RXBUFF_RXEN" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType From Name "From13" SID "11" Position [945, 546, 1080, 564] ShowName off CloseFcn "tagdialog Close" GotoTag "RADIO4RXBUFF_RXEN" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType From Name "From14" SID "12" Position [710, 36, 845, 54] ShowName off CloseFcn "tagdialog Close" GotoTag "DebugRx1Buffers" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType From Name "From15" SID "13" Position [715, 181, 850, 199] ShowName off CloseFcn "tagdialog Close" GotoTag "DebugRx2Buffers" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType From Name "From16" SID "14" Position [715, 316, 850, 334] ShowName off CloseFcn "tagdialog Close" GotoTag "DebugRx3Buffers" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType From Name "From17" SID "15" Position [710, 456, 845, 474] ShowName off CloseFcn "tagdialog Close" GotoTag "DebugRx4Buffers" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType From Name "From18" SID "16" Position [705, 549, 855, 571] ShowName off CloseFcn "tagdialog Close" GotoTag "MGCAGC_AGCDCO_SEL" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType From Name "From19" SID "17" Position [40, 466, 175, 484] ShowName off CloseFcn "tagdialog Close" GotoTag "StartTxRx" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType From Name "From2" SID "18" Position [275, 821, 410, 839] ShowName off CloseFcn "tagdialog Close" GotoTag "TransMode" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType From Name "From3" SID "19" Position [110, 671, 245, 689] ShowName off CloseFcn "tagdialog Close" GotoTag "StartTx" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType From Name "From4" SID "20" Position [270, 896, 405, 914] ShowName off CloseFcn "tagdialog Close" GotoTag "TxDelay" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType From Name "From5" SID "21" Position [860, 701, 995, 719] ShowName off CloseFcn "tagdialog Close" GotoTag "RADIO1TXBUFF_TXEN" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType From Name "From6" SID "22" Position [860, 796, 995, 814] ShowName off CloseFcn "tagdialog Close" GotoTag "RADIO2TXBUFF_TXEN" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType From Name "From7" SID "23" Position [860, 891, 995, 909] ShowName off CloseFcn "tagdialog Close" GotoTag "RADIO3TXBUFF_TXEN" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType From Name "From8" SID "24" Position [860, 991, 995, 1009] ShowName off CloseFcn "tagdialog Close" GotoTag "RADIO4TXBUFF_TXEN" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType From Name "From9" SID "25" Position [80, 236, 215, 254] ShowName off CloseFcn "tagdialog Close" GotoTag "StartCapture" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Goto Name "Goto1" SID "26" Position [555, 129, 660, 151] ShowName off GotoTag "WR_ADDR" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Goto Name "Goto2" SID "27" Position [1270, 17, 1430, 43] ShowName off GotoTag "Radio1_RSSI" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Goto Name "Goto3" SID "28" Position [495, 1007, 655, 1033] ShowName off GotoTag "AGC_Done_Detect" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Goto Name "Goto4" SID "29" Position [1275, 162, 1435, 188] ShowName off GotoTag "Radio2_RSSI" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Goto Name "Goto5" SID "30" Position [1275, 297, 1435, 323] ShowName off GotoTag "Radio3_RSSI" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Goto Name "Goto6" SID "31" Position [1275, 437, 1435, 463] ShowName off GotoTag "Radio4_RSSI" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Inverter" SID "32" Ports [1, 1] Position [770, 691, 795, 709] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "8.2" sg_icon_stat "25,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0." "82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 " "11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11." "22 9.22 ],[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npa" "tch([9.55 16.44 14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfpri" "ntf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\n" "fprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical" SID "33" Ports [3, 1] Position [235, 205, 275, 285] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "3" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,261" block_type "logical" block_version "8.2" sg_icon_stat "40,80,3,1,white,blue,0,a2abe52d,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 80 80 0 ],[0.77 0." "82 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 80 80 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[45.55 4" "5.55 50.55 45.55 50.55 50.55 50.55 45.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[40.55 40.55 45.55" " 45.55 40.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[35.55 35.55 40.55 40.55 35.55 ],[1" " 1 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[30.55 30.55 35.55 30.55 35.55 35.55 30.55 ],[0.931 0" ".946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n\ncolo" "r('black');disp('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "Memmory-mapped Registers" SID "34" Ports [] Position [270, 25, 310, 85] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "Memmory-mapped Registers" Location [280, 119, 1540, 841] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Reference Name "AGCDoneAddr" SID "35" Ports [2, 1] Position [975, 17, 1035, 73] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/To Register" SourceType "Xilinx Shared Memory Based To Register Block" infoedit "Register block that writes data to a shared memory register. Delay of one sample period." shared_memory_name "'AGCDoneAddr'" init "0" ownership "Locally owned and initialized" explicit_data_type on gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "14" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,381,266" block_type "toreg" block_version "10.1.3" sg_icon_stat "60,56,2,1,white,blue,0,10ab453e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.91" " ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36.88 44.8" "8 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36.88 28.88 ]," "[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]);\npatch([20." "2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0.973 ]);\nfprintf(" "'','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'di" "n');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMEN" "T: end icon text');" } Block { BlockType Reference Name "Convert1" SID "36" Ports [1, 1] Position [870, 512, 895, 528] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "16" bin_pt "14" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,461,375" block_type "convert" block_version "8.2" sg_icon_stat "25,16,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 16 16 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 16 16 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[10.22 10.22 12.2" "2 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[8.22 8.22 10.22 10.22 8.22 ],[0." "931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatch([9.55 16.44 " "14.44 12.44 10.44 7.55 9.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: en" "d icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'cast');\nfprin" "tf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert2" SID "37" Ports [1, 1] Position [870, 582, 895, 598] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "16" bin_pt "14" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,461,375" block_type "convert" block_version "8.2" sg_icon_stat "25,16,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 16 16 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 16 16 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[10.22 10.22 12.2" "2 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[8.22 8.22 10.22 10.22 8.22 ],[0." "931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatch([9.55 16.44 " "14.44 12.44 10.44 7.55 9.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: en" "d icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'cast');\nfprin" "tf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert3" SID "38" Ports [1, 1] Position [1035, 527, 1060, 543] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,461,375" block_type "convert" block_version "8.2" sg_icon_stat "25,16,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 16 16 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 16 16 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[10.22 10.22 12.2" "2 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[8.22 8.22 10.22 10.22 8.22 ],[0." "931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatch([9.55 16.44 " "14.44 12.44 10.44 7.55 9.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: en" "d icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'cast');\nfprin" "tf('','COMMENT: end icon text');" } Block { BlockType Reference Name "DebugRx1Buffers" SID "39" Ports [0, 1] Position [450, 430, 495, 460] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/From Register" SourceType "Xilinx Shared Memory Based From Register Block" infoedit "Register block that reads data to a shared memory register. Delay of one sample period." shared_memory_name "'DebugRx1Buffers'" init "0" period "1" ownership "Locally owned and initialized" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,381,234" block_type "fromreg" block_version "10.1.2" sg_icon_stat "45,30,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.91" " ]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\npatch([13.1 18.88 22.88 26.88 30.88 22.88 17.1 13.1 ],[19.44 19.44 23.4" "4 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([17.1 22.88 18.88 13.1 17.1 ],[15.44 15.44 19.44 19.44 15.44 ]," "[0.931 0.946 0.973 ]);\npatch([13.1 18.88 22.88 17.1 13.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([17." "1 30.88 26.88 22.88 18.88 13.1 17.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "DebugRx2Buffers" SID "40" Ports [0, 1] Position [450, 510, 495, 540] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/From Register" SourceType "Xilinx Shared Memory Based From Register Block" infoedit "Register block that reads data to a shared memory register. Delay of one sample period." shared_memory_name "'DebugRx2Buffers'" init "0" period "1" ownership "Locally owned and initialized" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,381,234" block_type "fromreg" block_version "10.1.2" sg_icon_stat "45,30,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.91" " ]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\npatch([13.1 18.88 22.88 26.88 30.88 22.88 17.1 13.1 ],[19.44 19.44 23.4" "4 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([17.1 22.88 18.88 13.1 17.1 ],[15.44 15.44 19.44 19.44 15.44 ]," "[0.931 0.946 0.973 ]);\npatch([13.1 18.88 22.88 17.1 13.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([17." "1 30.88 26.88 22.88 18.88 13.1 17.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "DebugRx3Buffers" SID "41" Ports [0, 1] Position [450, 595, 495, 625] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/From Register" SourceType "Xilinx Shared Memory Based From Register Block" infoedit "Register block that reads data to a shared memory register. Delay of one sample period." shared_memory_name "'DebugRx3Buffers'" init "0" period "1" ownership "Locally owned and initialized" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,381,234" block_type "fromreg" block_version "10.1.2" sg_icon_stat "45,30,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.91" " ]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\npatch([13.1 18.88 22.88 26.88 30.88 22.88 17.1 13.1 ],[19.44 19.44 23.4" "4 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([17.1 22.88 18.88 13.1 17.1 ],[15.44 15.44 19.44 19.44 15.44 ]," "[0.931 0.946 0.973 ]);\npatch([13.1 18.88 22.88 17.1 13.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([17." "1 30.88 26.88 22.88 18.88 13.1 17.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "DebugRx4Buffers" SID "42" Ports [0, 1] Position [450, 695, 495, 725] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/From Register" SourceType "Xilinx Shared Memory Based From Register Block" infoedit "Register block that reads data to a shared memory register. Delay of one sample period." shared_memory_name "'DebugRx4Buffers'" init "0" period "1" ownership "Locally owned and initialized" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,381,234" block_type "fromreg" block_version "10.1.2" sg_icon_stat "45,30,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.91" " ]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\npatch([13.1 18.88 22.88 26.88 30.88 22.88 17.1 13.1 ],[19.44 19.44 23.4" "4 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([17.1 22.88 18.88 13.1 17.1 ],[15.44 15.44 19.44 19.44 15.44 ]," "[0.931 0.946 0.973 ]);\npatch([13.1 18.88 22.88 17.1 13.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([17." "1 30.88 26.88 22.88 18.88 13.1 17.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "From Register1" SID "43" Ports [0, 1] Position [450, 100, 495, 130] ShowName off AttributesFormatString "RADIO1RXBUFF_RXEN\\n<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/From Register" SourceType "Xilinx Shared Memory Based From Register Block" infoedit "Register block that reads data to a shared memory register. Delay of one sample period." shared_memory_name "'RADIO1RXBUFF_RXEN'" init "0" period "1" ownership "Locally owned and initialized" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,381,246" block_type "fromreg" block_version "8.2" sg_icon_stat "45,30,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.91" " ]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\npatch([13.1 18.88 22.88 26.88 30.88 22.88 17.1 13.1 ],[19.44 19.44 23.4" "4 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([17.1 22.88 18.88 13.1 17.1 ],[15.44 15.44 19.44 19.44 15.44 ]," "[0.931 0.946 0.973 ]);\npatch([13.1 18.88 22.88 17.1 13.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([17." "1 30.88 26.88 22.88 18.88 13.1 17.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "From Register10" SID "44" Ports [0, 1] Position [55, 590, 100, 620] ShowName off AttributesFormatString "RADIO3TXBUFF_TXEN\\n<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/From Register" SourceType "Xilinx Shared Memory Based From Register Block" infoedit "Register block that reads data to a shared memory register. Delay of one sample period." shared_memory_name "'RADIO3TXBUFF_TXEN'" init "0" period "1" ownership "Locally owned and initialized" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,379,246" block_type "fromreg" block_version "8.2" sg_icon_stat "45,30,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.91" " ]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\npatch([13.1 18.88 22.88 26.88 30.88 22.88 17.1 13.1 ],[19.44 19.44 23.4" "4 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([17.1 22.88 18.88 13.1 17.1 ],[15.44 15.44 19.44 19.44 15.44 ]," "[0.931 0.946 0.973 ]);\npatch([13.1 18.88 22.88 17.1 13.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([17." "1 30.88 26.88 22.88 18.88 13.1 17.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "From Register11" SID "45" Ports [0, 1] Position [450, 265, 495, 295] ShowName off AttributesFormatString "RADIO3RXBUFF_RXEN\\n<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/From Register" SourceType "Xilinx Shared Memory Based From Register Block" infoedit "Register block that reads data to a shared memory register. Delay of one sample period." shared_memory_name "'RADIO3RXBUFF_RXEN'" init "0" period "1" ownership "Locally owned and initialized" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,381,246" block_type "fromreg" block_version "8.2" sg_icon_stat "45,30,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.91" " ]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\npatch([13.1 18.88 22.88 26.88 30.88 22.88 17.1 13.1 ],[19.44 19.44 23.4" "4 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([17.1 22.88 18.88 13.1 17.1 ],[15.44 15.44 19.44 19.44 15.44 ]," "[0.931 0.946 0.973 ]);\npatch([13.1 18.88 22.88 17.1 13.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([17." "1 30.88 26.88 22.88 18.88 13.1 17.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "From Register12" SID "46" Ports [0, 1] Position [55, 670, 100, 700] ShowName off AttributesFormatString "RADIO4TXBUFF_TXEN\\n<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/From Register" SourceType "Xilinx Shared Memory Based From Register Block" infoedit "Register block that reads data to a shared memory register. Delay of one sample period." shared_memory_name "'RADIO4TXBUFF_TXEN'" init "0" period "1" ownership "Locally owned and initialized" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,381,246" block_type "fromreg" block_version "8.2" sg_icon_stat "45,30,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.91" " ]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\npatch([13.1 18.88 22.88 26.88 30.88 22.88 17.1 13.1 ],[19.44 19.44 23.4" "4 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([17.1 22.88 18.88 13.1 17.1 ],[15.44 15.44 19.44 19.44 15.44 ]," "[0.931 0.946 0.973 ]);\npatch([13.1 18.88 22.88 17.1 13.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([17." "1 30.88 26.88 22.88 18.88 13.1 17.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "From Register13" SID "47" Ports [0, 1] Position [770, 505, 815, 535] ShowName off AttributesFormatString "MGC_AGC_SEL\\n<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/From Register" SourceType "Xilinx Shared Memory Based From Register Block" infoedit "Register block that reads data to a shared memory register. Delay of one sample period." shared_memory_name "'MGC_AGC_SEL'" init "1" period "1" ownership "Locally owned and initialized" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,447,246" block_type "fromreg" block_version "8.2" sg_icon_stat "45,30,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.91" " ]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\npatch([13.1 18.88 22.88 26.88 30.88 22.88 17.1 13.1 ],[19.44 19.44 23.4" "4 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([17.1 22.88 18.88 13.1 17.1 ],[15.44 15.44 19.44 19.44 15.44 ]," "[0.931 0.946 0.973 ]);\npatch([13.1 18.88 22.88 17.1 13.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([17." "1 30.88 26.88 22.88 18.88 13.1 17.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "From Register14" SID "48" Ports [0, 1] Position [770, 575, 815, 605] ShowName off AttributesFormatString "DCO_EN_SEL\\n<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/From Register" SourceType "Xilinx Shared Memory Based From Register Block" infoedit "Register block that reads data to a shared memory register. Delay of one sample period." shared_memory_name "'DCO_EN_SEL'" init "1" period "1" ownership "Locally owned and initialized" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,447,246" block_type "fromreg" block_version "8.2" sg_icon_stat "45,30,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.91" " ]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\npatch([13.1 18.88 22.88 26.88 30.88 22.88 17.1 13.1 ],[19.44 19.44 23.4" "4 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([17.1 22.88 18.88 13.1 17.1 ],[15.44 15.44 19.44 19.44 15.44 ]," "[0.931 0.946 0.973 ]);\npatch([13.1 18.88 22.88 17.1 13.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([17." "1 30.88 26.88 22.88 18.88 13.1 17.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "From Register15" SID "49" Ports [0, 1] Position [55, 185, 100, 215] ShowName off AttributesFormatString "StartTxRx\\n<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/From Register" SourceType "Xilinx Shared Memory Based From Register Block" infoedit "Register block that reads data to a shared memory register. Delay of one sample period." shared_memory_name "'StartTxRx'" init "0" period "1" ownership "Locally owned and initialized" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,381,246" block_type "fromreg" block_version "8.2" sg_icon_stat "45,30,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.91" " ]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\npatch([13.1 18.88 22.88 26.88 30.88 22.88 17.1 13.1 ],[19.44 19.44 23.4" "4 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([17.1 22.88 18.88 13.1 17.1 ],[15.44 15.44 19.44 19.44 15.44 ]," "[0.931 0.946 0.973 ]);\npatch([13.1 18.88 22.88 17.1 13.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([17." "1 30.88 26.88 22.88 18.88 13.1 17.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "From Register2" SID "50" Ports [0, 1] Position [450, 15, 495, 45] ShowName off AttributesFormatString "StartCapture\\n<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/From Register" SourceType "Xilinx Shared Memory Based From Register Block" infoedit "Register block that reads data to a shared memory register. Delay of one sample period." shared_memory_name "'StartCapture'" init "0" period "1" ownership "Locally owned and initialized" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,447,246" block_type "fromreg" block_version "8.2" sg_icon_stat "45,30,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.91" " ]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\npatch([13.1 18.88 22.88 26.88 30.88 22.88 17.1 13.1 ],[19.44 19.44 23.4" "4 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([17.1 22.88 18.88 13.1 17.1 ],[15.44 15.44 19.44 19.44 15.44 ]," "[0.931 0.946 0.973 ]);\npatch([13.1 18.88 22.88 17.1 13.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([17." "1 30.88 26.88 22.88 18.88 13.1 17.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "From Register3" SID "51" Ports [0, 1] Position [450, 345, 495, 375] ShowName off AttributesFormatString "RADIO4RXBUFF_RXEN\\n<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/From Register" SourceType "Xilinx Shared Memory Based From Register Block" infoedit "Register block that reads data to a shared memory register. Delay of one sample period." shared_memory_name "'RADIO4RXBUFF_RXEN'" init "0" period "1" ownership "Locally owned and initialized" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,381,246" block_type "fromreg" block_version "8.2" sg_icon_stat "45,30,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.91" " ]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\npatch([13.1 18.88 22.88 26.88 30.88 22.88 17.1 13.1 ],[19.44 19.44 23.4" "4 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([17.1 22.88 18.88 13.1 17.1 ],[15.44 15.44 19.44 19.44 15.44 ]," "[0.931 0.946 0.973 ]);\npatch([13.1 18.88 22.88 17.1 13.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([17." "1 30.88 26.88 22.88 18.88 13.1 17.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "From Register4" SID "52" Ports [0, 1] Position [55, 25, 100, 55] ShowName off AttributesFormatString "StartTx\\n<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/From Register" SourceType "Xilinx Shared Memory Based From Register Block" infoedit "Register block that reads data to a shared memory register. Delay of one sample period." shared_memory_name "'StartTx'" init "0" period "1" ownership "Locally owned and initialized" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,379,246" block_type "fromreg" block_version "8.2" sg_icon_stat "45,30,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.91" " ]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\npatch([13.1 18.88 22.88 26.88 30.88 22.88 17.1 13.1 ],[19.44 19.44 23.4" "4 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([17.1 22.88 18.88 13.1 17.1 ],[15.44 15.44 19.44 19.44 15.44 ]," "[0.931 0.946 0.973 ]);\npatch([13.1 18.88 22.88 17.1 13.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([17." "1 30.88 26.88 22.88 18.88 13.1 17.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "From Register5" SID "53" Ports [0, 1] Position [450, 185, 495, 215] ShowName off AttributesFormatString "RADIO2RXBUFF_RXEN\\n<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/From Register" SourceType "Xilinx Shared Memory Based From Register Block" infoedit "Register block that reads data to a shared memory register. Delay of one sample period." shared_memory_name "'RADIO2RXBUFF_RXEN'" init "0" period "1" ownership "Locally owned and initialized" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,381,246" block_type "fromreg" block_version "8.2" sg_icon_stat "45,30,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.91" " ]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\npatch([13.1 18.88 22.88 26.88 30.88 22.88 17.1 13.1 ],[19.44 19.44 23.4" "4 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([17.1 22.88 18.88 13.1 17.1 ],[15.44 15.44 19.44 19.44 15.44 ]," "[0.931 0.946 0.973 ]);\npatch([13.1 18.88 22.88 17.1 13.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([17." "1 30.88 26.88 22.88 18.88 13.1 17.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "From Register6" SID "54" Ports [0, 1] Position [55, 430, 100, 460] ShowName off AttributesFormatString "RADIO1TXBUFF_TXEN\\n<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/From Register" SourceType "Xilinx Shared Memory Based From Register Block" infoedit "Register block that reads data to a shared memory register. Delay of one sample period." shared_memory_name "'RADIO1TXBUFF_TXEN'" init "0" period "1" ownership "Locally owned and initialized" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,381,246" block_type "fromreg" block_version "8.2" sg_icon_stat "45,30,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.91" " ]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\npatch([13.1 18.88 22.88 26.88 30.88 22.88 17.1 13.1 ],[19.44 19.44 23.4" "4 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([17.1 22.88 18.88 13.1 17.1 ],[15.44 15.44 19.44 19.44 15.44 ]," "[0.931 0.946 0.973 ]);\npatch([13.1 18.88 22.88 17.1 13.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([17." "1 30.88 26.88 22.88 18.88 13.1 17.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "From Register7" SID "55" Ports [0, 1] Position [55, 105, 100, 135] ShowName off AttributesFormatString "StopTx\\n<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/From Register" SourceType "Xilinx Shared Memory Based From Register Block" infoedit "Register block that reads data to a shared memory register. Delay of one sample period." shared_memory_name "'StopTx'" init "0" period "1" ownership "Locally owned and initialized" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,381,246" block_type "fromreg" block_version "8.2" sg_icon_stat "45,30,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.91" " ]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\npatch([13.1 18.88 22.88 26.88 30.88 22.88 17.1 13.1 ],[19.44 19.44 23.4" "4 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([17.1 22.88 18.88 13.1 17.1 ],[15.44 15.44 19.44 19.44 15.44 ]," "[0.931 0.946 0.973 ]);\npatch([13.1 18.88 22.88 17.1 13.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([17." "1 30.88 26.88 22.88 18.88 13.1 17.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "From Register8" SID "56" Ports [0, 1] Position [55, 265, 100, 295] ShowName off AttributesFormatString "TransMode\\n<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/From Register" SourceType "Xilinx Shared Memory Based From Register Block" infoedit "Register block that reads data to a shared memory register. Delay of one sample period." shared_memory_name "'TransMode'" init "0" period "1" ownership "Locally owned and initialized" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,381,246" block_type "fromreg" block_version "8.2" sg_icon_stat "45,30,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.91" " ]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\npatch([13.1 18.88 22.88 26.88 30.88 22.88 17.1 13.1 ],[19.44 19.44 23.4" "4 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([17.1 22.88 18.88 13.1 17.1 ],[15.44 15.44 19.44 19.44 15.44 ]," "[0.931 0.946 0.973 ]);\npatch([13.1 18.88 22.88 17.1 13.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([17." "1 30.88 26.88 22.88 18.88 13.1 17.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "From Register9" SID "57" Ports [0, 1] Position [55, 510, 100, 540] ShowName off AttributesFormatString "RADIO2TXBUFF_TXEN\\n<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/From Register" SourceType "Xilinx Shared Memory Based From Register Block" infoedit "Register block that reads data to a shared memory register. Delay of one sample period." shared_memory_name "'RADIO2TXBUFF_TXEN'" init "0" period "1" ownership "Locally owned and initialized" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,379,246" block_type "fromreg" block_version "8.2" sg_icon_stat "45,30,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.91" " ]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\npatch([13.1 18.88 22.88 26.88 30.88 22.88 17.1 13.1 ],[19.44 19.44 23.4" "4 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([17.1 22.88 18.88 13.1 17.1 ],[15.44 15.44 19.44 19.44 15.44 ]," "[0.931 0.946 0.973 ]);\npatch([13.1 18.88 22.88 17.1 13.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([17." "1 30.88 26.88 22.88 18.88 13.1 17.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType From Name "From1" SID "58" Position [770, 21, 905, 39] ShowName off CloseFcn "tagdialog Close" GotoTag "WR_ADDR" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType From Name "From10" SID "59" Position [765, 116, 900, 134] ShowName off CloseFcn "tagdialog Close" GotoTag "Radio1_RSSI" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType From Name "From2" SID "60" Position [770, 51, 905, 69] ShowName off CloseFcn "tagdialog Close" GotoTag "AGC_Done_Detect" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType From Name "From3" SID "61" Position [765, 676, 900, 694] ShowName off CloseFcn "tagdialog Close" GotoTag "CAPTURE_IS_DONE" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType From Name "From4" SID "62" Position [765, 206, 900, 224] ShowName off CloseFcn "tagdialog Close" GotoTag "Radio2_RSSI" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType From Name "From6" SID "63" Position [765, 296, 900, 314] ShowName off CloseFcn "tagdialog Close" GotoTag "Radio3_RSSI" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType From Name "From8" SID "64" Position [770, 401, 905, 419] ShowName off CloseFcn "tagdialog Close" GotoTag "Radio4_RSSI" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Goto Name "Goto1" SID "65" Position [175, 107, 335, 133] ShowName off GotoTag "StopTx" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Goto Name "Goto10" SID "66" Position [175, 27, 335, 53] ShowName off GotoTag "StartTx" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Goto Name "Goto11" SID "67" Position [575, 187, 735, 213] ShowName off GotoTag "RADIO2RXBUFF_RXEN" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Goto Name "Goto12" SID "68" Position [575, 267, 735, 293] ShowName off GotoTag "RADIO3RXBUFF_RXEN" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Goto Name "Goto13" SID "69" Position [575, 347, 735, 373] ShowName off GotoTag "RADIO4RXBUFF_RXEN" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Goto Name "Goto14" SID "70" Position [575, 432, 735, 458] ShowName off GotoTag "DebugRx1Buffers" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Goto Name "Goto15" SID "71" Position [575, 512, 735, 538] ShowName off GotoTag "DebugRx2Buffers" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Goto Name "Goto16" SID "72" Position [575, 597, 735, 623] ShowName off GotoTag "DebugRx3Buffers" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Goto Name "Goto17" SID "73" Position [575, 697, 735, 723] ShowName off GotoTag "DebugRx4Buffers" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Goto Name "Goto18" SID "74" Position [1090, 522, 1250, 548] ShowName off GotoTag "MGCAGC_AGCDCO_SEL" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Goto Name "Goto19" SID "75" Position [175, 187, 335, 213] ShowName off GotoTag "StartTxRx" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Goto Name "Goto2" SID "76" Position [175, 347, 335, 373] ShowName off GotoTag "TxDelay" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Goto Name "Goto3" SID "77" Position [175, 267, 335, 293] ShowName off GotoTag "TransMode" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Goto Name "Goto4" SID "78" Position [175, 432, 335, 458] ShowName off GotoTag "RADIO1TXBUFF_TXEN" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Goto Name "Goto5" SID "79" Position [175, 512, 335, 538] ShowName off GotoTag "RADIO2TXBUFF_TXEN" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Goto Name "Goto6" SID "80" Position [175, 592, 335, 618] ShowName off GotoTag "RADIO3TXBUFF_TXEN" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Goto Name "Goto7" SID "81" Position [175, 672, 335, 698] ShowName off GotoTag "RADIO4TXBUFF_TXEN" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Goto Name "Goto8" SID "82" Position [575, 17, 735, 43] ShowName off GotoTag "StartCapture" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Goto Name "Goto9" SID "83" Position [575, 102, 735, 128] ShowName off GotoTag "RADIO1RXBUFF_RXEN" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Logical" SID "84" Ports [2, 1] Position [945, 505, 1000, 565] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,261" block_type "logical" block_version "10.1.3" sg_icon_stat "55,60,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 60 60 0 ],[0.77 0.82 0.91" " ]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ],[37.77 37.7" "7 44.77 37.77 44.77 44.77 44.77 37.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[30.77 30.77 37.77 37" ".77 30.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[23.77 23.77 30.77 30.77 23.77 ],[1 1" " 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[16.77 16.77 23.77 16.77 23.77 23.77 16.77 ],[0.931 0" ".946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('bl" "ack');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Radio1AGCDoneRSSI" SID "85" Ports [2, 1] Position [970, 112, 1030, 168] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/To Register" SourceType "Xilinx Shared Memory Based To Register Block" infoedit "Register block that writes data to a shared memory register. Delay of one sample period." shared_memory_name "'Radio1AGCDoneRSSI'" init "0" ownership "Locally owned and initialized" explicit_data_type on gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "10" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,381,266" block_type "toreg" block_version "10.1.3" sg_icon_stat "60,56,2,1,white,blue,0,10ab453e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.91" " ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36.88 44.8" "8 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36.88 28.88 ]," "[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]);\npatch([20." "2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0.973 ]);\nfprintf(" "'','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'di" "n');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMEN" "T: end icon text');" } Block { BlockType Reference Name "Radio2AGCDoneRSSI" SID "86" Ports [2, 1] Position [970, 202, 1030, 258] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/To Register" SourceType "Xilinx Shared Memory Based To Register Block" infoedit "Register block that writes data to a shared memory register. Delay of one sample period." shared_memory_name "'Radio2AGCDoneRSSI'" init "0" ownership "Locally owned and initialized" explicit_data_type on gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "10" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,381,266" block_type "toreg" block_version "10.1.3" sg_icon_stat "60,56,2,1,white,blue,0,10ab453e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.91" " ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36.88 44.8" "8 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36.88 28.88 ]," "[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]);\npatch([20." "2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0.973 ]);\nfprintf(" "'','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'di" "n');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMEN" "T: end icon text');" } Block { BlockType Reference Name "Radio3AGCDoneRSSI" SID "87" Ports [2, 1] Position [970, 292, 1030, 348] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/To Register" SourceType "Xilinx Shared Memory Based To Register Block" infoedit "Register block that writes data to a shared memory register. Delay of one sample period." shared_memory_name "'Radio3AGCDoneRSSI'" init "0" ownership "Locally owned and initialized" explicit_data_type on gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "10" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,381,266" block_type "toreg" block_version "10.1.3" sg_icon_stat "60,56,2,1,white,blue,0,10ab453e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.91" " ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36.88 44.8" "8 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36.88 28.88 ]," "[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]);\npatch([20." "2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0.973 ]);\nfprintf(" "'','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'di" "n');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMEN" "T: end icon text');" } Block { BlockType Reference Name "Radio4AGCDoneRSSI" SID "88" Ports [2, 1] Position [975, 397, 1035, 453] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/To Register" SourceType "Xilinx Shared Memory Based To Register Block" infoedit "Register block that writes data to a shared memory register. Delay of one sample period." shared_memory_name "'Radio4AGCDoneRSSI'" init "0" ownership "Locally owned and initialized" explicit_data_type on gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "10" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,381,266" block_type "toreg" block_version "10.1.3" sg_icon_stat "60,56,2,1,white,blue,0,10ab453e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 56 56 0 ],[0.77 0.82 0.91" " ]);\nplot([0 60 60 0 0 ],[0 0 56 56 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[36.88 36.88 44.8" "8 36.88 44.88 44.88 44.88 36.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[28.88 28.88 36.88 36.88 28.88 ]," "[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[20.88 20.88 28.88 28.88 20.88 ],[1 1 1 ]);\npatch([20." "2 47.76 39.76 31.76 23.76 12.2 20.2 ],[12.88 12.88 20.88 12.88 20.88 20.88 12.88 ],[0.931 0.946 0.973 ]);\nfprintf(" "'','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'di" "n');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMEN" "T: end icon text');" } Block { BlockType Reference Name "To Register" SID "89" Ports [2, 1] Position [935, 671, 980, 729] NamePlacement "alternate" ShowName off AttributesFormatString "CaptureDone\\n<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/To Register" SourceType "Xilinx Shared Memory Based To Register Block" infoedit "Register block that writes data to a shared memory register. Delay of one sample period." shared_memory_name "'CaptureDone'" init "0" ownership "Locally owned and initialized" explicit_data_type on gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,381,270" block_type "toreg" block_version "8.2" sg_icon_stat "45,58,2,1,white,blue,0,10ab453e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 58 58 0 ],[0.77 0.82 0.91" " ]);\nplot([0 45 45 0 0 ],[0 0 58 58 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[35.66 35.66 41." "66 35.66 41.66 41.66 41.66 35.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[29.66 29.66 35.66 35.66 29.66" " ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[23.66 23.66 29.66 29.66 23.66 ],[1 1 1 ]);\npatch(" "[14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[17.66 17.66 23.66 17.66 23.66 23.66 17.66 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'" ",1,'din');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('output',1,'dout');\nfprintf('','" "COMMENT: end icon text');" } Block { BlockType Reference Name "TxDelay" SID "90" Ports [0, 1] Position [55, 345, 100, 375] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/From Register" SourceType "Xilinx Shared Memory Based From Register Block" infoedit "Register block that reads data to a shared memory register. Delay of one sample period." shared_memory_name "'TxDelay'" init "1000" period "1" ownership "Locally owned and initialized" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "14" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,381,234" block_type "fromreg" block_version "10.1.2" sg_icon_stat "45,30,0,1,white,blue,0,b27a07ff,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.91" " ]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\npatch([13.1 18.88 22.88 26.88 30.88 22.88 17.1 13.1 ],[19.44 19.44 23.4" "4 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([17.1 22.88 18.88 13.1 17.1 ],[15.44 15.44 19.44 19.44 15.44 ]," "[0.931 0.946 0.973 ]);\npatch([13.1 18.88 22.88 17.1 13.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([17." "1 30.88 26.88 22.88 18.88 13.1 17.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "zero1" SID "91" Ports [0, 1] Position [865, 706, 885, 724] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "20,18,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.91" " ]);\nplot([0 20 20 0 0 ],[0 0 18 18 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[11.22 11.22 13.22" " 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[9.22 9.22 11.22 11.22 9.22 ],[0.93" "1 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([7.55 14.44 12." "44 10.44 8.44 5.55 7.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end ic" "on graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'1');\nfprintf('','CO" "MMENT: end icon text');" } Line { SrcBlock "From Register4" SrcPort 1 DstBlock "Goto10" DstPort 1 } Line { SrcBlock "From Register7" SrcPort 1 DstBlock "Goto1" DstPort 1 } Line { SrcBlock "From Register8" SrcPort 1 DstBlock "Goto3" DstPort 1 } Line { SrcBlock "TxDelay" SrcPort 1 DstBlock "Goto2" DstPort 1 } Line { SrcBlock "From Register6" SrcPort 1 DstBlock "Goto4" DstPort 1 } Line { SrcBlock "From Register9" SrcPort 1 DstBlock "Goto5" DstPort 1 } Line { SrcBlock "From Register10" SrcPort 1 DstBlock "Goto6" DstPort 1 } Line { SrcBlock "From Register12" SrcPort 1 DstBlock "Goto7" DstPort 1 } Line { SrcBlock "From Register2" SrcPort 1 DstBlock "Goto8" DstPort 1 } Line { SrcBlock "From Register5" SrcPort 1 DstBlock "Goto11" DstPort 1 } Line { SrcBlock "From Register11" SrcPort 1 DstBlock "Goto12" DstPort 1 } Line { SrcBlock "From Register3" SrcPort 1 DstBlock "Goto13" DstPort 1 } Line { SrcBlock "From Register1" SrcPort 1 DstBlock "Goto9" DstPort 1 } Line { SrcBlock "DebugRx1Buffers" SrcPort 1 DstBlock "Goto14" DstPort 1 } Line { SrcBlock "DebugRx2Buffers" SrcPort 1 DstBlock "Goto15" DstPort 1 } Line { SrcBlock "DebugRx3Buffers" SrcPort 1 DstBlock "Goto16" DstPort 1 } Line { SrcBlock "DebugRx4Buffers" SrcPort 1 DstBlock "Goto17" DstPort 1 } Line { SrcBlock "From2" SrcPort 1 Points [15, 0] Branch { DstBlock "AGCDoneAddr" DstPort 2 } Branch { Points [0, 95] Branch { DstBlock "Radio1AGCDoneRSSI" DstPort 2 } Branch { Points [0, 90] Branch { Points [0, 90] Branch { Points [0, 105] DstBlock "Radio4AGCDoneRSSI" DstPort 2 } Branch { DstBlock "Radio3AGCDoneRSSI" DstPort 2 } } Branch { DstBlock "Radio2AGCDoneRSSI" DstPort 2 } } } } Line { SrcBlock "From1" SrcPort 1 DstBlock "AGCDoneAddr" DstPort 1 } Line { SrcBlock "From4" SrcPort 1 DstBlock "Radio2AGCDoneRSSI" DstPort 1 } Line { SrcBlock "From6" SrcPort 1 DstBlock "Radio3AGCDoneRSSI" DstPort 1 } Line { SrcBlock "From8" SrcPort 1 DstBlock "Radio4AGCDoneRSSI" DstPort 1 } Line { SrcBlock "From10" SrcPort 1 DstBlock "Radio1AGCDoneRSSI" DstPort 1 } Line { SrcBlock "From Register13" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "From Register14" SrcPort 1 DstBlock "Convert2" DstPort 1 } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "Logical" DstPort 1 } Line { SrcBlock "Convert2" SrcPort 1 Points [25, 0; 0, -40] DstBlock "Logical" DstPort 2 } Line { SrcBlock "Logical" SrcPort 1 DstBlock "Convert3" DstPort 1 } Line { SrcBlock "Convert3" SrcPort 1 DstBlock "Goto18" DstPort 1 } Line { SrcBlock "zero1" SrcPort 1 DstBlock "To Register" DstPort 2 } Line { SrcBlock "From3" SrcPort 1 DstBlock "To Register" DstPort 1 } Line { SrcBlock "From Register15" SrcPort 1 DstBlock "Goto19" DstPort 1 } Annotation { Name "MGCAGC_AGCDCO_SEL will go high\nonly when AGC is selected (MGC_AGC_SEL=1) AND\nDC Offset (DCO) Correction" " in enabled (DCO_EN_SEL=1)" Position [1140, 572] } } } Block { BlockType SubSystem Name "Posedge" SID "92" Ports [1, 1] Position [330, 233, 375, 257] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "Posedge" Location [132, 719, 452, 817] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" SID "93" Position [25, 33, 55, 47] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Delay" SID "94" Ports [1, 1] Position [145, 45, 175, 75] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. If re" "gister retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "8.2" sg_icon_stat "30,30,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 30 30 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[19.44 19.44 23.44 " "19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[15.44 15.44 19.44 19.44 15.44 ],[0." "931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([10.1 23." "88 19.88 15.88 11.88 6.1 10.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-1}','texmode','on');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "95" Ports [1, 1] Position [90, 47, 120, 73] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "8.2" sg_icon_stat "30,26,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[16.33 16.33 " "19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 13.33 16.33 16.33" " 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ])" ";\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('" "not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical" SID "96" Ports [2, 1] Position [205, 29, 240, 71] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "8.2" sg_icon_stat "35,42,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 42 42 0 ],[0.77 0.82 0.91" " ]);\nplot([0 35 35 0 0 ],[0 0 42 42 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[26.55 26.55 31.55" " 26.55 31.55 31.55 31.55 26.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[21.55 21.55 26.55 26.55 21.55 " "],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[16.55 16.55 21.55 21.55 16.55 ],[1 1 1 ]);\npatch(" "[10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[11.55 11.55 16.55 11.55 16.55 16.55 11.55 ],[0.931 0.946 0.973 ]);\nfpr" "intf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('and');\n" "fprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "97" Position [265, 43, 295, 57] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "D" SrcPort 1 Points [0, 0; 15, 0] Branch { DstBlock "Inverter" DstPort 1 } Branch { DstBlock "Logical" DstPort 1 } } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Delay" DstPort 1 } Line { SrcBlock "Delay" SrcPort 1 Points [0, 0] DstBlock "Logical" DstPort 2 } Line { SrcBlock "Logical" SrcPort 1 Points [0, 0] DstBlock "Q" DstPort 1 } } } Block { BlockType SubSystem Name "Posedge1" SID "98" Ports [1, 1] Position [365, 648, 410, 672] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "Posedge1" Location [132, 719, 452, 817] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" SID "99" Position [25, 33, 55, 47] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Delay" SID "100" Ports [1, 1] Position [145, 45, 175, 75] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. If re" "gister retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "8.2" sg_icon_stat "30,30,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 30 30 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[19.44 19.44 23.44 " "19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[15.44 15.44 19.44 19.44 15.44 ],[0." "931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([10.1 23." "88 19.88 15.88 11.88 6.1 10.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-1}','texmode','on');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "101" Ports [1, 1] Position [90, 47, 120, 73] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "8.2" sg_icon_stat "30,26,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[16.33 16.33 " "19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 13.33 16.33 16.33" " 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ])" ";\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('" "not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical" SID "102" Ports [2, 1] Position [205, 29, 240, 71] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "8.2" sg_icon_stat "35,42,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 42 42 0 ],[0.77 0.82 0.91" " ]);\nplot([0 35 35 0 0 ],[0 0 42 42 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[26.55 26.55 31.55" " 26.55 31.55 31.55 31.55 26.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[21.55 21.55 26.55 26.55 21.55 " "],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[16.55 16.55 21.55 21.55 16.55 ],[1 1 1 ]);\npatch(" "[10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[11.55 11.55 16.55 11.55 16.55 16.55 11.55 ],[0.931 0.946 0.973 ]);\nfpr" "intf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('and');\n" "fprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "103" Position [265, 43, 295, 57] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "Logical" SrcPort 1 Points [0, 0] DstBlock "Q" DstPort 1 } Line { SrcBlock "Delay" SrcPort 1 Points [0, 0] DstBlock "Logical" DstPort 2 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Delay" DstPort 1 } Line { SrcBlock "D" SrcPort 1 Points [0, 0; 15, 0] Branch { DstBlock "Logical" DstPort 1 } Branch { DstBlock "Inverter" DstPort 1 } } } } Block { BlockType SubSystem Name "Posedge2" SID "104" Ports [1, 1] Position [365, 748, 410, 772] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "Posedge2" Location [132, 719, 452, 817] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" SID "105" Position [25, 33, 55, 47] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Delay" SID "106" Ports [1, 1] Position [145, 45, 175, 75] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. If re" "gister retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "8.2" sg_icon_stat "30,30,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 30 30 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[19.44 19.44 23.44 " "19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[15.44 15.44 19.44 19.44 15.44 ],[0." "931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([10.1 23." "88 19.88 15.88 11.88 6.1 10.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-1}','texmode','on');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "107" Ports [1, 1] Position [90, 47, 120, 73] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "8.2" sg_icon_stat "30,26,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[16.33 16.33 " "19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 13.33 16.33 16.33" " 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ])" ";\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('" "not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical" SID "108" Ports [2, 1] Position [205, 29, 240, 71] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "8.2" sg_icon_stat "35,42,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 42 42 0 ],[0.77 0.82 0.91" " ]);\nplot([0 35 35 0 0 ],[0 0 42 42 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[26.55 26.55 31.55" " 26.55 31.55 31.55 31.55 26.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[21.55 21.55 26.55 26.55 21.55 " "],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[16.55 16.55 21.55 21.55 16.55 ],[1 1 1 ]);\npatch(" "[10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[11.55 11.55 16.55 11.55 16.55 16.55 11.55 ],[0.931 0.946 0.973 ]);\nfpr" "intf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('and');\n" "fprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "109" Position [265, 43, 295, 57] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "Logical" SrcPort 1 Points [0, 0] DstBlock "Q" DstPort 1 } Line { SrcBlock "Delay" SrcPort 1 Points [0, 0] DstBlock "Logical" DstPort 2 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Delay" DstPort 1 } Line { SrcBlock "D" SrcPort 1 Points [0, 0; 15, 0] Branch { DstBlock "Logical" DstPort 1 } Branch { DstBlock "Inverter" DstPort 1 } } } } Block { BlockType SubSystem Name "Posedge3" SID "110" Ports [1, 1] Position [325, 1008, 370, 1032] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "Posedge3" Location [132, 719, 452, 817] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" SID "111" Position [25, 33, 55, 47] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Delay" SID "112" Ports [1, 1] Position [145, 45, 175, 75] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flop. If re" "gister retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "8.2" sg_icon_stat "30,30,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 30 30 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[19.44 19.44 23.44 " "19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[15.44 15.44 19.44 19.44 15.44 ],[0." "931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([10.1 23." "88 19.88 15.88 11.88 6.1 10.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('z^{-1}','texmode','on');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "113" Ports [1, 1] Position [90, 47, 120, 73] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "8.2" sg_icon_stat "30,26,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[16.33 16.33 " "19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 13.33 16.33 16.33" " 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13.33 10.33 ],[1 1 1 ])" ";\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7.33 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('" "not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical" SID "114" Ports [2, 1] Position [205, 29, 240, 71] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "8.2" sg_icon_stat "35,42,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 42 42 0 ],[0.77 0.82 0.91" " ]);\nplot([0 35 35 0 0 ],[0 0 42 42 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[26.55 26.55 31.55" " 26.55 31.55 31.55 31.55 26.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[21.55 21.55 26.55 26.55 21.55 " "],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[16.55 16.55 21.55 21.55 16.55 ],[1 1 1 ]);\npatch(" "[10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[11.55 11.55 16.55 11.55 16.55 16.55 11.55 ],[0.931 0.946 0.973 ]);\nfpr" "intf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('and');\n" "fprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "115" Position [265, 43, 295, 57] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "D" SrcPort 1 Points [0, 0; 15, 0] Branch { DstBlock "Inverter" DstPort 1 } Branch { DstBlock "Logical" DstPort 1 } } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Delay" DstPort 1 } Line { SrcBlock "Delay" SrcPort 1 Points [0, 0] DstBlock "Logical" DstPort 2 } Line { SrcBlock "Logical" SrcPort 1 Points [0, 0] DstBlock "Q" DstPort 1 } } } Block { BlockType DiscretePulseGenerator Name "Pulse\nGenerator" SID "116" Ports [0, 1] Position [35, 202, 65, 238] Period "1000000" PulseWidth "50" PhaseDelay "2" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType DiscretePulseGenerator Name "Pulse\nGenerator1" SID "117" Ports [0, 1] Position [60, 643, 105, 677] Period "10 * 2^14" PulseWidth "50" PhaseDelay "2" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType DiscretePulseGenerator Name "Pulse\nGenerator2" SID "118" Ports [0, 1] Position [60, 728, 105, 762] Period "10 * 2^14" PulseWidth "50" PhaseDelay "2.5 * 2^14" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType DiscretePulseGenerator Name "Pulse\nGenerator3" SID "119" Ports [0, 1] Position [55, 1003, 100, 1037] Period "20000" PulseWidth "50" PhaseDelay "374" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "RSSI Clock\nGenerator" SID "120" Ports [0, 1] Position [65, 942, 110, 968] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited cou" "nter is implemented by combining a counter with a comparator." cnt_type "Free Running" cnt_to "Inf" operation "Up" start_count "0" cnt_by_val "1" arith_type "Unsigned" n_bits "1" bin_pt "0" load_pin off rst off en off explicit_period "on" period "2" dbl_ovrd off use_behavioral_HDL off implementation "Fabric" xl_use_area off xl_area "[0,0,0,0,0,0,0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,356,630" block_type "counter" block_version "VER_STRING_GOES_HERE" sg_icon_stat "45,26,0,1,white,blue,0,7ac47ef5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 26 26 0 ],[0.77 0." "82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 26 26 0 ]);\npatch([15.325 19.66 22.66 25.66 28.66 22.66 18.325 15.325 ],[" "16.33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([18.325 22.66 19.66 15.325 18.325 ],[13.33 1" "3.33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([15.325 19.66 22.66 18.325 15.325 ],[10.33 10.33 13.33 13" ".33 10.33 ],[1 1 1 ]);\npatch([18.325 28.66 25.66 22.66 19.66 15.325 18.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 " "7.33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text')" ";\n\ncolor('black');disp('{\\fontsize{14}\\bf++}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "RSSI_ADC_CLK" SID "121" Ports [1, 1] Position [170, 948, 210, 962] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, do" "uble, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discar" "ded, depending on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" UseAsDAC off DACChannel "'1'" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "8.2" sg_icon_stat "40,14,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.95 0." "93 0.65 ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9.2" "2 9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22 9." "22 7.22 ],[0.985 0.979 0.895 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\n" "patch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.985 0.979 0.895 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('i" "nput',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType SubSystem Name "Radio 1\nRx Buffers" SID "122" Ports [5] Position [1175, 38, 1240, 142] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "Radio 1\nRx Buffers" Location [2, 74, 1270, 726] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "RSSI" SID "123" Position [450, 313, 480, 327] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "I/Q" SID "124" Position [545, 163, 575, 177] Port "2" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "Addr" SID "125" Position [325, 128, 355, 142] Port "3" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "WE" SID "126" Position [110, 183, 140, 197] Port "4" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "EN" SID "127" Position [110, 213, 140, 227] Port "5" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Convert1" SID "128" Ports [1, 1] Position [185, 212, 210, 228] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "16" bin_pt "14" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,374,375" block_type "convert" block_version "8.2" sg_icon_stat "25,16,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 16 16 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 16 16 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[10.22 10.22 12.2" "2 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[8.22 8.22 10.22 10.22 8.22 ],[0." "931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatch([9.55 16.44 " "14.44 12.44 10.44 7.55 9.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: en" "d icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'cast');\nfprin" "tf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out" SID "129" Ports [1, 1] Position [500, 30, 530, 40] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, double, o" "r fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarded, depen" "ding on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" UseAsDAC off DACChannel "'1'" has_advanced_control "0" sggui_pos "20,20,336,386" block_type "gatewayout" block_version "10.1.2" sg_icon_stat "30,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 10 10 0 ],[0.88 0.88 0.88" " ]);\nplot([0 30 30 0 0 ],[0 0 10 10 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ],[6.11 6.11 " "7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[5.11 5.11 6.11 6.11 5.11 ],[" "0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]);\npatch([13." "775 17.22 16.22 15.22 14.22 12.775 13.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.964 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ')" ";\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" } Block { BlockType Reference Name "Gateway Out1" SID "130" Ports [1, 1] Position [500, 70, 530, 80] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, double, o" "r fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarded, depen" "ding on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" UseAsDAC off DACChannel "'1'" has_advanced_control "0" sggui_pos "20,20,336,386" block_type "gatewayout" block_version "10.1.2" sg_icon_stat "30,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 10 10 0 ],[0.88 0.88 0.88" " ]);\nplot([0 30 30 0 0 ],[0 0 10 10 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ],[6.11 6.11 " "7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[5.11 5.11 6.11 6.11 5.11 ],[" "0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]);\npatch([13." "775 17.22 16.22 15.22 14.22 12.775 13.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.964 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ')" ";\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" } Block { BlockType Reference Name "Logical" SID "131" Ports [2, 1] Position [255, 175, 310, 235] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "9.1.01" sg_icon_stat "55,60,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 60 60 0 ],[0.77 0.82 0.91" " ]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ],[37.77 37.7" "7 44.77 37.77 44.77 44.77 44.77 37.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[30.77 30.77 37.77 37" ".77 30.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[23.77 23.77 30.77 30.77 23.77 ],[1 1" " 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[16.77 16.77 23.77 16.77 23.77 23.77 16.77 ],[0.931 0" ".946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('bl" "ack');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "Radio 1\nRSSI Buffer" SID "132" Ports [3] Position [645, 264, 700, 376] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "Radio 1\nRSSI Buffer" Location [2, 70, 1918, 1150] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Addr_14b" SID "133" Position [325, 348, 355, 362] NamePlacement "alternate" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "RSSI" SID "134" Position [95, 383, 125, 397] Port "2" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "WE" SID "135" Position [720, 478, 750, 492] Port "3" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "11MSB" SID "136" Ports [1, 1] Position [430, 346, 470, 364] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outp" "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

" "

Hardware notes: In hardware this block costs nothing." nbits "11" boolean_output off mode "Upper Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,407" block_type "slice" block_version "8.2" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[1" "1.22 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 " "11.22 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[" "1 1 1 ]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black" "');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "BIT[2]" SID "137" Ports [1, 1] Position [430, 401, 470, 419] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outp" "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

" "

Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "2" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,407" block_type "slice" block_version "8.2" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[1" "1.22 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 " "11.22 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[" "1 1 1 ]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black" "');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Concat" SID "138" Ports [2, 1] Position [685, 381, 725, 459] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary poi" "nt at zero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" block_version "10.1.2" sg_icon_stat "40,78,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 78 78 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 78 78 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[44.55" " 44.55 49.55 44.55 49.55 49.55 49.55 44.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[39.55 39.55 44" ".55 44.55 39.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[34.55 34.55 39.55 39.55 34.55 " "],[1 1 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[29.55 29.55 34.55 29.55 34.55 34.55 29.55 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor(" "'black');port_label('input',1,'hi');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\font" "size{20}\\}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert" SID "139" Ports [1, 1] Position [285, 382, 320, 398] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do" " not." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "16" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,461,375" block_type "convert" block_version "8.2" sg_icon_stat "35,16,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 16 16 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 16 16 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[1" "0.22 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[8.22 8.22 " "10.22 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[6.22 6.22 8.22 8.22 6.22 ],[" "1 1 1 ]);\npatch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black" "');port_label('output',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "140" Ports [1, 1] Position [510, 402, 540, 418] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,251" block_type "inv" block_version "10.1.2" sg_icon_stat "30,16,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 16 16 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 16 16 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[1" "0.22 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[8.22 8.22 " "10.22 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[6.22 6.22 8.22 8.22 6.22 ],[" "1 1 1 ]);\npatch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('bla" "ck');disp('not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register" SID "141" Ports [2, 1] Position [580, 378, 625, 422] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "10.1.2" sg_icon_stat "45,44,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28." "66 28.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 2" "8.66 28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 " "],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0" ".931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor" "('black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('ou" "tput',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Reinterpret1" SID "142" Ports [1, 1] Position [180, 382, 215, 398] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can changed the signal b" "etween signed and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs no" "thing.

Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is force" "d to unsigned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an outp" "ut of 56 (111000 in binary)." force_arith_type on arith_type "Unsigned" force_bin_pt on bin_pt "0" has_advanced_control "0" sggui_pos "436,54,356,312" block_type "reinterpret" block_version "9.1.01" sg_icon_stat "35,16,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 16 16 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 16 16 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[1" "0.22 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[8.22 8.22 " "10.22 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[6.22 6.22 8.22 8.22 6.22 ],[" "1 1 1 ]);\npatch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('bla" "ck');disp('reinterpret');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Shared Memory" SID "143" Ports [3, 1] Position [800, 323, 880, 517] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Shared Memory" SourceType "Xilinx Shared Memory Random Access Memory Block" shared_memory_name "'RSSIBuff_Radio1'" depth "2^11" ownership "Locally Owned and Initialized" initVector "0" en off mutex "Unprotected" mode "Read and Write" write_mode "Read After Write" time_out "0" latency "1" explicit_data_type on gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" xl_use_area off xl_area "[0,0,0,0,0,0,0]" implementation "Block RAM" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,384,381" block_type "shmem" block_version "10.1.2" sg_icon_stat "80,194,3,1,white,blue,0,bf435243,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 80 80 0 0 ],[0 0 194 194 0 ],[0.77" " 0.82 0.91 ]);\nplot([0 80 80 0 0 ],[0 0 194 194 0 ]);\npatch([15.525 31.42 42.42 53.42 64.42 42.42 26.525 15.5" "25 ],[109.21 109.21 120.21 109.21 120.21 120.21 120.21 109.21 ],[1 1 1 ]);\npatch([26.525 42.42 31.42 15.525 26" ".525 ],[98.21 98.21 109.21 109.21 98.21 ],[0.931 0.946 0.973 ]);\npatch([15.525 31.42 42.42 26.525 15.525 ],[87" ".21 87.21 98.21 98.21 87.21 ],[1 1 1 ]);\npatch([26.525 64.42 53.42 42.42 31.42 15.525 26.525 ],[76.21 76.21 87" ".21 76.21 87.21 87.21 76.21 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','CO" "MMENT: begin icon text');\ncolor('black');port_label('input',1,'addr');\ncolor('black');port_label('input',2,'d" "in');\ncolor('black');port_label('input',3,'we');\ncolor('black');port_label('output',1,'dout');\nfprintf('','C" "OMMENT: end icon text');" } Block { BlockType Terminator Name "Terminator2" SID "144" Position [945, 410, 965, 430] ShowName off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "RSSI" SrcPort 1 DstBlock "Reinterpret1" DstPort 1 } Line { SrcBlock "Convert" SrcPort 1 Points [35, 0] Branch { DstBlock "Register" DstPort 1 } Branch { Points [0, 50] DstBlock "Concat" DstPort 2 } } Line { SrcBlock "Addr_14b" SrcPort 1 Points [40, 0] Branch { DstBlock "11MSB" DstPort 1 } Branch { Points [0, 55] DstBlock "BIT[2]" DstPort 1 } } Line { SrcBlock "WE" SrcPort 1 DstBlock "Shared Memory" DstPort 3 } Line { SrcBlock "Reinterpret1" SrcPort 1 DstBlock "Convert" DstPort 1 } Line { SrcBlock "Concat" SrcPort 1 DstBlock "Shared Memory" DstPort 2 } Line { SrcBlock "BIT[2]" SrcPort 1 DstBlock "Inverter" DstPort 1 } Line { SrcBlock "11MSB" SrcPort 1 DstBlock "Shared Memory" DstPort 1 } Line { SrcBlock "Shared Memory" SrcPort 1 DstBlock "Terminator2" DstPort 1 } Line { SrcBlock "Register" SrcPort 1 DstBlock "Concat" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Register" DstPort 2 } } } Block { BlockType SubSystem Name "Radio 1 I/Q\nBuffer" SID "145" Ports [3] Position [645, 118, 700, 222] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "Radio 1 I/Q\nBuffer" Location [2, 74, 1270, 726] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Addr_14b" SID "146" Position [190, 68, 220, 82] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "I/Q_32b" SID "147" Position [190, 98, 220, 112] Port "2" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "WE" SID "148" Position [190, 128, 220, 142] Port "3" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Shared Memory" SID "149" Ports [3, 1] Position [320, 60, 400, 150] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Shared Memory" SourceType "Xilinx Shared Memory Random Access Memory Block" shared_memory_name "'RxBuff_Radio1'" depth "2^14" ownership "Locally Owned and Initialized" initVector "0" en off mutex "Unprotected" mode "Read and Write" write_mode "Read After Write" time_out "0" latency "1" explicit_data_type on gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" xl_use_area off xl_area "[0,0,0,0,0,0,0]" implementation "Block RAM" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,384,381" block_type "shmem" block_version "10.1.2" sg_icon_stat "80,90,3,1,white,blue,0,bf435243,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 80 80 0 0 ],[0 0 90 90 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 80 80 0 0 ],[0 0 90 90 0 ]);\npatch([15.525 31.42 42.42 53.42 64.42 42.42 26.525 15.525 ]" ",[57.21 57.21 68.21 57.21 68.21 68.21 68.21 57.21 ],[1 1 1 ]);\npatch([26.525 42.42 31.42 15.525 26.525 ],[46.2" "1 46.21 57.21 57.21 46.21 ],[0.931 0.946 0.973 ]);\npatch([15.525 31.42 42.42 26.525 15.525 ],[35.21 35.21 46.2" "1 46.21 35.21 ],[1 1 1 ]);\npatch([26.525 64.42 53.42 42.42 31.42 15.525 26.525 ],[24.21 24.21 35.21 24.21 35.2" "1 35.21 24.21 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin i" "con text');\ncolor('black');port_label('input',1,'addr');\ncolor('black');port_label('input',2,'din');\ncolor('" "black');port_label('input',3,'we');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end ic" "on text');" } Block { BlockType Terminator Name "Terminator" SID "150" Position [450, 95, 470, 115] ShowName off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "Addr_14b" SrcPort 1 DstBlock "Shared Memory" DstPort 1 } Line { SrcBlock "I/Q_32b" SrcPort 1 DstBlock "Shared Memory" DstPort 2 } Line { SrcBlock "WE" SrcPort 1 DstBlock "Shared Memory" DstPort 3 } Line { SrcBlock "Shared Memory" SrcPort 1 DstBlock "Terminator" DstPort 1 } } } Block { BlockType Scope Name "Scope" SID "151" Ports [2] Position [585, 14, 625, 96] Floating off Location [5, 49, 1285, 757] Open off NumInputPorts "2" ZoomMode "yonly" List { ListType AxesTitles axes1 "%" axes2 "%" } YMin "-5~-5" YMax "5~5" SaveName "ScopeData2" DataFormat "StructureWithTime" MaxDataPoints "40000" SampleTime "0" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "Logical" SrcPort 1 Points [55, 0] Branch { Points [95, 0] Branch { Points [0, -130] DstBlock "Gateway Out1" DstPort 1 } Branch { Labels [0, 0] DstBlock "Radio 1 I/Q\nBuffer" DstPort 3 } } Branch { Points [0, 150] DstBlock "Radio 1\nRSSI Buffer" DstPort 3 } } Line { SrcBlock "Addr" SrcPort 1 Points [75, 0] Branch { Points [0, -100] DstBlock "Gateway Out" DstPort 1 } Branch { Labels [0, 0] DstBlock "Radio 1 I/Q\nBuffer" DstPort 1 } Branch { Points [0, 150] DstBlock "Radio 1\nRSSI Buffer" DstPort 1 } } Line { SrcBlock "WE" SrcPort 1 DstBlock "Logical" DstPort 1 } Line { SrcBlock "EN" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "Logical" DstPort 2 } Line { SrcBlock "I/Q" SrcPort 1 DstBlock "Radio 1 I/Q\nBuffer" DstPort 2 } Line { SrcBlock "Gateway Out" SrcPort 1 DstBlock "Scope" DstPort 1 } Line { SrcBlock "Gateway Out1" SrcPort 1 DstBlock "Scope" DstPort 2 } Line { SrcBlock "RSSI" SrcPort 1 DstBlock "Radio 1\nRSSI Buffer" DstPort 2 } } } Block { BlockType SubSystem Name "Radio 1\nTx Buffer" SID "152" Ports [3, 1] Position [1015, 661, 1095, 719] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "Radio 1\nTx Buffer" Location [6, 74, 1274, 696] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "RdAddr_14b" SID "153" Position [350, 288, 380, 302] NamePlacement "alternate" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "Rst" SID "154" Position [30, 173, 60, 187] Port "2" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "En" SID "155" Position [30, 203, 60, 217] Port "3" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Constant" SID "156" Ports [0, 1] Position [630, 350, 655, 370] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,400,346" block_type "constant" block_version "10.1.2" sg_icon_stat "25,20,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 20 20 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[12.22 12.22 14.2" "2 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[10.22 10.22 12.22 12.22 10.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatch([9.55 1" "6.44 14.44 12.44 10.44 7.55 9.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'0');\nfprin" "tf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant1" SID "157" Ports [0, 1] Position [355, 345, 380, 365] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "32" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,400,346" block_type "constant" block_version "10.1.2" sg_icon_stat "25,20,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 20 20 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[12.22 12.22 14.2" "2 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[10.22 10.22 12.22 12.22 10.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatch([9.55 1" "6.44 14.44 12.44 10.44 7.55 9.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'0');\nfprin" "tf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant2" SID "158" Ports [0, 1] Position [355, 315, 380, 335] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,400,346" block_type "constant" block_version "10.1.2" sg_icon_stat "25,20,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 20 20 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[12.22 12.22 14.2" "2 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[10.22 10.22 12.22 12.22 10.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatch([9.55 1" "6.44 14.44 12.44 10.44 7.55 9.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'0');\nfprin" "tf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert" SID "159" Ports [1, 1] Position [350, 188, 375, 202] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "16" bin_pt "14" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,374,375" block_type "convert" block_version "8.2" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.22 11.22 " "9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 ],[0.931 0." "946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.55 16.44 14.44 " "12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon" " graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'cast');\nfprintf(''," "'COMMENT: end icon text');" } Block { BlockType Reference Name "Convert1" SID "160" Ports [1, 1] Position [100, 203, 120, 217] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "16" bin_pt "14" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,374,375" block_type "convert" block_version "8.2" sg_icon_stat "20,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 14 14 0 ],[0.77 0.82 0.91" " ]);\nplot([0 20 20 0 0 ],[0 0 14 14 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[9.22 9.22 11.22 9" ".22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[0.931 0.94" "6 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([7.55 14.44 12.44 10." "44 8.44 5.55 7.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon gra" "phics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'cast');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "161" Ports [1, 1] Position [150, 201, 180, 219] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "9.1.01" sg_icon_stat "30,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 18 18 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[11.22 11.22 1" "3.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[9.22 9.22 11.22 11.22 9.22" " ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([12" ".55 19.44 17.44 15.44 13.44 10.55 12.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf(''," "'COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nfprintf('" "','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical" SID "162" Ports [2, 1] Position [215, 165, 270, 225] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,261" block_type "logical" block_version "9.1.01" sg_icon_stat "55,60,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 60 60 0 ],[0.77 0.82 0.91" " ]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ],[37.77 37.7" "7 44.77 37.77 44.77 44.77 44.77 37.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[30.77 30.77 37.77 37" ".77 30.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[23.77 23.77 30.77 30.77 23.77 ],[1 1" " 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[16.77 16.77 23.77 16.77 23.77 23.77 16.77 ],[0.931 0" ".946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('bl" "ack');disp('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux" SID "163" Ports [3, 1] Position [750, 273, 795, 377] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,303" block_type "mux" block_version "10.1.2" sg_icon_stat "45,104,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 14.8571 89.1429 104 0 ],[0." "77 0.82 0.91 ]);\nplot([0 45 45 0 0 ],[0 14.8571 89.1429 104 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65" " 8.65 ],[58.66 58.66 64.66 58.66 64.66 64.66 64.66 58.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[52.66" " 52.66 58.66 58.66 52.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[46.66 46.66 52.66 52.66 46" ".66 ],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[40.66 40.66 46.66 40.66 46.66 46.66 40.66 ],[0" ".931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('input',3" ",'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Shared Memory" SID "164" Ports [3, 1] Position [445, 280, 525, 370] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Shared Memory" SourceType "Xilinx Shared Memory Random Access Memory Block" shared_memory_name "'TxBuff_Radio1'" depth "2^14" ownership "Locally Owned and Initialized" initVector "0" en off mutex "Unprotected" mode "Read and Write" write_mode "Read After Write" time_out "0" latency "1" explicit_data_type on gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" xl_use_area off xl_area "[0,0,0,0,0,0,0]" implementation "Block RAM" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,384,381" block_type "shmem" block_version "10.1.2" sg_icon_stat "80,90,3,1,white,blue,0,bf435243,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 80 80 0 0 ],[0 0 90 90 0 ],[0.77 0.82 0.91" " ]);\nplot([0 80 80 0 0 ],[0 0 90 90 0 ]);\npatch([15.525 31.42 42.42 53.42 64.42 42.42 26.525 15.525 ],[57.21 57.2" "1 68.21 57.21 68.21 68.21 68.21 57.21 ],[1 1 1 ]);\npatch([26.525 42.42 31.42 15.525 26.525 ],[46.21 46.21 57.21 57" ".21 46.21 ],[0.931 0.946 0.973 ]);\npatch([15.525 31.42 42.42 26.525 15.525 ],[35.21 35.21 46.21 46.21 35.21 ],[1 1" " 1 ]);\npatch([26.525 64.42 53.42 42.42 31.42 15.525 26.525 ],[24.21 24.21 35.21 24.21 35.21 35.21 24.21 ],[0.931 0" ".946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');" "port_label('input',1,'addr');\ncolor('black');port_label('input',2,'din');\ncolor('black');port_label('input',3,'we" "');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "IQ_32b" SID "165" Position [885, 318, 915, 332] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "Logical" SrcPort 1 DstBlock "Convert" DstPort 1 } Line { SrcBlock "Convert" SrcPort 1 Points [160, 0; 0, 95] DstBlock "Mux" DstPort 1 } Line { SrcBlock "Rst" SrcPort 1 DstBlock "Logical" DstPort 1 } Line { SrcBlock "En" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "Inverter" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical" DstPort 2 } Line { SrcBlock "RdAddr_14b" SrcPort 1 DstBlock "Shared Memory" DstPort 1 } Line { SrcBlock "Constant" SrcPort 1 DstBlock "Mux" DstPort 3 } Line { SrcBlock "Shared Memory" SrcPort 1 DstBlock "Mux" DstPort 2 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Shared Memory" DstPort 3 } Line { SrcBlock "Constant2" SrcPort 1 DstBlock "Shared Memory" DstPort 2 } Line { SrcBlock "Mux" SrcPort 1 DstBlock "IQ_32b" DstPort 1 } } } Block { BlockType SubSystem Name "Radio 1 Inputs" SID "166" Ports [2, 2] Position [900, 32, 1085, 83] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "Radio 1 Inputs" Location [534, 197, 1546, 748] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "DebugRxBuffers" SID "167" Position [180, 258, 210, 272] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "MGCAGC_AGCDCO_SEL" SID "168" Position [185, 348, 215, 362] Port "2" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType SubSystem Name "ADC I" SID "169" Ports [2, 2] Position [420, 254, 575, 301] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "ADC I" Location [693, 213, 1705, 865] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Debug" SID "170" Position [685, 53, 715, 67] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "MGCAGC_AGCDCO_SEL" SID "171" Position [130, 243, 160, 257] Port "2" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Constant Name "Constant1" SID "172" Position [15, 320, 45, 350] ShowName off Value "0" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Counter" SID "173" Ports [0, 1] Position [520, 340, 580, 400] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited co" "unter is implemented by combining a counter with a comparator." cnt_type "Free Running" cnt_to "Inf" operation "Down" start_count "2^14-1" cnt_by_val "1" arith_type "Unsigned" n_bits "14" bin_pt "0" load_pin off rst off en off explicit_period "on" period "1" dbl_ovrd off use_behavioral_HDL off implementation "Fabric" xl_use_area off xl_area "[0,0,0,0,0,0,0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,619" block_type "counter" block_version "10.1.3" sg_icon_stat "60,60,0,1,white,blue,0,cf0fdd8c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 60 60 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 60 60 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[38.8" "8 38.88 46.88 38.88 46.88 46.88 46.88 38.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[30.88 30.88 38.8" "8 38.88 30.88 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[22.88 22.88 30.88 30.88 22.88 ],[1" " 1 1 ]);\npatch([20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[14.88 14.88 22.88 14.88 22.88 22.88 14.88 ],[0.931 0" ".946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('bl" "ack');disp('{\\fontsize{14}\\bf--}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "FromAGC_Radio1_I" SID "174" Ports [1, 1] Position [115, 425, 180, 445] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, double and fixed point to Xilinx" " fixed point type.

Hardware notes: In hardware these blocks become top level input ports." gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "14" bin_pt "13" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off UseAsADC off ADCChannel "'1'" hdl_port "on" has_advanced_control "0" sggui_pos "20,20,348,406" block_type "gatewayin" block_version "10.1.3" sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0" ".93 0.65 ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[1" "2.22 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.2" "2 12.22 12.22 10.22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.2" "2 ],[1 1 1 ]);\npatch([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985" " 0.979 0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' " "');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux" SID "175" Ports [3, 1] Position [820, 88, 865, 192] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "1" bin_pt "0" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,303" block_type "mux" block_version "10.1.3" sg_icon_stat "45,104,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 14.8571 89.1429 104" " 0 ],[0.77 0.82 0.91 ]);\nplot([0 45 45 0 0 ],[0 14.8571 89.1429 104 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32" " 23.32 14.65 8.65 ],[58.66 58.66 64.66 58.66 64.66 64.66 64.66 58.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.6" "5 14.65 ],[52.66 52.66 58.66 58.66 52.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[46.66 " "46.66 52.66 52.66 46.66 ],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[40.66 40.66 46.66 40.6" "6 46.66 46.66 40.66 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: b" "egin icon text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncol" "or('black');port_label('input',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: " "end icon text');" } Block { BlockType Reference Name "Mux1" SID "176" Ports [3, 1] Position [820, 283, 865, 387] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "1" bin_pt "0" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,303" block_type "mux" block_version "10.1.3" sg_icon_stat "45,104,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 14.8571 89.1429 104" " 0 ],[0.77 0.82 0.91 ]);\nplot([0 45 45 0 0 ],[0 14.8571 89.1429 104 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32" " 23.32 14.65 8.65 ],[58.66 58.66 64.66 58.66 64.66 64.66 64.66 58.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.6" "5 14.65 ],[52.66 52.66 58.66 58.66 52.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[46.66 " "46.66 52.66 52.66 46.66 ],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[40.66 40.66 46.66 40.6" "6 46.66 46.66 40.66 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: b" "egin icon text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncol" "or('black');port_label('input',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: " "end icon text');" } Block { BlockType Reference Name "Mux2" SID "177" Ports [3, 1] Position [275, 283, 320, 387] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "1" bin_pt "0" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,303" block_type "mux" block_version "10.1.3" sg_icon_stat "45,104,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 14.8571 89.1429 104" " 0 ],[0.77 0.82 0.91 ]);\nplot([0 45 45 0 0 ],[0 14.8571 89.1429 104 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32" " 23.32 14.65 8.65 ],[58.66 58.66 64.66 58.66 64.66 64.66 64.66 58.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.6" "5 14.65 ],[52.66 52.66 58.66 58.66 52.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[46.66 " "46.66 52.66 52.66 46.66 ],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[40.66 40.66 46.66 40.6" "6 46.66 46.66 40.66 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: b" "egin icon text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncol" "or('black');port_label('input',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: " "end icon text');" } Block { BlockType Reference Name "Radio 1 ADC I" SID "178" Ports [1, 1] Position [105, 314, 200, 356] LibraryVersion "1.48" LinkData { BlockName "radio1_adc_I" DialogParameters { sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.6" "5 ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[12.22 12.22" " 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.22 12.22 12.22" " 10.22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\n" "patch([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('inpu" "t',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT:" " end icon text');\n" } } SourceBlock "WARP_Blockset/WARP Radio Board ADC//DACs/Radio 1 ADC I" SourceType "" ShowPortLabels "FromPortIcon" SystemSampleTime "-1" FunctionWithSeparateData off RTWMemSecFuncInitTerm "Inherit from model" RTWMemSecFuncExecute "Inherit from model" RTWMemSecDataConstants "Inherit from model" RTWMemSecDataInternal "Inherit from model" RTWMemSecDataParameters "Inherit from model" GeneratePreprocessorConditionals off samp_period "1" } Block { BlockType Reference Name "Register" SID "179" Ports [1, 1] Position [450, 321, 485, 349] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "8.2" sg_icon_stat "35,28,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 28 28 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 28 28 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[18.44 " "18.44 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[14.44 14.44 18.44 1" "8.44 14.44 ],[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 " "]);\npatch([12.1 25.88 21.88 17.88 13.88 8.1 12.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Reinterpret" SID "180" Ports [1, 1] Position [665, 354, 715, 386] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can changed the signal b" "etween signed and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs no" "thing.

Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is force" "d to unsigned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an outp" "ut of 56 (111000 in binary)." force_arith_type on arith_type "Signed (2's comp)" force_bin_pt on bin_pt "13" has_advanced_control "0" sggui_pos "20,20,336,312" block_type "reinterpret" block_version "10.1.3" sg_icon_stat "50,32,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 32 32 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 32 32 0 ]);\npatch([16.1 21.88 25.88 29.88 33.88 25.88 20.1 16.1 ],[20.4" "4 20.44 24.44 20.44 24.44 24.44 24.44 20.44 ],[1 1 1 ]);\npatch([20.1 25.88 21.88 16.1 20.1 ],[16.44 16.44 20.4" "4 20.44 16.44 ],[0.931 0.946 0.973 ]);\npatch([16.1 21.88 25.88 20.1 16.1 ],[12.44 12.44 16.44 16.44 12.44 ],[1" " 1 1 ]);\npatch([20.1 33.88 29.88 25.88 21.88 16.1 20.1 ],[8.44 8.44 12.44 8.44 12.44 12.44 8.44 ],[0.931 0.946" " 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('blac" "k');disp('reinterpret');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Slice" SID "181" Ports [1, 1] Position [670, 160, 730, 190] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outp" "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

" "

Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,376" block_type "slice" block_version "10.1.3" sg_icon_stat "60,30,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 30 30 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\npatch([21.1 26.88 30.88 34.88 38.88 30.88 25.1 21.1 ],[19.4" "4 19.44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([25.1 30.88 26.88 21.1 25.1 ],[15.44 15.44 19.4" "4 19.44 15.44 ],[0.931 0.946 0.973 ]);\npatch([21.1 26.88 30.88 25.1 21.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1" " 1 1 ]);\npatch([25.1 38.88 34.88 30.88 26.88 21.1 25.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946" " 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black'" ");port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "radio1_ADC_I_OTR" SID "182" Ports [1, 1] Position [110, 134, 165, 146] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, double and fixed point to Xilinx" " fixed point type.

Hardware notes: In hardware these blocks become top level input ports." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off UseAsADC off ADCChannel "'1'" hdl_port "on" has_advanced_control "0" sggui_pos "20,20,356,432" block_type "gatewayin" block_version "VER_STRING_GOES_HERE" sg_icon_stat "55,12,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 12 12 0 ],[0.95 0" ".93 0.65 ]);\nplot([0 55 55 0 0 ],[0 0 12 12 0 ]);\npatch([24.775 26.22 27.22 28.22 29.22 27.22 25.775 24.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([25.775 27.22 26.22 24.775 25.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.985 0.979 0.895 ]);\npatch([24.775 26.22 27.22 25.775 24.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([25.775 29.22 28.22 27.22 26.22 24.775 25.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.985 0." "979 0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "OTR I" SID "183" Position [925, 133, 955, 147] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Outport Name "ADC I" SID "184" Position [925, 328, 955, 342] Port "2" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "Constant1" SrcPort 1 Points [20, 0] Branch { Points [0, -195] DstBlock "radio1_ADC_I_OTR" DstPort 1 } Branch { DstBlock "Radio 1 ADC I" DstPort 1 } Branch { Points [0, 100] DstBlock "FromAGC_Radio1_I" DstPort 1 } } Line { SrcBlock "Mux" SrcPort 1 DstBlock "OTR I" DstPort 1 } Line { SrcBlock "Debug" SrcPort 1 Points [40, 0; 0, 45] Branch { DstBlock "Mux" DstPort 1 } Branch { Points [0, 195] DstBlock "Mux1" DstPort 1 } } Line { SrcBlock "radio1_ADC_I_OTR" SrcPort 1 DstBlock "Mux" DstPort 2 } Line { SrcBlock "Slice" SrcPort 1 DstBlock "Mux" DstPort 3 } Line { SrcBlock "Mux1" SrcPort 1 DstBlock "ADC I" DstPort 1 } Line { SrcBlock "Register" SrcPort 1 DstBlock "Mux1" DstPort 2 } Line { SrcBlock "Reinterpret" SrcPort 1 DstBlock "Mux1" DstPort 3 } Line { SrcBlock "Counter" SrcPort 1 Points [25, 0] Branch { DstBlock "Reinterpret" DstPort 1 } Branch { Points [0, -195] DstBlock "Slice" DstPort 1 } } Line { SrcBlock "MGCAGC_AGCDCO_SEL" SrcPort 1 Points [70, 0; 0, 50] DstBlock "Mux2" DstPort 1 } Line { SrcBlock "FromAGC_Radio1_I" SrcPort 1 Points [50, 0; 0, -65] DstBlock "Mux2" DstPort 3 } Line { SrcBlock "Mux2" SrcPort 1 DstBlock "Register" DstPort 1 } Line { SrcBlock "Radio 1 ADC I" SrcPort 1 DstBlock "Mux2" DstPort 2 } } } Block { BlockType SubSystem Name "ADC Q" SID "185" Ports [2, 2] Position [420, 324, 575, 366] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "ADC Q" Location [66, 91, 1078, 743] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Debug" SID "186" Position [630, 43, 660, 57] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "MGCAGC_AGCDCO_SEL" SID "187" Position [120, 233, 150, 247] Port "2" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Constant Name "Constant1" SID "188" Position [15, 310, 45, 340] ShowName off Value "0" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Counter" SID "189" Ports [0, 1] Position [460, 330, 520, 390] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited co" "unter is implemented by combining a counter with a comparator." cnt_type "Free Running" cnt_to "Inf" operation "Up" start_count "0" cnt_by_val "1" arith_type "Unsigned" n_bits "14" bin_pt "0" load_pin off rst off en off explicit_period "on" period "1" dbl_ovrd off use_behavioral_HDL off implementation "Fabric" xl_use_area off xl_area "[0,0,0,0,0,0,0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,619" block_type "counter" block_version "10.1.3" sg_icon_stat "60,60,0,1,white,blue,0,7ac47ef5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 60 60 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 60 60 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[38.8" "8 38.88 46.88 38.88 46.88 46.88 46.88 38.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[30.88 30.88 38.8" "8 38.88 30.88 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[22.88 22.88 30.88 30.88 22.88 ],[1" " 1 1 ]);\npatch([20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[14.88 14.88 22.88 14.88 22.88 22.88 14.88 ],[0.931 0" ".946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('bl" "ack');disp('{\\fontsize{14}\\bf++}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "FromAGC_Radio1_Q" SID "190" Ports [1, 1] Position [105, 415, 170, 435] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, double and fixed point to Xilinx" " fixed point type.

Hardware notes: In hardware these blocks become top level input ports." gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "14" bin_pt "13" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off UseAsADC off ADCChannel "'1'" hdl_port "on" has_advanced_control "0" sggui_pos "20,20,348,406" block_type "gatewayin" block_version "10.1.3" sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0" ".93 0.65 ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[1" "2.22 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.2" "2 12.22 12.22 10.22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.2" "2 ],[1 1 1 ]);\npatch([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985" " 0.979 0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' " "');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux" SID "191" Ports [3, 1] Position [765, 78, 810, 182] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "1" bin_pt "0" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,303" block_type "mux" block_version "10.1.3" sg_icon_stat "45,104,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 14.8571 89.1429 104" " 0 ],[0.77 0.82 0.91 ]);\nplot([0 45 45 0 0 ],[0 14.8571 89.1429 104 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32" " 23.32 14.65 8.65 ],[58.66 58.66 64.66 58.66 64.66 64.66 64.66 58.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.6" "5 14.65 ],[52.66 52.66 58.66 58.66 52.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[46.66 " "46.66 52.66 52.66 46.66 ],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[40.66 40.66 46.66 40.6" "6 46.66 46.66 40.66 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: b" "egin icon text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncol" "or('black');port_label('input',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: " "end icon text');" } Block { BlockType Reference Name "Mux1" SID "192" Ports [3, 1] Position [765, 273, 810, 377] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "1" bin_pt "0" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,303" block_type "mux" block_version "10.1.3" sg_icon_stat "45,104,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 14.8571 89.1429 104" " 0 ],[0.77 0.82 0.91 ]);\nplot([0 45 45 0 0 ],[0 14.8571 89.1429 104 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32" " 23.32 14.65 8.65 ],[58.66 58.66 64.66 58.66 64.66 64.66 64.66 58.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.6" "5 14.65 ],[52.66 52.66 58.66 58.66 52.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[46.66 " "46.66 52.66 52.66 46.66 ],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[40.66 40.66 46.66 40.6" "6 46.66 46.66 40.66 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: b" "egin icon text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncol" "or('black');port_label('input',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: " "end icon text');" } Block { BlockType Reference Name "Mux2" SID "193" Ports [3, 1] Position [265, 273, 310, 377] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "1" bin_pt "0" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,303" block_type "mux" block_version "10.1.3" sg_icon_stat "45,104,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 14.8571 89.1429 104" " 0 ],[0.77 0.82 0.91 ]);\nplot([0 45 45 0 0 ],[0 14.8571 89.1429 104 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32" " 23.32 14.65 8.65 ],[58.66 58.66 64.66 58.66 64.66 64.66 64.66 58.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.6" "5 14.65 ],[52.66 52.66 58.66 58.66 52.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[46.66 " "46.66 52.66 52.66 46.66 ],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[40.66 40.66 46.66 40.6" "6 46.66 46.66 40.66 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: b" "egin icon text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncol" "or('black');port_label('input',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: " "end icon text');" } Block { BlockType Reference Name "Radio 1 ADC Q" SID "194" Ports [1, 1] Position [90, 304, 185, 346] LibraryVersion "1.48" LinkData { BlockName "radio1_adc_Q" DialogParameters { sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.6" "5 ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[12.22 12.22" " 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.22 12.22 12.22" " 10.22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\n" "patch([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('inpu" "t',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT:" " end icon text');\n" } } SourceBlock "WARP_Blockset/WARP Radio Board ADC//DACs/Radio 1 ADC Q" SourceType "" ShowPortLabels "FromPortIcon" SystemSampleTime "-1" FunctionWithSeparateData off RTWMemSecFuncInitTerm "Inherit from model" RTWMemSecFuncExecute "Inherit from model" RTWMemSecDataConstants "Inherit from model" RTWMemSecDataInternal "Inherit from model" RTWMemSecDataParameters "Inherit from model" GeneratePreprocessorConditionals off samp_period "1" } Block { BlockType Reference Name "Register" SID "195" Ports [1, 1] Position [390, 311, 425, 339] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "8.2" sg_icon_stat "35,28,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 28 28 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 28 28 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[18.44 " "18.44 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[14.44 14.44 18.44 1" "8.44 14.44 ],[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 " "]);\npatch([12.1 25.88 21.88 17.88 13.88 8.1 12.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Reinterpret" SID "196" Ports [1, 1] Position [610, 344, 660, 376] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can changed the signal b" "etween signed and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs no" "thing.

Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is force" "d to unsigned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an outp" "ut of 56 (111000 in binary)." force_arith_type on arith_type "Signed (2's comp)" force_bin_pt on bin_pt "13" has_advanced_control "0" sggui_pos "20,20,336,312" block_type "reinterpret" block_version "10.1.3" sg_icon_stat "50,32,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 32 32 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 32 32 0 ]);\npatch([16.1 21.88 25.88 29.88 33.88 25.88 20.1 16.1 ],[20.4" "4 20.44 24.44 20.44 24.44 24.44 24.44 20.44 ],[1 1 1 ]);\npatch([20.1 25.88 21.88 16.1 20.1 ],[16.44 16.44 20.4" "4 20.44 16.44 ],[0.931 0.946 0.973 ]);\npatch([16.1 21.88 25.88 20.1 16.1 ],[12.44 12.44 16.44 16.44 12.44 ],[1" " 1 1 ]);\npatch([20.1 33.88 29.88 25.88 21.88 16.1 20.1 ],[8.44 8.44 12.44 8.44 12.44 12.44 8.44 ],[0.931 0.946" " 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('blac" "k');disp('reinterpret');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Slice" SID "197" Ports [1, 1] Position [615, 150, 675, 180] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outp" "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

" "

Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,376" block_type "slice" block_version "10.1.3" sg_icon_stat "60,30,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 30 30 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\npatch([21.1 26.88 30.88 34.88 38.88 30.88 25.1 21.1 ],[19.4" "4 19.44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([25.1 30.88 26.88 21.1 25.1 ],[15.44 15.44 19.4" "4 19.44 15.44 ],[0.931 0.946 0.973 ]);\npatch([21.1 26.88 30.88 25.1 21.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1" " 1 1 ]);\npatch([25.1 38.88 34.88 30.88 26.88 21.1 25.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946" " 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black'" ");port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "radio1_ADC_Q_OTR" SID "198" Ports [1, 1] Position [115, 124, 170, 136] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, double and fixed point to Xilinx" " fixed point type.

Hardware notes: In hardware these blocks become top level input ports." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off UseAsADC off ADCChannel "'1'" hdl_port "on" has_advanced_control "0" sggui_pos "20,20,356,432" block_type "gatewayin" block_version "VER_STRING_GOES_HERE" sg_icon_stat "55,12,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 12 12 0 ],[0.95 0" ".93 0.65 ]);\nplot([0 55 55 0 0 ],[0 0 12 12 0 ]);\npatch([24.775 26.22 27.22 28.22 29.22 27.22 25.775 24.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([25.775 27.22 26.22 24.775 25.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.985 0.979 0.895 ]);\npatch([24.775 26.22 27.22 25.775 24.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([25.775 29.22 28.22 27.22 26.22 24.775 25.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.985 0." "979 0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "OTR Q" SID "199" Position [905, 123, 935, 137] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Outport Name "ADC Q" SID "200" Position [905, 318, 935, 332] Port "2" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "Constant1" SrcPort 1 Points [20, 0] Branch { Points [0, -195] DstBlock "radio1_ADC_Q_OTR" DstPort 1 } Branch { DstBlock "Radio 1 ADC Q" DstPort 1 } Branch { Points [0, 100] DstBlock "FromAGC_Radio1_Q" DstPort 1 } } Line { SrcBlock "Mux" SrcPort 1 DstBlock "OTR Q" DstPort 1 } Line { SrcBlock "Debug" SrcPort 1 Points [40, 0; 0, 45] Branch { DstBlock "Mux" DstPort 1 } Branch { Points [0, 195] DstBlock "Mux1" DstPort 1 } } Line { SrcBlock "radio1_ADC_Q_OTR" SrcPort 1 DstBlock "Mux" DstPort 2 } Line { SrcBlock "Slice" SrcPort 1 DstBlock "Mux" DstPort 3 } Line { SrcBlock "Mux1" SrcPort 1 DstBlock "ADC Q" DstPort 1 } Line { SrcBlock "Register" SrcPort 1 DstBlock "Mux1" DstPort 2 } Line { SrcBlock "Reinterpret" SrcPort 1 DstBlock "Mux1" DstPort 3 } Line { SrcBlock "Counter" SrcPort 1 Points [30, 0] Branch { DstBlock "Reinterpret" DstPort 1 } Branch { Points [0, -195] DstBlock "Slice" DstPort 1 } } Line { SrcBlock "MGCAGC_AGCDCO_SEL" SrcPort 1 Points [70, 0; 0, 50] DstBlock "Mux2" DstPort 1 } Line { SrcBlock "FromAGC_Radio1_Q" SrcPort 1 Points [50, 0; 0, -65] DstBlock "Mux2" DstPort 3 } Line { SrcBlock "Radio 1 ADC Q" SrcPort 1 DstBlock "Mux2" DstPort 2 } Line { SrcBlock "Mux2" SrcPort 1 DstBlock "Register" DstPort 1 } } } Block { BlockType SubSystem Name "Concatenates_1" SID "201" Ports [4, 1] Position [695, 218, 740, 372] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "Concatenates_1" Location [2, 74, 1270, 726] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "OTR_I" SID "202" Position [395, 43, 425, 57] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "ADC_I" SID "203" Position [330, 93, 360, 107] Port "2" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "OTR_Q" SID "204" Position [390, 163, 420, 177] Port "3" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "ADC_Q" SID "205" Position [330, 213, 360, 227] Port "4" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Concat1" SID "206" Ports [2, 1] Position [490, 191, 520, 229] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary poi" "nt at zero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" block_version "8.2" sg_icon_stat "30,38,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 38 38 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 38 38 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[23.44 " "23.44 27.44 23.44 27.44 27.44 27.44 23.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[19.44 19.44 23.44 2" "3.44 19.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[15.44 15.44 19.44 19.44 15.44 ],[1 1 1 " "]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[11.44 11.44 15.44 11.44 15.44 15.44 11.44 ],[0.931 0.946 0" ".973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');po" "rt_label('input',1,'hi');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\fontsize{20}\\}" "','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Concat2" SID "207" Ports [2, 1] Position [490, 71, 520, 109] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary poi" "nt at zero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" block_version "8.2" sg_icon_stat "30,38,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 38 38 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 38 38 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[23.44 " "23.44 27.44 23.44 27.44 27.44 27.44 23.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[19.44 19.44 23.44 2" "3.44 19.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[15.44 15.44 19.44 19.44 15.44 ],[1 1 1 " "]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[11.44 11.44 15.44 11.44 15.44 15.44 11.44 ],[0.931 0.946 0" ".973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');po" "rt_label('input',1,'hi');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\fontsize{20}\\}" "','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Concat3" SID "208" Ports [2, 1] Position [550, 150, 575, 230] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary poi" "nt at zero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" block_version "8.2" sg_icon_stat "25,80,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 80 80 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 80 80 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[43" ".33 43.33 46.33 43.33 46.33 46.33 46.33 43.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[40.33 40.33 " "43.33 43.33 40.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[37.33 37.33 40.33 40.33 37.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[34.33 34.33 37.33 34.33 37.33 37.33 34.33 ]," "[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncol" "or('black');port_label('input',1,'hi');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\f" "ontsize{20}\\}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Concat4" SID "209" Ports [2, 1] Position [550, 30, 575, 110] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary poi" "nt at zero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" block_version "8.2" sg_icon_stat "25,80,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 80 80 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 80 80 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[43" ".33 43.33 46.33 43.33 46.33 46.33 46.33 43.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[40.33 40.33 " "43.33 43.33 40.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[37.33 37.33 40.33 40.33 37.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[34.33 34.33 37.33 34.33 37.33 37.33 34.33 ]," "[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncol" "or('black');port_label('input',1,'hi');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\f" "ontsize{20}\\}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Concat5" SID "210" Ports [2, 1] Position [635, 50, 660, 130] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary poi" "nt at zero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" block_version "8.2" sg_icon_stat "25,80,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 80 80 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 80 80 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[43" ".33 43.33 46.33 43.33 46.33 46.33 46.33 43.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[40.33 40.33 " "43.33 43.33 40.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[37.33 37.33 40.33 40.33 37.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[34.33 34.33 37.33 34.33 37.33 37.33 34.33 ]," "[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncol" "or('black');port_label('input',1,'hi');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\f" "ontsize{20}\\}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Reinterpret" SID "211" Ports [1, 1] Position [385, 90, 420, 110] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can changed the signal b" "etween signed and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs no" "thing.

Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is force" "d to unsigned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an outp" "ut of 56 (111000 in binary)." force_arith_type on arith_type "Unsigned" force_bin_pt on bin_pt "0" has_advanced_control "0" sggui_pos "20,20,356,309" block_type "reinterpret" block_version "8.2" sg_icon_stat "35,20,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 20 20 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 20 20 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[1" "2.22 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[10.22 10.2" "2 12.22 12.22 10.22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[8.22 8.22 10.22 10.22 8.2" "2 ],[1 1 1 ]);\npatch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931" " 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor" "('black');disp('reinterpret');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Reinterpret1" SID "212" Ports [1, 1] Position [390, 210, 425, 230] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can changed the signal b" "etween signed and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs no" "thing.

Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is force" "d to unsigned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an outp" "ut of 56 (111000 in binary)." force_arith_type on arith_type "Unsigned" force_bin_pt on bin_pt "0" has_advanced_control "0" sggui_pos "20,20,356,309" block_type "reinterpret" block_version "8.2" sg_icon_stat "35,20,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 20 20 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 20 20 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[1" "2.22 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[10.22 10.2" "2 12.22 12.22 10.22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[8.22 8.22 10.22 10.22 8.2" "2 ],[1 1 1 ]);\npatch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931" " 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor" "('black');disp('reinterpret');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "zero" SID "213" Ports [0, 1] Position [440, 191, 460, 209] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "20,18,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 20 20 0 0 ],[0 0 18 18 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[9.22 9.22 11.22 11" ".22 9.22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\np" "atch([7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfpr" "intf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('out" "put',1,'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "zero1" SID "214" Ports [0, 1] Position [440, 71, 460, 89] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "20,18,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 20 20 0 0 ],[0 0 18 18 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[9.22 9.22 11.22 11" ".22 9.22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\np" "atch([7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfpr" "intf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('out" "put',1,'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "32b" SID "215" Position [685, 83, 715, 97] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "Reinterpret1" SrcPort 1 DstBlock "Concat1" DstPort 2 } Line { SrcBlock "Reinterpret" SrcPort 1 DstBlock "Concat2" DstPort 2 } Line { SrcBlock "ADC_Q" SrcPort 1 DstBlock "Reinterpret1" DstPort 1 } Line { SrcBlock "OTR_Q" SrcPort 1 DstBlock "Concat3" DstPort 1 } Line { SrcBlock "ADC_I" SrcPort 1 DstBlock "Reinterpret" DstPort 1 } Line { SrcBlock "Concat5" SrcPort 1 DstBlock "32b" DstPort 1 } Line { SrcBlock "OTR_I" SrcPort 1 DstBlock "Concat4" DstPort 1 } Line { SrcBlock "Concat3" SrcPort 1 Points [25, 0; 0, -80] DstBlock "Concat5" DstPort 2 } Line { SrcBlock "Concat4" SrcPort 1 DstBlock "Concat5" DstPort 1 } Line { SrcBlock "Concat2" SrcPort 1 Points [0, 0] DstBlock "Concat4" DstPort 2 } Line { SrcBlock "zero1" SrcPort 1 DstBlock "Concat2" DstPort 1 } Line { SrcBlock "Concat1" SrcPort 1 DstBlock "Concat3" DstPort 2 } Line { SrcBlock "zero" SrcPort 1 DstBlock "Concat1" DstPort 1 } } } Block { BlockType Reference Name "Gateway Out1" SID "216" Ports [1, 1] Position [710, 135, 740, 145] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, double, o" "r fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarded, depen" "ding on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" UseAsDAC off DACChannel "'1'" has_advanced_control "0" sggui_pos "20,20,336,386" block_type "gatewayout" block_version "10.1.2" sg_icon_stat "30,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 10 10 0 ],[0.88 0.88 0.88" " ]);\nplot([0 30 30 0 0 ],[0 0 10 10 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ],[6.11 6.11 " "7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[5.11 5.11 6.11 6.11 5.11 ],[" "0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]);\npatch([13." "775 17.22 16.22 15.22 14.22 12.775 13.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.964 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ')" ";\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" } Block { BlockType Reference Name "Gateway Out4" SID "217" Ports [1, 1] Position [710, 120, 740, 130] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, double, o" "r fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarded, depen" "ding on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" UseAsDAC off DACChannel "'1'" has_advanced_control "0" sggui_pos "20,20,336,386" block_type "gatewayout" block_version "10.1.2" sg_icon_stat "30,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 10 10 0 ],[0.88 0.88 0.88" " ]);\nplot([0 30 30 0 0 ],[0 0 10 10 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ],[6.11 6.11 " "7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[5.11 5.11 6.11 6.11 5.11 ],[" "0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]);\npatch([13." "775 17.22 16.22 15.22 14.22 12.775 13.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.964 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ')" ";\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" } Block { BlockType SubSystem Name "RSSI" SID "218" Ports [1, 1] Position [470, 397, 540, 433] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "RSSI" Location [2, 74, 1184, 726] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Debug" SID "219" Position [465, 28, 495, 42] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Constant Name "Constant1" SID "220" Position [160, 100, 190, 130] ShowName off Value "0" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Counter" SID "221" Ports [0, 1] Position [380, 120, 440, 180] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited co" "unter is implemented by combining a counter with a comparator." cnt_type "Free Running" cnt_to "Inf" operation "Up" start_count "0" cnt_by_val "1" arith_type "Unsigned" n_bits "10" bin_pt "0" load_pin off rst off en off explicit_period "on" period "1" dbl_ovrd off use_behavioral_HDL off implementation "Fabric" xl_use_area off xl_area "[0,0,0,0,0,0,0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,619" block_type "counter" block_version "10.1.3" sg_icon_stat "60,60,0,1,white,blue,0,7ac47ef5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 60 60 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 60 60 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[38.8" "8 38.88 46.88 38.88 46.88 46.88 46.88 38.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[30.88 30.88 38.8" "8 38.88 30.88 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[22.88 22.88 30.88 30.88 22.88 ],[1" " 1 1 ]);\npatch([20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[14.88 14.88 22.88 14.88 22.88 22.88 14.88 ],[0.931 0" ".946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('bl" "ack');disp('{\\fontsize{14}\\bf++}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux" SID "222" Ports [3, 1] Position [600, 63, 645, 167] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "1" bin_pt "0" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,303" block_type "mux" block_version "10.1.3" sg_icon_stat "45,104,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 14.8571 89.1429 104" " 0 ],[0.77 0.82 0.91 ]);\nplot([0 45 45 0 0 ],[0 14.8571 89.1429 104 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32" " 23.32 14.65 8.65 ],[58.66 58.66 64.66 58.66 64.66 64.66 64.66 58.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.6" "5 14.65 ],[52.66 52.66 58.66 58.66 52.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[46.66 " "46.66 52.66 52.66 46.66 ],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[40.66 40.66 46.66 40.6" "6 46.66 46.66 40.66 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: b" "egin icon text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncol" "or('black');port_label('input',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: " "end icon text');" } Block { BlockType Reference Name "radio1_RSSI" SID "223" Ports [1, 1] Position [280, 109, 335, 121] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, double and fixed point to Xilinx" " fixed point type.

Hardware notes: In hardware these blocks become top level input ports." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "10" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Truncate" overflow "Wrap" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off UseAsADC off ADCChannel "'1'" hdl_port "on" has_advanced_control "0" sggui_pos "20,20,356,432" block_type "gatewayin" block_version "VER_STRING_GOES_HERE" sg_icon_stat "55,12,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 12 12 0 ],[0.95 0" ".93 0.65 ]);\nplot([0 55 55 0 0 ],[0 0 12 12 0 ]);\npatch([24.775 26.22 27.22 28.22 29.22 27.22 25.775 24.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([25.775 27.22 26.22 24.775 25.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.985 0.979 0.895 ]);\npatch([24.775 26.22 27.22 25.775 24.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([25.775 29.22 28.22 27.22 26.22 24.775 25.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.985 0." "979 0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "RSSI" SID "224" Position [740, 108, 770, 122] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "radio1_RSSI" DstPort 1 } Line { SrcBlock "Debug" SrcPort 1 Points [40, 0; 0, 45] DstBlock "Mux" DstPort 1 } Line { SrcBlock "radio1_RSSI" SrcPort 1 DstBlock "Mux" DstPort 2 } Line { SrcBlock "Counter" SrcPort 1 DstBlock "Mux" DstPort 3 } Line { SrcBlock "Mux" SrcPort 1 DstBlock "RSSI" DstPort 1 } } } Block { BlockType Scope Name "Scope" SID "225" Ports [2] Position [800, 111, 830, 164] Floating off Location [5, 34, 1285, 912] Open off NumInputPorts "2" List { ListType AxesTitles axes1 "%" axes2 "%" } YMin "-5~-5" YMax "5~5" DataFormat "StructureWithTime" SampleTime "0" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Outport Name "Radio 1 RSSI" SID "226" Position [655, 408, 685, 422] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Outport Name "Radio 1 I/Q" SID "227" Position [865, 288, 895, 302] Port "2" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "ADC Q" SrcPort 2 Points [85, 0] Branch { DstBlock "Concatenates_1" DstPort 4 } Branch { Points [0, -215] DstBlock "Gateway Out1" DstPort 1 } } Line { SrcBlock "ADC Q" SrcPort 1 Points [0, -20] DstBlock "Concatenates_1" DstPort 3 } Line { Labels [0, 0] SrcBlock "ADC I" SrcPort 2 Points [0, -15; 75, 0] Branch { DstBlock "Concatenates_1" DstPort 2 } Branch { Points [0, -150] DstBlock "Gateway Out4" DstPort 1 } } Line { SrcBlock "ADC I" SrcPort 1 Points [35, 0; 0, -30] DstBlock "Concatenates_1" DstPort 1 } Line { SrcBlock "Concatenates_1" SrcPort 1 Points [0, 0] DstBlock "Radio 1 I/Q" DstPort 1 } Line { SrcBlock "Gateway Out4" SrcPort 1 DstBlock "Scope" DstPort 1 } Line { SrcBlock "Gateway Out1" SrcPort 1 Points [40, 0] DstBlock "Scope" DstPort 2 } Line { SrcBlock "DebugRxBuffers" SrcPort 1 Points [160, 0] Branch { DstBlock "ADC I" DstPort 1 } Branch { Points [0, 70] Branch { DstBlock "ADC Q" DstPort 1 } Branch { Points [0, 80] DstBlock "RSSI" DstPort 1 } } } Line { SrcBlock "RSSI" SrcPort 1 DstBlock "Radio 1 RSSI" DstPort 1 } Line { SrcBlock "MGCAGC_AGCDCO_SEL" SrcPort 1 Points [110, 0] Branch { DstBlock "ADC Q" DstPort 2 } Branch { Points [0, -65] DstBlock "ADC I" DstPort 2 } } } } Block { BlockType SubSystem Name "Radio 1 Outputs" SID "228" Ports [1] Position [1180, 666, 1230, 714] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "Radio 1 Outputs" Location [2, 74, 1078, 531] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "32b" SID "229" Position [250, 93, 280, 107] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "16LSB" SID "230" Ports [1, 1] Position [430, 92, 470, 108] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type " "is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardware " "notes: In hardware this block costs nothing." nbits "16" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,442,407" block_type "slice" block_version "8.2" sg_icon_stat "40,16,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 16 16 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 16 16 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[10.22 10.22 1" "2.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[8.22 8.22 10.22 10.22 8.22" " ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatch([17" ".55 24.44 22.44 20.44 18.44 15.55 17.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprintf(''," "'COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'[a" ":b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "16MSB" SID "231" Ports [1, 1] Position [430, 36, 470, 54] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type " "is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardware " "notes: In hardware this block costs nothing." nbits "16" boolean_output off mode "Upper Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,442,407" block_type "slice" block_version "8.2" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22 11.22 1" "3.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22 11.22 9.22" " ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([17" ".55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf(''," "'COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'[a" ":b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Radio 1 DAC I" SID "232" Ports [1, 1] Position [685, 24, 780, 66] LibraryVersion "1.48" LinkData { BlockName "Convert" DialogParameters { sg_icon_stat "45,30,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 30 30 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\npatch([13.1 18.88 22.88 26.88 30.88 22.88 17.1 13.1 ],[19.4" "4 19.44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([17.1 22.88 18.88 13.1 17.1 ],[15.44 15.44 19.4" "4 19.44 15.44 ],[0.931 0.946 0.973 ]);\npatch([13.1 18.88 22.88 17.1 13.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1" " 1 1 ]);\npatch([17.1 30.88 26.88 22.88 18.88 13.1 17.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946" " 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black'" ");port_label('output',1,'cast');\nfprintf('','COMMENT: end icon text');" } BlockName "radio1_dac_I" DialogParameters { sg_icon_stat "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0" ".93 0.65 ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[1" "2.22 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.2" "2 12.22 12.22 10.22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.2" "2 ],[1 1 1 ]);\npatch([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985" " 0.979 0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','o" "n');\nfprintf('','COMMENT: end icon text');" } } SourceBlock "WARP_Blockset/WARP Radio Board ADC//DACs/Radio 1 DAC I" SourceType "" ShowPortLabels "FromPortIcon" SystemSampleTime "-1" FunctionWithSeparateData off RTWMemSecFuncInitTerm "Inherit from model" RTWMemSecFuncExecute "Inherit from model" RTWMemSecDataConstants "Inherit from model" RTWMemSecDataInternal "Inherit from model" RTWMemSecDataParameters "Inherit from model" GeneratePreprocessorConditionals off } Block { BlockType Reference Name "Radio 1 DAC Q" SID "233" Ports [1, 1] Position [685, 79, 780, 121] LibraryVersion "1.48" LinkData { BlockName "Convert" DialogParameters { sg_icon_stat "45,30,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 30 30 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\npatch([13.1 18.88 22.88 26.88 30.88 22.88 17.1 13.1 ],[19.4" "4 19.44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([17.1 22.88 18.88 13.1 17.1 ],[15.44 15.44 19.4" "4 19.44 15.44 ],[0.931 0.946 0.973 ]);\npatch([13.1 18.88 22.88 17.1 13.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1" " 1 1 ]);\npatch([17.1 30.88 26.88 22.88 18.88 13.1 17.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946" " 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black'" ");port_label('output',1,'cast');\nfprintf('','COMMENT: end icon text');" } BlockName "radio1_dac_Q" DialogParameters { sg_icon_stat "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0" ".93 0.65 ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[1" "2.22 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.2" "2 12.22 12.22 10.22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.2" "2 ],[1 1 1 ]);\npatch([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985" " 0.979 0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','o" "n');\nfprintf('','COMMENT: end icon text');" } } SourceBlock "WARP_Blockset/WARP Radio Board ADC//DACs/Radio 1 DAC Q" SourceType "" ShowPortLabels "FromPortIcon" SystemSampleTime "-1" FunctionWithSeparateData off RTWMemSecFuncInitTerm "Inherit from model" RTWMemSecFuncExecute "Inherit from model" RTWMemSecDataConstants "Inherit from model" RTWMemSecDataInternal "Inherit from model" RTWMemSecDataParameters "Inherit from model" GeneratePreprocessorConditionals off } Block { BlockType Reference Name "Register" SID "234" Ports [1, 1] Position [595, 31, 630, 59] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "8.2" sg_icon_stat "35,28,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 28 28 0 ],[0.77 0.82 0.91" " ]);\nplot([0 35 35 0 0 ],[0 0 28 28 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[18.44 18.44 22.44 " "18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[14.44 14.44 18.44 18.44 14.44 ],[0." "931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\npatch([12.1 25." "88 21.88 17.88 13.88 8.1 12.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\ncolor(" "'black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon " "text');" } Block { BlockType Reference Name "Register1" SID "235" Ports [1, 1] Position [595, 86, 630, 114] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "8.2" sg_icon_stat "35,28,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 28 28 0 ],[0.77 0.82 0.91" " ]);\nplot([0 35 35 0 0 ],[0 0 28 28 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[18.44 18.44 22.44 " "18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[14.44 14.44 18.44 18.44 14.44 ],[0." "931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\npatch([12.1 25." "88 21.88 17.88 13.88 8.1 12.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\ncolor(" "'black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon " "text');" } Block { BlockType Reference Name "Reinterpret" SID "236" Ports [1, 1] Position [530, 35, 575, 55] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can changed the signal between s" "igned and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothing.

" "Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsigned wi" "th 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111000 in " "binary)." force_arith_type on arith_type "Signed (2's comp)" force_bin_pt on bin_pt "15" has_advanced_control "0" sggui_pos "20,20,356,309" block_type "reinterpret" block_version "8.2" sg_icon_stat "45,20,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.91" " ]);\nplot([0 45 45 0 0 ],[0 0 20 20 0 ]);\npatch([17.55 20.44 22.44 24.44 26.44 22.44 19.55 17.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([19.55 22.44 20.44 17.55 19.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.931 0.946 0.973 ]);\npatch([17.55 20.44 22.44 19.55 17.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([19.55 26.44 24.44 22.44 20.44 17.55 19.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('reinterpret'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Reinterpret1" SID "237" Ports [1, 1] Position [530, 90, 575, 110] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can changed the signal between s" "igned and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothing.

" "Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsigned wi" "th 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111000 in " "binary)." force_arith_type on arith_type "Signed (2's comp)" force_bin_pt on bin_pt "15" has_advanced_control "0" sggui_pos "20,20,356,309" block_type "reinterpret" block_version "8.2" sg_icon_stat "45,20,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.91" " ]);\nplot([0 45 45 0 0 ],[0 0 20 20 0 ]);\npatch([17.55 20.44 22.44 24.44 26.44 22.44 19.55 17.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([19.55 22.44 20.44 17.55 19.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.931 0.946 0.973 ]);\npatch([17.55 20.44 22.44 19.55 17.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([19.55 26.44 24.44 22.44 20.44 17.55 19.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('reinterpret'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Terminator Name "Terminator1" SID "238" Position [840, 35, 860, 55] ShowName off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Terminator Name "Terminator2" SID "239" Position [840, 90, 860, 110] ShowName off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "Radio 1 DAC Q" SrcPort 1 DstBlock "Terminator2" DstPort 1 } Line { SrcBlock "Radio 1 DAC I" SrcPort 1 DstBlock "Terminator1" DstPort 1 } Line { SrcBlock "Reinterpret1" SrcPort 1 DstBlock "Register1" DstPort 1 } Line { SrcBlock "Reinterpret" SrcPort 1 DstBlock "Register" DstPort 1 } Line { SrcBlock "16LSB" SrcPort 1 DstBlock "Reinterpret1" DstPort 1 } Line { SrcBlock "16MSB" SrcPort 1 DstBlock "Reinterpret" DstPort 1 } Line { SrcBlock "Register" SrcPort 1 DstBlock "Radio 1 DAC I" DstPort 1 } Line { SrcBlock "Register1" SrcPort 1 DstBlock "Radio 1 DAC Q" DstPort 1 } Line { SrcBlock "32b" SrcPort 1 Points [65, 0] Branch { Points [0, -55] DstBlock "16MSB" DstPort 1 } Branch { DstBlock "16LSB" DstPort 1 } } } } Block { BlockType SubSystem Name "Radio 2\nRx Buffers" SID "240" Ports [5] Position [1175, 184, 1240, 286] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "Radio 2\nRx Buffers" Location [2, 74, 1270, 726] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "RSSI" SID "241" Position [450, 313, 480, 327] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "I/Q" SID "242" Position [545, 163, 575, 177] Port "2" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "Addr" SID "243" Position [325, 128, 355, 142] Port "3" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "WE" SID "244" Position [110, 183, 140, 197] Port "4" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "EN" SID "245" Position [110, 213, 140, 227] Port "5" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Convert1" SID "246" Ports [1, 1] Position [185, 212, 210, 228] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "16" bin_pt "14" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,374,375" block_type "convert" block_version "8.2" sg_icon_stat "25,16,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 16 16 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 16 16 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[10.22 10.22 12.2" "2 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[8.22 8.22 10.22 10.22 8.22 ],[0." "931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatch([9.55 16.44 " "14.44 12.44 10.44 7.55 9.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: en" "d icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'cast');\nfprin" "tf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out" SID "247" Ports [1, 1] Position [500, 30, 530, 40] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, double, o" "r fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarded, depen" "ding on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" UseAsDAC off DACChannel "'1'" has_advanced_control "0" sggui_pos "20,20,336,386" block_type "gatewayout" block_version "10.1.2" sg_icon_stat "30,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 10 10 0 ],[0.88 0.88 0.88" " ]);\nplot([0 30 30 0 0 ],[0 0 10 10 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ],[6.11 6.11 " "7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[5.11 5.11 6.11 6.11 5.11 ],[" "0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]);\npatch([13." "775 17.22 16.22 15.22 14.22 12.775 13.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.964 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ')" ";\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" } Block { BlockType Reference Name "Gateway Out1" SID "248" Ports [1, 1] Position [500, 70, 530, 80] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, double, o" "r fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarded, depen" "ding on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" UseAsDAC off DACChannel "'1'" has_advanced_control "0" sggui_pos "20,20,336,386" block_type "gatewayout" block_version "10.1.2" sg_icon_stat "30,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 10 10 0 ],[0.88 0.88 0.88" " ]);\nplot([0 30 30 0 0 ],[0 0 10 10 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ],[6.11 6.11 " "7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[5.11 5.11 6.11 6.11 5.11 ],[" "0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]);\npatch([13." "775 17.22 16.22 15.22 14.22 12.775 13.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.964 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ')" ";\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" } Block { BlockType Reference Name "Logical" SID "249" Ports [2, 1] Position [255, 175, 310, 235] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "9.1.01" sg_icon_stat "55,60,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 60 60 0 ],[0.77 0.82 0.91" " ]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ],[37.77 37.7" "7 44.77 37.77 44.77 44.77 44.77 37.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[30.77 30.77 37.77 37" ".77 30.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[23.77 23.77 30.77 30.77 23.77 ],[1 1" " 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[16.77 16.77 23.77 16.77 23.77 23.77 16.77 ],[0.931 0" ".946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('bl" "ack');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "Radio 2\nRSSI Buffer" SID "250" Ports [3] Position [645, 264, 700, 376] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "Radio 2\nRSSI Buffer" Location [6, 74, 1682, 1006] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Addr_14b" SID "251" Position [325, 348, 355, 362] NamePlacement "alternate" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "RSSI" SID "252" Position [95, 383, 125, 397] Port "2" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "WE" SID "253" Position [720, 478, 750, 492] Port "3" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "11MSB" SID "254" Ports [1, 1] Position [430, 346, 470, 364] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outp" "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

" "

Hardware notes: In hardware this block costs nothing." nbits "11" boolean_output off mode "Upper Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,407" block_type "slice" block_version "8.2" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[1" "1.22 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 " "11.22 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[" "1 1 1 ]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black" "');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "BIT[2]" SID "255" Ports [1, 1] Position [430, 401, 470, 419] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outp" "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

" "

Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "2" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,407" block_type "slice" block_version "8.2" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[1" "1.22 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 " "11.22 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[" "1 1 1 ]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black" "');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Concat" SID "256" Ports [2, 1] Position [685, 381, 725, 459] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary poi" "nt at zero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" block_version "10.1.2" sg_icon_stat "40,78,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 78 78 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 78 78 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[44.55" " 44.55 49.55 44.55 49.55 49.55 49.55 44.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[39.55 39.55 44" ".55 44.55 39.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[34.55 34.55 39.55 39.55 34.55 " "],[1 1 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[29.55 29.55 34.55 29.55 34.55 34.55 29.55 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor(" "'black');port_label('input',1,'hi');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\font" "size{20}\\}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert" SID "257" Ports [1, 1] Position [285, 382, 320, 398] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do" " not." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "16" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,461,375" block_type "convert" block_version "8.2" sg_icon_stat "35,16,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 16 16 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 16 16 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[1" "0.22 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[8.22 8.22 " "10.22 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[6.22 6.22 8.22 8.22 6.22 ],[" "1 1 1 ]);\npatch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black" "');port_label('output',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "258" Ports [1, 1] Position [510, 402, 540, 418] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,251" block_type "inv" block_version "10.1.2" sg_icon_stat "30,16,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 16 16 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 16 16 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[1" "0.22 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[8.22 8.22 " "10.22 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[6.22 6.22 8.22 8.22 6.22 ],[" "1 1 1 ]);\npatch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('bla" "ck');disp('not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register" SID "259" Ports [2, 1] Position [580, 378, 625, 422] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "10.1.2" sg_icon_stat "45,44,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28." "66 28.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 2" "8.66 28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 " "],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0" ".931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor" "('black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('ou" "tput',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Reinterpret1" SID "260" Ports [1, 1] Position [180, 382, 215, 398] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can changed the signal b" "etween signed and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs no" "thing.

Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is force" "d to unsigned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an outp" "ut of 56 (111000 in binary)." force_arith_type on arith_type "Unsigned" force_bin_pt on bin_pt "0" has_advanced_control "0" sggui_pos "436,54,356,312" block_type "reinterpret" block_version "9.1.01" sg_icon_stat "35,16,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 16 16 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 16 16 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[1" "0.22 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[8.22 8.22 " "10.22 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[6.22 6.22 8.22 8.22 6.22 ],[" "1 1 1 ]);\npatch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('bla" "ck');disp('reinterpret');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Shared Memory" SID "261" Ports [3, 1] Position [800, 323, 880, 517] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Shared Memory" SourceType "Xilinx Shared Memory Random Access Memory Block" shared_memory_name "'RSSIBuff_Radio2'" depth "2^11" ownership "Locally Owned and Initialized" initVector "0" en off mutex "Unprotected" mode "Read and Write" write_mode "Read After Write" time_out "0" latency "1" explicit_data_type on gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" xl_use_area off xl_area "[0,0,0,0,0,0,0]" implementation "Block RAM" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,384,381" block_type "shmem" block_version "10.1.2" sg_icon_stat "80,194,3,1,white,blue,0,bf435243,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 80 80 0 0 ],[0 0 194 194 0 ],[0.77" " 0.82 0.91 ]);\nplot([0 80 80 0 0 ],[0 0 194 194 0 ]);\npatch([15.525 31.42 42.42 53.42 64.42 42.42 26.525 15.5" "25 ],[109.21 109.21 120.21 109.21 120.21 120.21 120.21 109.21 ],[1 1 1 ]);\npatch([26.525 42.42 31.42 15.525 26" ".525 ],[98.21 98.21 109.21 109.21 98.21 ],[0.931 0.946 0.973 ]);\npatch([15.525 31.42 42.42 26.525 15.525 ],[87" ".21 87.21 98.21 98.21 87.21 ],[1 1 1 ]);\npatch([26.525 64.42 53.42 42.42 31.42 15.525 26.525 ],[76.21 76.21 87" ".21 76.21 87.21 87.21 76.21 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','CO" "MMENT: begin icon text');\ncolor('black');port_label('input',1,'addr');\ncolor('black');port_label('input',2,'d" "in');\ncolor('black');port_label('input',3,'we');\ncolor('black');port_label('output',1,'dout');\nfprintf('','C" "OMMENT: end icon text');" } Block { BlockType Terminator Name "Terminator2" SID "262" Position [945, 410, 965, 430] ShowName off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "RSSI" SrcPort 1 DstBlock "Reinterpret1" DstPort 1 } Line { SrcBlock "Convert" SrcPort 1 Points [35, 0] Branch { DstBlock "Register" DstPort 1 } Branch { Points [0, 50] DstBlock "Concat" DstPort 2 } } Line { SrcBlock "Addr_14b" SrcPort 1 Points [40, 0] Branch { DstBlock "11MSB" DstPort 1 } Branch { Points [0, 55] DstBlock "BIT[2]" DstPort 1 } } Line { SrcBlock "WE" SrcPort 1 DstBlock "Shared Memory" DstPort 3 } Line { SrcBlock "Reinterpret1" SrcPort 1 DstBlock "Convert" DstPort 1 } Line { SrcBlock "Concat" SrcPort 1 DstBlock "Shared Memory" DstPort 2 } Line { SrcBlock "BIT[2]" SrcPort 1 DstBlock "Inverter" DstPort 1 } Line { SrcBlock "11MSB" SrcPort 1 DstBlock "Shared Memory" DstPort 1 } Line { SrcBlock "Shared Memory" SrcPort 1 DstBlock "Terminator2" DstPort 1 } Line { SrcBlock "Register" SrcPort 1 DstBlock "Concat" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Register" DstPort 2 } } } Block { BlockType SubSystem Name "Radio 2 I/Q\nBuffer" SID "263" Ports [3] Position [645, 118, 700, 222] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "Radio 2 I/Q\nBuffer" Location [2, 74, 1270, 726] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Addr_14b" SID "264" Position [205, 68, 235, 82] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "I/Q_32b" SID "265" Position [205, 98, 235, 112] Port "2" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "WE" SID "266" Position [205, 128, 235, 142] Port "3" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Shared Memory" SID "267" Ports [3, 1] Position [315, 60, 395, 150] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Shared Memory" SourceType "Xilinx Shared Memory Random Access Memory Block" shared_memory_name "'RxBuff_Radio2'" depth "2^14" ownership "Locally Owned and Initialized" initVector "0" en off mutex "Unprotected" mode "Read and Write" write_mode "Read After Write" time_out "0" latency "1" explicit_data_type on gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" xl_use_area off xl_area "[0,0,0,0,0,0,0]" implementation "Block RAM" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,384,381" block_type "shmem" block_version "10.1.2" sg_icon_stat "80,90,3,1,white,blue,0,bf435243,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 80 80 0 0 ],[0 0 90 90 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 80 80 0 0 ],[0 0 90 90 0 ]);\npatch([15.525 31.42 42.42 53.42 64.42 42.42 26.525 15.525 ]" ",[57.21 57.21 68.21 57.21 68.21 68.21 68.21 57.21 ],[1 1 1 ]);\npatch([26.525 42.42 31.42 15.525 26.525 ],[46.2" "1 46.21 57.21 57.21 46.21 ],[0.931 0.946 0.973 ]);\npatch([15.525 31.42 42.42 26.525 15.525 ],[35.21 35.21 46.2" "1 46.21 35.21 ],[1 1 1 ]);\npatch([26.525 64.42 53.42 42.42 31.42 15.525 26.525 ],[24.21 24.21 35.21 24.21 35.2" "1 35.21 24.21 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin i" "con text');\ncolor('black');port_label('input',1,'addr');\ncolor('black');port_label('input',2,'din');\ncolor('" "black');port_label('input',3,'we');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end ic" "on text');" } Block { BlockType Terminator Name "Terminator" SID "268" Position [445, 95, 465, 115] ShowName off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "Addr_14b" SrcPort 1 DstBlock "Shared Memory" DstPort 1 } Line { SrcBlock "I/Q_32b" SrcPort 1 DstBlock "Shared Memory" DstPort 2 } Line { SrcBlock "WE" SrcPort 1 DstBlock "Shared Memory" DstPort 3 } Line { SrcBlock "Shared Memory" SrcPort 1 DstBlock "Terminator" DstPort 1 } } } Block { BlockType Scope Name "Scope" SID "269" Ports [2] Position [585, 14, 625, 96] Floating off Location [5, 49, 1285, 757] Open off NumInputPorts "2" ZoomMode "yonly" List { ListType AxesTitles axes1 "%" axes2 "%" } YMin "-5~-5" YMax "5~5" SaveName "ScopeData2" DataFormat "StructureWithTime" MaxDataPoints "40000" SampleTime "0" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "Logical" SrcPort 1 Points [45, 0] Branch { Points [105, 0] Branch { Points [0, -130] DstBlock "Gateway Out1" DstPort 1 } Branch { Labels [0, 0] DstBlock "Radio 2 I/Q\nBuffer" DstPort 3 } } Branch { Points [0, 150] DstBlock "Radio 2\nRSSI Buffer" DstPort 3 } } Line { SrcBlock "Addr" SrcPort 1 Points [75, 0] Branch { Points [0, -100] DstBlock "Gateway Out" DstPort 1 } Branch { Labels [0, 0] DstBlock "Radio 2 I/Q\nBuffer" DstPort 1 } Branch { Points [0, 150] DstBlock "Radio 2\nRSSI Buffer" DstPort 1 } } Line { SrcBlock "WE" SrcPort 1 DstBlock "Logical" DstPort 1 } Line { SrcBlock "EN" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "Logical" DstPort 2 } Line { SrcBlock "I/Q" SrcPort 1 DstBlock "Radio 2 I/Q\nBuffer" DstPort 2 } Line { SrcBlock "Gateway Out" SrcPort 1 DstBlock "Scope" DstPort 1 } Line { SrcBlock "Gateway Out1" SrcPort 1 DstBlock "Scope" DstPort 2 } Line { SrcBlock "RSSI" SrcPort 1 DstBlock "Radio 2\nRSSI Buffer" DstPort 2 } } } Block { BlockType SubSystem Name "Radio 2\nTx Buffer" SID "270" Ports [3, 1] Position [1015, 756, 1095, 814] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "Radio 2\nTx Buffer" Location [2, 74, 827, 638] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "RdAddr_14b" SID "271" Position [355, 288, 385, 302] NamePlacement "alternate" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "Rst" SID "272" Position [30, 173, 60, 187] Port "2" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "En" SID "273" Position [30, 203, 60, 217] Port "3" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Constant" SID "274" Ports [0, 1] Position [630, 350, 655, 370] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,400,346" block_type "constant" block_version "10.1.2" sg_icon_stat "25,20,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 20 20 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[12.22 12.22 14.2" "2 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[10.22 10.22 12.22 12.22 10.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatch([9.55 1" "6.44 14.44 12.44 10.44 7.55 9.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'0');\nfprin" "tf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant1" SID "275" Ports [0, 1] Position [355, 345, 380, 365] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "32" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,400,346" block_type "constant" block_version "10.1.2" sg_icon_stat "25,20,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 20 20 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[12.22 12.22 14.2" "2 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[10.22 10.22 12.22 12.22 10.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatch([9.55 1" "6.44 14.44 12.44 10.44 7.55 9.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'0');\nfprin" "tf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant2" SID "276" Ports [0, 1] Position [355, 315, 380, 335] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,400,346" block_type "constant" block_version "10.1.2" sg_icon_stat "25,20,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 20 20 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[12.22 12.22 14.2" "2 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[10.22 10.22 12.22 12.22 10.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatch([9.55 1" "6.44 14.44 12.44 10.44 7.55 9.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'0');\nfprin" "tf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert" SID "277" Ports [1, 1] Position [350, 188, 375, 202] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "16" bin_pt "14" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,374,375" block_type "convert" block_version "8.2" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.22 11.22 " "9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 ],[0.931 0." "946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.55 16.44 14.44 " "12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon" " graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'cast');\nfprintf(''," "'COMMENT: end icon text');" } Block { BlockType Reference Name "Convert1" SID "278" Ports [1, 1] Position [100, 203, 120, 217] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "16" bin_pt "14" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,374,375" block_type "convert" block_version "8.2" sg_icon_stat "20,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 14 14 0 ],[0.77 0.82 0.91" " ]);\nplot([0 20 20 0 0 ],[0 0 14 14 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[9.22 9.22 11.22 9" ".22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[0.931 0.94" "6 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([7.55 14.44 12.44 10." "44 8.44 5.55 7.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon gra" "phics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'cast');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "279" Ports [1, 1] Position [150, 201, 180, 219] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "9.1.01" sg_icon_stat "30,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 18 18 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[11.22 11.22 1" "3.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[9.22 9.22 11.22 11.22 9.22" " ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([12" ".55 19.44 17.44 15.44 13.44 10.55 12.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf(''," "'COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nfprintf('" "','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical" SID "280" Ports [2, 1] Position [215, 165, 270, 225] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "9.1.01" sg_icon_stat "55,60,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 60 60 0 ],[0.77 0.82 0.91" " ]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ],[37.77 37.7" "7 44.77 37.77 44.77 44.77 44.77 37.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[30.77 30.77 37.77 37" ".77 30.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[23.77 23.77 30.77 30.77 23.77 ],[1 1" " 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[16.77 16.77 23.77 16.77 23.77 23.77 16.77 ],[0.931 0" ".946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('bl" "ack');disp('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux" SID "281" Ports [3, 1] Position [750, 273, 795, 377] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,303" block_type "mux" block_version "10.1.2" sg_icon_stat "45,104,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 14.8571 89.1429 104 0 ],[0." "77 0.82 0.91 ]);\nplot([0 45 45 0 0 ],[0 14.8571 89.1429 104 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65" " 8.65 ],[58.66 58.66 64.66 58.66 64.66 64.66 64.66 58.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[52.66" " 52.66 58.66 58.66 52.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[46.66 46.66 52.66 52.66 46" ".66 ],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[40.66 40.66 46.66 40.66 46.66 46.66 40.66 ],[0" ".931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('input',3" ",'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Shared Memory" SID "282" Ports [3, 1] Position [445, 280, 525, 370] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Shared Memory" SourceType "Xilinx Shared Memory Random Access Memory Block" shared_memory_name "'TxBuff_Radio2'" depth "2^14" ownership "Locally Owned and Initialized" initVector "0" en off mutex "Unprotected" mode "Read and Write" write_mode "Read After Write" time_out "0" latency "1" explicit_data_type on gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" xl_use_area off xl_area "[0,0,0,0,0,0,0]" implementation "Block RAM" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,384,381" block_type "shmem" block_version "10.1.2" sg_icon_stat "80,90,3,1,white,blue,0,bf435243,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 80 80 0 0 ],[0 0 90 90 0 ],[0.77 0.82 0.91" " ]);\nplot([0 80 80 0 0 ],[0 0 90 90 0 ]);\npatch([15.525 31.42 42.42 53.42 64.42 42.42 26.525 15.525 ],[57.21 57.2" "1 68.21 57.21 68.21 68.21 68.21 57.21 ],[1 1 1 ]);\npatch([26.525 42.42 31.42 15.525 26.525 ],[46.21 46.21 57.21 57" ".21 46.21 ],[0.931 0.946 0.973 ]);\npatch([15.525 31.42 42.42 26.525 15.525 ],[35.21 35.21 46.21 46.21 35.21 ],[1 1" " 1 ]);\npatch([26.525 64.42 53.42 42.42 31.42 15.525 26.525 ],[24.21 24.21 35.21 24.21 35.21 35.21 24.21 ],[0.931 0" ".946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');" "port_label('input',1,'addr');\ncolor('black');port_label('input',2,'din');\ncolor('black');port_label('input',3,'we" "');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "IQ_32b" SID "283" Position [885, 318, 915, 332] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "Logical" SrcPort 1 DstBlock "Convert" DstPort 1 } Line { SrcBlock "Convert" SrcPort 1 Points [160, 0; 0, 95] DstBlock "Mux" DstPort 1 } Line { SrcBlock "Rst" SrcPort 1 DstBlock "Logical" DstPort 1 } Line { SrcBlock "En" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "Inverter" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical" DstPort 2 } Line { SrcBlock "RdAddr_14b" SrcPort 1 DstBlock "Shared Memory" DstPort 1 } Line { SrcBlock "Constant" SrcPort 1 DstBlock "Mux" DstPort 3 } Line { SrcBlock "Shared Memory" SrcPort 1 DstBlock "Mux" DstPort 2 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Shared Memory" DstPort 3 } Line { SrcBlock "Constant2" SrcPort 1 DstBlock "Shared Memory" DstPort 2 } Line { SrcBlock "Mux" SrcPort 1 DstBlock "IQ_32b" DstPort 1 } } } Block { BlockType SubSystem Name "Radio 2 Inputs" SID "284" Ports [2, 2] Position [905, 178, 1085, 227] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "Radio 2 Inputs" Location [2, 74, 1014, 726] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "DebugRxBuffers" SID "285" Position [175, 243, 205, 257] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "MGCAGC_AGCDCO_SEL" SID "286" Position [175, 333, 205, 347] Port "2" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType SubSystem Name "ADC I" SID "287" Ports [2, 2] Position [440, 237, 595, 288] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "ADC I" Location [2, 74, 1014, 726] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Debug" SID "288" Position [695, 53, 725, 67] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "MGCAGC_AGCDCO_SEL" SID "289" Position [210, 243, 240, 257] Port "2" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Constant Name "Constant1" SID "290" Position [25, 320, 55, 350] ShowName off Value "0" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Counter" SID "291" Ports [0, 1] Position [530, 340, 590, 400] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited co" "unter is implemented by combining a counter with a comparator." cnt_type "Free Running" cnt_to "Inf" operation "Down" start_count "2^14-1" cnt_by_val "1" arith_type "Unsigned" n_bits "14" bin_pt "0" load_pin off rst off en off explicit_period "on" period "1" dbl_ovrd off use_behavioral_HDL off implementation "Fabric" xl_use_area off xl_area "[0,0,0,0,0,0,0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,619" block_type "counter" block_version "10.1.3" sg_icon_stat "60,60,0,1,white,blue,0,cf0fdd8c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 60 60 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 60 60 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[38.8" "8 38.88 46.88 38.88 46.88 46.88 46.88 38.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[30.88 30.88 38.8" "8 38.88 30.88 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[22.88 22.88 30.88 30.88 22.88 ],[1" " 1 1 ]);\npatch([20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[14.88 14.88 22.88 14.88 22.88 22.88 14.88 ],[0.931 0" ".946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('bl" "ack');disp('{\\fontsize{14}\\bf--}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "FromAGC_Radio2_I" SID "292" Ports [1, 1] Position [170, 425, 235, 445] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, double and fixed point to Xilinx" " fixed point type.

Hardware notes: In hardware these blocks become top level input ports." gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "14" bin_pt "13" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off UseAsADC off ADCChannel "'1'" hdl_port "on" has_advanced_control "0" sggui_pos "20,20,348,406" block_type "gatewayin" block_version "10.1.3" sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0" ".93 0.65 ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[1" "2.22 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.2" "2 12.22 12.22 10.22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.2" "2 ],[1 1 1 ]);\npatch([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985" " 0.979 0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' " "');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux" SID "293" Ports [3, 1] Position [830, 88, 875, 192] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "1" bin_pt "0" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,303" block_type "mux" block_version "10.1.3" sg_icon_stat "45,104,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 14.8571 89.1429 104" " 0 ],[0.77 0.82 0.91 ]);\nplot([0 45 45 0 0 ],[0 14.8571 89.1429 104 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32" " 23.32 14.65 8.65 ],[58.66 58.66 64.66 58.66 64.66 64.66 64.66 58.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.6" "5 14.65 ],[52.66 52.66 58.66 58.66 52.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[46.66 " "46.66 52.66 52.66 46.66 ],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[40.66 40.66 46.66 40.6" "6 46.66 46.66 40.66 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: b" "egin icon text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncol" "or('black');port_label('input',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: " "end icon text');" } Block { BlockType Reference Name "Mux1" SID "294" Ports [3, 1] Position [830, 283, 875, 387] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "1" bin_pt "0" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,303" block_type "mux" block_version "10.1.3" sg_icon_stat "45,104,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 14.8571 89.1429 104" " 0 ],[0.77 0.82 0.91 ]);\nplot([0 45 45 0 0 ],[0 14.8571 89.1429 104 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32" " 23.32 14.65 8.65 ],[58.66 58.66 64.66 58.66 64.66 64.66 64.66 58.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.6" "5 14.65 ],[52.66 52.66 58.66 58.66 52.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[46.66 " "46.66 52.66 52.66 46.66 ],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[40.66 40.66 46.66 40.6" "6 46.66 46.66 40.66 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: b" "egin icon text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncol" "or('black');port_label('input',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: " "end icon text');" } Block { BlockType Reference Name "Mux2" SID "295" Ports [3, 1] Position [355, 283, 400, 387] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "1" bin_pt "0" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,303" block_type "mux" block_version "10.1.3" sg_icon_stat "45,104,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 14.8571 89.1429 104" " 0 ],[0.77 0.82 0.91 ]);\nplot([0 45 45 0 0 ],[0 14.8571 89.1429 104 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32" " 23.32 14.65 8.65 ],[58.66 58.66 64.66 58.66 64.66 64.66 64.66 58.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.6" "5 14.65 ],[52.66 52.66 58.66 58.66 52.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[46.66 " "46.66 52.66 52.66 46.66 ],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[40.66 40.66 46.66 40.6" "6 46.66 46.66 40.66 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: b" "egin icon text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncol" "or('black');port_label('input',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: " "end icon text');" } Block { BlockType Reference Name "Radio 2 ADC I" SID "296" Ports [1, 1] Position [150, 314, 245, 356] LibraryVersion "1.48" LinkData { BlockName "radio2_adc_I" DialogParameters { sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.6" "5 ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[12.22 12.22" " 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.22 12.22 12.22" " 10.22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\n" "patch([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('inpu" "t',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT:" " end icon text');\n" } } SourceBlock "WARP_Blockset/WARP Radio Board ADC//DACs/Radio 2 ADC I" SourceType "" ShowPortLabels "FromPortIcon" SystemSampleTime "-1" FunctionWithSeparateData off RTWMemSecFuncInitTerm "Inherit from model" RTWMemSecFuncExecute "Inherit from model" RTWMemSecDataConstants "Inherit from model" RTWMemSecDataInternal "Inherit from model" RTWMemSecDataParameters "Inherit from model" GeneratePreprocessorConditionals off samp_period "1" } Block { BlockType Reference Name "Register" SID "297" Ports [1, 1] Position [460, 321, 495, 349] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "8.2" sg_icon_stat "35,28,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 28 28 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 28 28 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[18.44 " "18.44 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[14.44 14.44 18.44 1" "8.44 14.44 ],[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 " "]);\npatch([12.1 25.88 21.88 17.88 13.88 8.1 12.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Reinterpret" SID "298" Ports [1, 1] Position [675, 354, 725, 386] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can changed the signal b" "etween signed and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs no" "thing.

Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is force" "d to unsigned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an outp" "ut of 56 (111000 in binary)." force_arith_type on arith_type "Signed (2's comp)" force_bin_pt on bin_pt "13" has_advanced_control "0" sggui_pos "20,20,336,312" block_type "reinterpret" block_version "10.1.3" sg_icon_stat "50,32,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 32 32 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 32 32 0 ]);\npatch([16.1 21.88 25.88 29.88 33.88 25.88 20.1 16.1 ],[20.4" "4 20.44 24.44 20.44 24.44 24.44 24.44 20.44 ],[1 1 1 ]);\npatch([20.1 25.88 21.88 16.1 20.1 ],[16.44 16.44 20.4" "4 20.44 16.44 ],[0.931 0.946 0.973 ]);\npatch([16.1 21.88 25.88 20.1 16.1 ],[12.44 12.44 16.44 16.44 12.44 ],[1" " 1 1 ]);\npatch([20.1 33.88 29.88 25.88 21.88 16.1 20.1 ],[8.44 8.44 12.44 8.44 12.44 12.44 8.44 ],[0.931 0.946" " 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('blac" "k');disp('reinterpret');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Slice" SID "299" Ports [1, 1] Position [680, 160, 740, 190] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outp" "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

" "

Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,376" block_type "slice" block_version "10.1.3" sg_icon_stat "60,30,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 30 30 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\npatch([21.1 26.88 30.88 34.88 38.88 30.88 25.1 21.1 ],[19.4" "4 19.44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([25.1 30.88 26.88 21.1 25.1 ],[15.44 15.44 19.4" "4 19.44 15.44 ],[0.931 0.946 0.973 ]);\npatch([21.1 26.88 30.88 25.1 21.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1" " 1 1 ]);\npatch([25.1 38.88 34.88 30.88 26.88 21.1 25.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946" " 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black'" ");port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "radio2_ADC_I_OTR" SID "300" Ports [1, 1] Position [295, 134, 350, 146] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, double and fixed point to Xilinx" " fixed point type.

Hardware notes: In hardware these blocks become top level input ports." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off UseAsADC off ADCChannel "'1'" hdl_port "on" has_advanced_control "0" sggui_pos "20,20,356,432" block_type "gatewayin" block_version "VER_STRING_GOES_HERE" sg_icon_stat "55,12,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 12 12 0 ],[0.95 0" ".93 0.65 ]);\nplot([0 55 55 0 0 ],[0 0 12 12 0 ]);\npatch([24.775 26.22 27.22 28.22 29.22 27.22 25.775 24.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([25.775 27.22 26.22 24.775 25.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.985 0.979 0.895 ]);\npatch([24.775 26.22 27.22 25.775 24.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([25.775 29.22 28.22 27.22 26.22 24.775 25.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.985 0." "979 0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "OTR I" SID "301" Position [935, 133, 965, 147] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Outport Name "ADC I" SID "302" Position [935, 328, 965, 342] Port "2" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "Constant1" SrcPort 1 Points [20, 0] Branch { Points [0, -195] DstBlock "radio2_ADC_I_OTR" DstPort 1 } Branch { DstBlock "Radio 2 ADC I" DstPort 1 } Branch { Points [0, 100] DstBlock "FromAGC_Radio2_I" DstPort 1 } } Line { SrcBlock "Mux" SrcPort 1 DstBlock "OTR I" DstPort 1 } Line { SrcBlock "Debug" SrcPort 1 Points [40, 0; 0, 45] Branch { DstBlock "Mux" DstPort 1 } Branch { Points [0, 195] DstBlock "Mux1" DstPort 1 } } Line { SrcBlock "radio2_ADC_I_OTR" SrcPort 1 DstBlock "Mux" DstPort 2 } Line { SrcBlock "Slice" SrcPort 1 DstBlock "Mux" DstPort 3 } Line { SrcBlock "Mux1" SrcPort 1 DstBlock "ADC I" DstPort 1 } Line { SrcBlock "Register" SrcPort 1 DstBlock "Mux1" DstPort 2 } Line { SrcBlock "Reinterpret" SrcPort 1 DstBlock "Mux1" DstPort 3 } Line { SrcBlock "Counter" SrcPort 1 Points [25, 0] Branch { DstBlock "Reinterpret" DstPort 1 } Branch { Points [0, -195] DstBlock "Slice" DstPort 1 } } Line { SrcBlock "MGCAGC_AGCDCO_SEL" SrcPort 1 Points [70, 0; 0, 50] DstBlock "Mux2" DstPort 1 } Line { SrcBlock "FromAGC_Radio2_I" SrcPort 1 Points [75, 0; 0, -65] DstBlock "Mux2" DstPort 3 } Line { SrcBlock "Mux2" SrcPort 1 DstBlock "Register" DstPort 1 } Line { SrcBlock "Radio 2 ADC I" SrcPort 1 DstBlock "Mux2" DstPort 2 } } } Block { BlockType SubSystem Name "ADC Q" SID "303" Ports [2, 2] Position [440, 304, 595, 351] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "ADC Q" Location [66, 91, 1078, 743] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Debug" SID "304" Position [670, 43, 700, 57] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "MGCAGC_AGCDCO_SEL" SID "305" Position [135, 233, 165, 247] Port "2" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Constant Name "Constant1" SID "306" Position [15, 310, 45, 340] ShowName off Value "0" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Counter" SID "307" Ports [0, 1] Position [500, 330, 560, 390] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited co" "unter is implemented by combining a counter with a comparator." cnt_type "Free Running" cnt_to "Inf" operation "Up" start_count "0" cnt_by_val "1" arith_type "Unsigned" n_bits "14" bin_pt "0" load_pin off rst off en off explicit_period "on" period "1" dbl_ovrd off use_behavioral_HDL off implementation "Fabric" xl_use_area off xl_area "[0,0,0,0,0,0,0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,619" block_type "counter" block_version "10.1.3" sg_icon_stat "60,60,0,1,white,blue,0,7ac47ef5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 60 60 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 60 60 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[38.8" "8 38.88 46.88 38.88 46.88 46.88 46.88 38.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[30.88 30.88 38.8" "8 38.88 30.88 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[22.88 22.88 30.88 30.88 22.88 ],[1" " 1 1 ]);\npatch([20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[14.88 14.88 22.88 14.88 22.88 22.88 14.88 ],[0.931 0" ".946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('bl" "ack');disp('{\\fontsize{14}\\bf++}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "FromAGC_Radio2_Q" SID "308" Ports [1, 1] Position [120, 415, 185, 435] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, double and fixed point to Xilinx" " fixed point type.

Hardware notes: In hardware these blocks become top level input ports." gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "14" bin_pt "13" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off UseAsADC off ADCChannel "'1'" hdl_port "on" has_advanced_control "0" sggui_pos "20,20,348,406" block_type "gatewayin" block_version "10.1.3" sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0" ".93 0.65 ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[1" "2.22 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.2" "2 12.22 12.22 10.22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.2" "2 ],[1 1 1 ]);\npatch([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985" " 0.979 0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' " "');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux" SID "309" Ports [3, 1] Position [805, 78, 850, 182] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "1" bin_pt "0" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,303" block_type "mux" block_version "10.1.3" sg_icon_stat "45,104,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 14.8571 89.1429 104" " 0 ],[0.77 0.82 0.91 ]);\nplot([0 45 45 0 0 ],[0 14.8571 89.1429 104 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32" " 23.32 14.65 8.65 ],[58.66 58.66 64.66 58.66 64.66 64.66 64.66 58.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.6" "5 14.65 ],[52.66 52.66 58.66 58.66 52.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[46.66 " "46.66 52.66 52.66 46.66 ],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[40.66 40.66 46.66 40.6" "6 46.66 46.66 40.66 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: b" "egin icon text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncol" "or('black');port_label('input',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: " "end icon text');" } Block { BlockType Reference Name "Mux1" SID "310" Ports [3, 1] Position [805, 273, 850, 377] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "1" bin_pt "0" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,303" block_type "mux" block_version "10.1.3" sg_icon_stat "45,104,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 14.8571 89.1429 104" " 0 ],[0.77 0.82 0.91 ]);\nplot([0 45 45 0 0 ],[0 14.8571 89.1429 104 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32" " 23.32 14.65 8.65 ],[58.66 58.66 64.66 58.66 64.66 64.66 64.66 58.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.6" "5 14.65 ],[52.66 52.66 58.66 58.66 52.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[46.66 " "46.66 52.66 52.66 46.66 ],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[40.66 40.66 46.66 40.6" "6 46.66 46.66 40.66 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: b" "egin icon text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncol" "or('black');port_label('input',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: " "end icon text');" } Block { BlockType Reference Name "Mux2" SID "311" Ports [3, 1] Position [280, 273, 325, 377] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "1" bin_pt "0" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,303" block_type "mux" block_version "10.1.3" sg_icon_stat "45,104,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 14.8571 89.1429 104" " 0 ],[0.77 0.82 0.91 ]);\nplot([0 45 45 0 0 ],[0 14.8571 89.1429 104 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32" " 23.32 14.65 8.65 ],[58.66 58.66 64.66 58.66 64.66 64.66 64.66 58.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.6" "5 14.65 ],[52.66 52.66 58.66 58.66 52.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[46.66 " "46.66 52.66 52.66 46.66 ],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[40.66 40.66 46.66 40.6" "6 46.66 46.66 40.66 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: b" "egin icon text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncol" "or('black');port_label('input',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: " "end icon text');" } Block { BlockType Reference Name "Radio 2 ADC Q" SID "312" Ports [1, 1] Position [100, 304, 195, 346] LibraryVersion "1.48" LinkData { BlockName "radio2_adc_Q" DialogParameters { sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.6" "5 ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[12.22 12.22" " 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.22 12.22 12.22" " 10.22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\n" "patch([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('inpu" "t',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT:" " end icon text');\n" } } SourceBlock "WARP_Blockset/WARP Radio Board ADC//DACs/Radio 2 ADC Q" SourceType "" ShowPortLabels "FromPortIcon" SystemSampleTime "-1" FunctionWithSeparateData off RTWMemSecFuncInitTerm "Inherit from model" RTWMemSecFuncExecute "Inherit from model" RTWMemSecDataConstants "Inherit from model" RTWMemSecDataInternal "Inherit from model" RTWMemSecDataParameters "Inherit from model" GeneratePreprocessorConditionals off samp_period "1" } Block { BlockType Reference Name "Register" SID "313" Ports [1, 1] Position [430, 311, 465, 339] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "8.2" sg_icon_stat "35,28,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 28 28 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 28 28 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[18.44 " "18.44 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[14.44 14.44 18.44 1" "8.44 14.44 ],[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 " "]);\npatch([12.1 25.88 21.88 17.88 13.88 8.1 12.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Reinterpret" SID "314" Ports [1, 1] Position [650, 344, 700, 376] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can changed the signal b" "etween signed and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs no" "thing.

Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is force" "d to unsigned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an outp" "ut of 56 (111000 in binary)." force_arith_type on arith_type "Signed (2's comp)" force_bin_pt on bin_pt "13" has_advanced_control "0" sggui_pos "20,20,336,312" block_type "reinterpret" block_version "10.1.3" sg_icon_stat "50,32,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 32 32 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 32 32 0 ]);\npatch([16.1 21.88 25.88 29.88 33.88 25.88 20.1 16.1 ],[20.4" "4 20.44 24.44 20.44 24.44 24.44 24.44 20.44 ],[1 1 1 ]);\npatch([20.1 25.88 21.88 16.1 20.1 ],[16.44 16.44 20.4" "4 20.44 16.44 ],[0.931 0.946 0.973 ]);\npatch([16.1 21.88 25.88 20.1 16.1 ],[12.44 12.44 16.44 16.44 12.44 ],[1" " 1 1 ]);\npatch([20.1 33.88 29.88 25.88 21.88 16.1 20.1 ],[8.44 8.44 12.44 8.44 12.44 12.44 8.44 ],[0.931 0.946" " 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('blac" "k');disp('reinterpret');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Slice" SID "315" Ports [1, 1] Position [655, 150, 715, 180] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outp" "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

" "

Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,376" block_type "slice" block_version "10.1.3" sg_icon_stat "60,30,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 30 30 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\npatch([21.1 26.88 30.88 34.88 38.88 30.88 25.1 21.1 ],[19.4" "4 19.44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([25.1 30.88 26.88 21.1 25.1 ],[15.44 15.44 19.4" "4 19.44 15.44 ],[0.931 0.946 0.973 ]);\npatch([21.1 26.88 30.88 25.1 21.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1" " 1 1 ]);\npatch([25.1 38.88 34.88 30.88 26.88 21.1 25.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946" " 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black'" ");port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "radio2_ADC_Q_OTR" SID "316" Ports [1, 1] Position [240, 124, 295, 136] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, double and fixed point to Xilinx" " fixed point type.

Hardware notes: In hardware these blocks become top level input ports." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off UseAsADC off ADCChannel "'1'" hdl_port "on" has_advanced_control "0" sggui_pos "20,20,356,432" block_type "gatewayin" block_version "VER_STRING_GOES_HERE" sg_icon_stat "55,12,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 12 12 0 ],[0.95 0" ".93 0.65 ]);\nplot([0 55 55 0 0 ],[0 0 12 12 0 ]);\npatch([24.775 26.22 27.22 28.22 29.22 27.22 25.775 24.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([25.775 27.22 26.22 24.775 25.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.985 0.979 0.895 ]);\npatch([24.775 26.22 27.22 25.775 24.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([25.775 29.22 28.22 27.22 26.22 24.775 25.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.985 0." "979 0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "OTR Q" SID "317" Position [945, 123, 975, 137] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Outport Name "ADC Q" SID "318" Position [945, 318, 975, 332] Port "2" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "Constant1" SrcPort 1 Points [10, 0] Branch { Points [0, 0] Branch { Points [0, 0; 0, -195] DstBlock "radio2_ADC_Q_OTR" DstPort 1 } Branch { DstBlock "Radio 2 ADC Q" DstPort 1 } } Branch { Points [0, 100] DstBlock "FromAGC_Radio2_Q" DstPort 1 } } Line { SrcBlock "Mux" SrcPort 1 DstBlock "OTR Q" DstPort 1 } Line { SrcBlock "Debug" SrcPort 1 Points [40, 0; 0, 45] Branch { DstBlock "Mux" DstPort 1 } Branch { Points [0, 195] DstBlock "Mux1" DstPort 1 } } Line { SrcBlock "radio2_ADC_Q_OTR" SrcPort 1 DstBlock "Mux" DstPort 2 } Line { SrcBlock "Slice" SrcPort 1 DstBlock "Mux" DstPort 3 } Line { SrcBlock "Mux1" SrcPort 1 DstBlock "ADC Q" DstPort 1 } Line { SrcBlock "Register" SrcPort 1 DstBlock "Mux1" DstPort 2 } Line { SrcBlock "Reinterpret" SrcPort 1 DstBlock "Mux1" DstPort 3 } Line { SrcBlock "Counter" SrcPort 1 Points [30, 0] Branch { DstBlock "Reinterpret" DstPort 1 } Branch { Points [0, -195] DstBlock "Slice" DstPort 1 } } Line { SrcBlock "MGCAGC_AGCDCO_SEL" SrcPort 1 Points [70, 0; 0, 50] DstBlock "Mux2" DstPort 1 } Line { SrcBlock "FromAGC_Radio2_Q" SrcPort 1 Points [50, 0; 0, -65] DstBlock "Mux2" DstPort 3 } Line { SrcBlock "Radio 2 ADC Q" SrcPort 1 DstBlock "Mux2" DstPort 2 } Line { SrcBlock "Mux2" SrcPort 1 DstBlock "Register" DstPort 1 } } } Block { BlockType SubSystem Name "Concatenates_1" SID "319" Ports [4, 1] Position [695, 218, 740, 372] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "Concatenates_1" Location [2, 74, 1270, 726] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "OTR_I" SID "320" Position [395, 43, 425, 57] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "ADC_I" SID "321" Position [330, 93, 360, 107] Port "2" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "OTR_Q" SID "322" Position [390, 163, 420, 177] Port "3" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "ADC_Q" SID "323" Position [330, 213, 360, 227] Port "4" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Concat1" SID "324" Ports [2, 1] Position [490, 191, 520, 229] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary poi" "nt at zero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" block_version "8.2" sg_icon_stat "30,38,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 38 38 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 38 38 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[23.44 " "23.44 27.44 23.44 27.44 27.44 27.44 23.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[19.44 19.44 23.44 2" "3.44 19.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[15.44 15.44 19.44 19.44 15.44 ],[1 1 1 " "]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[11.44 11.44 15.44 11.44 15.44 15.44 11.44 ],[0.931 0.946 0" ".973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');po" "rt_label('input',1,'hi');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\fontsize{20}\\}" "','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Concat2" SID "325" Ports [2, 1] Position [490, 71, 520, 109] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary poi" "nt at zero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" block_version "8.2" sg_icon_stat "30,38,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 38 38 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 38 38 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[23.44 " "23.44 27.44 23.44 27.44 27.44 27.44 23.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[19.44 19.44 23.44 2" "3.44 19.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[15.44 15.44 19.44 19.44 15.44 ],[1 1 1 " "]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[11.44 11.44 15.44 11.44 15.44 15.44 11.44 ],[0.931 0.946 0" ".973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');po" "rt_label('input',1,'hi');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\fontsize{20}\\}" "','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Concat3" SID "326" Ports [2, 1] Position [550, 150, 575, 230] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary poi" "nt at zero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" block_version "8.2" sg_icon_stat "25,80,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 80 80 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 80 80 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[43" ".33 43.33 46.33 43.33 46.33 46.33 46.33 43.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[40.33 40.33 " "43.33 43.33 40.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[37.33 37.33 40.33 40.33 37.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[34.33 34.33 37.33 34.33 37.33 37.33 34.33 ]," "[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncol" "or('black');port_label('input',1,'hi');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\f" "ontsize{20}\\}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Concat4" SID "327" Ports [2, 1] Position [550, 30, 575, 110] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary poi" "nt at zero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" block_version "8.2" sg_icon_stat "25,80,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 80 80 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 80 80 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[43" ".33 43.33 46.33 43.33 46.33 46.33 46.33 43.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[40.33 40.33 " "43.33 43.33 40.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[37.33 37.33 40.33 40.33 37.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[34.33 34.33 37.33 34.33 37.33 37.33 34.33 ]," "[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncol" "or('black');port_label('input',1,'hi');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\f" "ontsize{20}\\}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Concat5" SID "328" Ports [2, 1] Position [635, 50, 660, 130] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary poi" "nt at zero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" block_version "8.2" sg_icon_stat "25,80,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 80 80 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 80 80 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[43" ".33 43.33 46.33 43.33 46.33 46.33 46.33 43.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[40.33 40.33 " "43.33 43.33 40.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[37.33 37.33 40.33 40.33 37.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[34.33 34.33 37.33 34.33 37.33 37.33 34.33 ]," "[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncol" "or('black');port_label('input',1,'hi');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\f" "ontsize{20}\\}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Reinterpret" SID "329" Ports [1, 1] Position [385, 90, 420, 110] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can changed the signal b" "etween signed and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs no" "thing.

Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is force" "d to unsigned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an outp" "ut of 56 (111000 in binary)." force_arith_type on arith_type "Unsigned" force_bin_pt on bin_pt "0" has_advanced_control "0" sggui_pos "20,20,356,309" block_type "reinterpret" block_version "8.2" sg_icon_stat "35,20,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 20 20 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 20 20 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[1" "2.22 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[10.22 10.2" "2 12.22 12.22 10.22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[8.22 8.22 10.22 10.22 8.2" "2 ],[1 1 1 ]);\npatch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931" " 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor" "('black');disp('reinterpret');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Reinterpret1" SID "330" Ports [1, 1] Position [390, 210, 425, 230] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can changed the signal b" "etween signed and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs no" "thing.

Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is force" "d to unsigned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an outp" "ut of 56 (111000 in binary)." force_arith_type on arith_type "Unsigned" force_bin_pt on bin_pt "0" has_advanced_control "0" sggui_pos "20,20,356,309" block_type "reinterpret" block_version "8.2" sg_icon_stat "35,20,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 20 20 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 20 20 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[1" "2.22 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[10.22 10.2" "2 12.22 12.22 10.22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[8.22 8.22 10.22 10.22 8.2" "2 ],[1 1 1 ]);\npatch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931" " 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor" "('black');disp('reinterpret');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "zero" SID "331" Ports [0, 1] Position [440, 191, 460, 209] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "20,18,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 20 20 0 0 ],[0 0 18 18 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[9.22 9.22 11.22 11" ".22 9.22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\np" "atch([7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfpr" "intf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('out" "put',1,'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "zero1" SID "332" Ports [0, 1] Position [440, 71, 460, 89] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "20,18,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 20 20 0 0 ],[0 0 18 18 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[9.22 9.22 11.22 11" ".22 9.22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\np" "atch([7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfpr" "intf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('out" "put',1,'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "32b" SID "333" Position [685, 83, 715, 97] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "Reinterpret1" SrcPort 1 DstBlock "Concat1" DstPort 2 } Line { SrcBlock "Reinterpret" SrcPort 1 DstBlock "Concat2" DstPort 2 } Line { SrcBlock "ADC_Q" SrcPort 1 DstBlock "Reinterpret1" DstPort 1 } Line { SrcBlock "OTR_Q" SrcPort 1 DstBlock "Concat3" DstPort 1 } Line { SrcBlock "ADC_I" SrcPort 1 DstBlock "Reinterpret" DstPort 1 } Line { SrcBlock "Concat5" SrcPort 1 DstBlock "32b" DstPort 1 } Line { SrcBlock "OTR_I" SrcPort 1 DstBlock "Concat4" DstPort 1 } Line { SrcBlock "Concat3" SrcPort 1 Points [25, 0; 0, -80] DstBlock "Concat5" DstPort 2 } Line { SrcBlock "Concat4" SrcPort 1 DstBlock "Concat5" DstPort 1 } Line { SrcBlock "Concat2" SrcPort 1 Points [0, 0] DstBlock "Concat4" DstPort 2 } Line { SrcBlock "zero1" SrcPort 1 DstBlock "Concat2" DstPort 1 } Line { SrcBlock "Concat1" SrcPort 1 DstBlock "Concat3" DstPort 2 } Line { SrcBlock "zero" SrcPort 1 DstBlock "Concat1" DstPort 1 } } } Block { BlockType Reference Name "Gateway Out1" SID "334" Ports [1, 1] Position [710, 135, 740, 145] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, double, o" "r fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarded, depen" "ding on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" UseAsDAC off DACChannel "'1'" has_advanced_control "0" sggui_pos "20,20,336,386" block_type "gatewayout" block_version "10.1.2" sg_icon_stat "30,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 10 10 0 ],[0.88 0.88 0.88" " ]);\nplot([0 30 30 0 0 ],[0 0 10 10 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ],[6.11 6.11 " "7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[5.11 5.11 6.11 6.11 5.11 ],[" "0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]);\npatch([13." "775 17.22 16.22 15.22 14.22 12.775 13.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.964 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ')" ";\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" } Block { BlockType Reference Name "Gateway Out4" SID "335" Ports [1, 1] Position [710, 120, 740, 130] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, double, o" "r fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarded, depen" "ding on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" UseAsDAC off DACChannel "'1'" has_advanced_control "0" sggui_pos "20,20,336,386" block_type "gatewayout" block_version "10.1.2" sg_icon_stat "30,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 10 10 0 ],[0.88 0.88 0.88" " ]);\nplot([0 30 30 0 0 ],[0 0 10 10 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ],[6.11 6.11 " "7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[5.11 5.11 6.11 6.11 5.11 ],[" "0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]);\npatch([13." "775 17.22 16.22 15.22 14.22 12.775 13.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.964 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ')" ";\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" } Block { BlockType SubSystem Name "RSSI" SID "336" Ports [1, 1] Position [490, 392, 560, 428] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "RSSI" Location [2, 74, 1184, 726] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Debug" SID "337" Position [465, 28, 495, 42] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Constant Name "Constant1" SID "338" Position [160, 100, 190, 130] ShowName off Value "0" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Counter" SID "339" Ports [0, 1] Position [380, 120, 440, 180] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited co" "unter is implemented by combining a counter with a comparator." cnt_type "Free Running" cnt_to "Inf" operation "Up" start_count "0" cnt_by_val "1" arith_type "Unsigned" n_bits "10" bin_pt "0" load_pin off rst off en off explicit_period "on" period "1" dbl_ovrd off use_behavioral_HDL off implementation "Fabric" xl_use_area off xl_area "[0,0,0,0,0,0,0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,619" block_type "counter" block_version "10.1.3" sg_icon_stat "60,60,0,1,white,blue,0,7ac47ef5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 60 60 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 60 60 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[38.8" "8 38.88 46.88 38.88 46.88 46.88 46.88 38.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[30.88 30.88 38.8" "8 38.88 30.88 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[22.88 22.88 30.88 30.88 22.88 ],[1" " 1 1 ]);\npatch([20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[14.88 14.88 22.88 14.88 22.88 22.88 14.88 ],[0.931 0" ".946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('bl" "ack');disp('{\\fontsize{14}\\bf++}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux" SID "340" Ports [3, 1] Position [600, 63, 645, 167] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "1" bin_pt "0" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,303" block_type "mux" block_version "10.1.3" sg_icon_stat "45,104,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 14.8571 89.1429 104" " 0 ],[0.77 0.82 0.91 ]);\nplot([0 45 45 0 0 ],[0 14.8571 89.1429 104 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32" " 23.32 14.65 8.65 ],[58.66 58.66 64.66 58.66 64.66 64.66 64.66 58.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.6" "5 14.65 ],[52.66 52.66 58.66 58.66 52.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[46.66 " "46.66 52.66 52.66 46.66 ],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[40.66 40.66 46.66 40.6" "6 46.66 46.66 40.66 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: b" "egin icon text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncol" "or('black');port_label('input',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: " "end icon text');" } Block { BlockType Reference Name "radio2_RSSI" SID "341" Ports [1, 1] Position [280, 109, 335, 121] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, double and fixed point to Xilinx" " fixed point type.

Hardware notes: In hardware these blocks become top level input ports." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "10" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Truncate" overflow "Wrap" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off UseAsADC off ADCChannel "'1'" hdl_port "on" has_advanced_control "0" sggui_pos "20,20,356,432" block_type "gatewayin" block_version "VER_STRING_GOES_HERE" sg_icon_stat "55,12,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 12 12 0 ],[0.95 0" ".93 0.65 ]);\nplot([0 55 55 0 0 ],[0 0 12 12 0 ]);\npatch([24.775 26.22 27.22 28.22 29.22 27.22 25.775 24.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([25.775 27.22 26.22 24.775 25.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.985 0.979 0.895 ]);\npatch([24.775 26.22 27.22 25.775 24.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([25.775 29.22 28.22 27.22 26.22 24.775 25.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.985 0." "979 0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "RSSI" SID "342" Position [740, 108, 770, 122] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "radio2_RSSI" DstPort 1 } Line { SrcBlock "Debug" SrcPort 1 Points [40, 0; 0, 45] DstBlock "Mux" DstPort 1 } Line { SrcBlock "radio2_RSSI" SrcPort 1 DstBlock "Mux" DstPort 2 } Line { SrcBlock "Counter" SrcPort 1 DstBlock "Mux" DstPort 3 } Line { SrcBlock "Mux" SrcPort 1 DstBlock "RSSI" DstPort 1 } } } Block { BlockType Scope Name "Scope" SID "343" Ports [2] Position [800, 111, 830, 164] Floating off Location [5, 34, 1285, 912] Open off NumInputPorts "2" List { ListType AxesTitles axes1 "%" axes2 "%" } YMin "-5~-5" YMax "5~5" DataFormat "StructureWithTime" SampleTime "0" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Outport Name "Radio 2 RSSI" SID "344" Position [655, 403, 685, 417] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Outport Name "Radio 2 I/Q" SID "345" Position [865, 288, 895, 302] Port "2" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "ADC Q" SrcPort 2 Points [35, 0; 0, 20; 30, 0] Branch { DstBlock "Concatenates_1" DstPort 4 } Branch { Points [0, -215] DstBlock "Gateway Out1" DstPort 1 } } Line { SrcBlock "ADC Q" SrcPort 1 DstBlock "Concatenates_1" DstPort 3 } Line { Labels [0, 0] SrcBlock "ADC I" SrcPort 2 Points [55, 0] Branch { DstBlock "Concatenates_1" DstPort 2 } Branch { Points [0, -150] DstBlock "Gateway Out4" DstPort 1 } } Line { SrcBlock "ADC I" SrcPort 1 Points [15, 0; 0, -15] DstBlock "Concatenates_1" DstPort 1 } Line { SrcBlock "Concatenates_1" SrcPort 1 Points [0, 0] DstBlock "Radio 2 I/Q" DstPort 1 } Line { SrcBlock "Gateway Out4" SrcPort 1 DstBlock "Scope" DstPort 1 } Line { SrcBlock "Gateway Out1" SrcPort 1 Points [40, 0] DstBlock "Scope" DstPort 2 } Line { SrcBlock "DebugRxBuffers" SrcPort 1 Points [165, 0] Branch { DstBlock "ADC I" DstPort 1 } Branch { Points [0, 65] Branch { DstBlock "ADC Q" DstPort 1 } Branch { Points [0, 95] DstBlock "RSSI" DstPort 1 } } } Line { SrcBlock "RSSI" SrcPort 1 DstBlock "Radio 2 RSSI" DstPort 1 } Line { SrcBlock "MGCAGC_AGCDCO_SEL" SrcPort 1 Points [115, 0] Branch { Points [0, -65] DstBlock "ADC I" DstPort 2 } Branch { DstBlock "ADC Q" DstPort 2 } } } } Block { BlockType SubSystem Name "Radio 2 Outputs" SID "346" Ports [1] Position [1180, 761, 1230, 809] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "Radio 2 Outputs" Location [2, 74, 1078, 531] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "32b" SID "347" Position [250, 93, 280, 107] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "16LSB" SID "348" Ports [1, 1] Position [430, 92, 470, 108] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type " "is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardware " "notes: In hardware this block costs nothing." nbits "16" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,442,407" block_type "slice" block_version "8.2" sg_icon_stat "40,16,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 16 16 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 16 16 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[10.22 10.22 1" "2.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[8.22 8.22 10.22 10.22 8.22" " ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatch([17" ".55 24.44 22.44 20.44 18.44 15.55 17.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprintf(''," "'COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'[a" ":b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "16MSB" SID "349" Ports [1, 1] Position [430, 36, 470, 54] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type " "is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardware " "notes: In hardware this block costs nothing." nbits "16" boolean_output off mode "Upper Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,442,407" block_type "slice" block_version "8.2" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[11.22 11.22 1" "3.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 11.22 11.22 9.22" " ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([17" ".55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf(''," "'COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'[a" ":b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Radio 2 DAC I" SID "350" Ports [1, 1] Position [680, 24, 775, 66] LibraryVersion "1.48" LinkData { BlockName "Convert" DialogParameters { sg_icon_stat "45,30,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 30 30 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\npatch([13.1 18.88 22.88 26.88 30.88 22.88 17.1 13.1 ],[19.4" "4 19.44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([17.1 22.88 18.88 13.1 17.1 ],[15.44 15.44 19.4" "4 19.44 15.44 ],[0.931 0.946 0.973 ]);\npatch([13.1 18.88 22.88 17.1 13.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1" " 1 1 ]);\npatch([17.1 30.88 26.88 22.88 18.88 13.1 17.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946" " 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black'" ");port_label('output',1,'cast');\nfprintf('','COMMENT: end icon text');" } BlockName "radio2_dac_I" DialogParameters { sg_icon_stat "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0" ".93 0.65 ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[1" "2.22 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.2" "2 12.22 12.22 10.22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.2" "2 ],[1 1 1 ]);\npatch([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985" " 0.979 0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','o" "n');\nfprintf('','COMMENT: end icon text');" } } SourceBlock "WARP_Blockset/WARP Radio Board ADC//DACs/Radio 2 DAC I" SourceType "" ShowPortLabels "FromPortIcon" SystemSampleTime "-1" FunctionWithSeparateData off RTWMemSecFuncInitTerm "Inherit from model" RTWMemSecFuncExecute "Inherit from model" RTWMemSecDataConstants "Inherit from model" RTWMemSecDataInternal "Inherit from model" RTWMemSecDataParameters "Inherit from model" GeneratePreprocessorConditionals off } Block { BlockType Reference Name "Radio 2 DAC Q" SID "351" Ports [1, 1] Position [680, 79, 775, 121] LibraryVersion "1.48" LinkData { BlockName "Convert" DialogParameters { sg_icon_stat "45,30,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 30 30 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\npatch([13.1 18.88 22.88 26.88 30.88 22.88 17.1 13.1 ],[19.4" "4 19.44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([17.1 22.88 18.88 13.1 17.1 ],[15.44 15.44 19.4" "4 19.44 15.44 ],[0.931 0.946 0.973 ]);\npatch([13.1 18.88 22.88 17.1 13.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1" " 1 1 ]);\npatch([17.1 30.88 26.88 22.88 18.88 13.1 17.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946" " 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black'" ");port_label('output',1,'cast');\nfprintf('','COMMENT: end icon text');" } BlockName "radio2_dac_Q" DialogParameters { sg_icon_stat "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0" ".93 0.65 ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[1" "2.22 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.2" "2 12.22 12.22 10.22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.2" "2 ],[1 1 1 ]);\npatch([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985" " 0.979 0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','o" "n');\nfprintf('','COMMENT: end icon text');" } } SourceBlock "WARP_Blockset/WARP Radio Board ADC//DACs/Radio 2 DAC Q" SourceType "" ShowPortLabels "FromPortIcon" SystemSampleTime "-1" FunctionWithSeparateData off RTWMemSecFuncInitTerm "Inherit from model" RTWMemSecFuncExecute "Inherit from model" RTWMemSecDataConstants "Inherit from model" RTWMemSecDataInternal "Inherit from model" RTWMemSecDataParameters "Inherit from model" GeneratePreprocessorConditionals off } Block { BlockType Reference Name "Register" SID "352" Ports [1, 1] Position [595, 31, 630, 59] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "8.2" sg_icon_stat "35,28,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 28 28 0 ],[0.77 0.82 0.91" " ]);\nplot([0 35 35 0 0 ],[0 0 28 28 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[18.44 18.44 22.44 " "18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[14.44 14.44 18.44 18.44 14.44 ],[0." "931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\npatch([12.1 25." "88 21.88 17.88 13.88 8.1 12.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\ncolor(" "'black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon " "text');" } Block { BlockType Reference Name "Register1" SID "353" Ports [1, 1] Position [595, 86, 630, 114] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "8.2" sg_icon_stat "35,28,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 28 28 0 ],[0.77 0.82 0.91" " ]);\nplot([0 35 35 0 0 ],[0 0 28 28 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[18.44 18.44 22.44 " "18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[14.44 14.44 18.44 18.44 14.44 ],[0." "931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\npatch([12.1 25." "88 21.88 17.88 13.88 8.1 12.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,'d');\ncolor(" "'black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon " "text');" } Block { BlockType Reference Name "Reinterpret" SID "354" Ports [1, 1] Position [530, 35, 575, 55] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can changed the signal between s" "igned and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothing.

" "Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsigned wi" "th 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111000 in " "binary)." force_arith_type on arith_type "Signed (2's comp)" force_bin_pt on bin_pt "15" has_advanced_control "0" sggui_pos "20,20,356,309" block_type "reinterpret" block_version "8.2" sg_icon_stat "45,20,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.91" " ]);\nplot([0 45 45 0 0 ],[0 0 20 20 0 ]);\npatch([17.55 20.44 22.44 24.44 26.44 22.44 19.55 17.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([19.55 22.44 20.44 17.55 19.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.931 0.946 0.973 ]);\npatch([17.55 20.44 22.44 19.55 17.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([19.55 26.44 24.44 22.44 20.44 17.55 19.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('reinterpret'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Reinterpret1" SID "355" Ports [1, 1] Position [530, 90, 575, 110] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can changed the signal between s" "igned and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothing.

" "Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsigned wi" "th 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111000 in " "binary)." force_arith_type on arith_type "Signed (2's comp)" force_bin_pt on bin_pt "15" has_advanced_control "0" sggui_pos "20,20,356,309" block_type "reinterpret" block_version "8.2" sg_icon_stat "45,20,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.91" " ]);\nplot([0 45 45 0 0 ],[0 0 20 20 0 ]);\npatch([17.55 20.44 22.44 24.44 26.44 22.44 19.55 17.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([19.55 22.44 20.44 17.55 19.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.931 0.946 0.973 ]);\npatch([17.55 20.44 22.44 19.55 17.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([19.55 26.44 24.44 22.44 20.44 17.55 19.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('reinterpret'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Terminator Name "Terminator1" SID "356" Position [840, 35, 860, 55] ShowName off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Terminator Name "Terminator2" SID "357" Position [840, 90, 860, 110] ShowName off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "Radio 2 DAC Q" SrcPort 1 DstBlock "Terminator2" DstPort 1 } Line { SrcBlock "Radio 2 DAC I" SrcPort 1 DstBlock "Terminator1" DstPort 1 } Line { SrcBlock "Reinterpret1" SrcPort 1 DstBlock "Register1" DstPort 1 } Line { SrcBlock "Reinterpret" SrcPort 1 DstBlock "Register" DstPort 1 } Line { SrcBlock "16LSB" SrcPort 1 DstBlock "Reinterpret1" DstPort 1 } Line { SrcBlock "16MSB" SrcPort 1 DstBlock "Reinterpret" DstPort 1 } Line { SrcBlock "Register" SrcPort 1 DstBlock "Radio 2 DAC I" DstPort 1 } Line { SrcBlock "Register1" SrcPort 1 DstBlock "Radio 2 DAC Q" DstPort 1 } Line { SrcBlock "32b" SrcPort 1 Points [65, 0] Branch { Points [0, -55] DstBlock "16MSB" DstPort 1 } Branch { DstBlock "16LSB" DstPort 1 } } } } Block { BlockType SubSystem Name "Radio 3\nRx Buffers" SID "358" Ports [5] Position [1175, 323, 1240, 427] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "Radio 3\nRx Buffers" Location [2, 74, 1014, 726] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "RSSI" SID "359" Position [450, 313, 480, 327] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "I/Q" SID "360" Position [545, 163, 575, 177] Port "2" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "Addr" SID "361" Position [325, 128, 355, 142] Port "3" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "WE" SID "362" Position [110, 183, 140, 197] Port "4" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "EN" SID "363" Position [110, 213, 140, 227] Port "5" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Convert1" SID "364" Ports [1, 1] Position [185, 212, 210, 228] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "16" bin_pt "14" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,461,375" block_type "convert" block_version "8.2" sg_icon_stat "25,16,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 16 16 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 16 16 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[10.22 10.22 12.2" "2 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[8.22 8.22 10.22 10.22 8.22 ],[0." "931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatch([9.55 16.44 " "14.44 12.44 10.44 7.55 9.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: en" "d icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'cast');\nfprin" "tf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out" SID "365" Ports [1, 1] Position [500, 30, 530, 40] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, double, o" "r fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarded, depen" "ding on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" UseAsDAC off DACChannel "'1'" has_advanced_control "0" sggui_pos "20,20,336,386" block_type "gatewayout" block_version "10.1.2" sg_icon_stat "30,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 10 10 0 ],[0.88 0.88 0.88" " ]);\nplot([0 30 30 0 0 ],[0 0 10 10 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ],[6.11 6.11 " "7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[5.11 5.11 6.11 6.11 5.11 ],[" "0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]);\npatch([13." "775 17.22 16.22 15.22 14.22 12.775 13.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.964 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ')" ";\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" } Block { BlockType Reference Name "Gateway Out1" SID "366" Ports [1, 1] Position [500, 70, 530, 80] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, double, o" "r fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarded, depen" "ding on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" UseAsDAC off DACChannel "'1'" has_advanced_control "0" sggui_pos "20,20,336,386" block_type "gatewayout" block_version "10.1.2" sg_icon_stat "30,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 10 10 0 ],[0.88 0.88 0.88" " ]);\nplot([0 30 30 0 0 ],[0 0 10 10 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ],[6.11 6.11 " "7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[5.11 5.11 6.11 6.11 5.11 ],[" "0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]);\npatch([13." "775 17.22 16.22 15.22 14.22 12.775 13.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.964 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ')" ";\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" } Block { BlockType Reference Name "Logical" SID "367" Ports [2, 1] Position [255, 175, 310, 235] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "9.1.01" sg_icon_stat "55,60,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 60 60 0 ],[0.77 0.82 0.91" " ]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ],[37.77 37.7" "7 44.77 37.77 44.77 44.77 44.77 37.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[30.77 30.77 37.77 37" ".77 30.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[23.77 23.77 30.77 30.77 23.77 ],[1 1" " 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[16.77 16.77 23.77 16.77 23.77 23.77 16.77 ],[0.931 0" ".946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('bl" "ack');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "Radio 3\nRSSI Buffer" SID "368" Ports [3] Position [650, 264, 705, 376] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "Radio 3\nRSSI Buffer" Location [2, 70, 1918, 1150] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Addr_14b" SID "369" Position [325, 348, 355, 362] NamePlacement "alternate" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "RSSI" SID "370" Position [95, 383, 125, 397] Port "2" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "WE" SID "371" Position [720, 478, 750, 492] Port "3" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "11MSB" SID "372" Ports [1, 1] Position [430, 346, 470, 364] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outp" "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

" "

Hardware notes: In hardware this block costs nothing." nbits "11" boolean_output off mode "Upper Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,407" block_type "slice" block_version "8.2" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[1" "1.22 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 " "11.22 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[" "1 1 1 ]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black" "');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "BIT[2]" SID "373" Ports [1, 1] Position [430, 401, 470, 419] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outp" "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

" "

Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "2" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,407" block_type "slice" block_version "8.2" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[1" "1.22 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 " "11.22 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[" "1 1 1 ]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black" "');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Concat" SID "374" Ports [2, 1] Position [685, 381, 725, 459] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary poi" "nt at zero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" block_version "10.1.2" sg_icon_stat "40,78,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 78 78 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 78 78 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[44.55" " 44.55 49.55 44.55 49.55 49.55 49.55 44.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[39.55 39.55 44" ".55 44.55 39.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[34.55 34.55 39.55 39.55 34.55 " "],[1 1 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[29.55 29.55 34.55 29.55 34.55 34.55 29.55 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor(" "'black');port_label('input',1,'hi');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\font" "size{20}\\}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert" SID "375" Ports [1, 1] Position [285, 382, 320, 398] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do" " not." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "16" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,461,375" block_type "convert" block_version "8.2" sg_icon_stat "35,16,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 16 16 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 16 16 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[1" "0.22 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[8.22 8.22 " "10.22 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[6.22 6.22 8.22 8.22 6.22 ],[" "1 1 1 ]);\npatch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black" "');port_label('output',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "376" Ports [1, 1] Position [510, 402, 540, 418] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,251" block_type "inv" block_version "10.1.2" sg_icon_stat "30,16,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 16 16 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 16 16 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[1" "0.22 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[8.22 8.22 " "10.22 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[6.22 6.22 8.22 8.22 6.22 ],[" "1 1 1 ]);\npatch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('bla" "ck');disp('not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register" SID "377" Ports [2, 1] Position [580, 378, 625, 422] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "10.1.2" sg_icon_stat "45,44,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28." "66 28.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 2" "8.66 28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 " "],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0" ".931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor" "('black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('ou" "tput',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Reinterpret1" SID "378" Ports [1, 1] Position [180, 382, 215, 398] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can changed the signal b" "etween signed and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs no" "thing.

Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is force" "d to unsigned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an outp" "ut of 56 (111000 in binary)." force_arith_type on arith_type "Unsigned" force_bin_pt on bin_pt "0" has_advanced_control "0" sggui_pos "436,54,356,312" block_type "reinterpret" block_version "9.1.01" sg_icon_stat "35,16,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 16 16 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 16 16 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[1" "0.22 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[8.22 8.22 " "10.22 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[6.22 6.22 8.22 8.22 6.22 ],[" "1 1 1 ]);\npatch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('bla" "ck');disp('reinterpret');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Shared Memory" SID "379" Ports [3, 1] Position [800, 323, 880, 517] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Shared Memory" SourceType "Xilinx Shared Memory Random Access Memory Block" shared_memory_name "'RSSIBuff_Radio3'" depth "2^11" ownership "Locally Owned and Initialized" initVector "0" en off mutex "Unprotected" mode "Read and Write" write_mode "Read After Write" time_out "0" latency "1" explicit_data_type on gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" xl_use_area off xl_area "[0,0,0,0,0,0,0]" implementation "Block RAM" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,384,381" block_type "shmem" block_version "10.1.2" sg_icon_stat "80,194,3,1,white,blue,0,bf435243,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 80 80 0 0 ],[0 0 194 194 0 ],[0.77" " 0.82 0.91 ]);\nplot([0 80 80 0 0 ],[0 0 194 194 0 ]);\npatch([15.525 31.42 42.42 53.42 64.42 42.42 26.525 15.5" "25 ],[109.21 109.21 120.21 109.21 120.21 120.21 120.21 109.21 ],[1 1 1 ]);\npatch([26.525 42.42 31.42 15.525 26" ".525 ],[98.21 98.21 109.21 109.21 98.21 ],[0.931 0.946 0.973 ]);\npatch([15.525 31.42 42.42 26.525 15.525 ],[87" ".21 87.21 98.21 98.21 87.21 ],[1 1 1 ]);\npatch([26.525 64.42 53.42 42.42 31.42 15.525 26.525 ],[76.21 76.21 87" ".21 76.21 87.21 87.21 76.21 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','CO" "MMENT: begin icon text');\ncolor('black');port_label('input',1,'addr');\ncolor('black');port_label('input',2,'d" "in');\ncolor('black');port_label('input',3,'we');\ncolor('black');port_label('output',1,'dout');\nfprintf('','C" "OMMENT: end icon text');" } Block { BlockType Terminator Name "Terminator2" SID "380" Position [945, 410, 965, 430] ShowName off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "RSSI" SrcPort 1 DstBlock "Reinterpret1" DstPort 1 } Line { SrcBlock "Convert" SrcPort 1 Points [35, 0] Branch { DstBlock "Register" DstPort 1 } Branch { Points [0, 50] DstBlock "Concat" DstPort 2 } } Line { SrcBlock "Addr_14b" SrcPort 1 Points [40, 0] Branch { DstBlock "11MSB" DstPort 1 } Branch { Points [0, 55] DstBlock "BIT[2]" DstPort 1 } } Line { SrcBlock "WE" SrcPort 1 DstBlock "Shared Memory" DstPort 3 } Line { SrcBlock "Reinterpret1" SrcPort 1 DstBlock "Convert" DstPort 1 } Line { SrcBlock "Concat" SrcPort 1 DstBlock "Shared Memory" DstPort 2 } Line { SrcBlock "BIT[2]" SrcPort 1 DstBlock "Inverter" DstPort 1 } Line { SrcBlock "11MSB" SrcPort 1 DstBlock "Shared Memory" DstPort 1 } Line { SrcBlock "Shared Memory" SrcPort 1 DstBlock "Terminator2" DstPort 1 } Line { SrcBlock "Register" SrcPort 1 DstBlock "Concat" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Register" DstPort 2 } } } Block { BlockType SubSystem Name "Radio 3 I/Q\nBuffer" SID "381" Ports [3] Position [650, 116, 705, 224] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "Radio 3 I/Q\nBuffer" Location [2, 74, 1270, 726] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Addr_14b" SID "382" Position [200, 68, 230, 82] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "I/Q_32b" SID "383" Position [200, 98, 230, 112] Port "2" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "WE" SID "384" Position [200, 128, 230, 142] Port "3" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Shared Memory" SID "385" Ports [3, 1] Position [320, 60, 400, 150] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Shared Memory" SourceType "Xilinx Shared Memory Random Access Memory Block" shared_memory_name "'RxBuff_Radio3'" depth "2^14" ownership "Locally Owned and Initialized" initVector "0" en off mutex "Unprotected" mode "Read and Write" write_mode "Read After Write" time_out "0" latency "1" explicit_data_type on gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" xl_use_area off xl_area "[0,0,0,0,0,0,0]" implementation "Block RAM" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,384,381" block_type "shmem" block_version "10.1.2" sg_icon_stat "80,90,3,1,white,blue,0,bf435243,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 80 80 0 0 ],[0 0 90 90 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 80 80 0 0 ],[0 0 90 90 0 ]);\npatch([15.525 31.42 42.42 53.42 64.42 42.42 26.525 15.525 ]" ",[57.21 57.21 68.21 57.21 68.21 68.21 68.21 57.21 ],[1 1 1 ]);\npatch([26.525 42.42 31.42 15.525 26.525 ],[46.2" "1 46.21 57.21 57.21 46.21 ],[0.931 0.946 0.973 ]);\npatch([15.525 31.42 42.42 26.525 15.525 ],[35.21 35.21 46.2" "1 46.21 35.21 ],[1 1 1 ]);\npatch([26.525 64.42 53.42 42.42 31.42 15.525 26.525 ],[24.21 24.21 35.21 24.21 35.2" "1 35.21 24.21 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin i" "con text');\ncolor('black');port_label('input',1,'addr');\ncolor('black');port_label('input',2,'din');\ncolor('" "black');port_label('input',3,'we');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end ic" "on text');" } Block { BlockType Terminator Name "Terminator" SID "386" Position [450, 95, 470, 115] ShowName off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "Shared Memory" SrcPort 1 DstBlock "Terminator" DstPort 1 } Line { SrcBlock "WE" SrcPort 1 DstBlock "Shared Memory" DstPort 3 } Line { SrcBlock "I/Q_32b" SrcPort 1 DstBlock "Shared Memory" DstPort 2 } Line { SrcBlock "Addr_14b" SrcPort 1 DstBlock "Shared Memory" DstPort 1 } } } Block { BlockType Scope Name "Scope" SID "387" Ports [2] Position [585, 14, 625, 96] Floating off Location [5, 49, 1285, 757] Open off NumInputPorts "2" ZoomMode "yonly" List { ListType AxesTitles axes1 "%" axes2 "%" } YMin "-5~-5" YMax "5~5" SaveName "ScopeData2" DataFormat "StructureWithTime" MaxDataPoints "40000" SampleTime "0" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "Gateway Out1" SrcPort 1 DstBlock "Scope" DstPort 2 } Line { SrcBlock "Gateway Out" SrcPort 1 DstBlock "Scope" DstPort 1 } Line { SrcBlock "I/Q" SrcPort 1 DstBlock "Radio 3 I/Q\nBuffer" DstPort 2 } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "Logical" DstPort 2 } Line { SrcBlock "EN" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "WE" SrcPort 1 DstBlock "Logical" DstPort 1 } Line { SrcBlock "Addr" SrcPort 1 Points [75, 0] Branch { Points [0, -100] DstBlock "Gateway Out" DstPort 1 } Branch { Labels [0, 0] DstBlock "Radio 3 I/Q\nBuffer" DstPort 1 } Branch { Points [0, 150] DstBlock "Radio 3\nRSSI Buffer" DstPort 1 } } Line { SrcBlock "Logical" SrcPort 1 Points [65, 0] Branch { Points [85, 0] Branch { Points [0, -130] DstBlock "Gateway Out1" DstPort 1 } Branch { Labels [0, 0] DstBlock "Radio 3 I/Q\nBuffer" DstPort 3 } } Branch { Points [0, 150] DstBlock "Radio 3\nRSSI Buffer" DstPort 3 } } Line { SrcBlock "RSSI" SrcPort 1 DstBlock "Radio 3\nRSSI Buffer" DstPort 2 } } } Block { BlockType SubSystem Name "Radio 3\nTx Buffer" SID "388" Ports [3, 1] Position [1015, 852, 1095, 908] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "Radio 3\nTx Buffer" Location [2, 74, 1270, 726] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "RdAddr_14b" SID "389" Position [350, 288, 380, 302] NamePlacement "alternate" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "Rst" SID "390" Position [30, 173, 60, 187] Port "2" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "En" SID "391" Position [30, 203, 60, 217] Port "3" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Constant" SID "392" Ports [0, 1] Position [630, 350, 655, 370] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,400,346" block_type "constant" block_version "10.1.2" sg_icon_stat "25,20,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 20 20 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[12.22 12.22 14.2" "2 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[10.22 10.22 12.22 12.22 10.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatch([9.55 1" "6.44 14.44 12.44 10.44 7.55 9.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'0');\nfprin" "tf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant1" SID "393" Ports [0, 1] Position [355, 345, 380, 365] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "32" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,400,346" block_type "constant" block_version "10.1.2" sg_icon_stat "25,20,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 20 20 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[12.22 12.22 14.2" "2 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[10.22 10.22 12.22 12.22 10.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatch([9.55 1" "6.44 14.44 12.44 10.44 7.55 9.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'0');\nfprin" "tf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant2" SID "394" Ports [0, 1] Position [355, 315, 380, 335] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,400,346" block_type "constant" block_version "10.1.2" sg_icon_stat "25,20,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 20 20 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[12.22 12.22 14.2" "2 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[10.22 10.22 12.22 12.22 10.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatch([9.55 1" "6.44 14.44 12.44 10.44 7.55 9.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'0');\nfprin" "tf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert" SID "395" Ports [1, 1] Position [350, 188, 375, 202] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "16" bin_pt "14" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,374,375" block_type "convert" block_version "8.2" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.22 11.22 " "9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 ],[0.931 0." "946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.55 16.44 14.44 " "12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon" " graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'cast');\nfprintf(''," "'COMMENT: end icon text');" } Block { BlockType Reference Name "Convert1" SID "396" Ports [1, 1] Position [100, 203, 120, 217] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "16" bin_pt "14" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,374,375" block_type "convert" block_version "8.2" sg_icon_stat "20,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 14 14 0 ],[0.77 0.82 0.91" " ]);\nplot([0 20 20 0 0 ],[0 0 14 14 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[9.22 9.22 11.22 9" ".22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[0.931 0.94" "6 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([7.55 14.44 12.44 10." "44 8.44 5.55 7.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon gra" "phics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'cast');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "397" Ports [1, 1] Position [150, 201, 180, 219] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "9.1.01" sg_icon_stat "30,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 18 18 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[11.22 11.22 1" "3.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[9.22 9.22 11.22 11.22 9.22" " ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([12" ".55 19.44 17.44 15.44 13.44 10.55 12.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf(''," "'COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nfprintf('" "','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical" SID "398" Ports [2, 1] Position [215, 165, 270, 225] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "9.1.01" sg_icon_stat "55,60,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 60 60 0 ],[0.77 0.82 0.91" " ]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ],[37.77 37.7" "7 44.77 37.77 44.77 44.77 44.77 37.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[30.77 30.77 37.77 37" ".77 30.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[23.77 23.77 30.77 30.77 23.77 ],[1 1" " 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[16.77 16.77 23.77 16.77 23.77 23.77 16.77 ],[0.931 0" ".946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('bl" "ack');disp('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux" SID "399" Ports [3, 1] Position [750, 273, 795, 377] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,303" block_type "mux" block_version "10.1.2" sg_icon_stat "45,104,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 14.8571 89.1429 104 0 ],[0." "77 0.82 0.91 ]);\nplot([0 45 45 0 0 ],[0 14.8571 89.1429 104 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65" " 8.65 ],[58.66 58.66 64.66 58.66 64.66 64.66 64.66 58.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[52.66" " 52.66 58.66 58.66 52.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[46.66 46.66 52.66 52.66 46" ".66 ],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[40.66 40.66 46.66 40.66 46.66 46.66 40.66 ],[0" ".931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('input',3" ",'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Shared Memory" SID "400" Ports [3, 1] Position [445, 280, 525, 370] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Shared Memory" SourceType "Xilinx Shared Memory Random Access Memory Block" shared_memory_name "'TxBuff_Radio3'" depth "2^14" ownership "Locally Owned and Initialized" initVector "0" en off mutex "Unprotected" mode "Read and Write" write_mode "Read After Write" time_out "0" latency "1" explicit_data_type on gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" xl_use_area off xl_area "[0,0,0,0,0,0,0]" implementation "Block RAM" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,384,381" block_type "shmem" block_version "10.1.2" sg_icon_stat "80,90,3,1,white,blue,0,bf435243,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 80 80 0 0 ],[0 0 90 90 0 ],[0.77 0.82 0.91" " ]);\nplot([0 80 80 0 0 ],[0 0 90 90 0 ]);\npatch([15.525 31.42 42.42 53.42 64.42 42.42 26.525 15.525 ],[57.21 57.2" "1 68.21 57.21 68.21 68.21 68.21 57.21 ],[1 1 1 ]);\npatch([26.525 42.42 31.42 15.525 26.525 ],[46.21 46.21 57.21 57" ".21 46.21 ],[0.931 0.946 0.973 ]);\npatch([15.525 31.42 42.42 26.525 15.525 ],[35.21 35.21 46.21 46.21 35.21 ],[1 1" " 1 ]);\npatch([26.525 64.42 53.42 42.42 31.42 15.525 26.525 ],[24.21 24.21 35.21 24.21 35.21 35.21 24.21 ],[0.931 0" ".946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');" "port_label('input',1,'addr');\ncolor('black');port_label('input',2,'din');\ncolor('black');port_label('input',3,'we" "');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "IQ_32b" SID "401" Position [885, 318, 915, 332] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "Mux" SrcPort 1 DstBlock "IQ_32b" DstPort 1 } Line { SrcBlock "Constant2" SrcPort 1 DstBlock "Shared Memory" DstPort 2 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Shared Memory" DstPort 3 } Line { SrcBlock "Shared Memory" SrcPort 1 DstBlock "Mux" DstPort 2 } Line { SrcBlock "Constant" SrcPort 1 DstBlock "Mux" DstPort 3 } Line { SrcBlock "RdAddr_14b" SrcPort 1 DstBlock "Shared Memory" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical" DstPort 2 } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "Inverter" DstPort 1 } Line { SrcBlock "En" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Rst" SrcPort 1 DstBlock "Logical" DstPort 1 } Line { SrcBlock "Convert" SrcPort 1 Points [160, 0; 0, 95] DstBlock "Mux" DstPort 1 } Line { SrcBlock "Logical" SrcPort 1 DstBlock "Convert" DstPort 1 } } } Block { BlockType SubSystem Name "Radio 3 Inputs" SID "402" Ports [2, 2] Position [905, 310, 1080, 370] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "Radio 3 Inputs" Location [2, 74, 1014, 726] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "DebugRxBuffers" SID "403" Position [180, 248, 210, 262] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "MGCAGC_AGCDCO_SEL" SID "404" Position [185, 328, 215, 342] Port "2" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType SubSystem Name "ADC I" SID "405" Ports [2, 2] Position [410, 245, 565, 285] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "ADC I" Location [37, 74, 1049, 726] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Debug" SID "406" Position [645, 13, 675, 27] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "MGCAGC_AGCDCO_SEL" SID "407" Position [125, 203, 155, 217] Port "2" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Constant Name "Constant1" SID "408" Position [15, 280, 45, 310] ShowName off Value "0" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Counter" SID "409" Ports [0, 1] Position [480, 300, 540, 360] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited co" "unter is implemented by combining a counter with a comparator." cnt_type "Free Running" cnt_to "Inf" operation "Down" start_count "2^14-1" cnt_by_val "1" arith_type "Unsigned" n_bits "14" bin_pt "0" load_pin off rst off en off explicit_period "on" period "1" dbl_ovrd off use_behavioral_HDL off implementation "Fabric" xl_use_area off xl_area "[0,0,0,0,0,0,0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,619" block_type "counter" block_version "10.1.3" sg_icon_stat "60,60,0,1,white,blue,0,cf0fdd8c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 60 60 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 60 60 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[38.8" "8 38.88 46.88 38.88 46.88 46.88 46.88 38.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[30.88 30.88 38.8" "8 38.88 30.88 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[22.88 22.88 30.88 30.88 22.88 ],[1" " 1 1 ]);\npatch([20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[14.88 14.88 22.88 14.88 22.88 22.88 14.88 ],[0.931 0" ".946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('bl" "ack');disp('{\\fontsize{14}\\bf--}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "FromAGC_Radio3_I" SID "410" Ports [1, 1] Position [110, 385, 175, 405] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, double and fixed point to Xilinx" " fixed point type.

Hardware notes: In hardware these blocks become top level input ports." gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "14" bin_pt "13" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off UseAsADC off ADCChannel "'1'" hdl_port "on" has_advanced_control "0" sggui_pos "20,20,348,406" block_type "gatewayin" block_version "10.1.3" sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0" ".93 0.65 ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[1" "2.22 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.2" "2 12.22 12.22 10.22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.2" "2 ],[1 1 1 ]);\npatch([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985" " 0.979 0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' " "');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux" SID "411" Ports [3, 1] Position [780, 48, 825, 152] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "1" bin_pt "0" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,303" block_type "mux" block_version "10.1.3" sg_icon_stat "45,104,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 14.8571 89.1429 104" " 0 ],[0.77 0.82 0.91 ]);\nplot([0 45 45 0 0 ],[0 14.8571 89.1429 104 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32" " 23.32 14.65 8.65 ],[58.66 58.66 64.66 58.66 64.66 64.66 64.66 58.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.6" "5 14.65 ],[52.66 52.66 58.66 58.66 52.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[46.66 " "46.66 52.66 52.66 46.66 ],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[40.66 40.66 46.66 40.6" "6 46.66 46.66 40.66 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: b" "egin icon text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncol" "or('black');port_label('input',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: " "end icon text');" } Block { BlockType Reference Name "Mux1" SID "412" Ports [3, 1] Position [780, 243, 825, 347] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "1" bin_pt "0" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,303" block_type "mux" block_version "10.1.3" sg_icon_stat "45,104,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 14.8571 89.1429 104" " 0 ],[0.77 0.82 0.91 ]);\nplot([0 45 45 0 0 ],[0 14.8571 89.1429 104 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32" " 23.32 14.65 8.65 ],[58.66 58.66 64.66 58.66 64.66 64.66 64.66 58.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.6" "5 14.65 ],[52.66 52.66 58.66 58.66 52.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[46.66 " "46.66 52.66 52.66 46.66 ],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[40.66 40.66 46.66 40.6" "6 46.66 46.66 40.66 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: b" "egin icon text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncol" "or('black');port_label('input',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: " "end icon text');" } Block { BlockType Reference Name "Mux2" SID "413" Ports [3, 1] Position [270, 243, 315, 347] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "1" bin_pt "0" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,303" block_type "mux" block_version "10.1.3" sg_icon_stat "45,104,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 14.8571 89.1429 104" " 0 ],[0.77 0.82 0.91 ]);\nplot([0 45 45 0 0 ],[0 14.8571 89.1429 104 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32" " 23.32 14.65 8.65 ],[58.66 58.66 64.66 58.66 64.66 64.66 64.66 58.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.6" "5 14.65 ],[52.66 52.66 58.66 58.66 52.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[46.66 " "46.66 52.66 52.66 46.66 ],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[40.66 40.66 46.66 40.6" "6 46.66 46.66 40.66 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: b" "egin icon text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncol" "or('black');port_label('input',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: " "end icon text');" } Block { BlockType Reference Name "Radio 3 ADC I" SID "414" Ports [1, 1] Position [80, 274, 175, 316] LibraryVersion "1.48" LinkData { BlockName "radio3_adc_I" DialogParameters { sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.6" "5 ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[12.22 12.22" " 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.22 12.22 12.22" " 10.22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\n" "patch([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('inpu" "t',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT:" " end icon text');\n" } } SourceBlock "WARP_Blockset/WARP Radio Board ADC//DACs/Radio 3 ADC I" SourceType "" ShowPortLabels "FromPortIcon" SystemSampleTime "-1" FunctionWithSeparateData off RTWMemSecFuncInitTerm "Inherit from model" RTWMemSecFuncExecute "Inherit from model" RTWMemSecDataConstants "Inherit from model" RTWMemSecDataInternal "Inherit from model" RTWMemSecDataParameters "Inherit from model" GeneratePreprocessorConditionals off samp_period "1" } Block { BlockType Reference Name "Register" SID "415" Ports [1, 1] Position [405, 281, 440, 309] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "8.2" sg_icon_stat "35,28,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 28 28 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 28 28 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[18.44 " "18.44 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[14.44 14.44 18.44 1" "8.44 14.44 ],[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 " "]);\npatch([12.1 25.88 21.88 17.88 13.88 8.1 12.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Reinterpret" SID "416" Ports [1, 1] Position [625, 314, 675, 346] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can changed the signal b" "etween signed and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs no" "thing.

Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is force" "d to unsigned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an outp" "ut of 56 (111000 in binary)." force_arith_type on arith_type "Signed (2's comp)" force_bin_pt on bin_pt "13" has_advanced_control "0" sggui_pos "20,20,336,312" block_type "reinterpret" block_version "10.1.3" sg_icon_stat "50,32,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 32 32 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 32 32 0 ]);\npatch([16.1 21.88 25.88 29.88 33.88 25.88 20.1 16.1 ],[20.4" "4 20.44 24.44 20.44 24.44 24.44 24.44 20.44 ],[1 1 1 ]);\npatch([20.1 25.88 21.88 16.1 20.1 ],[16.44 16.44 20.4" "4 20.44 16.44 ],[0.931 0.946 0.973 ]);\npatch([16.1 21.88 25.88 20.1 16.1 ],[12.44 12.44 16.44 16.44 12.44 ],[1" " 1 1 ]);\npatch([20.1 33.88 29.88 25.88 21.88 16.1 20.1 ],[8.44 8.44 12.44 8.44 12.44 12.44 8.44 ],[0.931 0.946" " 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('blac" "k');disp('reinterpret');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Slice" SID "417" Ports [1, 1] Position [630, 120, 690, 150] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outp" "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

" "

Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,376" block_type "slice" block_version "10.1.3" sg_icon_stat "60,30,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 30 30 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\npatch([21.1 26.88 30.88 34.88 38.88 30.88 25.1 21.1 ],[19.4" "4 19.44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([25.1 30.88 26.88 21.1 25.1 ],[15.44 15.44 19.4" "4 19.44 15.44 ],[0.931 0.946 0.973 ]);\npatch([21.1 26.88 30.88 25.1 21.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1" " 1 1 ]);\npatch([25.1 38.88 34.88 30.88 26.88 21.1 25.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946" " 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black'" ");port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "radio3_ADC_I_OTR" SID "418" Ports [1, 1] Position [400, 94, 455, 106] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, double and fixed point to Xilinx" " fixed point type.

Hardware notes: In hardware these blocks become top level input ports." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off UseAsADC off ADCChannel "'1'" hdl_port "on" has_advanced_control "0" sggui_pos "20,20,356,432" block_type "gatewayin" block_version "VER_STRING_GOES_HERE" sg_icon_stat "55,12,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 12 12 0 ],[0.95 0" ".93 0.65 ]);\nplot([0 55 55 0 0 ],[0 0 12 12 0 ]);\npatch([24.775 26.22 27.22 28.22 29.22 27.22 25.775 24.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([25.775 27.22 26.22 24.775 25.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.985 0.979 0.895 ]);\npatch([24.775 26.22 27.22 25.775 24.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([25.775 29.22 28.22 27.22 26.22 24.775 25.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.985 0." "979 0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "OTR I" SID "419" Position [885, 93, 915, 107] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Outport Name "ADC I" SID "420" Position [885, 288, 915, 302] Port "2" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "Constant1" SrcPort 1 Points [20, 0] Branch { DstBlock "Radio 3 ADC I" DstPort 1 } Branch { Points [-10, 0] Branch { Points [0, -195] DstBlock "radio3_ADC_I_OTR" DstPort 1 } Branch { Points [0, 100] DstBlock "FromAGC_Radio3_I" DstPort 1 } } } Line { SrcBlock "Mux" SrcPort 1 DstBlock "OTR I" DstPort 1 } Line { SrcBlock "Debug" SrcPort 1 Points [40, 0; 0, 45] Branch { DstBlock "Mux" DstPort 1 } Branch { Points [0, 195] DstBlock "Mux1" DstPort 1 } } Line { SrcBlock "radio3_ADC_I_OTR" SrcPort 1 DstBlock "Mux" DstPort 2 } Line { SrcBlock "Slice" SrcPort 1 DstBlock "Mux" DstPort 3 } Line { SrcBlock "Mux1" SrcPort 1 DstBlock "ADC I" DstPort 1 } Line { SrcBlock "Register" SrcPort 1 DstBlock "Mux1" DstPort 2 } Line { SrcBlock "Reinterpret" SrcPort 1 DstBlock "Mux1" DstPort 3 } Line { SrcBlock "Counter" SrcPort 1 Points [25, 0] Branch { DstBlock "Reinterpret" DstPort 1 } Branch { Points [0, -195] DstBlock "Slice" DstPort 1 } } Line { SrcBlock "MGCAGC_AGCDCO_SEL" SrcPort 1 Points [70, 0; 0, 50] DstBlock "Mux2" DstPort 1 } Line { SrcBlock "FromAGC_Radio3_I" SrcPort 1 Points [50, 0; 0, -65] DstBlock "Mux2" DstPort 3 } Line { SrcBlock "Mux2" SrcPort 1 DstBlock "Register" DstPort 1 } Line { SrcBlock "Radio 3 ADC I" SrcPort 1 DstBlock "Mux2" DstPort 2 } } } Block { BlockType SubSystem Name "ADC Q" SID "421" Ports [2, 2] Position [410, 305, 565, 345] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "ADC Q" Location [2, 74, 1014, 726] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Debug" SID "422" Position [695, 13, 725, 27] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "MGCAGC_AGCDCO_SEL" SID "423" Position [165, 203, 195, 217] Port "2" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Constant Name "Constant1" SID "424" Position [15, 280, 45, 310] ShowName off Value "0" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Counter" SID "425" Ports [0, 1] Position [525, 300, 585, 360] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited co" "unter is implemented by combining a counter with a comparator." cnt_type "Free Running" cnt_to "Inf" operation "Up" start_count "0" cnt_by_val "1" arith_type "Unsigned" n_bits "14" bin_pt "0" load_pin off rst off en off explicit_period "on" period "1" dbl_ovrd off use_behavioral_HDL off implementation "Fabric" xl_use_area off xl_area "[0,0,0,0,0,0,0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,619" block_type "counter" block_version "10.1.3" sg_icon_stat "60,60,0,1,white,blue,0,7ac47ef5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 60 60 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 60 60 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[38.8" "8 38.88 46.88 38.88 46.88 46.88 46.88 38.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[30.88 30.88 38.8" "8 38.88 30.88 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[22.88 22.88 30.88 30.88 22.88 ],[1" " 1 1 ]);\npatch([20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[14.88 14.88 22.88 14.88 22.88 22.88 14.88 ],[0.931 0" ".946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('bl" "ack');disp('{\\fontsize{14}\\bf++}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "FromAGC_Radio3_Q" SID "426" Ports [1, 1] Position [150, 385, 215, 405] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, double and fixed point to Xilinx" " fixed point type.

Hardware notes: In hardware these blocks become top level input ports." gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "14" bin_pt "13" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off UseAsADC off ADCChannel "'1'" hdl_port "on" has_advanced_control "0" sggui_pos "20,20,348,406" block_type "gatewayin" block_version "10.1.3" sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0" ".93 0.65 ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[1" "2.22 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.2" "2 12.22 12.22 10.22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.2" "2 ],[1 1 1 ]);\npatch([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985" " 0.979 0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' " "');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux" SID "427" Ports [3, 1] Position [830, 48, 875, 152] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "1" bin_pt "0" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,303" block_type "mux" block_version "10.1.3" sg_icon_stat "45,104,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 14.8571 89.1429 104" " 0 ],[0.77 0.82 0.91 ]);\nplot([0 45 45 0 0 ],[0 14.8571 89.1429 104 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32" " 23.32 14.65 8.65 ],[58.66 58.66 64.66 58.66 64.66 64.66 64.66 58.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.6" "5 14.65 ],[52.66 52.66 58.66 58.66 52.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[46.66 " "46.66 52.66 52.66 46.66 ],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[40.66 40.66 46.66 40.6" "6 46.66 46.66 40.66 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: b" "egin icon text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncol" "or('black');port_label('input',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: " "end icon text');" } Block { BlockType Reference Name "Mux1" SID "428" Ports [3, 1] Position [830, 243, 875, 347] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "1" bin_pt "0" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,303" block_type "mux" block_version "10.1.3" sg_icon_stat "45,104,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 14.8571 89.1429 104" " 0 ],[0.77 0.82 0.91 ]);\nplot([0 45 45 0 0 ],[0 14.8571 89.1429 104 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32" " 23.32 14.65 8.65 ],[58.66 58.66 64.66 58.66 64.66 64.66 64.66 58.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.6" "5 14.65 ],[52.66 52.66 58.66 58.66 52.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[46.66 " "46.66 52.66 52.66 46.66 ],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[40.66 40.66 46.66 40.6" "6 46.66 46.66 40.66 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: b" "egin icon text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncol" "or('black');port_label('input',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: " "end icon text');" } Block { BlockType Reference Name "Mux2" SID "429" Ports [3, 1] Position [310, 243, 355, 347] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "1" bin_pt "0" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,303" block_type "mux" block_version "10.1.3" sg_icon_stat "45,104,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 14.8571 89.1429 104" " 0 ],[0.77 0.82 0.91 ]);\nplot([0 45 45 0 0 ],[0 14.8571 89.1429 104 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32" " 23.32 14.65 8.65 ],[58.66 58.66 64.66 58.66 64.66 64.66 64.66 58.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.6" "5 14.65 ],[52.66 52.66 58.66 58.66 52.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[46.66 " "46.66 52.66 52.66 46.66 ],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[40.66 40.66 46.66 40.6" "6 46.66 46.66 40.66 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: b" "egin icon text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncol" "or('black');port_label('input',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: " "end icon text');" } Block { BlockType Reference Name "Radio 3 ADC Q" SID "430" Ports [1, 1] Position [85, 274, 180, 316] LibraryVersion "1.48" LinkData { BlockName "radio3_adc_Q" DialogParameters { sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.6" "5 ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[12.22 12.22" " 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.22 12.22 12.22" " 10.22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\n" "patch([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('inpu" "t',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT:" " end icon text');\n" } } SourceBlock "WARP_Blockset/WARP Radio Board ADC//DACs/Radio 3 ADC Q" SourceType "" ShowPortLabels "FromPortIcon" SystemSampleTime "-1" FunctionWithSeparateData off RTWMemSecFuncInitTerm "Inherit from model" RTWMemSecFuncExecute "Inherit from model" RTWMemSecDataConstants "Inherit from model" RTWMemSecDataInternal "Inherit from model" RTWMemSecDataParameters "Inherit from model" GeneratePreprocessorConditionals off samp_period "1" } Block { BlockType Reference Name "Register" SID "431" Ports [1, 1] Position [455, 281, 490, 309] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "8.2" sg_icon_stat "35,28,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 28 28 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 28 28 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[18.44 " "18.44 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[14.44 14.44 18.44 1" "8.44 14.44 ],[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 " "]);\npatch([12.1 25.88 21.88 17.88 13.88 8.1 12.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Reinterpret" SID "432" Ports [1, 1] Position [675, 314, 725, 346] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can changed the signal b" "etween signed and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs no" "thing.

Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is force" "d to unsigned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an outp" "ut of 56 (111000 in binary)." force_arith_type on arith_type "Signed (2's comp)" force_bin_pt on bin_pt "13" has_advanced_control "0" sggui_pos "20,20,336,312" block_type "reinterpret" block_version "10.1.3" sg_icon_stat "50,32,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 32 32 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 32 32 0 ]);\npatch([16.1 21.88 25.88 29.88 33.88 25.88 20.1 16.1 ],[20.4" "4 20.44 24.44 20.44 24.44 24.44 24.44 20.44 ],[1 1 1 ]);\npatch([20.1 25.88 21.88 16.1 20.1 ],[16.44 16.44 20.4" "4 20.44 16.44 ],[0.931 0.946 0.973 ]);\npatch([16.1 21.88 25.88 20.1 16.1 ],[12.44 12.44 16.44 16.44 12.44 ],[1" " 1 1 ]);\npatch([20.1 33.88 29.88 25.88 21.88 16.1 20.1 ],[8.44 8.44 12.44 8.44 12.44 12.44 8.44 ],[0.931 0.946" " 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('blac" "k');disp('reinterpret');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Slice" SID "433" Ports [1, 1] Position [680, 120, 740, 150] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outp" "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

" "

Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,376" block_type "slice" block_version "10.1.3" sg_icon_stat "60,30,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 30 30 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\npatch([21.1 26.88 30.88 34.88 38.88 30.88 25.1 21.1 ],[19.4" "4 19.44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([25.1 30.88 26.88 21.1 25.1 ],[15.44 15.44 19.4" "4 19.44 15.44 ],[0.931 0.946 0.973 ]);\npatch([21.1 26.88 30.88 25.1 21.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1" " 1 1 ]);\npatch([25.1 38.88 34.88 30.88 26.88 21.1 25.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946" " 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black'" ");port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "radio3_ADC_Q_OTR" SID "434" Ports [1, 1] Position [115, 94, 170, 106] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, double and fixed point to Xilinx" " fixed point type.

Hardware notes: In hardware these blocks become top level input ports." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off UseAsADC off ADCChannel "'1'" hdl_port "on" has_advanced_control "0" sggui_pos "20,20,356,432" block_type "gatewayin" block_version "VER_STRING_GOES_HERE" sg_icon_stat "55,12,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 12 12 0 ],[0.95 0" ".93 0.65 ]);\nplot([0 55 55 0 0 ],[0 0 12 12 0 ]);\npatch([24.775 26.22 27.22 28.22 29.22 27.22 25.775 24.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([25.775 27.22 26.22 24.775 25.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.985 0.979 0.895 ]);\npatch([24.775 26.22 27.22 25.775 24.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([25.775 29.22 28.22 27.22 26.22 24.775 25.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.985 0." "979 0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "OTR Q" SID "435" Position [975, 93, 1005, 107] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Outport Name "ADC Q" SID "436" Position [970, 288, 1000, 302] Port "2" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "Constant1" SrcPort 1 Points [10, 0] Branch { Points [0, -195] DstBlock "radio3_ADC_Q_OTR" DstPort 1 } Branch { Points [0, 100] DstBlock "FromAGC_Radio3_Q" DstPort 1 } Branch { DstBlock "Radio 3 ADC Q" DstPort 1 } } Line { SrcBlock "Mux" SrcPort 1 DstBlock "OTR Q" DstPort 1 } Line { SrcBlock "Debug" SrcPort 1 Points [40, 0; 0, 45] Branch { DstBlock "Mux" DstPort 1 } Branch { Points [0, 195] DstBlock "Mux1" DstPort 1 } } Line { SrcBlock "radio3_ADC_Q_OTR" SrcPort 1 DstBlock "Mux" DstPort 2 } Line { SrcBlock "Slice" SrcPort 1 DstBlock "Mux" DstPort 3 } Line { SrcBlock "Mux1" SrcPort 1 DstBlock "ADC Q" DstPort 1 } Line { SrcBlock "Register" SrcPort 1 DstBlock "Mux1" DstPort 2 } Line { SrcBlock "Reinterpret" SrcPort 1 DstBlock "Mux1" DstPort 3 } Line { SrcBlock "Counter" SrcPort 1 Points [30, 0] Branch { DstBlock "Reinterpret" DstPort 1 } Branch { Points [0, -195] DstBlock "Slice" DstPort 1 } } Line { SrcBlock "MGCAGC_AGCDCO_SEL" SrcPort 1 Points [70, 0; 0, 50] DstBlock "Mux2" DstPort 1 } Line { SrcBlock "FromAGC_Radio3_Q" SrcPort 1 Points [50, 0; 0, -65] DstBlock "Mux2" DstPort 3 } Line { SrcBlock "Radio 3 ADC Q" SrcPort 1 DstBlock "Mux2" DstPort 2 } Line { SrcBlock "Mux2" SrcPort 1 DstBlock "Register" DstPort 1 } } } Block { BlockType SubSystem Name "Concatenates_1" SID "437" Ports [4, 1] Position [695, 218, 740, 372] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "Concatenates_1" Location [2, 74, 1270, 726] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "OTR_I" SID "438" Position [395, 43, 425, 57] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "ADC_I" SID "439" Position [330, 93, 360, 107] Port "2" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "OTR_Q" SID "440" Position [390, 163, 420, 177] Port "3" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "ADC_Q" SID "441" Position [330, 213, 360, 227] Port "4" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Concat1" SID "442" Ports [2, 1] Position [490, 191, 520, 229] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary poi" "nt at zero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" block_version "8.2" sg_icon_stat "30,38,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 38 38 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 38 38 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[23.44 " "23.44 27.44 23.44 27.44 27.44 27.44 23.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[19.44 19.44 23.44 2" "3.44 19.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[15.44 15.44 19.44 19.44 15.44 ],[1 1 1 " "]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[11.44 11.44 15.44 11.44 15.44 15.44 11.44 ],[0.931 0.946 0" ".973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');po" "rt_label('input',1,'hi');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\fontsize{20}\\}" "','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Concat2" SID "443" Ports [2, 1] Position [490, 71, 520, 109] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary poi" "nt at zero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" block_version "8.2" sg_icon_stat "30,38,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 38 38 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 38 38 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[23.44 " "23.44 27.44 23.44 27.44 27.44 27.44 23.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[19.44 19.44 23.44 2" "3.44 19.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[15.44 15.44 19.44 19.44 15.44 ],[1 1 1 " "]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[11.44 11.44 15.44 11.44 15.44 15.44 11.44 ],[0.931 0.946 0" ".973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');po" "rt_label('input',1,'hi');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\fontsize{20}\\}" "','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Concat3" SID "444" Ports [2, 1] Position [550, 150, 575, 230] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary poi" "nt at zero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" block_version "8.2" sg_icon_stat "25,80,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 80 80 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 80 80 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[43" ".33 43.33 46.33 43.33 46.33 46.33 46.33 43.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[40.33 40.33 " "43.33 43.33 40.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[37.33 37.33 40.33 40.33 37.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[34.33 34.33 37.33 34.33 37.33 37.33 34.33 ]," "[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncol" "or('black');port_label('input',1,'hi');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\f" "ontsize{20}\\}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Concat4" SID "445" Ports [2, 1] Position [550, 30, 575, 110] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary poi" "nt at zero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" block_version "8.2" sg_icon_stat "25,80,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 80 80 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 80 80 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[43" ".33 43.33 46.33 43.33 46.33 46.33 46.33 43.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[40.33 40.33 " "43.33 43.33 40.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[37.33 37.33 40.33 40.33 37.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[34.33 34.33 37.33 34.33 37.33 37.33 34.33 ]," "[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncol" "or('black');port_label('input',1,'hi');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\f" "ontsize{20}\\}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Concat5" SID "446" Ports [2, 1] Position [635, 50, 660, 130] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary poi" "nt at zero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" block_version "8.2" sg_icon_stat "25,80,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 80 80 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 80 80 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[43" ".33 43.33 46.33 43.33 46.33 46.33 46.33 43.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[40.33 40.33 " "43.33 43.33 40.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[37.33 37.33 40.33 40.33 37.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[34.33 34.33 37.33 34.33 37.33 37.33 34.33 ]," "[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncol" "or('black');port_label('input',1,'hi');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\f" "ontsize{20}\\}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Reinterpret" SID "447" Ports [1, 1] Position [385, 90, 420, 110] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can changed the signal b" "etween signed and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs no" "thing.

Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is force" "d to unsigned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an outp" "ut of 56 (111000 in binary)." force_arith_type on arith_type "Unsigned" force_bin_pt on bin_pt "0" has_advanced_control "0" sggui_pos "20,20,356,309" block_type "reinterpret" block_version "8.2" sg_icon_stat "35,20,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 20 20 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 20 20 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[1" "2.22 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[10.22 10.2" "2 12.22 12.22 10.22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[8.22 8.22 10.22 10.22 8.2" "2 ],[1 1 1 ]);\npatch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931" " 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor" "('black');disp('reinterpret');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Reinterpret1" SID "448" Ports [1, 1] Position [390, 210, 425, 230] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can changed the signal b" "etween signed and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs no" "thing.

Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is force" "d to unsigned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an outp" "ut of 56 (111000 in binary)." force_arith_type on arith_type "Unsigned" force_bin_pt on bin_pt "0" has_advanced_control "0" sggui_pos "20,20,356,309" block_type "reinterpret" block_version "8.2" sg_icon_stat "35,20,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 20 20 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 20 20 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[1" "2.22 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[10.22 10.2" "2 12.22 12.22 10.22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[8.22 8.22 10.22 10.22 8.2" "2 ],[1 1 1 ]);\npatch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931" " 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor" "('black');disp('reinterpret');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "zero" SID "449" Ports [0, 1] Position [440, 191, 460, 209] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "20,18,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 20 20 0 0 ],[0 0 18 18 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[9.22 9.22 11.22 11" ".22 9.22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\np" "atch([7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfpr" "intf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('out" "put',1,'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "zero1" SID "450" Ports [0, 1] Position [440, 71, 460, 89] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "20,18,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 20 20 0 0 ],[0 0 18 18 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[9.22 9.22 11.22 11" ".22 9.22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\np" "atch([7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfpr" "intf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('out" "put',1,'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "32b" SID "451" Position [840, 83, 870, 97] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "Reinterpret1" SrcPort 1 DstBlock "Concat1" DstPort 2 } Line { SrcBlock "Reinterpret" SrcPort 1 DstBlock "Concat2" DstPort 2 } Line { SrcBlock "ADC_Q" SrcPort 1 DstBlock "Reinterpret1" DstPort 1 } Line { SrcBlock "OTR_Q" SrcPort 1 DstBlock "Concat3" DstPort 1 } Line { SrcBlock "ADC_I" SrcPort 1 DstBlock "Reinterpret" DstPort 1 } Line { SrcBlock "Concat5" SrcPort 1 DstBlock "32b" DstPort 1 } Line { SrcBlock "OTR_I" SrcPort 1 DstBlock "Concat4" DstPort 1 } Line { SrcBlock "Concat3" SrcPort 1 Points [25, 0; 0, -80] DstBlock "Concat5" DstPort 2 } Line { SrcBlock "Concat4" SrcPort 1 DstBlock "Concat5" DstPort 1 } Line { SrcBlock "Concat2" SrcPort 1 Points [0, 0] DstBlock "Concat4" DstPort 2 } Line { SrcBlock "zero1" SrcPort 1 DstBlock "Concat2" DstPort 1 } Line { SrcBlock "Concat1" SrcPort 1 DstBlock "Concat3" DstPort 2 } Line { SrcBlock "zero" SrcPort 1 DstBlock "Concat1" DstPort 1 } } } Block { BlockType Reference Name "Gateway Out1" SID "452" Ports [1, 1] Position [725, 135, 755, 145] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, double, o" "r fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarded, depen" "ding on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" UseAsDAC off DACChannel "'1'" has_advanced_control "0" sggui_pos "20,20,336,386" block_type "gatewayout" block_version "10.1.2" sg_icon_stat "30,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 10 10 0 ],[0.88 0.88 0.88" " ]);\nplot([0 30 30 0 0 ],[0 0 10 10 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ],[6.11 6.11 " "7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[5.11 5.11 6.11 6.11 5.11 ],[" "0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]);\npatch([13." "775 17.22 16.22 15.22 14.22 12.775 13.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.964 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ')" ";\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" } Block { BlockType Reference Name "Gateway Out4" SID "453" Ports [1, 1] Position [725, 120, 755, 130] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, double, o" "r fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarded, depen" "ding on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" UseAsDAC off DACChannel "'1'" has_advanced_control "0" sggui_pos "20,20,336,386" block_type "gatewayout" block_version "10.1.2" sg_icon_stat "30,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 10 10 0 ],[0.88 0.88 0.88" " ]);\nplot([0 30 30 0 0 ],[0 0 10 10 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ],[6.11 6.11 " "7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[5.11 5.11 6.11 6.11 5.11 ],[" "0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]);\npatch([13." "775 17.22 16.22 15.22 14.22 12.775 13.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.964 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ')" ";\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" } Block { BlockType SubSystem Name "RSSI" SID "454" Ports [1, 1] Position [495, 397, 565, 433] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "RSSI" Location [2, 74, 1184, 726] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Debug" SID "455" Position [465, 28, 495, 42] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Constant Name "Constant1" SID "456" Position [160, 100, 190, 130] ShowName off Value "0" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Counter" SID "457" Ports [0, 1] Position [380, 120, 440, 180] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited co" "unter is implemented by combining a counter with a comparator." cnt_type "Free Running" cnt_to "Inf" operation "Up" start_count "0" cnt_by_val "1" arith_type "Unsigned" n_bits "10" bin_pt "0" load_pin off rst off en off explicit_period "on" period "1" dbl_ovrd off use_behavioral_HDL off implementation "Fabric" xl_use_area off xl_area "[0,0,0,0,0,0,0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,619" block_type "counter" block_version "10.1.3" sg_icon_stat "60,60,0,1,white,blue,0,7ac47ef5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 60 60 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 60 60 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[38.8" "8 38.88 46.88 38.88 46.88 46.88 46.88 38.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[30.88 30.88 38.8" "8 38.88 30.88 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[22.88 22.88 30.88 30.88 22.88 ],[1" " 1 1 ]);\npatch([20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[14.88 14.88 22.88 14.88 22.88 22.88 14.88 ],[0.931 0" ".946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('bl" "ack');disp('{\\fontsize{14}\\bf++}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux" SID "458" Ports [3, 1] Position [600, 63, 645, 167] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "1" bin_pt "0" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,303" block_type "mux" block_version "10.1.3" sg_icon_stat "45,104,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 14.8571 89.1429 104" " 0 ],[0.77 0.82 0.91 ]);\nplot([0 45 45 0 0 ],[0 14.8571 89.1429 104 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32" " 23.32 14.65 8.65 ],[58.66 58.66 64.66 58.66 64.66 64.66 64.66 58.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.6" "5 14.65 ],[52.66 52.66 58.66 58.66 52.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[46.66 " "46.66 52.66 52.66 46.66 ],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[40.66 40.66 46.66 40.6" "6 46.66 46.66 40.66 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: b" "egin icon text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncol" "or('black');port_label('input',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: " "end icon text');" } Block { BlockType Reference Name "radio3_RSSI" SID "459" Ports [1, 1] Position [280, 109, 335, 121] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, double and fixed point to Xilinx" " fixed point type.

Hardware notes: In hardware these blocks become top level input ports." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "10" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Truncate" overflow "Wrap" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off UseAsADC off ADCChannel "'1'" hdl_port "on" has_advanced_control "0" sggui_pos "20,20,356,432" block_type "gatewayin" block_version "VER_STRING_GOES_HERE" sg_icon_stat "55,12,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 12 12 0 ],[0.95 0" ".93 0.65 ]);\nplot([0 55 55 0 0 ],[0 0 12 12 0 ]);\npatch([24.775 26.22 27.22 28.22 29.22 27.22 25.775 24.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([25.775 27.22 26.22 24.775 25.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.985 0.979 0.895 ]);\npatch([24.775 26.22 27.22 25.775 24.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([25.775 29.22 28.22 27.22 26.22 24.775 25.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.985 0." "979 0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "RSSI" SID "460" Position [740, 108, 770, 122] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "radio3_RSSI" DstPort 1 } Line { SrcBlock "Debug" SrcPort 1 Points [40, 0; 0, 45] DstBlock "Mux" DstPort 1 } Line { SrcBlock "radio3_RSSI" SrcPort 1 DstBlock "Mux" DstPort 2 } Line { SrcBlock "Counter" SrcPort 1 DstBlock "Mux" DstPort 3 } Line { SrcBlock "Mux" SrcPort 1 DstBlock "RSSI" DstPort 1 } } } Block { BlockType Scope Name "Scope" SID "461" Ports [2] Position [800, 111, 830, 164] Floating off Location [5, 34, 1285, 912] Open off NumInputPorts "2" List { ListType AxesTitles axes1 "%" axes2 "%" } YMin "-5~-5" YMax "5~5" DataFormat "StructureWithTime" SampleTime "0" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Outport Name "Radio 3 RSSI" SID "462" Position [645, 408, 675, 422] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Outport Name "Radio 3 I/Q" SID "463" Position [865, 288, 895, 302] Port "2" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "ADC Q" SrcPort 2 Points [65, 0; 0, 20; 30, 0] Branch { DstBlock "Concatenates_1" DstPort 4 } Branch { Points [0, -215] DstBlock "Gateway Out1" DstPort 1 } } Line { SrcBlock "ADC Q" SrcPort 1 DstBlock "Concatenates_1" DstPort 3 } Line { SrcBlock "ADC I" SrcPort 2 Points [85, 0] Branch { DstBlock "Concatenates_1" DstPort 2 } Branch { Points [0, -150] DstBlock "Gateway Out4" DstPort 1 } } Line { SrcBlock "ADC I" SrcPort 1 Points [0, -20] DstBlock "Concatenates_1" DstPort 1 } Line { SrcBlock "Concatenates_1" SrcPort 1 Points [0, 0] DstBlock "Radio 3 I/Q" DstPort 1 } Line { SrcBlock "Gateway Out4" SrcPort 1 DstBlock "Scope" DstPort 1 } Line { SrcBlock "Gateway Out1" SrcPort 1 Points [25, 0] DstBlock "Scope" DstPort 2 } Line { SrcBlock "DebugRxBuffers" SrcPort 1 Points [145, 0] Branch { DstBlock "ADC I" DstPort 1 } Branch { Points [0, 60] Branch { DstBlock "ADC Q" DstPort 1 } Branch { Points [0, 100] DstBlock "RSSI" DstPort 1 } } } Line { SrcBlock "RSSI" SrcPort 1 DstBlock "Radio 3 RSSI" DstPort 1 } Line { SrcBlock "MGCAGC_AGCDCO_SEL" SrcPort 1 Points [95, 0] Branch { DstBlock "ADC Q" DstPort 2 } Branch { Points [0, -60] DstBlock "ADC I" DstPort 2 } } Annotation { Position [518, 257] } } } Block { BlockType SubSystem Name "Radio 3 Outputs" SID "464" Ports [1] Position [1180, 858, 1225, 902] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "Radio 3 Outputs" Location [60, 247, 880, 529] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "32b" SID "465" Position [145, 148, 175, 162] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "16LSB" SID "466" Ports [1, 1] Position [305, 147, 340, 163] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type " "is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardware " "notes: In hardware this block costs nothing." nbits "16" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "593,46,442,407" block_type "slice" block_version "9.1.01" sg_icon_stat "35,16,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 16 16 0 ],[0.77 0.82 0.91" " ]);\nplot([0 35 35 0 0 ],[0 0 16 16 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[10.22 10.22 1" "2.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[8.22 8.22 10.22 10.22 8.22" " ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatch([14" ".55 21.44 19.44 17.44 15.44 12.55 14.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprintf(''," "'COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'[a" ":b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "16MSB" SID "467" Ports [1, 1] Position [305, 82, 345, 98] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type " "is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardware " "notes: In hardware this block costs nothing." nbits "16" boolean_output off mode "Upper Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "593,46,442,407" block_type "slice" block_version "9.1.01" sg_icon_stat "40,16,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 16 16 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 16 16 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[10.22 10.22 1" "2.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[8.22 8.22 10.22 10.22 8.22" " ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatch([17" ".55 24.44 22.44 20.44 18.44 15.55 17.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprintf(''," "'COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'[a" ":b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Radio 3 DAC I" SID "468" Ports [1, 1] Position [560, 69, 655, 111] LibraryVersion "1.48" LinkData { BlockName "Convert" DialogParameters { sg_icon_stat "45,30,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 30 30 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\npatch([13.1 18.88 22.88 26.88 30.88 22.88 17.1 13.1 ],[19.4" "4 19.44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([17.1 22.88 18.88 13.1 17.1 ],[15.44 15.44 19.4" "4 19.44 15.44 ],[0.931 0.946 0.973 ]);\npatch([13.1 18.88 22.88 17.1 13.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1" " 1 1 ]);\npatch([17.1 30.88 26.88 22.88 18.88 13.1 17.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946" " 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black'" ");port_label('output',1,'cast');\nfprintf('','COMMENT: end icon text');" } BlockName "radio3_dac_I" DialogParameters { sg_icon_stat "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0" ".93 0.65 ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[1" "2.22 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.2" "2 12.22 12.22 10.22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.2" "2 ],[1 1 1 ]);\npatch([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985" " 0.979 0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','o" "n');\nfprintf('','COMMENT: end icon text');" } } SourceBlock "WARP_Blockset/WARP Radio Board ADC//DACs/Radio 3 DAC I" SourceType "" ShowPortLabels "FromPortIcon" SystemSampleTime "-1" FunctionWithSeparateData off RTWMemSecFuncInitTerm "Inherit from model" RTWMemSecFuncExecute "Inherit from model" RTWMemSecDataConstants "Inherit from model" RTWMemSecDataInternal "Inherit from model" RTWMemSecDataParameters "Inherit from model" GeneratePreprocessorConditionals off } Block { BlockType Reference Name "Radio 3 DAC Q" SID "469" Ports [1, 1] Position [560, 134, 655, 176] LibraryVersion "1.48" LinkData { BlockName "Convert" DialogParameters { sg_icon_stat "45,30,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 30 30 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\npatch([13.1 18.88 22.88 26.88 30.88 22.88 17.1 13.1 ],[19.4" "4 19.44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([17.1 22.88 18.88 13.1 17.1 ],[15.44 15.44 19.4" "4 19.44 15.44 ],[0.931 0.946 0.973 ]);\npatch([13.1 18.88 22.88 17.1 13.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1" " 1 1 ]);\npatch([17.1 30.88 26.88 22.88 18.88 13.1 17.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946" " 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black'" ");port_label('output',1,'cast');\nfprintf('','COMMENT: end icon text');" } BlockName "radio3_dac_Q" DialogParameters { sg_icon_stat "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0" ".93 0.65 ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[1" "2.22 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.2" "2 12.22 12.22 10.22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.2" "2 ],[1 1 1 ]);\npatch([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985" " 0.979 0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','o" "n');\nfprintf('','COMMENT: end icon text');" } } SourceBlock "WARP_Blockset/WARP Radio Board ADC//DACs/Radio 3 DAC Q" SourceType "" ShowPortLabels "FromPortIcon" SystemSampleTime "-1" FunctionWithSeparateData off RTWMemSecFuncInitTerm "Inherit from model" RTWMemSecFuncExecute "Inherit from model" RTWMemSecDataConstants "Inherit from model" RTWMemSecDataInternal "Inherit from model" RTWMemSecDataParameters "Inherit from model" GeneratePreprocessorConditionals off } Block { BlockType Reference Name "Register" SID "470" Ports [1, 1] Position [475, 79, 520, 101] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "568,185,356,193" block_type "register" block_version "9.1.01" sg_icon_stat "45,22,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 22 22 0 ],[0.77 0.82 0.91" " ]);\nplot([0 45 45 0 0 ],[0 0 22 22 0 ]);\npatch([15.325 19.66 22.66 25.66 28.66 22.66 18.325 15.325 ],[14.33 14.3" "3 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([18.325 22.66 19.66 15.325 18.325 ],[11.33 11.33 14.33 14" ".33 11.33 ],[0.931 0.946 0.973 ]);\npatch([15.325 19.66 22.66 18.325 15.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 1 1 " "]);\npatch([18.325 28.66 25.66 22.66 19.66 15.325 18.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label" "('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprint" "f('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "471" Ports [1, 1] Position [475, 144, 520, 166] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "568,185,356,193" block_type "register" block_version "9.1.01" sg_icon_stat "45,22,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 22 22 0 ],[0.77 0.82 0.91" " ]);\nplot([0 45 45 0 0 ],[0 0 22 22 0 ]);\npatch([15.325 19.66 22.66 25.66 28.66 22.66 18.325 15.325 ],[14.33 14.3" "3 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([18.325 22.66 19.66 15.325 18.325 ],[11.33 11.33 14.33 14" ".33 11.33 ],[0.931 0.946 0.973 ]);\npatch([15.325 19.66 22.66 18.325 15.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 1 1 " "]);\npatch([18.325 28.66 25.66 22.66 19.66 15.325 18.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label" "('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprint" "f('','COMMENT: end icon text');" } Block { BlockType Reference Name "Reinterpret" SID "472" Ports [1, 1] Position [380, 81, 440, 99] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can changed the signal between s" "igned and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothing.

" "Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsigned wi" "th 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111000 in " "binary)." force_arith_type on arith_type "Signed (2's comp)" force_bin_pt on bin_pt "15" has_advanced_control "0" sggui_pos "436,54,356,309" block_type "reinterpret" block_version "9.1.01" sg_icon_stat "60,18,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.91" " ]);\nplot([0 60 60 0 0 ],[0 0 18 18 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[11.22 11.22 1" "3.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[9.22 9.22 11.22 11.22 9.22" " ],[0.931 0.946 0.973 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([27" ".55 34.44 32.44 30.44 28.44 25.55 27.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf(''," "'COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('reinterpret');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Reinterpret1" SID "473" Ports [1, 1] Position [380, 146, 440, 164] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can changed the signal between s" "igned and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothing.

" "Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsigned wi" "th 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111000 in " "binary)." force_arith_type on arith_type "Signed (2's comp)" force_bin_pt on bin_pt "15" has_advanced_control "0" sggui_pos "436,54,356,309" block_type "reinterpret" block_version "9.1.01" sg_icon_stat "60,18,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.91" " ]);\nplot([0 60 60 0 0 ],[0 0 18 18 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[11.22 11.22 1" "3.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[9.22 9.22 11.22 11.22 9.22" " ],[0.931 0.946 0.973 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([27" ".55 34.44 32.44 30.44 28.44 25.55 27.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf(''," "'COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('reinterpret');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Terminator Name "Terminator" SID "474" Position [680, 80, 700, 100] ShowName off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Terminator Name "Terminator1" SID "475" Position [685, 145, 705, 165] ShowName off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "32b" SrcPort 1 Points [85, 0] Branch { DstBlock "16LSB" DstPort 1 } Branch { Points [0, -65] DstBlock "16MSB" DstPort 1 } } Line { SrcBlock "16MSB" SrcPort 1 DstBlock "Reinterpret" DstPort 1 } Line { SrcBlock "16LSB" SrcPort 1 DstBlock "Reinterpret1" DstPort 1 } Line { SrcBlock "Reinterpret" SrcPort 1 DstBlock "Register" DstPort 1 } Line { SrcBlock "Reinterpret1" SrcPort 1 DstBlock "Register1" DstPort 1 } Line { SrcBlock "Register" SrcPort 1 DstBlock "Radio 3 DAC I" DstPort 1 } Line { SrcBlock "Register1" SrcPort 1 DstBlock "Radio 3 DAC Q" DstPort 1 } Line { SrcBlock "Radio 3 DAC I" SrcPort 1 DstBlock "Terminator" DstPort 1 } Line { SrcBlock "Radio 3 DAC Q" SrcPort 1 DstBlock "Terminator1" DstPort 1 } } } Block { BlockType SubSystem Name "Radio 4\nRx Buffers" SID "476" Ports [5] Position [1175, 465, 1240, 565] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "Radio 4\nRx Buffers" Location [2, 74, 1270, 726] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "RSSI" SID "477" Position [450, 313, 480, 327] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "I/Q" SID "478" Position [545, 163, 575, 177] Port "2" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "Addr" SID "479" Position [325, 128, 355, 142] Port "3" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "WE" SID "480" Position [110, 183, 140, 197] Port "4" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "EN" SID "481" Position [110, 213, 140, 227] Port "5" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Convert1" SID "482" Ports [1, 1] Position [185, 212, 210, 228] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "16" bin_pt "14" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,374,375" block_type "convert" block_version "8.2" sg_icon_stat "25,16,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 16 16 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 16 16 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[10.22 10.22 12.2" "2 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[8.22 8.22 10.22 10.22 8.22 ],[0." "931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatch([9.55 16.44 " "14.44 12.44 10.44 7.55 9.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: en" "d icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'cast');\nfprin" "tf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out" SID "483" Ports [1, 1] Position [500, 30, 530, 40] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, double, o" "r fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarded, depen" "ding on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" UseAsDAC off DACChannel "'1'" has_advanced_control "0" sggui_pos "20,20,336,386" block_type "gatewayout" block_version "10.1.2" sg_icon_stat "30,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 10 10 0 ],[0.88 0.88 0.88" " ]);\nplot([0 30 30 0 0 ],[0 0 10 10 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ],[6.11 6.11 " "7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[5.11 5.11 6.11 6.11 5.11 ],[" "0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]);\npatch([13." "775 17.22 16.22 15.22 14.22 12.775 13.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.964 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ')" ";\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" } Block { BlockType Reference Name "Gateway Out1" SID "484" Ports [1, 1] Position [500, 70, 530, 80] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, double, o" "r fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarded, depen" "ding on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" UseAsDAC off DACChannel "'1'" has_advanced_control "0" sggui_pos "20,20,336,386" block_type "gatewayout" block_version "10.1.2" sg_icon_stat "30,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 10 10 0 ],[0.88 0.88 0.88" " ]);\nplot([0 30 30 0 0 ],[0 0 10 10 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ],[6.11 6.11 " "7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[5.11 5.11 6.11 6.11 5.11 ],[" "0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]);\npatch([13." "775 17.22 16.22 15.22 14.22 12.775 13.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.964 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ')" ";\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" } Block { BlockType Reference Name "Logical" SID "485" Ports [2, 1] Position [255, 175, 310, 235] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "9.1.01" sg_icon_stat "55,60,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 60 60 0 ],[0.77 0.82 0.91" " ]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ],[37.77 37.7" "7 44.77 37.77 44.77 44.77 44.77 37.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[30.77 30.77 37.77 37" ".77 30.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[23.77 23.77 30.77 30.77 23.77 ],[1 1" " 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[16.77 16.77 23.77 16.77 23.77 23.77 16.77 ],[0.931 0" ".946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('bl" "ack');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "Radio 4\nRSSI Buffer" SID "486" Ports [3] Position [650, 264, 705, 376] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "Radio 4\nRSSI Buffer" Location [2, 70, 1918, 1150] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Addr_14b" SID "487" Position [325, 348, 355, 362] NamePlacement "alternate" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "RSSI" SID "488" Position [95, 383, 125, 397] Port "2" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "WE" SID "489" Position [720, 478, 750, 492] Port "3" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "11MSB" SID "490" Ports [1, 1] Position [430, 346, 470, 364] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outp" "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

" "

Hardware notes: In hardware this block costs nothing." nbits "11" boolean_output off mode "Upper Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,407" block_type "slice" block_version "8.2" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[1" "1.22 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 " "11.22 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[" "1 1 1 ]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black" "');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "BIT[2]" SID "491" Ports [1, 1] Position [430, 401, 470, 419] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outp" "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

" "

Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output on mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "2" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,407" block_type "slice" block_version "8.2" sg_icon_stat "40,18,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 18 18 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[1" "1.22 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[9.22 9.22 " "11.22 11.22 9.22 ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[7.22 7.22 9.22 9.22 7.22 ],[" "1 1 1 ]);\npatch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black" "');port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Concat" SID "492" Ports [2, 1] Position [685, 381, 725, 459] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary poi" "nt at zero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" block_version "10.1.2" sg_icon_stat "40,78,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 78 78 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 78 78 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[44.55" " 44.55 49.55 44.55 49.55 49.55 49.55 44.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[39.55 39.55 44" ".55 44.55 39.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[34.55 34.55 39.55 39.55 34.55 " "],[1 1 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[29.55 29.55 34.55 29.55 34.55 34.55 29.55 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor(" "'black');port_label('input',1,'hi');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\font" "size{20}\\}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert" SID "493" Ports [1, 1] Position [285, 382, 320, 398] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do" " not." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "16" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,461,375" block_type "convert" block_version "8.2" sg_icon_stat "35,16,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 16 16 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 16 16 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[1" "0.22 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[8.22 8.22 " "10.22 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[6.22 6.22 8.22 8.22 6.22 ],[" "1 1 1 ]);\npatch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black" "');port_label('output',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "494" Ports [1, 1] Position [510, 402, 540, 418] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,251" block_type "inv" block_version "10.1.2" sg_icon_stat "30,16,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 16 16 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 16 16 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[1" "0.22 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[8.22 8.22 " "10.22 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[6.22 6.22 8.22 8.22 6.22 ],[" "1 1 1 ]);\npatch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('bla" "ck');disp('not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register" SID "495" Ports [2, 1] Position [580, 378, 625, 422] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "register" block_version "10.1.2" sg_icon_stat "45,44,2,1,white,blue,0,6bd0930c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 44 44 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 44 44 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[28." "66 28.66 34.66 28.66 34.66 34.66 34.66 28.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[22.66 22.66 2" "8.66 28.66 22.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[16.66 16.66 22.66 22.66 16.66 " "],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[10.66 10.66 16.66 10.66 16.66 16.66 10.66 ],[0" ".931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor" "('black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'en');\ncolor('black');port_label('ou" "tput',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Reinterpret1" SID "496" Ports [1, 1] Position [180, 382, 215, 398] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can changed the signal b" "etween signed and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs no" "thing.

Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is force" "d to unsigned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an outp" "ut of 56 (111000 in binary)." force_arith_type on arith_type "Unsigned" force_bin_pt on bin_pt "0" has_advanced_control "0" sggui_pos "436,54,356,312" block_type "reinterpret" block_version "9.1.01" sg_icon_stat "35,16,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 16 16 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 16 16 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[1" "0.22 10.22 12.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[8.22 8.22 " "10.22 10.22 8.22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[6.22 6.22 8.22 8.22 6.22 ],[" "1 1 1 ]);\npatch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.94" "6 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('bla" "ck');disp('reinterpret');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Shared Memory" SID "497" Ports [3, 1] Position [800, 323, 880, 517] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Shared Memory" SourceType "Xilinx Shared Memory Random Access Memory Block" shared_memory_name "'RSSIBuff_Radio4'" depth "2^11" ownership "Locally Owned and Initialized" initVector "0" en off mutex "Unprotected" mode "Read and Write" write_mode "Read After Write" time_out "0" latency "1" explicit_data_type on gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" xl_use_area off xl_area "[0,0,0,0,0,0,0]" implementation "Block RAM" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,384,381" block_type "shmem" block_version "10.1.2" sg_icon_stat "80,194,3,1,white,blue,0,bf435243,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 80 80 0 0 ],[0 0 194 194 0 ],[0.77" " 0.82 0.91 ]);\nplot([0 80 80 0 0 ],[0 0 194 194 0 ]);\npatch([15.525 31.42 42.42 53.42 64.42 42.42 26.525 15.5" "25 ],[109.21 109.21 120.21 109.21 120.21 120.21 120.21 109.21 ],[1 1 1 ]);\npatch([26.525 42.42 31.42 15.525 26" ".525 ],[98.21 98.21 109.21 109.21 98.21 ],[0.931 0.946 0.973 ]);\npatch([15.525 31.42 42.42 26.525 15.525 ],[87" ".21 87.21 98.21 98.21 87.21 ],[1 1 1 ]);\npatch([26.525 64.42 53.42 42.42 31.42 15.525 26.525 ],[76.21 76.21 87" ".21 76.21 87.21 87.21 76.21 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','CO" "MMENT: begin icon text');\ncolor('black');port_label('input',1,'addr');\ncolor('black');port_label('input',2,'d" "in');\ncolor('black');port_label('input',3,'we');\ncolor('black');port_label('output',1,'dout');\nfprintf('','C" "OMMENT: end icon text');" } Block { BlockType Terminator Name "Terminator2" SID "498" Position [945, 410, 965, 430] ShowName off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "RSSI" SrcPort 1 DstBlock "Reinterpret1" DstPort 1 } Line { SrcBlock "Convert" SrcPort 1 Points [35, 0] Branch { DstBlock "Register" DstPort 1 } Branch { Points [0, 50] DstBlock "Concat" DstPort 2 } } Line { SrcBlock "Addr_14b" SrcPort 1 Points [40, 0] Branch { DstBlock "11MSB" DstPort 1 } Branch { Points [0, 55] DstBlock "BIT[2]" DstPort 1 } } Line { SrcBlock "WE" SrcPort 1 DstBlock "Shared Memory" DstPort 3 } Line { SrcBlock "Reinterpret1" SrcPort 1 DstBlock "Convert" DstPort 1 } Line { SrcBlock "Concat" SrcPort 1 DstBlock "Shared Memory" DstPort 2 } Line { SrcBlock "BIT[2]" SrcPort 1 DstBlock "Inverter" DstPort 1 } Line { SrcBlock "11MSB" SrcPort 1 DstBlock "Shared Memory" DstPort 1 } Line { SrcBlock "Shared Memory" SrcPort 1 DstBlock "Terminator2" DstPort 1 } Line { SrcBlock "Register" SrcPort 1 DstBlock "Concat" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Register" DstPort 2 } } } Block { BlockType SubSystem Name "Radio 4 I/Q\nBuffer" SID "499" Ports [3] Position [650, 116, 705, 224] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "Radio 4 I/Q\nBuffer" Location [2, 74, 1270, 726] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Addr_14b" SID "500" Position [205, 68, 235, 82] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "I/Q_32b" SID "501" Position [205, 98, 235, 112] Port "2" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "WE" SID "502" Position [205, 128, 235, 142] Port "3" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Shared Memory" SID "503" Ports [3, 1] Position [320, 60, 400, 150] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Shared Memory" SourceType "Xilinx Shared Memory Random Access Memory Block" shared_memory_name "'RxBuff_Radio4'" depth "2^14" ownership "Locally Owned and Initialized" initVector "0" en off mutex "Unprotected" mode "Read and Write" write_mode "Read After Write" time_out "0" latency "1" explicit_data_type on gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" xl_use_area off xl_area "[0,0,0,0,0,0,0]" implementation "Block RAM" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,384,381" block_type "shmem" block_version "10.1.2" sg_icon_stat "80,90,3,1,white,blue,0,bf435243,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 80 80 0 0 ],[0 0 90 90 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 80 80 0 0 ],[0 0 90 90 0 ]);\npatch([15.525 31.42 42.42 53.42 64.42 42.42 26.525 15.525 ]" ",[57.21 57.21 68.21 57.21 68.21 68.21 68.21 57.21 ],[1 1 1 ]);\npatch([26.525 42.42 31.42 15.525 26.525 ],[46.2" "1 46.21 57.21 57.21 46.21 ],[0.931 0.946 0.973 ]);\npatch([15.525 31.42 42.42 26.525 15.525 ],[35.21 35.21 46.2" "1 46.21 35.21 ],[1 1 1 ]);\npatch([26.525 64.42 53.42 42.42 31.42 15.525 26.525 ],[24.21 24.21 35.21 24.21 35.2" "1 35.21 24.21 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin i" "con text');\ncolor('black');port_label('input',1,'addr');\ncolor('black');port_label('input',2,'din');\ncolor('" "black');port_label('input',3,'we');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end ic" "on text');" } Block { BlockType Terminator Name "Terminator" SID "504" Position [450, 95, 470, 115] ShowName off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "Shared Memory" SrcPort 1 DstBlock "Terminator" DstPort 1 } Line { SrcBlock "WE" SrcPort 1 DstBlock "Shared Memory" DstPort 3 } Line { SrcBlock "I/Q_32b" SrcPort 1 DstBlock "Shared Memory" DstPort 2 } Line { SrcBlock "Addr_14b" SrcPort 1 DstBlock "Shared Memory" DstPort 1 } } } Block { BlockType Scope Name "Scope" SID "505" Ports [2] Position [585, 14, 625, 96] Floating off Location [5, 49, 1285, 757] Open off NumInputPorts "2" ZoomMode "yonly" List { ListType AxesTitles axes1 "%" axes2 "%" } YMin "-5~-5" YMax "5~5" SaveName "ScopeData2" DataFormat "StructureWithTime" MaxDataPoints "40000" SampleTime "0" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "Gateway Out1" SrcPort 1 DstBlock "Scope" DstPort 2 } Line { SrcBlock "Gateway Out" SrcPort 1 DstBlock "Scope" DstPort 1 } Line { SrcBlock "I/Q" SrcPort 1 DstBlock "Radio 4 I/Q\nBuffer" DstPort 2 } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "Logical" DstPort 2 } Line { SrcBlock "EN" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "WE" SrcPort 1 DstBlock "Logical" DstPort 1 } Line { SrcBlock "Addr" SrcPort 1 Points [75, 0] Branch { Points [0, -100] DstBlock "Gateway Out" DstPort 1 } Branch { Labels [0, 0] DstBlock "Radio 4 I/Q\nBuffer" DstPort 1 } Branch { Points [0, 150] DstBlock "Radio 4\nRSSI Buffer" DstPort 1 } } Line { SrcBlock "Logical" SrcPort 1 Points [65, 0] Branch { Points [85, 0] Branch { Points [0, -130] DstBlock "Gateway Out1" DstPort 1 } Branch { Labels [0, 0] DstBlock "Radio 4 I/Q\nBuffer" DstPort 3 } } Branch { Points [0, 150] DstBlock "Radio 4\nRSSI Buffer" DstPort 3 } } Line { SrcBlock "RSSI" SrcPort 1 DstBlock "Radio 4\nRSSI Buffer" DstPort 2 } } } Block { BlockType SubSystem Name "Radio 4\nTx Buffer" SID "506" Ports [3, 1] Position [1015, 952, 1095, 1008] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "Radio 4\nTx Buffer" Location [2, 74, 1270, 726] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "RdAddr_14b" SID "507" Position [350, 288, 380, 302] NamePlacement "alternate" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "Rst" SID "508" Position [30, 173, 60, 187] Port "2" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "En" SID "509" Position [30, 203, 60, 217] Port "3" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Constant" SID "510" Ports [0, 1] Position [630, 350, 655, 370] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,400,346" block_type "constant" block_version "10.1.2" sg_icon_stat "25,20,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 20 20 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[12.22 12.22 14.2" "2 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[10.22 10.22 12.22 12.22 10.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatch([9.55 1" "6.44 14.44 12.44 10.44 7.55 9.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'0');\nfprin" "tf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant1" SID "511" Ports [0, 1] Position [355, 345, 380, 365] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "32" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,400,346" block_type "constant" block_version "10.1.2" sg_icon_stat "25,20,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 20 20 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[12.22 12.22 14.2" "2 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[10.22 10.22 12.22 12.22 10.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatch([9.55 1" "6.44 14.44 12.44 10.44 7.55 9.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'0');\nfprin" "tf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Constant2" SID "512" Ports [0, 1] Position [355, 315, 380, 335] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,400,346" block_type "constant" block_version "10.1.2" sg_icon_stat "25,20,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 20 20 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[12.22 12.22 14.2" "2 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[10.22 10.22 12.22 12.22 10.22 ]," "[0.931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatch([9.55 1" "6.44 14.44 12.44 10.44 7.55 9.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'0');\nfprin" "tf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert" SID "513" Ports [1, 1] Position [350, 188, 375, 202] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "16" bin_pt "14" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,374,375" block_type "convert" block_version "8.2" sg_icon_stat "25,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 14 14 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 14 14 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[9.22 9.22 11.22 " "9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[7.22 7.22 9.22 9.22 7.22 ],[0.931 0." "946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([9.55 16.44 14.44 " "12.44 10.44 7.55 9.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon" " graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'cast');\nfprintf(''," "'COMMENT: end icon text');" } Block { BlockType Reference Name "Convert1" SID "514" Ports [1, 1] Position [100, 203, 120, 217] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "16" bin_pt "14" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,374,375" block_type "convert" block_version "8.2" sg_icon_stat "20,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 14 14 0 ],[0.77 0.82 0.91" " ]);\nplot([0 20 20 0 0 ],[0 0 14 14 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[9.22 9.22 11.22 9" ".22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[0.931 0.94" "6 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\npatch([7.55 14.44 12.44 10." "44 8.44 5.55 7.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon gra" "phics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'cast');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "515" Ports [1, 1] Position [150, 201, 180, 219] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "9.1.01" sg_icon_stat "30,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 18 18 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[11.22 11.22 1" "3.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[9.22 9.22 11.22 11.22 9.22" " ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([12" ".55 19.44 17.44 15.44 13.44 10.55 12.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf(''," "'COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nfprintf('" "','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical" SID "516" Ports [2, 1] Position [215, 165, 270, 225] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "logical" block_version "9.1.01" sg_icon_stat "55,60,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 60 60 0 ],[0.77 0.82 0.91" " ]);\nplot([0 55 55 0 0 ],[0 0 60 60 0 ]);\npatch([11.425 21.54 28.54 35.54 42.54 28.54 18.425 11.425 ],[37.77 37.7" "7 44.77 37.77 44.77 44.77 44.77 37.77 ],[1 1 1 ]);\npatch([18.425 28.54 21.54 11.425 18.425 ],[30.77 30.77 37.77 37" ".77 30.77 ],[0.931 0.946 0.973 ]);\npatch([11.425 21.54 28.54 18.425 11.425 ],[23.77 23.77 30.77 30.77 23.77 ],[1 1" " 1 ]);\npatch([18.425 42.54 35.54 28.54 21.54 11.425 18.425 ],[16.77 16.77 23.77 16.77 23.77 23.77 16.77 ],[0.931 0" ".946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('bl" "ack');disp('or');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux" SID "517" Ports [3, 1] Position [750, 273, 795, 377] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,303" block_type "mux" block_version "10.1.2" sg_icon_stat "45,104,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 14.8571 89.1429 104 0 ],[0." "77 0.82 0.91 ]);\nplot([0 45 45 0 0 ],[0 14.8571 89.1429 104 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65" " 8.65 ],[58.66 58.66 64.66 58.66 64.66 64.66 64.66 58.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[52.66" " 52.66 58.66 58.66 52.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[46.66 46.66 52.66 52.66 46" ".66 ],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[40.66 40.66 46.66 40.66 46.66 46.66 40.66 ],[0" ".931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('input',3" ",'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Shared Memory" SID "518" Ports [3, 1] Position [445, 280, 525, 370] AttributesFormatString "<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Shared Memory" SourceType "Xilinx Shared Memory Random Access Memory Block" shared_memory_name "'TxBuff_Radio4'" depth "2^14" ownership "Locally Owned and Initialized" initVector "0" en off mutex "Unprotected" mode "Read and Write" write_mode "Read After Write" time_out "0" latency "1" explicit_data_type on gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "32" bin_pt "0" preci_type "Single" xl_use_area off xl_area "[0,0,0,0,0,0,0]" implementation "Block RAM" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,384,381" block_type "shmem" block_version "10.1.2" sg_icon_stat "80,90,3,1,white,blue,0,bf435243,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 80 80 0 0 ],[0 0 90 90 0 ],[0.77 0.82 0.91" " ]);\nplot([0 80 80 0 0 ],[0 0 90 90 0 ]);\npatch([15.525 31.42 42.42 53.42 64.42 42.42 26.525 15.525 ],[57.21 57.2" "1 68.21 57.21 68.21 68.21 68.21 57.21 ],[1 1 1 ]);\npatch([26.525 42.42 31.42 15.525 26.525 ],[46.21 46.21 57.21 57" ".21 46.21 ],[0.931 0.946 0.973 ]);\npatch([15.525 31.42 42.42 26.525 15.525 ],[35.21 35.21 46.21 46.21 35.21 ],[1 1" " 1 ]);\npatch([26.525 64.42 53.42 42.42 31.42 15.525 26.525 ],[24.21 24.21 35.21 24.21 35.21 35.21 24.21 ],[0.931 0" ".946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');" "port_label('input',1,'addr');\ncolor('black');port_label('input',2,'din');\ncolor('black');port_label('input',3,'we" "');\ncolor('black');port_label('output',1,'dout');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "IQ_32b" SID "519" Position [885, 318, 915, 332] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "Mux" SrcPort 1 DstBlock "IQ_32b" DstPort 1 } Line { SrcBlock "Constant2" SrcPort 1 DstBlock "Shared Memory" DstPort 2 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Shared Memory" DstPort 3 } Line { SrcBlock "Shared Memory" SrcPort 1 DstBlock "Mux" DstPort 2 } Line { SrcBlock "Constant" SrcPort 1 DstBlock "Mux" DstPort 3 } Line { SrcBlock "RdAddr_14b" SrcPort 1 DstBlock "Shared Memory" DstPort 1 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Logical" DstPort 2 } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "Inverter" DstPort 1 } Line { SrcBlock "En" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "Rst" SrcPort 1 DstBlock "Logical" DstPort 1 } Line { SrcBlock "Convert" SrcPort 1 Points [160, 0; 0, 95] DstBlock "Mux" DstPort 1 } Line { SrcBlock "Logical" SrcPort 1 DstBlock "Convert" DstPort 1 } } } Block { BlockType SubSystem Name "Radio 4 Inputs" SID "520" Ports [2, 2] Position [910, 450, 1080, 510] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "Radio 4 Inputs" Location [2, 74, 1014, 726] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "DebugRxBuffers" SID "521" Position [180, 228, 210, 242] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "MGCAGC_AGCDCO_SEL" SID "522" Position [180, 323, 210, 337] Port "2" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType SubSystem Name "ADC I" SID "523" Ports [2, 2] Position [430, 223, 580, 267] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "ADC I" Location [37, 74, 1049, 726] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Debug" SID "524" Position [685, 13, 715, 27] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "MGCAGC_AGCDCO_SEL" SID "525" Position [135, 203, 165, 217] Port "2" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Constant Name "Constant1" SID "526" Position [15, 280, 45, 310] ShowName off Value "0" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Counter" SID "527" Ports [0, 1] Position [520, 300, 580, 360] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited co" "unter is implemented by combining a counter with a comparator." cnt_type "Free Running" cnt_to "Inf" operation "Down" start_count "2^14-1" cnt_by_val "1" arith_type "Unsigned" n_bits "14" bin_pt "0" load_pin off rst off en off explicit_period "on" period "1" dbl_ovrd off use_behavioral_HDL off implementation "Fabric" xl_use_area off xl_area "[0,0,0,0,0,0,0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,619" block_type "counter" block_version "10.1.3" sg_icon_stat "60,60,0,1,white,blue,0,cf0fdd8c,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 60 60 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 60 60 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[38.8" "8 38.88 46.88 38.88 46.88 46.88 46.88 38.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[30.88 30.88 38.8" "8 38.88 30.88 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[22.88 22.88 30.88 30.88 22.88 ],[1" " 1 1 ]);\npatch([20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[14.88 14.88 22.88 14.88 22.88 22.88 14.88 ],[0.931 0" ".946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('bl" "ack');disp('{\\fontsize{14}\\bf--}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "FromAGC_Radio4_I" SID "528" Ports [1, 1] Position [120, 385, 185, 405] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, double and fixed point to Xilinx" " fixed point type.

Hardware notes: In hardware these blocks become top level input ports." gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "14" bin_pt "13" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off UseAsADC off ADCChannel "'1'" hdl_port "on" has_advanced_control "0" sggui_pos "20,20,348,406" block_type "gatewayin" block_version "10.1.3" sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0" ".93 0.65 ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[1" "2.22 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.2" "2 12.22 12.22 10.22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.2" "2 ],[1 1 1 ]);\npatch([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985" " 0.979 0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' " "');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux" SID "529" Ports [3, 1] Position [820, 48, 865, 152] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "1" bin_pt "0" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,303" block_type "mux" block_version "10.1.3" sg_icon_stat "45,104,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 14.8571 89.1429 104" " 0 ],[0.77 0.82 0.91 ]);\nplot([0 45 45 0 0 ],[0 14.8571 89.1429 104 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32" " 23.32 14.65 8.65 ],[58.66 58.66 64.66 58.66 64.66 64.66 64.66 58.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.6" "5 14.65 ],[52.66 52.66 58.66 58.66 52.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[46.66 " "46.66 52.66 52.66 46.66 ],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[40.66 40.66 46.66 40.6" "6 46.66 46.66 40.66 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: b" "egin icon text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncol" "or('black');port_label('input',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: " "end icon text');" } Block { BlockType Reference Name "Mux1" SID "530" Ports [3, 1] Position [820, 243, 865, 347] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "1" bin_pt "0" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,303" block_type "mux" block_version "10.1.3" sg_icon_stat "45,104,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 14.8571 89.1429 104" " 0 ],[0.77 0.82 0.91 ]);\nplot([0 45 45 0 0 ],[0 14.8571 89.1429 104 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32" " 23.32 14.65 8.65 ],[58.66 58.66 64.66 58.66 64.66 64.66 64.66 58.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.6" "5 14.65 ],[52.66 52.66 58.66 58.66 52.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[46.66 " "46.66 52.66 52.66 46.66 ],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[40.66 40.66 46.66 40.6" "6 46.66 46.66 40.66 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: b" "egin icon text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncol" "or('black');port_label('input',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: " "end icon text');" } Block { BlockType Reference Name "Mux2" SID "531" Ports [3, 1] Position [280, 243, 325, 347] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "1" bin_pt "0" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,303" block_type "mux" block_version "10.1.3" sg_icon_stat "45,104,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 14.8571 89.1429 104" " 0 ],[0.77 0.82 0.91 ]);\nplot([0 45 45 0 0 ],[0 14.8571 89.1429 104 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32" " 23.32 14.65 8.65 ],[58.66 58.66 64.66 58.66 64.66 64.66 64.66 58.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.6" "5 14.65 ],[52.66 52.66 58.66 58.66 52.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[46.66 " "46.66 52.66 52.66 46.66 ],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[40.66 40.66 46.66 40.6" "6 46.66 46.66 40.66 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: b" "egin icon text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncol" "or('black');port_label('input',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: " "end icon text');" } Block { BlockType Reference Name "Radio 4 ADC I" SID "532" Ports [1, 1] Position [85, 274, 180, 316] LibraryVersion "1.48" LinkData { BlockName "radio4_adc_I" DialogParameters { sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.6" "5 ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[12.22 12.22" " 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.22 12.22 12.22" " 10.22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\n" "patch([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('inpu" "t',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT:" " end icon text');\n" } } SourceBlock "WARP_Blockset/WARP Radio Board ADC//DACs/Radio 4 ADC I" SourceType "" ShowPortLabels "FromPortIcon" SystemSampleTime "-1" FunctionWithSeparateData off RTWMemSecFuncInitTerm "Inherit from model" RTWMemSecFuncExecute "Inherit from model" RTWMemSecDataConstants "Inherit from model" RTWMemSecDataInternal "Inherit from model" RTWMemSecDataParameters "Inherit from model" GeneratePreprocessorConditionals off samp_period "1" } Block { BlockType Reference Name "Register" SID "533" Ports [1, 1] Position [445, 281, 480, 309] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "8.2" sg_icon_stat "35,28,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 28 28 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 28 28 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[18.44 " "18.44 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[14.44 14.44 18.44 1" "8.44 14.44 ],[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 " "]);\npatch([12.1 25.88 21.88 17.88 13.88 8.1 12.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Reinterpret" SID "534" Ports [1, 1] Position [665, 314, 715, 346] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can changed the signal b" "etween signed and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs no" "thing.

Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is force" "d to unsigned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an outp" "ut of 56 (111000 in binary)." force_arith_type on arith_type "Signed (2's comp)" force_bin_pt on bin_pt "13" has_advanced_control "0" sggui_pos "20,20,336,312" block_type "reinterpret" block_version "10.1.3" sg_icon_stat "50,32,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 32 32 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 32 32 0 ]);\npatch([16.1 21.88 25.88 29.88 33.88 25.88 20.1 16.1 ],[20.4" "4 20.44 24.44 20.44 24.44 24.44 24.44 20.44 ],[1 1 1 ]);\npatch([20.1 25.88 21.88 16.1 20.1 ],[16.44 16.44 20.4" "4 20.44 16.44 ],[0.931 0.946 0.973 ]);\npatch([16.1 21.88 25.88 20.1 16.1 ],[12.44 12.44 16.44 16.44 12.44 ],[1" " 1 1 ]);\npatch([20.1 33.88 29.88 25.88 21.88 16.1 20.1 ],[8.44 8.44 12.44 8.44 12.44 12.44 8.44 ],[0.931 0.946" " 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('blac" "k');disp('reinterpret');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Slice" SID "535" Ports [1, 1] Position [670, 120, 730, 150] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outp" "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

" "

Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,376" block_type "slice" block_version "10.1.3" sg_icon_stat "60,30,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 30 30 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\npatch([21.1 26.88 30.88 34.88 38.88 30.88 25.1 21.1 ],[19.4" "4 19.44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([25.1 30.88 26.88 21.1 25.1 ],[15.44 15.44 19.4" "4 19.44 15.44 ],[0.931 0.946 0.973 ]);\npatch([21.1 26.88 30.88 25.1 21.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1" " 1 1 ]);\npatch([25.1 38.88 34.88 30.88 26.88 21.1 25.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946" " 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black'" ");port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "radio4_ADC_I_OTR" SID "536" Ports [1, 1] Position [440, 94, 495, 106] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, double and fixed point to Xilinx" " fixed point type.

Hardware notes: In hardware these blocks become top level input ports." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off UseAsADC off ADCChannel "'1'" hdl_port "on" has_advanced_control "0" sggui_pos "20,20,356,432" block_type "gatewayin" block_version "VER_STRING_GOES_HERE" sg_icon_stat "55,12,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 12 12 0 ],[0.95 0" ".93 0.65 ]);\nplot([0 55 55 0 0 ],[0 0 12 12 0 ]);\npatch([24.775 26.22 27.22 28.22 29.22 27.22 25.775 24.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([25.775 27.22 26.22 24.775 25.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.985 0.979 0.895 ]);\npatch([24.775 26.22 27.22 25.775 24.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([25.775 29.22 28.22 27.22 26.22 24.775 25.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.985 0." "979 0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "OTR I" SID "537" Position [925, 93, 955, 107] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Outport Name "ADC I" SID "538" Position [925, 288, 955, 302] Port "2" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "Constant1" SrcPort 1 Points [10, 0] Branch { Points [0, -195] DstBlock "radio4_ADC_I_OTR" DstPort 1 } Branch { DstBlock "Radio 4 ADC I" DstPort 1 } Branch { Points [0, 100] DstBlock "FromAGC_Radio4_I" DstPort 1 } } Line { SrcBlock "Mux" SrcPort 1 DstBlock "OTR I" DstPort 1 } Line { SrcBlock "Debug" SrcPort 1 Points [40, 0; 0, 45] Branch { DstBlock "Mux" DstPort 1 } Branch { Points [0, 195] DstBlock "Mux1" DstPort 1 } } Line { SrcBlock "radio4_ADC_I_OTR" SrcPort 1 DstBlock "Mux" DstPort 2 } Line { SrcBlock "Slice" SrcPort 1 DstBlock "Mux" DstPort 3 } Line { SrcBlock "Mux1" SrcPort 1 DstBlock "ADC I" DstPort 1 } Line { SrcBlock "Register" SrcPort 1 DstBlock "Mux1" DstPort 2 } Line { SrcBlock "Reinterpret" SrcPort 1 DstBlock "Mux1" DstPort 3 } Line { SrcBlock "Counter" SrcPort 1 Points [25, 0] Branch { DstBlock "Reinterpret" DstPort 1 } Branch { Points [0, -195] DstBlock "Slice" DstPort 1 } } Line { SrcBlock "MGCAGC_AGCDCO_SEL" SrcPort 1 Points [70, 0; 0, 50] DstBlock "Mux2" DstPort 1 } Line { SrcBlock "FromAGC_Radio4_I" SrcPort 1 Points [50, 0; 0, -65] DstBlock "Mux2" DstPort 3 } Line { SrcBlock "Radio 4 ADC I" SrcPort 1 DstBlock "Mux2" DstPort 2 } Line { SrcBlock "Mux2" SrcPort 1 DstBlock "Register" DstPort 1 } } } Block { BlockType SubSystem Name "ADC Q" SID "539" Ports [2, 2] Position [430, 298, 580, 342] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "ADC Q" Location [22, 84, 1034, 736] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Debug" SID "540" Position [675, 13, 705, 27] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "MGCAGC_AGCDCO_SEL" SID "541" Position [120, 203, 150, 217] Port "2" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Constant Name "Constant1" SID "542" Position [15, 280, 45, 310] ShowName off Value "0" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Counter" SID "543" Ports [0, 1] Position [505, 300, 565, 360] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited co" "unter is implemented by combining a counter with a comparator." cnt_type "Free Running" cnt_to "Inf" operation "Up" start_count "0" cnt_by_val "1" arith_type "Unsigned" n_bits "14" bin_pt "0" load_pin off rst off en off explicit_period "on" period "1" dbl_ovrd off use_behavioral_HDL off implementation "Fabric" xl_use_area off xl_area "[0,0,0,0,0,0,0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,619" block_type "counter" block_version "10.1.3" sg_icon_stat "60,60,0,1,white,blue,0,7ac47ef5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 60 60 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 60 60 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[38.8" "8 38.88 46.88 38.88 46.88 46.88 46.88 38.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[30.88 30.88 38.8" "8 38.88 30.88 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[22.88 22.88 30.88 30.88 22.88 ],[1" " 1 1 ]);\npatch([20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[14.88 14.88 22.88 14.88 22.88 22.88 14.88 ],[0.931 0" ".946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('bl" "ack');disp('{\\fontsize{14}\\bf++}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "FromAGC_Radio4_Q" SID "544" Ports [1, 1] Position [105, 385, 170, 405] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, double and fixed point to Xilinx" " fixed point type.

Hardware notes: In hardware these blocks become top level input ports." gui_display_data_type "Fixed-point" arith_type "Signed (2's comp)" n_bits "14" bin_pt "13" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off UseAsADC off ADCChannel "'1'" hdl_port "on" has_advanced_control "0" sggui_pos "20,20,348,406" block_type "gatewayin" block_version "10.1.3" sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0" ".93 0.65 ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[1" "2.22 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.2" "2 12.22 12.22 10.22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.2" "2 ],[1 1 1 ]);\npatch([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985" " 0.979 0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' " "');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux" SID "545" Ports [3, 1] Position [810, 48, 855, 152] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "1" bin_pt "0" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,303" block_type "mux" block_version "10.1.3" sg_icon_stat "45,104,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 14.8571 89.1429 104" " 0 ],[0.77 0.82 0.91 ]);\nplot([0 45 45 0 0 ],[0 14.8571 89.1429 104 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32" " 23.32 14.65 8.65 ],[58.66 58.66 64.66 58.66 64.66 64.66 64.66 58.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.6" "5 14.65 ],[52.66 52.66 58.66 58.66 52.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[46.66 " "46.66 52.66 52.66 46.66 ],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[40.66 40.66 46.66 40.6" "6 46.66 46.66 40.66 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: b" "egin icon text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncol" "or('black');port_label('input',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: " "end icon text');" } Block { BlockType Reference Name "Mux1" SID "546" Ports [3, 1] Position [810, 243, 855, 347] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "1" bin_pt "0" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,303" block_type "mux" block_version "10.1.3" sg_icon_stat "45,104,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 14.8571 89.1429 104" " 0 ],[0.77 0.82 0.91 ]);\nplot([0 45 45 0 0 ],[0 14.8571 89.1429 104 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32" " 23.32 14.65 8.65 ],[58.66 58.66 64.66 58.66 64.66 64.66 64.66 58.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.6" "5 14.65 ],[52.66 52.66 58.66 58.66 52.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[46.66 " "46.66 52.66 52.66 46.66 ],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[40.66 40.66 46.66 40.6" "6 46.66 46.66 40.66 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: b" "egin icon text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncol" "or('black');port_label('input',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: " "end icon text');" } Block { BlockType Reference Name "Mux2" SID "547" Ports [3, 1] Position [265, 243, 310, 347] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "1" bin_pt "0" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,303" block_type "mux" block_version "10.1.3" sg_icon_stat "45,104,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 14.8571 89.1429 104" " 0 ],[0.77 0.82 0.91 ]);\nplot([0 45 45 0 0 ],[0 14.8571 89.1429 104 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32" " 23.32 14.65 8.65 ],[58.66 58.66 64.66 58.66 64.66 64.66 64.66 58.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.6" "5 14.65 ],[52.66 52.66 58.66 58.66 52.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[46.66 " "46.66 52.66 52.66 46.66 ],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[40.66 40.66 46.66 40.6" "6 46.66 46.66 40.66 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: b" "egin icon text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncol" "or('black');port_label('input',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: " "end icon text');" } Block { BlockType Reference Name "Radio 4 ADC Q" SID "548" Ports [1, 1] Position [85, 274, 180, 316] LibraryVersion "1.48" LinkData { BlockName "radio4_adc_Q" DialogParameters { sg_icon_stat "65,20,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 65 65 0 0 ],[0 0 20 20 0 ],[0.95 0.93 0.6" "5 ]);\nplot([0 65 65 0 0 ],[0 0 20 20 0 ]);\npatch([27.55 30.44 32.44 34.44 36.44 32.44 29.55 27.55 ],[12.22 12.22" " 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([29.55 32.44 30.44 27.55 29.55 ],[10.22 10.22 12.22 12.22" " 10.22 ],[0.985 0.979 0.895 ]);\npatch([27.55 30.44 32.44 29.55 27.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\n" "patch([29.55 36.44 34.44 32.44 30.44 27.55 29.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985 0.979 0.895 ]);\nf" "printf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('inpu" "t',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','COMMENT:" " end icon text');\n" } } SourceBlock "WARP_Blockset/WARP Radio Board ADC//DACs/Radio 4 ADC Q" SourceType "" ShowPortLabels "FromPortIcon" SystemSampleTime "-1" FunctionWithSeparateData off RTWMemSecFuncInitTerm "Inherit from model" RTWMemSecFuncExecute "Inherit from model" RTWMemSecDataConstants "Inherit from model" RTWMemSecDataInternal "Inherit from model" RTWMemSecDataParameters "Inherit from model" GeneratePreprocessorConditionals off samp_period "1" } Block { BlockType Reference Name "Register" SID "549" Ports [1, 1] Position [385, 281, 420, 309] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "8.2" sg_icon_stat "35,28,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 28 28 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 28 28 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[18.44 " "18.44 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[14.44 14.44 18.44 1" "8.44 14.44 ],[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 " "]);\npatch([12.1 25.88 21.88 17.88 13.88 8.1 12.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_l" "abel('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Reinterpret" SID "550" Ports [1, 1] Position [655, 314, 705, 346] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can changed the signal b" "etween signed and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs no" "thing.

Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is force" "d to unsigned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an outp" "ut of 56 (111000 in binary)." force_arith_type on arith_type "Signed (2's comp)" force_bin_pt on bin_pt "13" has_advanced_control "0" sggui_pos "20,20,336,312" block_type "reinterpret" block_version "10.1.3" sg_icon_stat "50,32,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 32 32 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 32 32 0 ]);\npatch([16.1 21.88 25.88 29.88 33.88 25.88 20.1 16.1 ],[20.4" "4 20.44 24.44 20.44 24.44 24.44 24.44 20.44 ],[1 1 1 ]);\npatch([20.1 25.88 21.88 16.1 20.1 ],[16.44 16.44 20.4" "4 20.44 16.44 ],[0.931 0.946 0.973 ]);\npatch([16.1 21.88 25.88 20.1 16.1 ],[12.44 12.44 16.44 16.44 12.44 ],[1" " 1 1 ]);\npatch([20.1 33.88 29.88 25.88 21.88 16.1 20.1 ],[8.44 8.44 12.44 8.44 12.44 12.44 8.44 ],[0.931 0.946" " 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('blac" "k');disp('reinterpret');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Slice" SID "551" Ports [1, 1] Position [660, 120, 720, 150] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The outp" "ut type is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

" "

Hardware notes: In hardware this block costs nothing." nbits "1" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,449,376" block_type "slice" block_version "10.1.3" sg_icon_stat "60,30,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 30 30 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 30 30 0 ]);\npatch([21.1 26.88 30.88 34.88 38.88 30.88 25.1 21.1 ],[19.4" "4 19.44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([25.1 30.88 26.88 21.1 25.1 ],[15.44 15.44 19.4" "4 19.44 15.44 ],[0.931 0.946 0.973 ]);\npatch([21.1 26.88 30.88 25.1 21.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1" " 1 1 ]);\npatch([25.1 38.88 34.88 30.88 26.88 21.1 25.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946" " 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black'" ");port_label('output',1,'[a:b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "radio4_ADC_Q_OTR" SID "552" Ports [1, 1] Position [115, 94, 170, 106] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, double and fixed point to Xilinx" " fixed point type.

Hardware notes: In hardware these blocks become top level input ports." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off UseAsADC off ADCChannel "'1'" hdl_port "on" has_advanced_control "0" sggui_pos "20,20,356,432" block_type "gatewayin" block_version "VER_STRING_GOES_HERE" sg_icon_stat "55,12,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 12 12 0 ],[0.95 0" ".93 0.65 ]);\nplot([0 55 55 0 0 ],[0 0 12 12 0 ]);\npatch([24.775 26.22 27.22 28.22 29.22 27.22 25.775 24.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([25.775 27.22 26.22 24.775 25.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.985 0.979 0.895 ]);\npatch([24.775 26.22 27.22 25.775 24.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([25.775 29.22 28.22 27.22 26.22 24.775 25.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.985 0." "979 0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "OTR Q" SID "553" Position [955, 93, 985, 107] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Outport Name "ADC Q" SID "554" Position [950, 288, 980, 302] Port "2" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "Constant1" SrcPort 1 Points [10, 0] Branch { Points [0, -195] DstBlock "radio4_ADC_Q_OTR" DstPort 1 } Branch { DstBlock "Radio 4 ADC Q" DstPort 1 } Branch { Points [0, 100] DstBlock "FromAGC_Radio4_Q" DstPort 1 } } Line { SrcBlock "Mux" SrcPort 1 DstBlock "OTR Q" DstPort 1 } Line { SrcBlock "Debug" SrcPort 1 Points [40, 0; 0, 45] Branch { DstBlock "Mux" DstPort 1 } Branch { Points [0, 195] DstBlock "Mux1" DstPort 1 } } Line { SrcBlock "radio4_ADC_Q_OTR" SrcPort 1 DstBlock "Mux" DstPort 2 } Line { SrcBlock "Slice" SrcPort 1 DstBlock "Mux" DstPort 3 } Line { SrcBlock "Mux1" SrcPort 1 DstBlock "ADC Q" DstPort 1 } Line { SrcBlock "Register" SrcPort 1 DstBlock "Mux1" DstPort 2 } Line { SrcBlock "Reinterpret" SrcPort 1 DstBlock "Mux1" DstPort 3 } Line { SrcBlock "Counter" SrcPort 1 Points [30, 0] Branch { DstBlock "Reinterpret" DstPort 1 } Branch { Points [0, -195] DstBlock "Slice" DstPort 1 } } Line { SrcBlock "MGCAGC_AGCDCO_SEL" SrcPort 1 Points [70, 0; 0, 50] DstBlock "Mux2" DstPort 1 } Line { SrcBlock "FromAGC_Radio4_Q" SrcPort 1 Points [50, 0; 0, -65] DstBlock "Mux2" DstPort 3 } Line { SrcBlock "Radio 4 ADC Q" SrcPort 1 DstBlock "Mux2" DstPort 2 } Line { SrcBlock "Mux2" SrcPort 1 DstBlock "Register" DstPort 1 } } } Block { BlockType SubSystem Name "Concatenates_1" SID "555" Ports [4, 1] Position [695, 218, 740, 372] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "Concatenates_1" Location [2, 74, 1270, 726] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "OTR_I" SID "556" Position [395, 43, 425, 57] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "ADC_I" SID "557" Position [330, 93, 360, 107] Port "2" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "OTR_Q" SID "558" Position [390, 163, 420, 177] Port "3" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "ADC_Q" SID "559" Position [330, 213, 360, 227] Port "4" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Concat1" SID "560" Ports [2, 1] Position [490, 191, 520, 229] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary poi" "nt at zero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" block_version "8.2" sg_icon_stat "30,38,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 38 38 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 38 38 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[23.44 " "23.44 27.44 23.44 27.44 27.44 27.44 23.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[19.44 19.44 23.44 2" "3.44 19.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[15.44 15.44 19.44 19.44 15.44 ],[1 1 1 " "]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[11.44 11.44 15.44 11.44 15.44 15.44 11.44 ],[0.931 0.946 0" ".973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');po" "rt_label('input',1,'hi');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\fontsize{20}\\}" "','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Concat2" SID "561" Ports [2, 1] Position [490, 71, 520, 109] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary poi" "nt at zero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" block_version "8.2" sg_icon_stat "30,38,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 38 38 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 38 38 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[23.44 " "23.44 27.44 23.44 27.44 27.44 27.44 23.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[19.44 19.44 23.44 2" "3.44 19.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[15.44 15.44 19.44 19.44 15.44 ],[1 1 1 " "]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[11.44 11.44 15.44 11.44 15.44 15.44 11.44 ],[0.931 0.946 0" ".973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');po" "rt_label('input',1,'hi');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\fontsize{20}\\}" "','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Concat3" SID "562" Ports [2, 1] Position [550, 150, 575, 230] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary poi" "nt at zero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" block_version "8.2" sg_icon_stat "25,80,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 80 80 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 80 80 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[43" ".33 43.33 46.33 43.33 46.33 46.33 46.33 43.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[40.33 40.33 " "43.33 43.33 40.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[37.33 37.33 40.33 40.33 37.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[34.33 34.33 37.33 34.33 37.33 37.33 34.33 ]," "[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncol" "or('black');port_label('input',1,'hi');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\f" "ontsize{20}\\}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Concat4" SID "563" Ports [2, 1] Position [550, 30, 575, 110] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary poi" "nt at zero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" block_version "8.2" sg_icon_stat "25,80,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 80 80 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 80 80 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[43" ".33 43.33 46.33 43.33 46.33 46.33 46.33 43.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[40.33 40.33 " "43.33 43.33 40.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[37.33 37.33 40.33 40.33 37.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[34.33 34.33 37.33 34.33 37.33 37.33 34.33 ]," "[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncol" "or('black');port_label('input',1,'hi');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\f" "ontsize{20}\\}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Concat5" SID "564" Ports [2, 1] Position [635, 50, 660, 130] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Concat" SourceType "Xilinx Bus Concatenator Block" infoedit "Concatenates two or more inputs. Output will be cast to an unsigned value with the binary poi" "nt at zero." num_inputs "2" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "concat" block_version "8.2" sg_icon_stat "25,80,2,1,white,blue,0,16398980,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 80 80 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 25 25 0 0 ],[0 0 80 80 0 ]);\npatch([5.325 9.66 12.66 15.66 18.66 12.66 8.325 5.325 ],[43" ".33 43.33 46.33 43.33 46.33 46.33 46.33 43.33 ],[1 1 1 ]);\npatch([8.325 12.66 9.66 5.325 8.325 ],[40.33 40.33 " "43.33 43.33 40.33 ],[0.931 0.946 0.973 ]);\npatch([5.325 9.66 12.66 8.325 5.325 ],[37.33 37.33 40.33 40.33 37.3" "3 ],[1 1 1 ]);\npatch([8.325 18.66 15.66 12.66 9.66 5.325 8.325 ],[34.33 34.33 37.33 34.33 37.33 37.33 34.33 ]," "[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncol" "or('black');port_label('input',1,'hi');\ncolor('black');port_label('input',2,'lo');\n\ncolor('black');disp('\\f" "ontsize{20}\\}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Reinterpret" SID "565" Ports [1, 1] Position [385, 90, 420, 110] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can changed the signal b" "etween signed and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs no" "thing.

Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is force" "d to unsigned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an outp" "ut of 56 (111000 in binary)." force_arith_type on arith_type "Unsigned" force_bin_pt on bin_pt "0" has_advanced_control "0" sggui_pos "20,20,356,309" block_type "reinterpret" block_version "8.2" sg_icon_stat "35,20,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 20 20 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 20 20 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[1" "2.22 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[10.22 10.2" "2 12.22 12.22 10.22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[8.22 8.22 10.22 10.22 8.2" "2 ],[1 1 1 ]);\npatch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931" " 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor" "('black');disp('reinterpret');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Reinterpret1" SID "566" Ports [1, 1] Position [390, 210, 425, 230] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can changed the signal b" "etween signed and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs no" "thing.

Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is force" "d to unsigned with 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an outp" "ut of 56 (111000 in binary)." force_arith_type on arith_type "Unsigned" force_bin_pt on bin_pt "0" has_advanced_control "0" sggui_pos "20,20,356,309" block_type "reinterpret" block_version "8.2" sg_icon_stat "35,20,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 20 20 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 20 20 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[1" "2.22 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[10.22 10.2" "2 12.22 12.22 10.22 ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[8.22 8.22 10.22 10.22 8.2" "2 ],[1 1 1 ]);\npatch([14.55 21.44 19.44 17.44 15.44 12.55 14.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931" " 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor" "('black');disp('reinterpret');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "zero" SID "567" Ports [0, 1] Position [440, 191, 460, 209] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "20,18,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 20 20 0 0 ],[0 0 18 18 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[9.22 9.22 11.22 11" ".22 9.22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\np" "atch([7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfpr" "intf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('out" "put',1,'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "zero1" SID "568" Ports [0, 1] Position [440, 71, 460, 89] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "0" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "20,18,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 20 20 0 0 ],[0 0 18 18 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[9.22 9.22 11.22 11" ".22 9.22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\np" "atch([7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfpr" "intf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('out" "put',1,'0');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "32b" SID "569" Position [840, 83, 870, 97] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "Reinterpret1" SrcPort 1 DstBlock "Concat1" DstPort 2 } Line { SrcBlock "Reinterpret" SrcPort 1 DstBlock "Concat2" DstPort 2 } Line { SrcBlock "ADC_Q" SrcPort 1 DstBlock "Reinterpret1" DstPort 1 } Line { SrcBlock "OTR_Q" SrcPort 1 DstBlock "Concat3" DstPort 1 } Line { SrcBlock "ADC_I" SrcPort 1 DstBlock "Reinterpret" DstPort 1 } Line { SrcBlock "Concat5" SrcPort 1 DstBlock "32b" DstPort 1 } Line { SrcBlock "OTR_I" SrcPort 1 DstBlock "Concat4" DstPort 1 } Line { SrcBlock "Concat3" SrcPort 1 Points [25, 0; 0, -80] DstBlock "Concat5" DstPort 2 } Line { SrcBlock "Concat4" SrcPort 1 DstBlock "Concat5" DstPort 1 } Line { SrcBlock "Concat2" SrcPort 1 Points [0, 0] DstBlock "Concat4" DstPort 2 } Line { SrcBlock "zero1" SrcPort 1 DstBlock "Concat2" DstPort 1 } Line { SrcBlock "Concat1" SrcPort 1 DstBlock "Concat3" DstPort 2 } Line { SrcBlock "zero" SrcPort 1 DstBlock "Concat1" DstPort 1 } } } Block { BlockType Reference Name "Gateway Out1" SID "570" Ports [1, 1] Position [725, 135, 755, 145] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, double, o" "r fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarded, depen" "ding on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" UseAsDAC off DACChannel "'1'" has_advanced_control "0" sggui_pos "20,20,336,386" block_type "gatewayout" block_version "10.1.2" sg_icon_stat "30,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 10 10 0 ],[0.88 0.88 0.88" " ]);\nplot([0 30 30 0 0 ],[0 0 10 10 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ],[6.11 6.11 " "7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[5.11 5.11 6.11 6.11 5.11 ],[" "0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]);\npatch([13." "775 17.22 16.22 15.22 14.22 12.775 13.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.964 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ')" ";\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" } Block { BlockType Reference Name "Gateway Out4" SID "571" Ports [1, 1] Position [725, 120, 755, 130] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, double, o" "r fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarded, depen" "ding on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" UseAsDAC off DACChannel "'1'" has_advanced_control "0" sggui_pos "20,20,336,386" block_type "gatewayout" block_version "10.1.2" sg_icon_stat "30,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 10 10 0 ],[0.88 0.88 0.88" " ]);\nplot([0 30 30 0 0 ],[0 0 10 10 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ],[6.11 6.11 " "7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[5.11 5.11 6.11 6.11 5.11 ],[" "0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]);\npatch([13." "775 17.22 16.22 15.22 14.22 12.775 13.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.964 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ')" ";\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" } Block { BlockType SubSystem Name "RSSI" SID "572" Ports [1, 1] Position [500, 407, 570, 443] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "RSSI" Location [2, 74, 1184, 726] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Debug" SID "573" Position [465, 28, 495, 42] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Constant Name "Constant1" SID "574" Position [160, 100, 190, 130] ShowName off Value "0" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Counter" SID "575" Ports [0, 1] Position [380, 120, 440, 180] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited co" "unter is implemented by combining a counter with a comparator." cnt_type "Free Running" cnt_to "Inf" operation "Up" start_count "0" cnt_by_val "1" arith_type "Unsigned" n_bits "10" bin_pt "0" load_pin off rst off en off explicit_period "on" period "1" dbl_ovrd off use_behavioral_HDL off implementation "Fabric" xl_use_area off xl_area "[0,0,0,0,0,0,0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,348,619" block_type "counter" block_version "10.1.3" sg_icon_stat "60,60,0,1,white,blue,0,7ac47ef5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 60 60 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 60 60 0 0 ],[0 0 60 60 0 ]);\npatch([12.2 23.76 31.76 39.76 47.76 31.76 20.2 12.2 ],[38.8" "8 38.88 46.88 38.88 46.88 46.88 46.88 38.88 ],[1 1 1 ]);\npatch([20.2 31.76 23.76 12.2 20.2 ],[30.88 30.88 38.8" "8 38.88 30.88 ],[0.931 0.946 0.973 ]);\npatch([12.2 23.76 31.76 20.2 12.2 ],[22.88 22.88 30.88 30.88 22.88 ],[1" " 1 1 ]);\npatch([20.2 47.76 39.76 31.76 23.76 12.2 20.2 ],[14.88 14.88 22.88 14.88 22.88 22.88 14.88 ],[0.931 0" ".946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('bl" "ack');disp('{\\fontsize{14}\\bf++}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Mux" SID "576" Ports [3, 1] Position [600, 63, 645, 167] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "1" bin_pt "0" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,303" block_type "mux" block_version "10.1.3" sg_icon_stat "45,104,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 14.8571 89.1429 104" " 0 ],[0.77 0.82 0.91 ]);\nplot([0 45 45 0 0 ],[0 14.8571 89.1429 104 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32" " 23.32 14.65 8.65 ],[58.66 58.66 64.66 58.66 64.66 64.66 64.66 58.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.6" "5 14.65 ],[52.66 52.66 58.66 58.66 52.66 ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[46.66 " "46.66 52.66 52.66 46.66 ],[1 1 1 ]);\npatch([14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[40.66 40.66 46.66 40.6" "6 46.66 46.66 40.66 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: b" "egin icon text');\ncolor('black');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncol" "or('black');port_label('input',3,'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: " "end icon text');" } Block { BlockType Reference Name "radio4_RSSI" SID "577" Ports [1, 1] Position [280, 109, 335, 121] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, double and fixed point to Xilinx" " fixed point type.

Hardware notes: In hardware these blocks become top level input ports." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "10" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Truncate" overflow "Wrap" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off UseAsADC off ADCChannel "'1'" hdl_port "on" has_advanced_control "0" sggui_pos "20,20,356,432" block_type "gatewayin" block_version "VER_STRING_GOES_HERE" sg_icon_stat "55,12,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 12 12 0 ],[0.95 0" ".93 0.65 ]);\nplot([0 55 55 0 0 ],[0 0 12 12 0 ]);\npatch([24.775 26.22 27.22 28.22 29.22 27.22 25.775 24.775 ]" ",[7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([25.775 27.22 26.22 24.775 25.775 ],[6.11 6.11 7." "11 7.11 6.11 ],[0.985 0.979 0.895 ]);\npatch([24.775 26.22 27.22 25.775 24.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1" " 1 1 ]);\npatch([25.775 29.22 28.22 27.22 26.22 24.775 25.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.985 0." "979 0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black" "');port_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');" "\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "RSSI" SID "578" Position [740, 108, 770, 122] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "radio4_RSSI" DstPort 1 } Line { SrcBlock "Debug" SrcPort 1 Points [40, 0; 0, 45] DstBlock "Mux" DstPort 1 } Line { SrcBlock "radio4_RSSI" SrcPort 1 DstBlock "Mux" DstPort 2 } Line { SrcBlock "Counter" SrcPort 1 DstBlock "Mux" DstPort 3 } Line { SrcBlock "Mux" SrcPort 1 DstBlock "RSSI" DstPort 1 } } } Block { BlockType Scope Name "Scope" SID "579" Ports [2] Position [800, 111, 830, 164] Floating off Location [5, 34, 1285, 912] Open off NumInputPorts "2" List { ListType AxesTitles axes1 "%" axes2 "%" } YMin "-5~-5" YMax "5~5" DataFormat "StructureWithTime" SampleTime "0" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Outport Name "Radio 4 RSSI" SID "580" Position [650, 418, 680, 432] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Outport Name "Radio 4 I/Q" SID "581" Position [865, 288, 895, 302] Port "2" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "ADC Q" SrcPort 2 Points [50, 0; 0, 25; 30, 0] Branch { DstBlock "Concatenates_1" DstPort 4 } Branch { Points [0, -215] DstBlock "Gateway Out1" DstPort 1 } } Line { SrcBlock "ADC Q" SrcPort 1 Points [0, 5] DstBlock "Concatenates_1" DstPort 3 } Line { SrcBlock "ADC I" SrcPort 2 Points [0, 20; 70, 0] Branch { DstBlock "Concatenates_1" DstPort 2 } Branch { Points [0, -150] DstBlock "Gateway Out4" DstPort 1 } } Line { SrcBlock "ADC I" SrcPort 1 DstBlock "Concatenates_1" DstPort 1 } Line { SrcBlock "Concatenates_1" SrcPort 1 Points [0, 0] DstBlock "Radio 4 I/Q" DstPort 1 } Line { SrcBlock "Gateway Out4" SrcPort 1 DstBlock "Scope" DstPort 1 } Line { SrcBlock "Gateway Out1" SrcPort 1 Points [25, 0] DstBlock "Scope" DstPort 2 } Line { SrcBlock "DebugRxBuffers" SrcPort 1 Points [150, 0] Branch { DstBlock "ADC I" DstPort 1 } Branch { Points [0, 75] Branch { DstBlock "ADC Q" DstPort 1 } Branch { Points [0, 115] DstBlock "RSSI" DstPort 1 } } } Line { SrcBlock "RSSI" SrcPort 1 DstBlock "Radio 4 RSSI" DstPort 1 } Line { SrcBlock "MGCAGC_AGCDCO_SEL" SrcPort 1 Points [115, 0] Branch { DstBlock "ADC Q" DstPort 2 } Branch { Points [0, -75] DstBlock "ADC I" DstPort 2 } } Annotation { Position [518, 257] } } } Block { BlockType SubSystem Name "Radio 4 Outputs" SID "582" Ports [1] Position [1180, 958, 1225, 1002] NamePlacement "alternate" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "Radio 4 Outputs" Location [60, 247, 880, 529] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "32b" SID "583" Position [145, 148, 175, 162] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "16LSB" SID "584" Ports [1, 1] Position [305, 147, 340, 163] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type " "is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardware " "notes: In hardware this block costs nothing." nbits "16" boolean_output off mode "Lower Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "593,46,442,407" block_type "slice" block_version "9.1.01" sg_icon_stat "35,16,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 16 16 0 ],[0.77 0.82 0.91" " ]);\nplot([0 35 35 0 0 ],[0 0 16 16 0 ]);\npatch([12.55 15.44 17.44 19.44 21.44 17.44 14.55 12.55 ],[10.22 10.22 1" "2.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([14.55 17.44 15.44 12.55 14.55 ],[8.22 8.22 10.22 10.22 8.22" " ],[0.931 0.946 0.973 ]);\npatch([12.55 15.44 17.44 14.55 12.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatch([14" ".55 21.44 19.44 17.44 15.44 12.55 14.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprintf(''," "'COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'[a" ":b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "16MSB" SID "585" Ports [1, 1] Position [305, 82, 345, 98] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Slice" SourceType "Xilinx Bit Slice Extractor Block" infoedit "Extracts a given range of bits from each input sample and presents it at the output. The output type " "is ordinarily unsigned with binary point at zero, but can be Boolean when the slice is one bit wide.

Hardware " "notes: In hardware this block costs nothing." nbits "16" boolean_output off mode "Upper Bit Location + Width" bit1 "0" base1 "MSB of Input" bit0 "0" base0 "LSB of Input" dbl_ovrd off has_advanced_control "0" sggui_pos "593,46,442,407" block_type "slice" block_version "9.1.01" sg_icon_stat "40,16,1,1,white,blue,0,1fd851a7,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 16 16 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 16 16 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[10.22 10.22 1" "2.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[8.22 8.22 10.22 10.22 8.22" " ],[0.931 0.946 0.973 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatch([17" ".55 24.44 22.44 20.44 18.44 15.55 17.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprintf(''," "'COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'[a" ":b]');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Radio 4 DAC I" SID "586" Ports [1, 1] Position [560, 69, 655, 111] LibraryVersion "1.48" LinkData { BlockName "Convert" DialogParameters { sg_icon_stat "45,30,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 30 30 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\npatch([13.1 18.88 22.88 26.88 30.88 22.88 17.1 13.1 ],[19.4" "4 19.44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([17.1 22.88 18.88 13.1 17.1 ],[15.44 15.44 19.4" "4 19.44 15.44 ],[0.931 0.946 0.973 ]);\npatch([13.1 18.88 22.88 17.1 13.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1" " 1 1 ]);\npatch([17.1 30.88 26.88 22.88 18.88 13.1 17.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946" " 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black'" ");port_label('output',1,'cast');\nfprintf('','COMMENT: end icon text');" } BlockName "radio4_dac_I" DialogParameters { sg_icon_stat "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0" ".93 0.65 ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[1" "2.22 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.2" "2 12.22 12.22 10.22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.2" "2 ],[1 1 1 ]);\npatch([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985" " 0.979 0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','o" "n');\nfprintf('','COMMENT: end icon text');" } } SourceBlock "WARP_Blockset/WARP Radio Board ADC//DACs/Radio 4 DAC I" SourceType "" ShowPortLabels "FromPortIcon" SystemSampleTime "-1" FunctionWithSeparateData off RTWMemSecFuncInitTerm "Inherit from model" RTWMemSecFuncExecute "Inherit from model" RTWMemSecDataConstants "Inherit from model" RTWMemSecDataInternal "Inherit from model" RTWMemSecDataParameters "Inherit from model" GeneratePreprocessorConditionals off } Block { BlockType Reference Name "Radio 4 DAC Q" SID "587" Ports [1, 1] Position [560, 134, 655, 176] LibraryVersion "1.48" LinkData { BlockName "Convert" DialogParameters { sg_icon_stat "45,30,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 30 30 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\npatch([13.1 18.88 22.88 26.88 30.88 22.88 17.1 13.1 ],[19.4" "4 19.44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([17.1 22.88 18.88 13.1 17.1 ],[15.44 15.44 19.4" "4 19.44 15.44 ],[0.931 0.946 0.973 ]);\npatch([13.1 18.88 22.88 17.1 13.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1" " 1 1 ]);\npatch([17.1 30.88 26.88 22.88 18.88 13.1 17.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946" " 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black'" ");port_label('output',1,'cast');\nfprintf('','COMMENT: end icon text');" } BlockName "radio4_dac_Q" DialogParameters { sg_icon_stat "60,20,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 20 20 0 ],[0.95 0" ".93 0.65 ]);\nplot([0 60 60 0 0 ],[0 0 20 20 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[1" "2.22 12.22 14.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[10.22 10.2" "2 12.22 12.22 10.22 ],[0.985 0.979 0.895 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[8.22 8.22 10.22 10.22 8.2" "2 ],[1 1 1 ]);\npatch([27.55 34.44 32.44 30.44 28.44 25.55 27.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.985" " 0.979 0.895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bl" "ack');port_label('input',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','o" "n');\nfprintf('','COMMENT: end icon text');" } } SourceBlock "WARP_Blockset/WARP Radio Board ADC//DACs/Radio 4 DAC Q" SourceType "" ShowPortLabels "FromPortIcon" SystemSampleTime "-1" FunctionWithSeparateData off RTWMemSecFuncInitTerm "Inherit from model" RTWMemSecFuncExecute "Inherit from model" RTWMemSecDataConstants "Inherit from model" RTWMemSecDataInternal "Inherit from model" RTWMemSecDataParameters "Inherit from model" GeneratePreprocessorConditionals off } Block { BlockType Reference Name "Register" SID "588" Ports [1, 1] Position [475, 79, 520, 101] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "568,185,356,193" block_type "register" block_version "9.1.01" sg_icon_stat "45,22,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 22 22 0 ],[0.77 0.82 0.91" " ]);\nplot([0 45 45 0 0 ],[0 0 22 22 0 ]);\npatch([15.325 19.66 22.66 25.66 28.66 22.66 18.325 15.325 ],[14.33 14.3" "3 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([18.325 22.66 19.66 15.325 18.325 ],[11.33 11.33 14.33 14" ".33 11.33 ],[0.931 0.946 0.973 ]);\npatch([15.325 19.66 22.66 18.325 15.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 1 1 " "]);\npatch([18.325 28.66 25.66 22.66 19.66 15.325 18.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label" "('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprint" "f('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register1" SID "589" Ports [1, 1] Position [475, 144, 520, 166] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "568,185,356,193" block_type "register" block_version "9.1.01" sg_icon_stat "45,22,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 22 22 0 ],[0.77 0.82 0.91" " ]);\nplot([0 45 45 0 0 ],[0 0 22 22 0 ]);\npatch([15.325 19.66 22.66 25.66 28.66 22.66 18.325 15.325 ],[14.33 14.3" "3 17.33 14.33 17.33 17.33 17.33 14.33 ],[1 1 1 ]);\npatch([18.325 22.66 19.66 15.325 18.325 ],[11.33 11.33 14.33 14" ".33 11.33 ],[0.931 0.946 0.973 ]);\npatch([15.325 19.66 22.66 18.325 15.325 ],[8.33 8.33 11.33 11.33 8.33 ],[1 1 1 " "]);\npatch([18.325 28.66 25.66 22.66 19.66 15.325 18.325 ],[5.33 5.33 8.33 5.33 8.33 8.33 5.33 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label" "('input',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprint" "f('','COMMENT: end icon text');" } Block { BlockType Reference Name "Reinterpret" SID "590" Ports [1, 1] Position [380, 81, 440, 99] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can changed the signal between s" "igned and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothing.

" "Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsigned wi" "th 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111000 in " "binary)." force_arith_type on arith_type "Signed (2's comp)" force_bin_pt on bin_pt "15" has_advanced_control "0" sggui_pos "436,54,356,309" block_type "reinterpret" block_version "9.1.01" sg_icon_stat "60,18,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.91" " ]);\nplot([0 60 60 0 0 ],[0 0 18 18 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[11.22 11.22 1" "3.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[9.22 9.22 11.22 11.22 9.22" " ],[0.931 0.946 0.973 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([27" ".55 34.44 32.44 30.44 28.44 25.55 27.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf(''," "'COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('reinterpret');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Reinterpret1" SID "591" Ports [1, 1] Position [380, 146, 440, 164] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Reinterpret" SourceType "Xilinx Type Reinterpreter Block" infoedit "Changes signal type without altering the binary representation. You can changed the signal between s" "igned and unsigned, and relocate the binary point.

Hardware notes: In hardware this block costs nothing.

" "Example: Suppose the input is 6 bits wide, signed, with 2 fractional bits, and the output is forced to unsigned wi" "th 0 fractional bits. Then an input of -2.0 (1110.00 in binary 2's complement) becomes an output of 56 (111000 in " "binary)." force_arith_type on arith_type "Signed (2's comp)" force_bin_pt on bin_pt "15" has_advanced_control "0" sggui_pos "436,54,356,309" block_type "reinterpret" block_version "9.1.01" sg_icon_stat "60,18,1,1,white,blue,0,6b04d0b0,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 60 60 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.91" " ]);\nplot([0 60 60 0 0 ],[0 0 18 18 0 ]);\npatch([25.55 28.44 30.44 32.44 34.44 30.44 27.55 25.55 ],[11.22 11.22 1" "3.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([27.55 30.44 28.44 25.55 27.55 ],[9.22 9.22 11.22 11.22 9.22" " ],[0.931 0.946 0.973 ]);\npatch([25.55 28.44 30.44 27.55 25.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([27" ".55 34.44 32.44 30.44 28.44 25.55 27.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf(''," "'COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('reinterpret');\nf" "printf('','COMMENT: end icon text');" } Block { BlockType Terminator Name "Terminator" SID "592" Position [680, 80, 700, 100] ShowName off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Terminator Name "Terminator1" SID "593" Position [685, 145, 705, 165] ShowName off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "32b" SrcPort 1 Points [85, 0] Branch { DstBlock "16LSB" DstPort 1 } Branch { Points [0, -65] DstBlock "16MSB" DstPort 1 } } Line { SrcBlock "16MSB" SrcPort 1 DstBlock "Reinterpret" DstPort 1 } Line { SrcBlock "16LSB" SrcPort 1 DstBlock "Reinterpret1" DstPort 1 } Line { SrcBlock "Reinterpret" SrcPort 1 DstBlock "Register" DstPort 1 } Line { SrcBlock "Reinterpret1" SrcPort 1 DstBlock "Register1" DstPort 1 } Line { SrcBlock "Register" SrcPort 1 DstBlock "Radio 4 DAC I" DstPort 1 } Line { SrcBlock "Register1" SrcPort 1 DstBlock "Radio 4 DAC Q" DstPort 1 } Line { SrcBlock "Radio 4 DAC I" SrcPort 1 DstBlock "Terminator" DstPort 1 } Line { SrcBlock "Radio 4 DAC Q" SrcPort 1 DstBlock "Terminator1" DstPort 1 } } } Block { BlockType Reference Name "Register" SID "594" Ports [1, 1] Position [250, 1006, 285, 1034] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst off en off dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "8.2" sg_icon_stat "35,28,1,1,white,blue,0,c80657c5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 28 28 0 ],[0.77 0." "82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 28 28 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[18.44 18" ".44 22.44 18.44 22.44 22.44 22.44 18.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[14.44 14.44 18.44 18.4" "4 14.44 ],[0.931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[10.44 10.44 14.44 14.44 10.44 ],[1 1 1 ]);\n" "patch([12.1 25.88 21.88 17.88 13.88 8.1 12.1 ],[6.44 6.44 10.44 6.44 10.44 10.44 6.44 ],[0.931 0.946 0.973 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('i" "nput',1,'d');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode','on');\nfprint" "f('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "Rx Control" SID "595" Ports [1, 2] Position [415, 224, 510, 266] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "Rx Control" Location [2, 74, 1270, 710] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "159" Block { BlockType Inport Name "Start" SID "596" Position [15, 298, 45, 312] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Convert" SID "597" Ports [1, 1] Position [635, 162, 665, 178] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,461,334" block_type "convert" block_version "10.1.2" sg_icon_stat "30,16,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 16 16 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 16 16 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[10.22 10.22 1" "2.22 10.22 12.22 12.22 12.22 10.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[8.22 8.22 10.22 10.22 8.22" " ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[6.22 6.22 8.22 8.22 6.22 ],[1 1 1 ]);\npatch([12" ".55 19.44 17.44 15.44 13.44 10.55 12.55 ],[4.22 4.22 6.22 4.22 6.22 6.22 4.22 ],[0.931 0.946 0.973 ]);\nfprintf(''," "'COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'ca" "st');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out1" SID "598" Ports [1, 1] Position [585, 25, 615, 35] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, double, o" "r fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarded, depen" "ding on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" UseAsDAC off DACChannel "'1'" has_advanced_control "0" sggui_pos "20,20,336,386" block_type "gatewayout" block_version "10.1.2" sg_icon_stat "30,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 10 10 0 ],[0.88 0.88 0.88" " ]);\nplot([0 30 30 0 0 ],[0 0 10 10 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ],[6.11 6.11 " "7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[5.11 5.11 6.11 6.11 5.11 ],[" "0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]);\npatch([13." "775 17.22 16.22 15.22 14.22 12.775 13.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.964 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ')" ";\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" } Block { BlockType Reference Name "Gateway Out2" SID "599" Ports [1, 1] Position [585, 40, 615, 50] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, double, o" "r fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarded, depen" "ding on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" UseAsDAC off DACChannel "'1'" has_advanced_control "0" sggui_pos "20,20,336,386" block_type "gatewayout" block_version "10.1.2" sg_icon_stat "30,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 10 10 0 ],[0.88 0.88 0.88" " ]);\nplot([0 30 30 0 0 ],[0 0 10 10 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ],[6.11 6.11 " "7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[5.11 5.11 6.11 6.11 5.11 ],[" "0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]);\npatch([13." "775 17.22 16.22 15.22 14.22 12.775 13.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.964 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ')" ";\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" } Block { BlockType Reference Name "Gateway Out3" SID "600" Ports [1, 1] Position [585, 55, 615, 65] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, double, o" "r fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarded, depen" "ding on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" UseAsDAC off DACChannel "'1'" has_advanced_control "0" sggui_pos "20,20,336,386" block_type "gatewayout" block_version "10.1.2" sg_icon_stat "30,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 10 10 0 ],[0.88 0.88 0.88" " ]);\nplot([0 30 30 0 0 ],[0 0 10 10 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ],[6.11 6.11 " "7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[5.11 5.11 6.11 6.11 5.11 ],[" "0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]);\npatch([13." "775 17.22 16.22 15.22 14.22 12.775 13.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.964 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ')" ";\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" } Block { BlockType Reference Name "Gateway Out4" SID "601" Ports [1, 1] Position [585, 70, 615, 80] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, double, o" "r fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarded, depen" "ding on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" UseAsDAC off DACChannel "'1'" has_advanced_control "0" sggui_pos "20,20,336,386" block_type "gatewayout" block_version "10.1.2" sg_icon_stat "30,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 10 10 0 ],[0.88 0.88 0.88" " ]);\nplot([0 30 30 0 0 ],[0 0 10 10 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ],[6.11 6.11 " "7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[5.11 5.11 6.11 6.11 5.11 ],[" "0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]);\npatch([13." "775 17.22 16.22 15.22 14.22 12.775 13.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.964 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ')" ";\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" } Block { BlockType Reference Name "Gateway Out5" SID "602" Ports [1, 1] Position [585, 85, 615, 95] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, double, o" "r fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarded, depen" "ding on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" UseAsDAC off DACChannel "'1'" has_advanced_control "0" sggui_pos "20,20,336,386" block_type "gatewayout" block_version "10.1.2" sg_icon_stat "30,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 10 10 0 ],[0.88 0.88 0.88" " ]);\nplot([0 30 30 0 0 ],[0 0 10 10 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ],[6.11 6.11 " "7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[5.11 5.11 6.11 6.11 5.11 ],[" "0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]);\npatch([13." "775 17.22 16.22 15.22 14.22 12.775 13.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.964 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ')" ";\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" } Block { BlockType Goto Name "Goto2" SID "603" Position [695, 160, 825, 180] ShowName off GotoTag "CAPTURE_IS_DONE" TagVisibility "global" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Inverter1" SID "604" Ports [1, 1] Position [360, 281, 385, 299] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "8.2" sg_icon_stat "25,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13.2" "2 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ],[0." "931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16.44 " "14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: en" "d icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nfprintf('','COMMENT: " "end icon text');" } Block { BlockType Reference Name "Inverter2" SID "605" Ports [1, 1] Position [570, 161, 595, 179] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "8.2" sg_icon_stat "25,18,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13.2" "2 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ],[0." "931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16.44 " "14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: en" "d icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nfprintf('','COMMENT: " "end icon text');" } Block { BlockType Reference Name "Relational1" SID "606" Ports [2, 1] Position [425, 354, 470, 401] BlockMirror on NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a>=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "relational" block_version "8.2" sg_icon_stat "45,47,2,1,white,blue,0,6218dc92,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 47 47 0 ],[0.77 0.82 0.91" " ]);\nplot([0 45 45 0 0 ],[0 0 47 47 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[29.66 29.66 35." "66 29.66 35.66 35.66 35.66 29.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[23.66 23.66 29.66 29.66 23.66" " ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[17.66 17.66 23.66 23.66 17.66 ],[1 1 1 ]);\npatch(" "[14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[11.66 11.66 17.66 11.66 17.66 17.66 11.66 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'" ",1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa \\geq b','texmode'" ",'on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Rx Addr Counter1" SID "607" Ports [2, 1] Position [425, 276, 465, 329] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited counter is" " implemented by combining a counter with a comparator." cnt_type "Free Running" cnt_to "Inf" operation "Up" start_count "0" cnt_by_val "1" arith_type "Unsigned" n_bits "14" bin_pt "0" load_pin off rst on en on explicit_period "off" period "1" dbl_ovrd off use_behavioral_HDL off implementation "Fabric" xl_use_area off xl_area "[0,0,0,0,0,0,0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,356,630" block_type "counter" block_version "8.2" sg_icon_stat "40,53,2,1,white,blue,0,ae3608d6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 53 53 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 53 53 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[31.55 31.55 36.55" " 31.55 36.55 36.55 36.55 31.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[26.55 26.55 31.55 31.55 26.55 " "],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[21.55 21.55 26.55 26.55 21.55 ],[1 1 1 ]);\npatch(" "[13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[16.55 16.55 21.55 16.55 21.55 21.55 16.55 ],[0.931 0.946 0.973 ]);\nfpr" "intf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,'rst');\ncolor('black');port_label('input',2,'en');\n\ncolor('black');disp('{\\fontsize{14}\\bf++}','texmode','on" "');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Scope Name "Rx Control" SID "608" Ports [5] Position [665, 22, 695, 98] Floating off Location [5, 34, 1285, 742] Open off NumInputPorts "5" ZoomMode "yonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" } TimeRange "70000" YMin "0~0~0~0~0" YMax "1~1~1~1~20000" SaveName "ScopeData1" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType SubSystem Name "S-R Latch1" SID "609" Ports [2, 1] Position [225, 297, 265, 333] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "S-R Latch1" Location [2, 74, 1184, 1000] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "S" SID "610" Position [125, 198, 155, 212] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "R" SID "611" Position [125, 178, 155, 192] NamePlacement "alternate" Port "2" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Convert" SID "612" Ports [1, 1] Position [200, 178, 230, 192] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do" " not." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "16" bin_pt "14" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,374,375" block_type "convert" block_version "8.2" sg_icon_stat "30,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 14 14 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 14 14 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[9" ".22 9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[7.22 7.22 9.22" " 9.22 7.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 " "]);\npatch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');por" "t_label('output',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert1" SID "613" Ports [1, 1] Position [200, 198, 230, 212] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do" " not." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "16" bin_pt "14" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,374,375" block_type "convert" block_version "8.2" sg_icon_stat "30,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 14 14 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 14 14 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[9" ".22 9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[7.22 7.22 9.22" " 9.22 7.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 " "]);\npatch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');por" "t_label('output',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register" SID "614" Ports [3, 1] Position [280, 153, 330, 217] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "8.2" sg_icon_stat "50,64,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 64 64 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 64 64 0 ]);\npatch([9.425 19.54 26.54 33.54 40.54 26.54 16.425 9.425 ],[" "39.77 39.77 46.77 39.77 46.77 46.77 46.77 39.77 ],[1 1 1 ]);\npatch([16.425 26.54 19.54 9.425 16.425 ],[32.77 3" "2.77 39.77 39.77 32.77 ],[0.931 0.946 0.973 ]);\npatch([9.425 19.54 26.54 16.425 9.425 ],[25.77 25.77 32.77 32." "77 25.77 ],[1 1 1 ]);\npatch([16.425 40.54 33.54 26.54 19.54 9.425 16.425 ],[18.77 18.77 25.77 18.77 25.77 25.7" "7 18.77 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon te" "xt');\ncolor('black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');p" "ort_label('input',3,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode'," "'on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "zero3" SID "615" Ports [0, 1] Position [215, 156, 235, 174] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "20,18,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 20 20 0 0 ],[0 0 18 18 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[9.22 9.22 11.22 11" ".22 9.22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\np" "atch([7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfpr" "intf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('out" "put',1,'1');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "616" Position [395, 178, 425, 192] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "Register" DstPort 3 } Line { SrcBlock "Convert" SrcPort 1 DstBlock "Register" DstPort 2 } Line { SrcBlock "Register" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "S" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "R" SrcPort 1 DstBlock "Convert" DstPort 1 } Line { SrcBlock "zero3" SrcPort 1 DstBlock "Register" DstPort 1 } } } Block { BlockType Reference Name "zero3" SID "617" Ports [0, 1] Position [510, 380, 565, 400] BlockMirror on NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "2^14-1" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "14" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "20,20,400,346" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "55,20,0,1,white,blue,0,fddc9e01,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 20 20 0 ],[0.77 0.82 0.91" " ]);\nplot([0 55 55 0 0 ],[0 0 20 20 0 ]);\npatch([22.55 25.44 27.44 29.44 31.44 27.44 24.55 22.55 ],[12.22 12.22 1" "4.22 12.22 14.22 14.22 14.22 12.22 ],[1 1 1 ]);\npatch([24.55 27.44 25.44 22.55 24.55 ],[10.22 10.22 12.22 12.22 10" ".22 ],[0.931 0.946 0.973 ]);\npatch([22.55 25.44 27.44 24.55 22.55 ],[8.22 8.22 10.22 10.22 8.22 ],[1 1 1 ]);\npatc" "h([24.55 31.44 29.44 27.44 25.44 22.55 24.55 ],[6.22 6.22 8.22 6.22 8.22 8.22 6.22 ],[0.931 0.946 0.973 ]);\nfprint" "f('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1," "'16383');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "WrAddr" SID "618" Position [730, 298, 760, 312] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Outport Name "WrEn" SID "619" Position [730, 233, 760, 247] Port "2" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "Start" SrcPort 1 Points [145, 0] Branch { DstBlock "S-R Latch1" DstPort 1 } Branch { Points [0, -275] DstBlock "Gateway Out1" DstPort 1 } } Line { SrcBlock "S-R Latch1" SrcPort 1 Points [60, 0] Branch { DstBlock "Rx Addr Counter1" DstPort 2 } Branch { Points [0, -25] Branch { DstBlock "Inverter1" DstPort 1 } Branch { Points [0, -50] Branch { Points [200, 0] Branch { DstBlock "WrEn" DstPort 1 } Branch { Points [0, -70] DstBlock "Inverter2" DstPort 1 } } Branch { Points [0, -180] DstBlock "Gateway Out3" DstPort 1 } } } } Line { SrcBlock "Inverter1" SrcPort 1 Points [15, 0] Branch { DstBlock "Rx Addr Counter1" DstPort 1 } Branch { Points [0, -215] DstBlock "Gateway Out4" DstPort 1 } } Line { SrcBlock "Rx Addr Counter1" SrcPort 1 Points [45, 0] Branch { Points [0, 60] DstBlock "Relational1" DstPort 1 } Branch { DstBlock "WrAddr" DstPort 1 } Branch { Points [0, -215] DstBlock "Gateway Out5" DstPort 1 } } Line { SrcBlock "Gateway Out5" SrcPort 1 DstBlock "Rx Control" DstPort 5 } Line { SrcBlock "Gateway Out4" SrcPort 1 DstBlock "Rx Control" DstPort 4 } Line { SrcBlock "Gateway Out3" SrcPort 1 DstBlock "Rx Control" DstPort 3 } Line { SrcBlock "Gateway Out2" SrcPort 1 DstBlock "Rx Control" DstPort 2 } Line { SrcBlock "Gateway Out1" SrcPort 1 DstBlock "Rx Control" DstPort 1 } Line { SrcBlock "zero3" SrcPort 1 DstBlock "Relational1" DstPort 2 } Line { SrcBlock "Relational1" SrcPort 1 Points [-220, 0; 0, -55] Branch { DstBlock "S-R Latch1" DstPort 2 } Branch { Points [0, -280] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "Inverter2" SrcPort 1 DstBlock "Convert" DstPort 1 } Line { SrcBlock "Convert" SrcPort 1 DstBlock "Goto2" DstPort 1 } } } Block { BlockType Reference Name "StartCapture" SID "620" Ports [1, 1] Position [120, 214, 175, 226] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, double and fixed point to Xilinx " "fixed point type.

Hardware notes: In hardware these blocks become top level input ports." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off UseAsADC off ADCChannel "'1'" hdl_port "on" has_advanced_control "0" sggui_pos "20,20,356,432" block_type "gatewayin" block_version "VER_STRING_GOES_HERE" sg_icon_stat "55,12,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 12 12 0 ],[0.95 0." "93 0.65 ]);\nplot([0 55 55 0 0 ],[0 0 12 12 0 ]);\npatch([24.775 26.22 27.22 28.22 29.22 27.22 25.775 24.775 ],[" "7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([25.775 27.22 26.22 24.775 25.775 ],[6.11 6.11 7.11 " "7.11 6.11 ],[0.985 0.979 0.895 ]);\npatch([24.775 26.22 27.22 25.775 24.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1" " ]);\npatch([25.775 29.22 28.22 27.22 26.22 24.775 25.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.985 0.979 0" ".895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');por" "t_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprin" "tf('','COMMENT: end icon text');" } Block { BlockType Reference Name "StartTx" SID "621" Ports [1, 1] Position [160, 654, 215, 666] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, double and fixed point to Xilinx " "fixed point type.

Hardware notes: In hardware these blocks become top level input ports." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off UseAsADC off ADCChannel "'1'" hdl_port "on" has_advanced_control "0" sggui_pos "20,20,356,432" block_type "gatewayin" block_version "VER_STRING_GOES_HERE" sg_icon_stat "55,12,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 12 12 0 ],[0.95 0." "93 0.65 ]);\nplot([0 55 55 0 0 ],[0 0 12 12 0 ]);\npatch([24.775 26.22 27.22 28.22 29.22 27.22 25.775 24.775 ],[" "7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([25.775 27.22 26.22 24.775 25.775 ],[6.11 6.11 7.11 " "7.11 6.11 ],[0.985 0.979 0.895 ]);\npatch([24.775 26.22 27.22 25.775 24.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1" " ]);\npatch([25.775 29.22 28.22 27.22 26.22 24.775 25.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.985 0.979 0" ".895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');por" "t_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprin" "tf('','COMMENT: end icon text');" } Block { BlockType Reference Name "StopTx" SID "622" Ports [1, 1] Position [160, 739, 215, 751] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway In" SourceType "Xilinx Gateway In Block" infoedit "Gateway in block. Converts inputs of type Simulink integer, double and fixed point to Xilinx " "fixed point type.

Hardware notes: In hardware these blocks become top level input ports." gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" quantization "Round (unbiased: +/- Inf)" overflow "Saturate" period "1" dbl_ovrd off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" inherit_from_input off UseAsADC off ADCChannel "'1'" hdl_port "on" has_advanced_control "0" sggui_pos "20,20,356,432" block_type "gatewayin" block_version "VER_STRING_GOES_HERE" sg_icon_stat "55,12,1,1,white,yellow,1,00d3666e,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 12 12 0 ],[0.95 0." "93 0.65 ]);\nplot([0 55 55 0 0 ],[0 0 12 12 0 ]);\npatch([24.775 26.22 27.22 28.22 29.22 27.22 25.775 24.775 ],[" "7.11 7.11 8.11 7.11 8.11 8.11 8.11 7.11 ],[1 1 1 ]);\npatch([25.775 27.22 26.22 24.775 25.775 ],[6.11 6.11 7.11 " "7.11 6.11 ],[0.985 0.979 0.895 ]);\npatch([24.775 26.22 27.22 25.775 24.775 ],[5.11 5.11 6.11 6.11 5.11 ],[1 1 1" " ]);\npatch([25.775 29.22 28.22 27.22 26.22 24.775 25.775 ],[4.11 4.11 5.11 4.11 5.11 5.11 4.11 ],[0.985 0.979 0" ".895 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');por" "t_label('input',1,'\\fontsize{11pt}\\bf In ','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprin" "tf('','COMMENT: end icon text');" } Block { BlockType Terminator Name "Terminator" SID "623" Position [260, 945, 280, 965] ShowName off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType SubSystem Name "Tx Control" SID "624" Ports [4, 2] Position [570, 650, 680, 715] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "Tx Control" Location [2, 74, 1254, 710] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "StartTx" SID "625" Position [390, 368, 420, 382] NamePlacement "alternate" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "StopTx" SID "626" Position [145, 423, 175, 437] Port "2" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "ContinuousTx" SID "627" Position [150, 353, 180, 367] Port "3" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "TxDelay" SID "628" Position [750, 413, 780, 427] Port "4" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Convert1" SID "629" Ports [1, 1] Position [470, 366, 500, 384] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,461,375" block_type "convert" block_version "9.1.01" sg_icon_stat "30,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 18 18 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[11.22 11.22 1" "3.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[9.22 9.22 11.22 11.22 9.22" " ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([12" ".55 19.44 17.44 15.44 13.44 10.55 12.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf(''," "'COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'ca" "st');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert2" SID "630" Ports [1, 1] Position [230, 421, 260, 439] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do not." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,461,375" block_type "convert" block_version "9.1.01" sg_icon_stat "30,18,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.91" " ]);\nplot([0 30 30 0 0 ],[0 0 18 18 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[11.22 11.22 1" "3.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[9.22 9.22 11.22 11.22 9.22" " ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([12" ".55 19.44 17.44 15.44 13.44 10.55 12.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf(''," "'COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');port_label('output',1,'ca" "st');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "From Register4" SID "631" Ports [0, 1] Position [1230, 220, 1275, 250] BlockMirror on NamePlacement "alternate" ShowName off AttributesFormatString "TxLength\\n<< % >>" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/From Register" SourceType "Xilinx Shared Memory Based From Register Block" infoedit "Register block that reads data to a shared memory register. Delay of one sample period." shared_memory_name "'TxLength'" init "2^14-1" period "1" ownership "Locally owned and initialized" gui_display_data_type "Fixed-point" arith_type "Unsigned" n_bits "14" bin_pt "0" preci_type "Single" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,381,246" block_type "fromreg" block_version "8.2" sg_icon_stat "45,30,0,1,white,blue,0,b27a07ff,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 30 30 0 ],[0.77 0.82 0.91" " ]);\nplot([0 45 45 0 0 ],[0 0 30 30 0 ]);\npatch([13.1 18.88 22.88 26.88 30.88 22.88 17.1 13.1 ],[19.44 19.44 23.4" "4 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([17.1 22.88 18.88 13.1 17.1 ],[15.44 15.44 19.44 19.44 15.44 ]," "[0.931 0.946 0.973 ]);\npatch([13.1 18.88 22.88 17.1 13.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 ]);\npatch([17." "1 30.88 26.88 22.88 18.88 13.1 17.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973 ]);\nfprintf('','" "COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('output',1,'dout'" ");\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Gateway Out1" SID "632" Ports [1, 1] Position [1295, 620, 1325, 630] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, double, o" "r fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarded, depen" "ding on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" UseAsDAC off DACChannel "'1'" has_advanced_control "0" sggui_pos "20,20,336,386" block_type "gatewayout" block_version "10.1.2" sg_icon_stat "30,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 10 10 0 ],[0.88 0.88 0.88" " ]);\nplot([0 30 30 0 0 ],[0 0 10 10 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ],[6.11 6.11 " "7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[5.11 5.11 6.11 6.11 5.11 ],[" "0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]);\npatch([13." "775 17.22 16.22 15.22 14.22 12.775 13.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.964 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ')" ";\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" } Block { BlockType Reference Name "Gateway Out2" SID "633" Ports [1, 1] Position [1295, 635, 1325, 645] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, double, o" "r fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarded, depen" "ding on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" UseAsDAC off DACChannel "'1'" has_advanced_control "0" sggui_pos "20,20,336,386" block_type "gatewayout" block_version "10.1.2" sg_icon_stat "30,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 10 10 0 ],[0.88 0.88 0.88" " ]);\nplot([0 30 30 0 0 ],[0 0 10 10 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ],[6.11 6.11 " "7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[5.11 5.11 6.11 6.11 5.11 ],[" "0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]);\npatch([13." "775 17.22 16.22 15.22 14.22 12.775 13.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.964 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ')" ";\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" } Block { BlockType Reference Name "Gateway Out3" SID "634" Ports [1, 1] Position [1295, 650, 1325, 660] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, double, o" "r fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarded, depen" "ding on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" UseAsDAC off DACChannel "'1'" has_advanced_control "0" sggui_pos "20,20,336,386" block_type "gatewayout" block_version "10.1.2" sg_icon_stat "30,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 10 10 0 ],[0.88 0.88 0.88" " ]);\nplot([0 30 30 0 0 ],[0 0 10 10 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ],[6.11 6.11 " "7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[5.11 5.11 6.11 6.11 5.11 ],[" "0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]);\npatch([13." "775 17.22 16.22 15.22 14.22 12.775 13.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.964 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ')" ";\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" } Block { BlockType Reference Name "Gateway Out4" SID "635" Ports [1, 1] Position [1295, 665, 1325, 675] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, double, o" "r fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarded, depen" "ding on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" UseAsDAC off DACChannel "'1'" has_advanced_control "0" sggui_pos "20,20,336,386" block_type "gatewayout" block_version "10.1.2" sg_icon_stat "30,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 10 10 0 ],[0.88 0.88 0.88" " ]);\nplot([0 30 30 0 0 ],[0 0 10 10 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ],[6.11 6.11 " "7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[5.11 5.11 6.11 6.11 5.11 ],[" "0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]);\npatch([13." "775 17.22 16.22 15.22 14.22 12.775 13.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.964 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ')" ";\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" } Block { BlockType Reference Name "Gateway Out5" SID "636" Ports [1, 1] Position [1295, 680, 1325, 690] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, double, o" "r fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarded, depen" "ding on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" UseAsDAC off DACChannel "'1'" has_advanced_control "0" sggui_pos "20,20,336,386" block_type "gatewayout" block_version "10.1.2" sg_icon_stat "30,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 10 10 0 ],[0.88 0.88 0.88" " ]);\nplot([0 30 30 0 0 ],[0 0 10 10 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ],[6.11 6.11 " "7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[5.11 5.11 6.11 6.11 5.11 ],[" "0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]);\npatch([13." "775 17.22 16.22 15.22 14.22 12.775 13.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.964 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ')" ";\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" } Block { BlockType Reference Name "Gateway Out6" SID "637" Ports [1, 1] Position [1295, 695, 1325, 705] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, double, o" "r fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarded, depen" "ding on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" UseAsDAC off DACChannel "'1'" has_advanced_control "0" sggui_pos "20,20,336,386" block_type "gatewayout" block_version "10.1.2" sg_icon_stat "30,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 10 10 0 ],[0.88 0.88 0.88" " ]);\nplot([0 30 30 0 0 ],[0 0 10 10 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ],[6.11 6.11 " "7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[5.11 5.11 6.11 6.11 5.11 ],[" "0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]);\npatch([13." "775 17.22 16.22 15.22 14.22 12.775 13.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.964 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ')" ";\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" } Block { BlockType Reference Name "Gateway Out7" SID "638" Ports [1, 1] Position [1295, 710, 1325, 720] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, double, o" "r fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarded, depen" "ding on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" UseAsDAC off DACChannel "'1'" has_advanced_control "0" sggui_pos "20,20,336,386" block_type "gatewayout" block_version "10.1.2" sg_icon_stat "30,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 10 10 0 ],[0.88 0.88 0.88" " ]);\nplot([0 30 30 0 0 ],[0 0 10 10 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ],[6.11 6.11 " "7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[5.11 5.11 6.11 6.11 5.11 ],[" "0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]);\npatch([13." "775 17.22 16.22 15.22 14.22 12.775 13.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.964 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ')" ";\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" } Block { BlockType Reference Name "Gateway Out8" SID "639" Ports [1, 1] Position [1295, 725, 1325, 735] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, double, o" "r fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discarded, depen" "ding on how they are configured." inherit_from_input off hdl_port off timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" UseAsDAC off DACChannel "'1'" has_advanced_control "0" sggui_pos "20,20,336,386" block_type "gatewayout" block_version "10.1.2" sg_icon_stat "30,10,1,1,white,grey,1,632ec840,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 10 10 0 ],[0.88 0.88 0.88" " ]);\nplot([0 30 30 0 0 ],[0 0 10 10 0 ]);\npatch([12.775 14.22 15.22 16.22 17.22 15.22 13.775 12.775 ],[6.11 6.11 " "7.11 6.11 7.11 7.11 7.11 6.11 ],[1 1 1 ]);\npatch([13.775 15.22 14.22 12.775 13.775 ],[5.11 5.11 6.11 6.11 5.11 ],[" "0.964 0.964 0.964 ]);\npatch([12.775 14.22 15.22 13.775 12.775 ],[4.11 4.11 5.11 5.11 4.11 ],[1 1 1 ]);\npatch([13." "775 17.22 16.22 15.22 14.22 12.775 13.775 ],[3.11 3.11 4.11 3.11 4.11 4.11 3.11 ],[0.964 0.964 0.964 ]);\nfprintf('" "','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input',1,' ')" ";\ncolor('black');port_label('output',1,'\\fontsize{11pt} Out ','texmode','on');\nfprintf('','COMMENT: end icon tex" "t');" } Block { BlockType Reference Name "Inverter" SID "640" Ports [1, 1] Position [765, 476, 790, 494] BlockMirror on NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "inv" block_version "8.2" sg_icon_stat "25,18,1,1,white,blue,0,267846e5,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 25 25 0 0 ],[0 0 18 18 0 ],[0.77 0.82 0.91" " ]);\nplot([0 25 25 0 0 ],[0 0 18 18 0 ]);\npatch([7.55 10.44 12.44 14.44 16.44 12.44 9.55 7.55 ],[11.22 11.22 13.2" "2 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([9.55 12.44 10.44 7.55 9.55 ],[9.22 9.22 11.22 11.22 9.22 ],[0." "931 0.946 0.973 ]);\npatch([7.55 10.44 12.44 9.55 7.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\npatch([9.55 16.44 " "14.44 12.44 10.44 7.55 9.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: en" "d icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');disp('not');\nfprintf('','COMMENT: " "end icon text');" } Block { BlockType Reference Name "Logical" SID "641" Ports [2, 1] Position [665, 376, 700, 409] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,261" block_type "logical" block_version "8.2" sg_icon_stat "35,33,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 33 33 0 ],[0.77 0.82 0.91" " ]);\nplot([0 35 35 0 0 ],[0 0 33 33 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[20.44 20.44 24.44 " "20.44 24.44 24.44 24.44 20.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[16.44 16.44 20.44 20.44 16.44 ],[0." "931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[12.44 12.44 16.44 16.44 12.44 ],[1 1 1 ]);\npatch([12.1 25." "88 21.88 17.88 13.88 8.1 12.1 ],[8.44 8.44 12.44 8.44 12.44 12.44 8.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('and');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Reference Name "Logical1" SID "642" Ports [2, 1] Position [970, 326, 1005, 359] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,261" block_type "logical" block_version "8.2" sg_icon_stat "35,33,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 33 33 0 ],[0.77 0.82 0.91" " ]);\nplot([0 35 35 0 0 ],[0 0 33 33 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[20.44 20.44 24.44 " "20.44 24.44 24.44 24.44 20.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[16.44 16.44 20.44 20.44 16.44 ],[0." "931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[12.44 12.44 16.44 16.44 12.44 ],[1 1 1 ]);\npatch([12.1 25." "88 21.88 17.88 13.88 8.1 12.1 ],[8.44 8.44 12.44 8.44 12.44 12.44 8.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('and');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Reference Name "Logical2" SID "643" Ports [2, 1] Position [645, 216, 680, 249] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "OR" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,261" block_type "logical" block_version "8.2" sg_icon_stat "35,33,2,1,white,blue,0,7ede7d88,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 33 33 0 ],[0.77 0.82 0.91" " ]);\nplot([0 35 35 0 0 ],[0 0 33 33 0 ]);\npatch([8.1 13.88 17.88 21.88 25.88 17.88 12.1 8.1 ],[20.44 20.44 24.44 " "20.44 24.44 24.44 24.44 20.44 ],[1 1 1 ]);\npatch([12.1 17.88 13.88 8.1 12.1 ],[16.44 16.44 20.44 20.44 16.44 ],[0." "931 0.946 0.973 ]);\npatch([8.1 13.88 17.88 12.1 8.1 ],[12.44 12.44 16.44 16.44 12.44 ],[1 1 1 ]);\npatch([12.1 25." "88 21.88 17.88 13.88 8.1 12.1 ],[8.44 8.44 12.44 8.44 12.44 12.44 8.44 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMEN" "T: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\ncolor('black');disp('or');\nfprintf('','COM" "MENT: end icon text');" } Block { BlockType SubSystem Name "Posedge2" SID "644" Ports [1, 1] Position [570, 233, 605, 247] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "Posedge2" Location [132, 719, 452, 817] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "D" SID "645" Position [25, 33, 55, 47] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Delay" SID "646" Ports [1, 1] Position [145, 45, 175, 75] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Delay" SourceType "Xilinx Delay Block" infoedit "Hardware notes: A delay line is a chain, each link of which is an SRL16 followed by a flip-flo" "p. If register retiming is enabled, the delay line is a chain of flip-flops." rst off infoeditControl "Selection of Reset will increase slice count due to use of real FFs and instead of SRLs" en off latency "1" dbl_ovrd off reg_retiming off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "delay" block_version "8.2" sg_icon_stat "30,30,1,1,white,blue,0,07b98262,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 30 30 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 30 30 0 ]);\npatch([6.1 11.88 15.88 19.88 23.88 15.88 10.1 6.1 ],[19.44 " "19.44 23.44 19.44 23.44 23.44 23.44 19.44 ],[1 1 1 ]);\npatch([10.1 15.88 11.88 6.1 10.1 ],[15.44 15.44 19.44 1" "9.44 15.44 ],[0.931 0.946 0.973 ]);\npatch([6.1 11.88 15.88 10.1 6.1 ],[11.44 11.44 15.44 15.44 11.44 ],[1 1 1 " "]);\npatch([10.1 23.88 19.88 15.88 11.88 6.1 10.1 ],[7.44 7.44 11.44 7.44 11.44 11.44 7.44 ],[0.931 0.946 0.973" " ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\ncolor('black');di" "sp('z^{-1}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Inverter" SID "647" Ports [1, 1] Position [90, 47, 120, 73] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Inverter" SourceType "Xilinx Inverter Block" infoedit "Bitwise logical negation (one's complement) operator." en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,251" block_type "inv" block_version "8.2" sg_icon_stat "30,26,1,1,white,blue,0,267846e5,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 26 26 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 26 26 0 ]);\npatch([8.325 12.66 15.66 18.66 21.66 15.66 11.325 8.325 ],[" "16.33 16.33 19.33 16.33 19.33 19.33 19.33 16.33 ],[1 1 1 ]);\npatch([11.325 15.66 12.66 8.325 11.325 ],[13.33 1" "3.33 16.33 16.33 13.33 ],[0.931 0.946 0.973 ]);\npatch([8.325 12.66 15.66 11.325 8.325 ],[10.33 10.33 13.33 13." "33 10.33 ],[1 1 1 ]);\npatch([11.325 21.66 18.66 15.66 12.66 8.325 11.325 ],[7.33 7.33 10.33 7.33 10.33 10.33 7" ".33 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text')" ";\n\n\ncolor('black');disp('not');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Logical" SID "648" Ports [2, 1] Position [205, 29, 240, 71] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Logical" SourceType "Xilinx Logical Block Block" logical_function "AND" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "0" align_bp on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,261" block_type "logical" block_version "8.2" sg_icon_stat "35,42,2,1,white,blue,0,83a4b621,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 0 42 42 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 35 35 0 0 ],[0 0 42 42 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5.875 ],[26.55" " 26.55 31.55 26.55 31.55 31.55 31.55 26.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[21.55 21.55 26" ".55 26.55 21.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[16.55 16.55 21.55 21.55 16.55 " "],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[11.55 11.55 16.55 11.55 16.55 16.55 11.55 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\n\n\n" "color('black');disp('and');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "649" Position [265, 43, 295, 57] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "Logical" SrcPort 1 Points [0, 0] DstBlock "Q" DstPort 1 } Line { SrcBlock "Delay" SrcPort 1 Points [0, 0] DstBlock "Logical" DstPort 2 } Line { SrcBlock "Inverter" SrcPort 1 DstBlock "Delay" DstPort 1 } Line { SrcBlock "D" SrcPort 1 Points [0, 0; 15, 0] Branch { DstBlock "Logical" DstPort 1 } Branch { DstBlock "Inverter" DstPort 1 } } } } Block { BlockType Reference Name "Relational" SID "650" Ports [2, 1] Position [1085, 223, 1130, 272] BlockMirror on ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a<=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "relational" block_version "8.2" sg_icon_stat "45,49,2,1,white,blue,0,52e4b236,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 49 49 0 ],[0.77 0.82 0.91" " ]);\nplot([0 45 45 0 0 ],[0 0 49 49 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 30.66 36." "66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 30.66 24.66" " ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1 1 ]);\npatch(" "[14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'" ",1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa \\leq b','texmode'" ",'on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Relational1" SID "651" Ports [2, 1] Position [845, 367, 890, 438] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Relational" SourceType "Xilinx Arithmetic Relational Operator Block" mode "a>=b" en off latency "0" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,348,193" block_type "relational" block_version "8.2" sg_icon_stat "45,71,2,1,white,blue,0,6218dc92,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 71 71 0 ],[0.77 0.82 0.91" " ]);\nplot([0 45 45 0 0 ],[0 0 71 71 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[41.66 41.66 47." "66 41.66 47.66 47.66 47.66 41.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[35.66 35.66 41.66 41.66 35.66" " ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[29.66 29.66 35.66 35.66 29.66 ],[1 1 1 ]);\npatch(" "[14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[23.66 23.66 29.66 23.66 29.66 29.66 23.66 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'" ",1,'a');\ncolor('black');port_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bfa \\geq b','texmode'" ",'on');\ncolor('black');disp(' ');\nfprintf('','COMMENT: end icon text');" } Block { BlockType SubSystem Name "S-R Latch" SID "652" Ports [2, 1] Position [555, 367, 595, 403] MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "S-R Latch" Location [2, 74, 1184, 726] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "S" SID "653" Position [125, 198, 155, 212] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Inport Name "R" SID "654" Position [125, 178, 155, 192] NamePlacement "alternate" Port "2" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Convert" SID "655" Ports [1, 1] Position [200, 178, 230, 192] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do" " not." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "16" bin_pt "14" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,374,375" block_type "convert" block_version "8.2" sg_icon_stat "30,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 14 14 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 14 14 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[9" ".22 9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[7.22 7.22 9.22" " 9.22 7.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 " "]);\npatch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');por" "t_label('output',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Convert1" SID "656" Ports [1, 1] Position [200, 198, 230, 212] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Convert" SourceType "Xilinx Type Converter Block" infoedit "Hardware notes: rounding and saturating require hardware resources; truncating and wrapping do" " not." gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "16" bin_pt "14" float_type "Single" exp_bits "8" fraction_bits "24" quantization "Truncate" overflow "Wrap" en off latency "0" dbl_ovrd off pipeline off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "20,20,374,375" block_type "convert" block_version "8.2" sg_icon_stat "30,14,1,1,white,blue,0,edca21da,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 30 30 0 0 ],[0 0 14 14 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 30 30 0 0 ],[0 0 14 14 0 ]);\npatch([10.55 13.44 15.44 17.44 19.44 15.44 12.55 10.55 ],[9" ".22 9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([12.55 15.44 13.44 10.55 12.55 ],[7.22 7.22 9.22" " 9.22 7.22 ],[0.931 0.946 0.973 ]);\npatch([10.55 13.44 15.44 12.55 10.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 " "]);\npatch([12.55 19.44 17.44 15.44 13.44 10.55 12.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.97" "3 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\n\ncolor('black');por" "t_label('output',1,'cast');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Register" SID "657" Ports [3, 1] Position [280, 153, 330, 217] NamePlacement "alternate" ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Register" SourceType "Xilinx Register Block" init "0" rst on en on dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "register" block_version "8.2" sg_icon_stat "50,64,3,1,white,blue,0,30546de1,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 64 64 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 50 50 0 0 ],[0 0 64 64 0 ]);\npatch([9.425 19.54 26.54 33.54 40.54 26.54 16.425 9.425 ],[" "39.77 39.77 46.77 39.77 46.77 46.77 46.77 39.77 ],[1 1 1 ]);\npatch([16.425 26.54 19.54 9.425 16.425 ],[32.77 3" "2.77 39.77 39.77 32.77 ],[0.931 0.946 0.973 ]);\npatch([9.425 19.54 26.54 16.425 9.425 ],[25.77 25.77 32.77 32." "77 25.77 ],[1 1 1 ]);\npatch([16.425 40.54 33.54 26.54 19.54 9.425 16.425 ],[18.77 18.77 25.77 18.77 25.77 25.7" "7 18.77 ],[0.931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon te" "xt');\ncolor('black');port_label('input',1,'d');\ncolor('black');port_label('input',2,'rst');\ncolor('black');p" "ort_label('input',3,'en');\ncolor('black');port_label('output',1,'q');\ncolor('black');disp('z^{-1}','texmode'," "'on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "zero3" SID "658" Ports [0, 1] Position [215, 156, 235, 174] ShowName off LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Constant" SourceType "Xilinx Constant Block Block" const "1" gui_display_data_type "Fixed-point" arith_type "Boolean" n_bits "1" bin_pt "0" preci_type "Single" exp_width "8" frac_width "24" explicit_period off period "1" dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block." equ "P=C" opselect "C" inp2 "PCIN>>17" opr "+" inp1 "P" carry "CIN" dbl_ovrd off has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "constant" block_version "VER_STRING_GOES_HERE" sg_icon_stat "20,18,0,1,white,blue,0,1c72b5be,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 20 20 0 0 ],[0 0 18 18 0 ],[0.77 0" ".82 0.91 ]);\nplot([0 20 20 0 0 ],[0 0 18 18 0 ]);\npatch([5.55 8.44 10.44 12.44 14.44 10.44 7.55 5.55 ],[11.22" " 11.22 13.22 11.22 13.22 13.22 13.22 11.22 ],[1 1 1 ]);\npatch([7.55 10.44 8.44 5.55 7.55 ],[9.22 9.22 11.22 11" ".22 9.22 ],[0.931 0.946 0.973 ]);\npatch([5.55 8.44 10.44 7.55 5.55 ],[7.22 7.22 9.22 9.22 7.22 ],[1 1 1 ]);\np" "atch([7.55 14.44 12.44 10.44 8.44 5.55 7.55 ],[5.22 5.22 7.22 5.22 7.22 7.22 5.22 ],[0.931 0.946 0.973 ]);\nfpr" "intf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('out" "put',1,'1');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Outport Name "Q" SID "659" Position [395, 178, 425, 192] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "Convert1" SrcPort 1 DstBlock "Register" DstPort 3 } Line { SrcBlock "Convert" SrcPort 1 DstBlock "Register" DstPort 2 } Line { SrcBlock "Register" SrcPort 1 DstBlock "Q" DstPort 1 } Line { SrcBlock "S" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "R" SrcPort 1 DstBlock "Convert" DstPort 1 } Line { SrcBlock "zero3" SrcPort 1 DstBlock "Register" DstPort 1 } } } Block { BlockType Reference Name "Transmisson\nMode Selector" SID "660" Ports [3, 1] Position [315, 343, 350, 447] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Mux" SourceType "Xilinx Bus Multiplexer Block" inputs "2" en off latency "0" precision "Full" arith_type "Unsigned" n_bits "16" bin_pt "14" quantization "Truncate" overflow "Wrap" dbl_ovrd off xl_use_area off xl_area "[0,0,0,0,0,0,0]" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "mux" block_version "9.1.01" sg_icon_stat "35,104,3,1,white,blue,3,eb98d690,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 35 35 0 0 ],[0 14.8571 89.1429 104 0 ],[0." "77 0.82 0.91 ]);\nplot([0 35 35 0 0 ],[0 14.8571 89.1429 104 0 ]);\npatch([5.875 13.1 18.1 23.1 28.1 18.1 10.875 5." "875 ],[57.55 57.55 62.55 57.55 62.55 62.55 62.55 57.55 ],[1 1 1 ]);\npatch([10.875 18.1 13.1 5.875 10.875 ],[52.55 " "52.55 57.55 57.55 52.55 ],[0.931 0.946 0.973 ]);\npatch([5.875 13.1 18.1 10.875 5.875 ],[47.55 47.55 52.55 52.55 47" ".55 ],[1 1 1 ]);\npatch([10.875 28.1 23.1 18.1 13.1 5.875 10.875 ],[42.55 42.55 47.55 42.55 47.55 47.55 42.55 ],[0." "931 0.946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('bla" "ck');port_label('input',1,'sel');\ncolor('black');port_label('input',2,'d0');\ncolor('black');port_label('input',3," "'d1');\n\ncolor('black');disp('\\bf{}','texmode','on');\nfprintf('','COMMENT: end icon text');" } Block { BlockType Reference Name "Tx Addr Counter" SID "661" Ports [2, 1] Position [1085, 308, 1130, 357] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited counter is" " implemented by combining a counter with a comparator." cnt_type "Free Running" cnt_to "Inf" operation "Up" start_count "0" cnt_by_val "1" arith_type "Unsigned" n_bits "14" bin_pt "0" load_pin off rst on en on explicit_period "off" period "1" dbl_ovrd off use_behavioral_HDL off implementation "Fabric" xl_use_area off xl_area "[0,0,0,0,0,0,0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,356,630" block_type "counter" block_version "8.2" sg_icon_stat "45,49,2,1,white,blue,0,ae3608d6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 45 45 0 0 ],[0 0 49 49 0 ],[0.77 0.82 0.91" " ]);\nplot([0 45 45 0 0 ],[0 0 49 49 0 ]);\npatch([8.65 17.32 23.32 29.32 35.32 23.32 14.65 8.65 ],[30.66 30.66 36." "66 30.66 36.66 36.66 36.66 30.66 ],[1 1 1 ]);\npatch([14.65 23.32 17.32 8.65 14.65 ],[24.66 24.66 30.66 30.66 24.66" " ],[0.931 0.946 0.973 ]);\npatch([8.65 17.32 23.32 14.65 8.65 ],[18.66 18.66 24.66 24.66 18.66 ],[1 1 1 ]);\npatch(" "[14.65 35.32 29.32 23.32 17.32 8.65 14.65 ],[12.66 12.66 18.66 12.66 18.66 18.66 12.66 ],[0.931 0.946 0.973 ]);\nfp" "rintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'" ",1,'rst');\ncolor('black');port_label('input',2,'en');\n\ncolor('black');disp('{\\fontsize{14}\\bf++}','texmode','o" "n');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Scope Name "Tx Control" SID "662" Ports [8] Position [1375, 624, 1405, 731] Floating off Location [1, 45, 1281, 719] Open off NumInputPorts "8" ZoomMode "yonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" axes4 "%" axes5 "%" axes6 "%" axes7 "%" axes8 "%" } TimeRange "70000" YMin "0~0~0~0~0~0~0~0" YMax "2~1~1~1~1~100~1~20000" SaveName "ScopeData3" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Reference Name "Tx Delay Counter" SID "663" Ports [2, 1] Position [745, 356, 785, 409] NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Counter" SourceType "Xilinx Counter Block" infoedit "Hardware notes: Free running counters are the least expensive in hardware. A count limited counter is" " implemented by combining a counter with a comparator." cnt_type "Free Running" cnt_to "Inf" operation "Up" start_count "0" cnt_by_val "1" arith_type "Unsigned" n_bits "14" bin_pt "0" load_pin off rst on en on explicit_period "off" period "1" dbl_ovrd off use_behavioral_HDL off implementation "Fabric" xl_use_area off xl_area "[0,0,0,0,0,0,0]" use_rpm "off" has_advanced_control "0" sggui_pos "20,20,356,630" block_type "counter" block_version "8.2" sg_icon_stat "40,53,2,1,white,blue,0,ae3608d6,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 53 53 0 ],[0.77 0.82 0.91" " ]);\nplot([0 40 40 0 0 ],[0 0 53 53 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[31.55 31.55 36.55" " 31.55 36.55 36.55 36.55 31.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[26.55 26.55 31.55 31.55 26.55 " "],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[21.55 21.55 26.55 26.55 21.55 ],[1 1 1 ]);\npatch(" "[13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[16.55 16.55 21.55 16.55 21.55 21.55 16.55 ],[0.931 0.946 0.973 ]);\nfpr" "intf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('input'," "1,'rst');\ncolor('black');port_label('input',2,'en');\n\ncolor('black');disp('{\\fontsize{14}\\bf++}','texmode','on" "');\nfprintf('','COMMENT: end icon text');\n" } Block { BlockType Outport Name "Addr" SID "664" Position [1315, 328, 1345, 342] IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Block { BlockType Outport Name "Vout" SID "665" Position [1160, 418, 1190, 432] Port "2" IconDisplay "Port number" MaskIconFrame on MaskIconOpaque on MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" } Line { SrcBlock "Transmisson\nMode Selector" SrcPort 1 Points [20, 0] Branch { DstBlock "S-R Latch" DstPort 2 } Branch { Points [0, -170] DstBlock "Logical2" DstPort 1 } } Line { SrcBlock "Tx Delay Counter" SrcPort 1 Points [25, 0] Branch { DstBlock "Relational1" DstPort 1 } Branch { Points [0, 315] DstBlock "Gateway Out6" DstPort 1 } } Line { SrcBlock "TxDelay" SrcPort 1 DstBlock "Relational1" DstPort 2 } Line { SrcBlock "ContinuousTx" SrcPort 1 Points [105, 0] Branch { DstBlock "Transmisson\nMode Selector" DstPort 1 } Branch { Points [0, 265] DstBlock "Gateway Out1" DstPort 1 } } Line { SrcBlock "StartTx" SrcPort 1 DstBlock "Convert1" DstPort 1 } Line { SrcBlock "StopTx" SrcPort 1 DstBlock "Convert2" DstPort 1 } Line { SrcBlock "Logical" SrcPort 1 DstBlock "Tx Delay Counter" DstPort 2 } Line { SrcBlock "S-R Latch" SrcPort 1 Points [20, 0] Branch { Points [0, 0] Branch { DstBlock "Logical" DstPort 1 } Branch { Points [0, 0; 0, -50] DstBlock "Logical1" DstPort 1 } } Branch { Points [0, 300] DstBlock "Gateway Out5" DstPort 1 } } Line { SrcBlock "Relational1" SrcPort 1 Points [50, 0] Branch { Points [0, 80] DstBlock "Inverter" DstPort 1 } Branch { Points [0, -55] DstBlock "Logical1" DstPort 2 } } Line { SrcBlock "Inverter" SrcPort 1 Points [-130, 0; 0, -85] DstBlock "Logical" DstPort 2 } Line { SrcBlock "Logical1" SrcPort 1 Points [30, 0] Branch { DstBlock "Tx Addr Counter" DstPort 2 } Branch { Points [0, 80] Branch { DstBlock "Vout" DstPort 1 } Branch { Points [0, 290] DstBlock "Gateway Out7" DstPort 1 } } } Line { SrcBlock "Tx Addr Counter" SrcPort 1 Points [65, 0] Branch { DstBlock "Addr" DstPort 1 } Branch { Points [0, -75] DstBlock "Relational" DstPort 2 } Branch { Points [0, 395] DstBlock "Gateway Out8" DstPort 1 } } Line { SrcBlock "From Register4" SrcPort 1 DstBlock "Relational" DstPort 1 } Line { SrcBlock "Posedge2" SrcPort 1 DstBlock "Logical2" DstPort 2 } Line { SrcBlock "Relational" SrcPort 1 Points [-90, 0; 0, -60; -710, 0; 0, 205] Branch { DstBlock "Transmisson\nMode Selector" DstPort 2 } Branch { Points [0, 245] DstBlock "Gateway Out2" DstPort 1 } } Line { SrcBlock "Logical2" SrcPort 1 Points [20, 0] Branch { Points [240, 0; 0, 85] DstBlock "Tx Addr Counter" DstPort 1 } Branch { Points [0, 135] DstBlock "Tx Delay Counter" DstPort 1 } } Line { SrcBlock "Convert1" SrcPort 1 Points [25, 0] Branch { DstBlock "S-R Latch" DstPort 1 } Branch { Points [0, -135] DstBlock "Posedge2" DstPort 1 } Branch { Points [0, 295] DstBlock "Gateway Out4" DstPort 1 } } Line { SrcBlock "Convert2" SrcPort 1 Points [5, 0] Branch { DstBlock "Transmisson\nMode Selector" DstPort 3 } Branch { Points [0, 225] DstBlock "Gateway Out3" DstPort 1 } } Line { SrcBlock "Gateway Out5" SrcPort 1 DstBlock "Tx Control" DstPort 5 } Line { SrcBlock "Gateway Out4" SrcPort 1 DstBlock "Tx Control" DstPort 4 } Line { SrcBlock "Gateway Out3" SrcPort 1 DstBlock "Tx Control" DstPort 3 } Line { SrcBlock "Gateway Out2" SrcPort 1 DstBlock "Tx Control" DstPort 2 } Line { SrcBlock "Gateway Out1" SrcPort 1 DstBlock "Tx Control" DstPort 1 } Line { SrcBlock "Gateway Out6" SrcPort 1 DstBlock "Tx Control" DstPort 6 } Line { SrcBlock "Gateway Out7" SrcPort 1 DstBlock "Tx Control" DstPort 7 } Line { SrcBlock "Gateway Out8" SrcPort 1 DstBlock "Tx Control" DstPort 8 } } } Block { BlockType Reference Name "debug_AGC_Done" SID "666" Ports [1, 1] Position [270, 1088, 310, 1102] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, do" "uble, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discar" "ded, depending on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" UseAsDAC off DACChannel "'1'" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "8.2" sg_icon_stat "40,14,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.95 0." "93 0.65 ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9.2" "2 9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22 9." "22 7.22 ],[0.985 0.979 0.895 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\n" "patch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.985 0.979 0.895 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('i" "nput',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Reference Name "debug_Capturing" SID "667" Ports [1, 1] Position [580, 528, 620, 542] BlockMirror on NamePlacement "alternate" LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, do" "uble, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discar" "ded, depending on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" UseAsDAC off DACChannel "'1'" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "8.2" sg_icon_stat "40,14,1,1,white,yellow,1,cc31b7ac,left,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.95 0." "93 0.65 ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9.2" "2 9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22 9." "22 7.22 ],[0.985 0.979 0.895 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\n" "patch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.985 0.979 0.895 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('i" "nput',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Block { BlockType Reference Name "debug_Transmitting" SID "668" Ports [1, 1] Position [755, 763, 795, 777] LibraryVersion "1.2" SourceBlock "xbsIndex_r4/Gateway Out" SourceType "Xilinx Gateway Out Block" infoedit "Gateway out block. Converts Xilinx fixed point inputs into ouputs of type Simulink integer, do" "uble, or fixed point.

Hardware notes: In hardware these blocks become top level output ports or are discar" "ded, depending on how they are configured." inherit_from_input off hdl_port on timing_constraint "None" locs_specified off LOCs "{}" xl_use_area off xl_area "[0,0,0,0,0,0,0]" UseAsDAC off DACChannel "'1'" has_advanced_control "0" sggui_pos "-1,-1,-1,-1" block_type "gatewayout" block_version "8.2" sg_icon_stat "40,14,1,1,white,yellow,1,cc31b7ac,right,,[ ],[ ]" sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 14 14 0 ],[0.95 0." "93 0.65 ]);\nplot([0 40 40 0 0 ],[0 0 14 14 0 ]);\npatch([15.55 18.44 20.44 22.44 24.44 20.44 17.55 15.55 ],[9.2" "2 9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([17.55 20.44 18.44 15.55 17.55 ],[7.22 7.22 9.22 9." "22 7.22 ],[0.985 0.979 0.895 ]);\npatch([15.55 18.44 20.44 17.55 15.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\n" "patch([17.55 24.44 22.44 20.44 18.44 15.55 17.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.985 0.979 0.895 ]);\n" "fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('i" "nput',1,' ');\ncolor('black');port_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','CO" "MMENT: end icon text');" } Line { SrcBlock "Pulse\nGenerator" SrcPort 1 DstBlock "StartCapture" DstPort 1 } Line { SrcBlock "From9" SrcPort 1 DstBlock "Logical" DstPort 2 } Line { SrcBlock "Logical" SrcPort 1 DstBlock "Posedge" DstPort 1 } Line { SrcBlock "StartCapture" SrcPort 1 DstBlock "Logical" DstPort 1 } Line { SrcBlock "Radio 3 Inputs" SrcPort 2 DstBlock "Radio 3\nRx Buffers" DstPort 2 } Line { SrcBlock "From12" SrcPort 1 DstBlock "Radio 3\nRx Buffers" DstPort 5 } Line { SrcBlock "Radio 2 Inputs" SrcPort 2 DstBlock "Radio 2\nRx Buffers" DstPort 2 } Line { SrcBlock "From11" SrcPort 1 DstBlock "Radio 2\nRx Buffers" DstPort 5 } Line { SrcBlock "Posedge" SrcPort 1 DstBlock "Rx Control" DstPort 1 } Line { SrcBlock "From15" SrcPort 1 DstBlock "Radio 2 Inputs" DstPort 1 } Line { SrcBlock "From16" SrcPort 1 DstBlock "Radio 3 Inputs" DstPort 1 } Line { SrcBlock "Radio 1 Inputs" SrcPort 2 DstBlock "Radio 1\nRx Buffers" DstPort 2 } Line { SrcBlock "From10" SrcPort 1 DstBlock "Radio 1\nRx Buffers" DstPort 5 } Line { SrcBlock "From14" SrcPort 1 DstBlock "Radio 1 Inputs" DstPort 1 } Line { SrcBlock "Radio 4 Inputs" SrcPort 2 DstBlock "Radio 4\nRx Buffers" DstPort 2 } Line { SrcBlock "From13" SrcPort 1 DstBlock "Radio 4\nRx Buffers" DstPort 5 } Line { SrcBlock "From17" SrcPort 1 DstBlock "Radio 4 Inputs" DstPort 1 } Line { SrcBlock "Rx Control" SrcPort 1 Points [25, 0] Branch { Points [130, 0] Branch { DstBlock "Radio 2\nRx Buffers" DstPort 3 } Branch { Points [0, -145] DstBlock "Radio 1\nRx Buffers" DstPort 3 } Branch { Points [0, 140] Branch { DstBlock "Radio 3\nRx Buffers" DstPort 3 } Branch { Points [0, 140] DstBlock "Radio 4\nRx Buffers" DstPort 3 } } } Branch { DstBlock "Goto1" DstPort 1 } } Line { SrcBlock "Rx Control" SrcPort 2 Points [180, 0] Branch { Labels [1, 0] DstBlock "Radio 2\nRx Buffers" DstPort 4 } Branch { Points [0, 140] Branch { DstBlock "Radio 3\nRx Buffers" DstPort 4 } Branch { Points [0, 140] Branch { DstBlock "Radio 4\nRx Buffers" DstPort 4 } Branch { DstBlock "debug_Capturing" DstPort 1 } } } Branch { Points [0, -145] DstBlock "Radio 1\nRx Buffers" DstPort 4 } } Line { SrcBlock "Radio 2\nTx Buffer" SrcPort 1 DstBlock "Radio 2 Outputs" DstPort 1 } Line { SrcBlock "Posedge1" SrcPort 1 DstBlock "Tx Control" DstPort 1 } Line { SrcBlock "From2" SrcPort 1 Points [75, 0; 0, -140] DstBlock "Tx Control" DstPort 3 } Line { SrcBlock "Posedge2" SrcPort 1 Points [60, 0; 0, -85] DstBlock "Tx Control" DstPort 2 } Line { SrcBlock " 1" SrcPort 1 DstBlock "Posedge2" DstPort 1 } Line { SrcBlock "StopTx" SrcPort 1 DstBlock " 1" DstPort 1 } Line { SrcBlock "Pulse\nGenerator2" SrcPort 1 DstBlock "StopTx" DstPort 1 } Line { SrcBlock " " SrcPort 1 DstBlock "Posedge1" DstPort 1 } Line { SrcBlock "Pulse\nGenerator1" SrcPort 1 DstBlock "StartTx" DstPort 1 } Line { SrcBlock "From6" SrcPort 1 DstBlock "Radio 2\nTx Buffer" DstPort 3 } Line { SrcBlock "From4" SrcPort 1 Points [105, 0; 0, -200] DstBlock "Tx Control" DstPort 4 } Line { SrcBlock "Tx Control" SrcPort 2 Points [25, 0] Branch { Points [0, 70] DstBlock "debug_Transmitting" DstPort 1 } Branch { DstBlock "Inverter" DstPort 1 } } Line { SrcBlock "Radio 3\nTx Buffer" SrcPort 1 DstBlock "Radio 3 Outputs" DstPort 1 } Line { SrcBlock "From7" SrcPort 1 DstBlock "Radio 3\nTx Buffer" DstPort 3 } Line { SrcBlock "Radio 1\nTx Buffer" SrcPort 1 DstBlock "Radio 1 Outputs" DstPort 1 } Line { SrcBlock "From5" SrcPort 1 DstBlock "Radio 1\nTx Buffer" DstPort 3 } Line { SrcBlock "Radio 4\nTx Buffer" SrcPort 1 DstBlock "Radio 4 Outputs" DstPort 1 } Line { SrcBlock "From8" SrcPort 1 DstBlock "Radio 4\nTx Buffer" DstPort 3 } Line { SrcBlock "Tx Control" SrcPort 1 Points [155, 0] Branch { DstBlock "Radio 1\nTx Buffer" DstPort 1 } Branch { Points [0, 95] Branch { DstBlock "Radio 2\nTx Buffer" DstPort 1 } Branch { Points [0, 95] Branch { DstBlock "Radio 3\nTx Buffer" DstPort 1 } Branch { Points [0, 100] DstBlock "Radio 4\nTx Buffer" DstPort 1 } } } } Line { SrcBlock "Inverter" SrcPort 1 Points [55, 0] Branch { Points [0, -10] DstBlock "Radio 1\nTx Buffer" DstPort 2 } Branch { Points [0, 85] Branch { DstBlock "Radio 2\nTx Buffer" DstPort 2 } Branch { Points [0, 95] Branch { DstBlock "Radio 3\nTx Buffer" DstPort 2 } Branch { Points [0, 100] DstBlock "Radio 4\nTx Buffer" DstPort 2 } } } } Line { SrcBlock "From1" SrcPort 1 DstBlock " 1" DstPort 2 } Line { SrcBlock "Radio 1 Inputs" SrcPort 1 Points [15, 0] Branch { Points [0, -15] DstBlock "Goto2" DstPort 1 } Branch { Points [0, 5] DstBlock "Radio 1\nRx Buffers" DstPort 1 } } Line { SrcBlock "Radio 2 Inputs" SrcPort 1 Points [25, 0] Branch { Points [0, -15] DstBlock "Goto4" DstPort 1 } Branch { Points [0, 5] DstBlock "Radio 2\nRx Buffers" DstPort 1 } } Line { SrcBlock "Radio 3 Inputs" SrcPort 1 Points [35, 0] Branch { Points [0, -15] DstBlock "Goto5" DstPort 1 } Branch { Points [0, 10] DstBlock "Radio 3\nRx Buffers" DstPort 1 } } Line { SrcBlock "Radio 4 Inputs" SrcPort 1 Points [15, 0] Branch { Points [0, -15] DstBlock "Goto6" DstPort 1 } Branch { Points [0, 10] DstBlock "Radio 4\nRx Buffers" DstPort 1 } } Line { SrcBlock "From18" SrcPort 1 Points [15, 0; 0, -65] Branch { DstBlock "Radio 4 Inputs" DstPort 2 } Branch { Points [0, -140] Branch { DstBlock "Radio 3 Inputs" DstPort 2 } Branch { Points [0, -140] Branch { DstBlock "Radio 2 Inputs" DstPort 2 } Branch { Points [0, -145] DstBlock "Radio 1 Inputs" DstPort 2 } } } } Line { SrcBlock "From19" SrcPort 1 Points [15, 0] Branch { Points [0, 165] DstBlock " " DstPort 1 } Branch { Points [0, -205] DstBlock "Logical" DstPort 3 } } Line { SrcBlock "StartTx" SrcPort 1 DstBlock " " DstPort 2 } Line { SrcBlock "From3" SrcPort 1 DstBlock " " DstPort 3 } Line { SrcBlock "RSSI Clock\nGenerator" SrcPort 1 DstBlock "RSSI_ADC_CLK" DstPort 1 } Line { SrcBlock "RSSI_ADC_CLK" SrcPort 1 DstBlock "Terminator" DstPort 1 } Line { SrcBlock "AGC_Done" SrcPort 1 Points [15, 0] Branch { Points [0, 75] DstBlock "debug_AGC_Done" DstPort 1 } Branch { DstBlock "Register" DstPort 1 } } Line { SrcBlock "Pulse\nGenerator3" SrcPort 1 DstBlock "AGC_Done" DstPort 1 } Line { SrcBlock "Register" SrcPort 1 DstBlock "Posedge3" DstPort 1 } Line { SrcBlock "Posedge3" SrcPort 1 DstBlock "Convert2" DstPort 1 } Line { SrcBlock "Convert2" SrcPort 1 DstBlock "Goto3" DstPort 1 } Annotation { Position [348, 1029] } } } MatData { NumRecords 1 DataRecord { Tag DataTag0 Data " %)30 . J'P 8 ( @ % \" $ ! 0 % 0 !@ $ , 0 . . 8 ( ! " "% \" $ ' 0 0 !P '1A7, !V86QU97, . & $ 8 ( 0 % \" $ # 0 " ". 0 8 ( ! % \" $ + 0 0 \"P $A$3\"!.971L:7-T . 2 8 " " ( ! % \" $ 8 0 0 & $5X<&]R=\"!A7=H97)E(&EN(%-U8E-Y&EL:6YX9F%M:6QY <&%R= " " #0 #@ #@ & \" 0 !0 @ ! \" $ $ @ !X8S1V'0G*3L*9G!R:6YT9B@G)RPG0T]-345.5#H@96YD(&EC;VX@=&5X=\"&EL:6YX9F%M:6QY " " <&%R= &QE9&MS971T:6YG7!E 7-T96T@1V5N97)A=&]R X X !@ @ $ 4 ( 0 < ! ! ' =FER=&5X-" " . 0 8 ( ! % \" $ ) 0 0 \"0 'AC-'9F>#$P, . , 8 " " ( ! % \" $ # 0 0 , +3$Q X X !@ @ $ 4 ( 0 8 " " ! ! & 9F8Q-3$W . , 8 ( ! % \" 0 0 X " "P !@ @ $ 4 ( 0 , ! ! P!84U0 #@ # & \" 0 !0 @ " " $ $ . 0 8 ( ! % \" $ - 0 0 #0 $-L;V-K(" "$5N86)L97, . 0 8 ( ! % \" $ , 0 0 # \"XO=S)?;F5T;&ES= . " " , 8 ( ! % \" 0 0 X P !@ @ $ 4 ( " " 0 , ! ! P!O9F8 #@ # & \" 0 !0 @ ! @ $ $ \" #$P . " " , 8 ( ! % \" $ # 0 0 , ,3 P X P !@ @ $ 4 ( " " ! ! #@ # & \" 0 !0 @ $ $ . " ", 8 ( ! % \" 0 0 X P !@ @ $ 4 ( " " ! ! #@ $@ & \" 0 !0 @ ! & $ $ !@ !!8V-O7-G96X X X !@ @ $ 4 ( 0 8 ! ! & ,3 N,2XS . 6 8" " ( ! % \" $ C 0 0 (P #4Q+#4P+\"TQ+\"TQ+')E9\"QB96EG92PP+# W-S,T+')I9VAT " " . P $ 8 ( ! % \" $ \". 0 0 0 C@$ &9P'0G*3L* . , 8 ( ! % \" 0 " " 0 X P !@ @ $ 4 ( ! ! #@ # & \" 0" " !0 @ $ $ . , 8 ( ! % \" $ $ 0 " " 0 0 5DA$3 X X !@ @ & 4 ( 0 $ ! D ( . . 8 " " ( !@ % \" $ ! 0 ) \" #@ #@ & \" 0 !0 @ " " ! !@ $ $ 8 Y+C(N,#$ X ! !@ @ $ 4 ( 0 P ! ! " ", >&QE9&MP;W-T9V5N X ! !@ @ $ 4 ( 0 T ! ! - >&QE9&MS971T:" "6YG

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