Changes between Version 1 and Version 2 of 802.11/PacketFlow

Timestamp:

Jul 30, 2013, 12:24:44 AM (11 years ago)

Author:

murphpo

Comment:

--

802.11/PacketFlow

@@ -5 +5 @@
 As packets move through the 802.11 reference design, the packet contents must be accessible by CPU High, CPU Low and the PHY cores. The design achieves this using the interconnects illustrated in the figure blow.
 
-[[Image(wiki:802.11/files:wlan_ref_des_pkt_buf_interconnects.png)]]
+[[Image(wiki:802.11/files:wlan_ref_des_interconnects.png)]]
 
 Each MicroBlaze has access to two AXI interconnects. For both CPUs the MicroBlaze DP port (non-cached peripheral memory access port) is connected to an AXI4 Lite interconnect. The peripheral cores connected to each AXI4 Lite interconnect are accessible by only one CPU. The cores are divided between CPUs based on which part of the MAC needs to access them. For example the radio_controller, w3_ad_controller and PHY configuration registers are all attached to the interconnect for CPU Low. Similarly the Ethernet cores are attached to the peripheral bus for CPU High. The mailbox and mutex ports for each CPU are also attached to their corresponding peripheral busses.
@@ -21 +21 @@
 Each packet buffer stores more than just the raw Tx/Rx bytes for the PHY. The MAC uses each buffer to store other metadata. The contents of each packet buffer are illustrated below.
 
-[[Image(wiki:802.11/files:wlan_ref_des_pkt_buf_offsets.png)]]
+[[Image(wiki:802.11/files:wlan_ref_des_pkt_buf_offsets.png,height=300)]]
 
 The MAC code utilizes the first section of each packet buffer for metadata about the packet contained in that buffer. This metadata is stored in the {{{tx_frame_info}}} and {{{rx_frame_info}}} structs, defined in wlan_lib.h.