Changes between Version 20 and Version 21 of 802.11/PacketFlow


Ignore:
Timestamp:
Apr 15, 2016, 2:51:54 PM (18 months ago)
Author:
murphpo
Comment:

--

Legend:

Unmodified
Added
Removed
Modified
  • 802.11/PacketFlow

    v20 v21  
    7070
    7171== Tx Packet Buffer States ==
    72 The lower-level MAC and PHY process a single Tx packet at any given time. While a packet is being transmitted the upper-level MAC prepares the next packet for transmission. Two buffers from the Tx packet buffer RAM are used for this ping-pong approach.
     72[[Image(tx_pkt_buf_pingpong_impl.png,width=300,align=right)]]
    7373
    74 The handshake between the upper and lower level MACs to initiate new packet transmissions is illustrated below. The handshake uses two IPC messages:
    75  * {{{IPC_MBOX_TX_MPDU_READY(pkt_buf_index)}}}: indication from CPU High that the packet in {{{pkt_buf_index}}} is ready for transmission
    76  * {{{IPC_MBOX_TX_MPDU_DONE(pkt_buf_index)}}}: indication from CPU Low that transmission of the packet in {{{pkt_buf_index}}} is complete.
     74The {{{tx_frame_info_t}}} struct has a {{{tx_pkt_buf_state}}} field used by the upper and lower MAC designs to coordinate access to the packet buffer contents. There are four possible states for an Rx packet buffer:
     75 * {{{UNINITIALIZED}}}: the default state following a reconfiguration of the FPGA. The MAC code never sets a buffer to this state.
     76 * {{{HIGH_CTRL}}}: the buffer is under control of CPU High. The MAC code in CPU Low must not read or write the buffer.
     77 * {{{LOW_CTRL}}}:  the buffer is under control of CPU Low and the Rx PHY. The MAC code in CPU High must not read or write the buffer.
     78 * {{{READY}}}: the buffer contains a packet that is ready to be transmitted by the lower MAC and Tx PHY.
     79 * {{{DONE}}}: the buffer contains a packet that has already been transmitted by the lower MAC and Tx PHY.
    7780
    78 It is critical that CPU High not modify the contents of any packet buffer for which it has sent {{{IPC_MBOX_TX_MPDU_READY}}} until it receives the corresponding {{{IPC_MBOX_TX_MPDU_DONE}}} message. Likewise CPU Low must only modify packet buffers for which it as received {{{IPC_MBOX_TX_MPDU_READY}}} and only before it sends {{{IPC_MBOX_TX_MPDU_DONE}}}.
     81Each packet buffer transitions between these states in a rigid sequence. Each state transition is implemented by one CPU.
    7982
    80 [[Image(wiki:802.11/files:wlan_tx_ping_pong_msgs.png)]]
     83'''CPU High:'''[[BR]]
     84{{{HIGH_CTRL → READY}}}: after successful dequeue, immediately before sending {{{MPDU_READY}}} message to CPU Low[[BR]]
     85{{{DONE → HIGH_CTRL}}}: after receiving {{{MPDU_DONE}}} message, at start of {{{MPDU_DONE}}} handler[[BR]]
    8186
    82 The upper-level MAC framework calls an application-specific callback function upon receipt of the {{{IPC_MBOX_TX_MPDU_DONE}}} message. The MAC application can use this callback to manage internal state, create log entries, update statistics, etc.
     87'''CPU Low:'''[[BR]]
     88{{{READY → LOW_CTRL}}}: after receipt of {{{MPDU_READY}}} message by CPU Low[[BR]]
     89{{{LOW_CTRL → DONE}}}: after return of MAC frame_transmit(), before sending {{{MPDU_DONE}}} message[[BR]]
     90
     91This architecture is effectively a pipelined ping/pong scheme. Only two packet buffers are ever in the {{{READY}}} and/or {{{LOW_CTRL}}} states, minimizing disruption to the queue priorities implemented in CPU High. CPU High is allowed to dequeue a new packet into a {{{HIGH_CTRL}}} buffer before it runs post-Tx processing on the latest {{{DONE}}} buffer, minimizing the duration where CPU Low might be waiting for a new packet to transmit while CPU High is busy processing previous transmissions.
     92
     93The figure to the right illustrates the sequence of state transitions and IPC messages for the preparation, transmission, and post-Tx handling of 2 packets.
    8394
    8495== Rx Packet Buffer States ==
     
    89100 * {{{READY}}}: the buffer contains a packet that has been processed by the lower MAC and is ready for further processing by the upper MAC. CPU Low must send a {{{RX_MPDU_READY}}} message to CPU High after setting an Rx buffer to this state.
    90101
    91 Following at-boot initialization, there are 3 valid state transitions for Rx packet buffers:
    92  * {{{LOW_CTRL → READY}}}: CPU Low releases ownership of an Rx buffer after completing processing of a new reception, immediately before sending the {{{RX_MPDU_READY}}} message to CPU High
    93  * {{{READY → HIGH_CTRL}}}: CPU High takes ownership of an Rx buffer after receiving the {{{RX_MPDU_READY}}} message from CPU Low
    94  * {{{HIGH_CTRL → LOW_CTRL}}}: CPU High finishes processing a reception and returns the buffer to control of CPU Low for use by a future reception
     102Following at-boot initialization, there are 3 valid state transitions for Rx packet buffers. Each transition is only implemeted by one CPU.
    95103
     104'''CPU High:'''[[BR]]
     105{{{READY → HIGH_CTRL}}}: CPU High takes ownership of an Rx buffer after receiving the {{{RX_MPDU_READY}}} message from CPU Low[[BR]]
     106{{{HIGH_CTRL → LOW_CTRL}}}: CPU High finishes processing a reception and returns the buffer to control of CPU Low for use by a future reception
    96107
     108'''CPU Low:'''[[BR]]
     109{{{LOW_CTRL → READY}}}: CPU Low releases ownership of an Rx buffer after completing processing of a new reception, immediately before sending the {{{RX_MPDU_READY}}} message to CPU High