{{{#!comment [[Include(wiki:802.11/beta-note)]] }}} [[TracNav(802.11/TOC)]] = 802.11 Reference Design v1.6.0: Resource Usage = The 802.11 Reference Design targets the Virtex-6 LX240T FPGA on WARP v3 hardware. The FPGA resources used by the design change with each revision. The resource usage for the current release is listed below. == FPGA Resources == The table below summarizes the FPGA resource usage for v0.96 of the 802.11 Reference Design. ||= Resource =||= Used =|| || Slice Registers || 79,819 out of 301,440 (26%) || || LUTs || 71,422 out of 150,720 (47%) || || Block RAMs (see note 1) || 253 of 416 (60%) || || DSP48 (multipliers) || 182 of 768 (23%) || || MMCM_ADV || 3 of 12 (25%) || || Ethernet MAC || 2 of 4 (50%) || || IOBs (see note 2) || 354 of 600 (58%) || * '''Note 1''': the ISE MAP reports utilization of RAMB36E1 and RAMB18E1 separately, even though these represent overlapping resources in the FPGA (each RAMB36E1 can be used as 2 RAMB18E1). The block RAM usage above lists the total number of RAMB36E1 primitives in the FPGA and {{{num(RAMB36E1) + ceil(num(RAMB18E1)/2)}}} as the number used. See the MAP report below for more details. * '''Note 2''': the IOB count includes all IOBs used by the design, not just the RF interfaces. Many of these pins are used for the DDR3 memory interface, Ethernet interfaces, user I/O, etc. == MAP Report == The resource usage section of the MAP report of the 802.11 Reference Design is copied below. You can find the full MAP report in the {{{implementation/system_map.mrp}}} file in your local copy of the 802.11 Reference Design XPS project. {{{ Release 14.4 Map P.49d (nt64) Xilinx Mapping Report File for Design 'system' Design Information ------------------ Command Line : map -mt 4 -o system_map.ncd -w -pr b -ol high -t 13 -register_duplication on -timing -detail system.ngd system.pcf Target Device : xc6vlx240t Target Package : ff1156 Target Speed : -2 Mapper Version : virtex6 -- $Revision: 1.55 $ Design Summary -------------- Number of errors: 0 Number of warnings: 352 Slice Logic Utilization: Number of Slice Registers: 79,819 out of 301,440 26% Number used as Flip Flops: 79,657 Number used as Latches: 4 Number used as Latch-thrus: 0 Number used as AND/OR logics: 158 Number of Slice LUTs: 71,422 out of 150,720 47% Number used as logic: 58,148 out of 150,720 38% Number using O6 output only: 44,295 Number using O5 output only: 1,473 Number using O5 and O6: 12,380 Number used as ROM: 0 Number used as Memory: 7,890 out of 58,400 13% Number used as Dual Port RAM: 2,522 Number using O6 output only: 1,546 Number using O5 output only: 27 Number using O5 and O6: 949 Number used as Single Port RAM: 31 Number using O6 output only: 19 Number using O5 output only: 0 Number using O5 and O6: 12 Number used as Shift Register: 5,337 Number using O6 output only: 4,897 Number using O5 output only: 17 Number using O5 and O6: 423 Number used exclusively as route-thrus: 5,384 Number with same-slice register load: 4,418 Number with same-slice carry load: 493 Number with other load: 473 Slice Logic Distribution: Number of occupied Slices: 28,620 out of 37,680 75% Number of LUT Flip Flop pairs used: 91,113 Number with an unused Flip Flop: 22,231 out of 91,113 24% Number with an unused LUT: 19,691 out of 91,113 21% Number of fully used LUT-FF pairs: 49,191 out of 91,113 53% Number of unique control sets: 2,828 Number of slice register sites lost to control set restrictions: 10,593 out of 301,440 3% A LUT Flip Flop pair for this architecture represents one LUT paired with one Flip Flop within a slice. A control set is a unique combination of clock, reset, set, and enable signals for a registered element. The Slice Logic Distribution report is not meaningful if the design is over-mapped for a non-slice resource or if Placement fails. OVERMAPPING of BRAM resources should be ignored if the design is over-mapped for a non-BRAM resource or if placement fails. IO Utilization: Number of bonded IOBs: 354 out of 600 59% Number of LOCed IOBs: 354 out of 354 100% IOB Flip Flops: 105 IOB Master Pads: 10 IOB Slave Pads: 10 Specific Feature Utilization: Number of RAMB36E1/FIFO36E1s: 235 out of 416 56% Number using RAMB36E1 only: 235 Number using FIFO36E1 only: 0 Number of RAMB18E1/FIFO18E1s: 36 out of 832 4% Number using RAMB18E1 only: 36 Number using FIFO18E1 only: 0 Number of BUFG/BUFGCTRLs: 9 out of 32 28% Number used as BUFGs: 9 Number used as BUFGCTRLs: 0 Number of ILOGICE1/ISERDESE1s: 108 out of 720 15% Number used as ILOGICE1s: 43 Number used as ISERDESE1s: 65 Number of OLOGICE1/OSERDESE1s: 189 out of 720 26% Number used as OLOGICE1s: 64 Number used as OSERDESE1s: 125 Number of BSCANs: 2 out of 4 50% Number of BUFHCEs: 0 out of 144 0% Number of BUFIODQSs: 10 out of 72 13% Number of BUFRs: 5 out of 36 13% Number of LOCed BUFRs: 2 out of 5 40% Number of CAPTUREs: 0 out of 1 0% Number of DSP48E1s: 182 out of 768 23% Number of EFUSE_USRs: 0 out of 1 0% Number of FRAME_ECCs: 0 out of 1 0% Number of GTXE1s: 0 out of 20 0% Number of IBUFDS_GTXE1s: 0 out of 12 0% Number of ICAPs: 0 out of 2 0% Number of IDELAYCTRLs: 5 out of 18 27% Number of IODELAYE1s: 112 out of 720 15% Number of LOCed IODELAYE1s: 10 out of 112 8% Number of MMCM_ADVs: 3 out of 12 25% Number of PCIE_2_0s: 0 out of 2 0% Number of STARTUPs: 1 out of 1 100% Number of SYSMONs: 1 out of 1 100% Number of TEMAC_SINGLEs: 2 out of 4 50% Number of RPM macros: 15 Average Fanout of Non-Clock Nets: 3.53 }}} == CPU RAM Resources == The following gives the amount of space used by each SDK Software project when compiled in SDK 14.4. After a project is compiled, these values can be found in the {{{.elf.size}}} file in the SDK_Workspace folder. ||= '''Project''' =||= '''gcc Options''' =||= '''Instructions'''[[BR]]{{{.text}}}[[BR]]bytes =||= '''Data'''[[BR]]{{{.data}}} + {{{.bss}}}[[BR]]bytes =||= '''Total Size'''[[BR]]bytes =|| || AP || -Os -g3 || 203762|| 68102|| 271864|| || STA || -O2 -g3 || 207702|| 68166|| 275868|| || IBSS || -O2 -g3 || 204774|| 68076|| 272850|| || DCF || -Os -g || 54349|| 5552|| 59901|| || NOMAC || -O2 -g || 51174|| 6364|| 57538||