{{{#!comment [[Include(wiki:802.11/beta-note)]] }}} [[TracNav(802.11/TOC)]] = 802.11 Reference Design: Resource Usage = The 802.11 Reference Design targets the Virtex-6 LX240T FPGA on WARP v3 hardware. The FPGA resources used by the design change with each revision. The resource usage for the current release is listed below. == FPGA Resources == The table below summarizes the FPGA resource usage for v0.95 of the 802.11 Reference Design. ||= Resource =||= Used =||= Available[[BR]]LX240T =||= Percent Used =|| || Slice Registers || 66469 || 301440 || 22% || || LUTs || 61409 || 150720 || 40% || || Block RAMs (see note 1) || 244 || 416 || 59% || || DSP48 (multipliers) || 155 || 768 || 20% || || MMCM_ADV || 3 || 12 || 25% || || Ethernet MAC || 2 || 4 || 50% || || IOBs (see note 2) || 344 || 600 || 57% || * '''Note 1''': the ISE MAP reports utilization of RAMB36E1 and RAMB18E1 separately, even though these represent overlapping resources in the FPGA (each RAMB36E1 can be used as 2 RAMB18E1). The block RAM usage above lists the total number of RAMB36E1 primitives in the FPGA and {{{num(RAMB36E1) + ceil(num(RAMB18E1)/2)}}} as the number used. See the MAP report below for more details. * '''Note 2''': the IOB count includes all IOBs used by the design, not just the RF interfaces. Many of these pins are used for the DDR3 memory interface, Ethernet interfaces, user I/O, etc. == MAP Report == The resource usage section of the MAP report for the v0.95 release of the 802.11 Reference Design is copied below. You can find the full MAP report in the {{{implementation/system_map.mrp}}} file in your local copy of the 802.11 Reference Design XPS project. {{{ Release 14.4 Map P.49d (nt64) Xilinx Mapping Report File for Design 'system' Design Information ------------------ Command Line : map -mt 4 -o system_map.ncd -w -pr b -ol high -t 7 -register_duplication on -timing -detail system.ngd system.pcf Target Device : xc6vlx240t Target Package : ff1156 Target Speed : -2 Mapper Version : virtex6 -- $Revision: 1.55 $ Mapped Date : Mon Jul 14 10:01:10 2014 Design Summary -------------- Number of errors: 0 Number of warnings: 303 Slice Logic Utilization: Number of Slice Registers: 66,469 out of 301,440 22% Number used as Flip Flops: 66,312 Number used as Latches: 4 Number used as Latch-thrus: 0 Number used as AND/OR logics: 153 Number of Slice LUTs: 61,409 out of 150,720 40% Number used as logic: 51,384 out of 150,720 34% Number using O6 output only: 39,964 Number using O5 output only: 1,247 Number using O5 and O6: 10,173 Number used as ROM: 0 Number used as Memory: 6,926 out of 58,400 11% Number used as Dual Port RAM: 2,376 Number using O6 output only: 1,576 Number using O5 output only: 19 Number using O5 and O6: 781 Number used as Single Port RAM: 7 Number using O6 output only: 3 Number using O5 output only: 0 Number using O5 and O6: 4 Number used as Shift Register: 4,543 Number using O6 output only: 4,346 Number using O5 output only: 18 Number using O5 and O6: 179 Number used exclusively as route-thrus: 3,099 Number with same-slice register load: 2,828 Number with same-slice carry load: 253 Number with other load: 18 Slice Logic Distribution: Number of occupied Slices: 25,380 out of 37,680 67% Number of LUT Flip Flop pairs used: 79,536 Number with an unused Flip Flop: 20,890 out of 79,536 26% Number with an unused LUT: 18,127 out of 79,536 22% Number of fully used LUT-FF pairs: 40,519 out of 79,536 50% Number of unique control sets: 2,407 Number of slice register sites lost to control set restrictions: 9,106 out of 301,440 3% A LUT Flip Flop pair for this architecture represents one LUT paired with one Flip Flop within a slice. A control set is a unique combination of clock, reset, set, and enable signals for a registered element. The Slice Logic Distribution report is not meaningful if the design is over-mapped for a non-slice resource or if Placement fails. OVERMAPPING of BRAM resources should be ignored if the design is over-mapped for a non-BRAM resource or if placement fails. IO Utilization: Number of bonded IOBs: 344 out of 600 57% Number of LOCed IOBs: 344 out of 344 100% IOB Flip Flops: 163 IOB Master Pads: 10 IOB Slave Pads: 10 Specific Feature Utilization: Number of RAMB36E1/FIFO36E1s: 225 out of 416 54% Number using RAMB36E1 only: 225 Number using FIFO36E1 only: 0 Number of RAMB18E1/FIFO18E1s: 37 out of 832 4% Number using RAMB18E1 only: 37 Number using FIFO18E1 only: 0 Number of BUFG/BUFGCTRLs: 11 out of 32 34% Number used as BUFGs: 11 Number used as BUFGCTRLs: 0 Number of ILOGICE1/ISERDESE1s: 129 out of 720 17% Number used as ILOGICE1s: 64 Number used as ISERDESE1s: 65 Number of OLOGICE1/OSERDESE1s: 224 out of 720 31% Number used as OLOGICE1s: 99 Number used as OSERDESE1s: 125 Number of BSCANs: 2 out of 4 50% Number of BUFHCEs: 0 out of 144 0% Number of BUFIODQSs: 12 out of 72 16% Number of BUFRs: 5 out of 36 13% Number of LOCed BUFRs: 2 out of 5 40% Number of CAPTUREs: 0 out of 1 0% Number of DSP48E1s: 155 out of 768 20% Number of EFUSE_USRs: 0 out of 1 0% Number of FRAME_ECCs: 0 out of 1 0% Number of GTXE1s: 0 out of 20 0% Number of IBUFDS_GTXE1s: 0 out of 12 0% Number of ICAPs: 0 out of 2 0% Number of IDELAYCTRLs: 5 out of 18 27% Number of IODELAYE1s: 112 out of 720 15% Number of LOCed IODELAYE1s: 10 out of 112 8% Number of MMCM_ADVs: 3 out of 12 25% Number of PCIE_2_0s: 0 out of 2 0% Number of STARTUPs: 1 out of 1 100% Number of SYSMONs: 1 out of 1 100% Number of TEMAC_SINGLEs: 2 out of 4 50% Number of RPM macros: 15 Average Fanout of Non-Clock Nets: 3.61 Peak Memory Usage: 3520 MB Total REAL time to MAP completion: 1 hrs 17 secs Total CPU time to MAP completion (all processors): 1 hrs 1 mins 16 secs }}}