| 1 | = Adding 4 antenna support = |
| 2 | '''WORK IN PROGRESS''' |
| 3 | |
| 4 | == MHS Changes == |
| 5 | |
| 6 | Add new instances of {{{w3_ad_bridge}}} and {{{w3_iic_eeprom_axi}}} cores: |
| 7 | {{{#!sh |
| 8 | BEGIN w3_ad_bridge |
| 9 | PARAMETER INSTANCE = ad_bridge_FMC |
| 10 | PARAMETER HW_VER = 3.01.e |
| 11 | # Clock ports (inputs to w3_ad_bridge) |
| 12 | PORT sys_samp_clk_Tx = clk_20MHz |
| 13 | PORT sys_samp_clk_Tx_90 = clk_20MHz_90degphase |
| 14 | PORT sys_samp_clk_Rx = clk_20MHz |
| 15 | PORT ad_TXCLK_out_en = RF_AD_TXCLK_out_en |
| 16 | # Top-level AD9963 ports |
| 17 | PORT ad_RFA_TXD = rfc_txd |
| 18 | PORT ad_RFA_TXCLK = rfc_txclk |
| 19 | PORT ad_RFA_TXIQ = rfc_txiq |
| 20 | PORT ad_RFA_TRXD = rfc_trxd |
| 21 | PORT ad_RFA_TRXCLK = rfc_trxclk |
| 22 | PORT ad_RFA_TRXIQ = rfc_trxiq |
| 23 | PORT ad_RFB_TXD = rfd_txd |
| 24 | PORT ad_RFB_TXCLK = rfd_txclk |
| 25 | PORT ad_RFB_TXIQ = rfd_txiq |
| 26 | PORT ad_RFB_TRXD = rfd_trxd |
| 27 | PORT ad_RFB_TRXCLK = rfd_trxclk |
| 28 | PORT ad_RFB_TRXIQ = rfd_trxiq |
| 29 | PORT user_RFA_TXD_I = RFC_TX_I |
| 30 | PORT user_RFA_TXD_Q = RFC_TX_Q |
| 31 | PORT user_RFA_RXD_I = RFC_RX_I |
| 32 | PORT user_RFA_RXD_Q = RFC_RX_Q |
| 33 | PORT user_RFB_TXD_I = RFD_TX_I |
| 34 | PORT user_RFB_TXD_Q = RFD_TX_Q |
| 35 | PORT user_RFB_RXD_I = RFD_RX_I |
| 36 | PORT user_RFB_RXD_Q = RFD_RX_Q |
| 37 | END |
| 38 | |
| 39 | BEGIN w3_iic_eeprom_axi |
| 40 | PARAMETER INSTANCE = w3_iic_eeprom_FMC |
| 41 | PARAMETER HW_VER = 1.00.b |
| 42 | PARAMETER C_BASEADDR = 0x70410000 |
| 43 | PARAMETER C_HIGHADDR = 0x7041ffff |
| 44 | PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 7 |
| 45 | PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 7 |
| 46 | PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 7 |
| 47 | PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 7 |
| 48 | PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 7 |
| 49 | BUS_INTERFACE S_AXI = mb_low_axi_periph |
| 50 | PORT S_AXI_ACLK = clk_160MHz |
| 51 | PORT iic_scl = iic_eeprom_fmc_scl_pin |
| 52 | PORT iic_sda = iic_eeprom_fmc_sda_pin |
| 53 | END |
| 54 | }}} |
| 55 | |
| 56 | Add port connections to {{{radio_controller_axi}}} instance: |
| 57 | {{{ |
| 58 | BEGIN radio_controller_axi |
| 59 | ... |
| 60 | PORT RFC_TxEn = RFC_TxEn |
| 61 | PORT RFC_RxEn = RFC_RxEn |
| 62 | PORT RFC_RxHP = RFC_RxHP |
| 63 | PORT RFC_SHDN = RFC_SHDN |
| 64 | PORT RFC_SPI_SCLK = RFC_SPI_SCLK |
| 65 | PORT RFC_SPI_MOSI = RFC_SPI_MOSI |
| 66 | PORT RFC_SPI_CSn = RFC_SPI_CSn |
| 67 | PORT RFC_B = RFC_B |
| 68 | PORT RFC_LD = RFC_LD |
| 69 | PORT RFC_PAEn_24 = RFC_PAEn_24 |
| 70 | PORT RFC_PAEn_5 = RFC_PAEn_5 |
| 71 | PORT RFC_AntSw = RFC_AntSw |
| 72 | PORT RFD_TxEn = RFD_TxEn |
| 73 | PORT RFD_RxEn = RFD_RxEn |
| 74 | PORT RFD_RxHP = RFD_RxHP |
| 75 | PORT RFD_SHDN = RFD_SHDN |
| 76 | PORT RFD_SPI_SCLK = RFD_SPI_SCLK |
| 77 | PORT RFD_SPI_MOSI = RFD_SPI_MOSI |
| 78 | PORT RFD_SPI_CSn = RFD_SPI_CSn |
| 79 | PORT RFD_B = RFD_B |
| 80 | PORT RFD_LD = RFD_LD |
| 81 | PORT RFD_PAEn_24 = RFD_PAEn_24 |
| 82 | PORT RFD_PAEn_5 = RFD_PAEn_5 |
| 83 | PORT RFD_AntSw = RFD_AntSw |
| 84 | .... |
| 85 | PORT usr_RFC_statLED_Tx = RFC_led_g |
| 86 | PORT usr_RFC_statLED_Rx = RFC_led_r |
| 87 | PORT usr_RFD_statLED_Tx = RFD_led_g |
| 88 | PORT usr_RFD_statLED_Rx = RFD_led_r |
| 89 | .... |
| 90 | PORT usr_RFC_TxEn = phy_rc_txen_c |
| 91 | PORT usr_RFC_RxEn = rc_usr_rxen |
| 92 | PORT usr_RFC_RxHP = agc_rfc_rxhp |
| 93 | PORT usr_RFC_RxGainBB = agc_rfc_g_bb |
| 94 | PORT usr_RFC_RxGainRF = agc_rfc_g_rf |
| 95 | PORT usr_RFC_TxGain = phy_rc_tx_gain_c |
| 96 | PORT usr_RFD_TxEn = phy_rc_txen_d |
| 97 | PORT usr_RFD_RxEn = rc_usr_rxen |
| 98 | PORT usr_RFD_RxHP = agc_rfd_rxhp |
| 99 | PORT usr_RFD_RxGainBB = agc_rfd_g_bb |
| 100 | PORT usr_RFD_RxGainRF = agc_rfd_g_rf |
| 101 | PORT usr_RFD_TxGain = phy_rc_tx_gain_d |
| 102 | .... |
| 103 | END |
| 104 | }}} |
| 105 | |
| 106 | |
| 107 | Add parameter and port connections to {{{w3_ad_controller_axi}}} instance: |
| 108 | {{{#!sh |
| 109 | BEGIN w3_ad_controller_axi |
| 110 | ... |
| 111 | PARAMETER INCLUDE_RFC_RFD_IO = 1 |
| 112 | ... |
| 113 | PORT RFC_AD_spi_cs_n = RFC_AD_spi_cs_n |
| 114 | PORT RFC_AD_spi_sdio = RFC_AD_spi_sdio |
| 115 | PORT RFC_AD_spi_sclk = RFC_AD_spi_sclk |
| 116 | PORT RFC_AD_reset_n = RFC_AD_reset_n |
| 117 | PORT RFD_AD_spi_cs_n = RFD_AD_spi_cs_n |
| 118 | PORT RFD_AD_spi_sdio = RFD_AD_spi_sdio |
| 119 | PORT RFD_AD_spi_sclk = RFD_AD_spi_sclk |
| 120 | PORT RFD_AD_reset_n = RFD_AD_reset_n |
| 121 | ... |
| 122 | END |
| 123 | }}} |
| 124 | |
| 125 | Add port connections to WLAN PHY cores: |
| 126 | |
| 127 | {{{#!sh |
| 128 | BEGIN wlan_phy_tx_pmd_axiw |
| 129 | ... |
| 130 | PORT rfc_dac_i = RFC_TX_I |
| 131 | PORT rfc_dac_q = RFC_TX_Q |
| 132 | PORT rfd_dac_i = RFD_TX_I |
| 133 | PORT rfd_dac_q = RFD_TX_Q |
| 134 | ... |
| 135 | PORT rc_usr_txen_c = phy_rc_txen_c |
| 136 | PORT rc_usr_txen_d = phy_rc_txen_d |
| 137 | ... |
| 138 | PORT rc_tx_gain_c = phy_rc_tx_gain_c |
| 139 | PORT rc_tx_gain_d = phy_rc_tx_gain_d |
| 140 | ... |
| 141 | PORT phy_tx_gain_c = mac_phy_tx_gain_c |
| 142 | PORT phy_tx_gain_d = mac_phy_tx_gain_d |
| 143 | ... |
| 144 | END |
| 145 | |
| 146 | BEGIN wlan_phy_rx_pmd_axiw |
| 147 | ... |
| 148 | PORT rfc_rx_i = agc_rfc_i |
| 149 | PORT rfc_rx_q = agc_rfc_q |
| 150 | PORT rfc_rssi = RFC_RSSI_D |
| 151 | PORT rfd_rx_i = agc_rfd_i |
| 152 | PORT rfd_rx_q = agc_rfd_q |
| 153 | PORT rfd_rssi = RFD_RSSI_D |
| 154 | ... |
| 155 | PORT rfc_g_rf = agc_rfc_g_rf |
| 156 | PORT rfc_g_bb = agc_rfc_g_bb |
| 157 | PORT rfd_g_rf = agc_rfd_g_rf |
| 158 | PORT rfd_g_bb = agc_rfd_g_bb |
| 159 | }}} |
| 160 | |
| 161 | |
| 162 | |
| 163 | == UCF Changes == |
| 164 | |
| 165 | {{{#!sh |
| 166 | |
| 167 | ############################# |
| 168 | # FMC-RF-2X245 RF Interfaces |
| 169 | ############################# |
| 170 | |
| 171 | #User LEDs |
| 172 | NET "RFC_LED_G" LOC = L19 | IOSTANDARD = LVCMOS25; |
| 173 | NET "RFC_LED_R" LOC = L18 | IOSTANDARD = LVCMOS25; |
| 174 | |
| 175 | NET "RFD_LED_G" LOC = D16 | IOSTANDARD = LVCMOS25; |
| 176 | NET "RFD_LED_R" LOC = A15 | IOSTANDARD = LVCMOS25; |
| 177 | |
| 178 | #FMC module I2C EEPROM |
| 179 | NET "iic_eeprom_fmc_scl_pin" LOC = F23 | IOSTANDARD = LVCMOS25; |
| 180 | NET "iic_eeprom_fmc_sda_pin" LOC = F24 | IOSTANDARD = LVCMOS25; |
| 181 | |
| 182 | #RSSI ADC |
| 183 | NET "RFC_RSSI_D<0>" LOC = D21 | IOSTANDARD = LVCMOS25; |
| 184 | NET "RFC_RSSI_D<1>" LOC = E19 | IOSTANDARD = LVCMOS25; |
| 185 | NET "RFC_RSSI_D<2>" LOC = G20 | IOSTANDARD = LVCMOS25; |
| 186 | NET "RFC_RSSI_D<3>" LOC = E22 | IOSTANDARD = LVCMOS25; |
| 187 | NET "RFC_RSSI_D<4>" LOC = E23 | IOSTANDARD = LVCMOS25; |
| 188 | NET "RFC_RSSI_D<5>" LOC = F21 | IOSTANDARD = LVCMOS25; |
| 189 | NET "RFC_RSSI_D<6>" LOC = B20 | IOSTANDARD = LVCMOS25; |
| 190 | NET "RFC_RSSI_D<7>" LOC = B23 | IOSTANDARD = LVCMOS25; |
| 191 | NET "RFC_RSSI_D<8>" LOC = C19 | IOSTANDARD = LVCMOS25; |
| 192 | NET "RFC_RSSI_D<9>" LOC = C23 | IOSTANDARD = LVCMOS25; |
| 193 | |
| 194 | NET "RFD_RSSI_D<0>" LOC = D19 | IOSTANDARD = LVCMOS25; |
| 195 | NET "RFD_RSSI_D<1>" LOC = E21 | IOSTANDARD = LVCMOS25; |
| 196 | NET "RFD_RSSI_D<2>" LOC = A23 | IOSTANDARD = LVCMOS25; |
| 197 | NET "RFD_RSSI_D<3>" LOC = A24 | IOSTANDARD = LVCMOS25; |
| 198 | NET "RFD_RSSI_D<4>" LOC = F19 | IOSTANDARD = LVCMOS25; |
| 199 | NET "RFD_RSSI_D<5>" LOC = H19 | IOSTANDARD = LVCMOS25; |
| 200 | NET "RFD_RSSI_D<6>" LOC = F20 | IOSTANDARD = LVCMOS25; |
| 201 | NET "RFD_RSSI_D<7>" LOC = H20 | IOSTANDARD = LVCMOS25; |
| 202 | NET "RFD_RSSI_D<8>" LOC = C20 | IOSTANDARD = LVCMOS25; |
| 203 | NET "RFD_RSSI_D<9>" LOC = J20 | IOSTANDARD = LVCMOS25; |
| 204 | |
| 205 | NET "FMC_RF_RSSI_CLK" LOC = G13 | IOSTANDARD = LVCMOS25; |
| 206 | NET "FMC_RF_RSSI_PD" LOC = A21 | IOSTANDARD = LVCMOS25; |
| 207 | |
| 208 | #FMC module RF A pins (probably renamed RF C in user project) |
| 209 | |
| 210 | #ADC/DAC |
| 211 | NET "RFC_AD_spi_sclk_pin" LOC = B25 | IOSTANDARD = LVCMOS25; |
| 212 | NET "RFC_AD_SPI_SDIO" LOC = D26 | IOSTANDARD = LVCMOS25 | PULLDOWN; |
| 213 | NET "RFC_AD_spi_cs_n_pin" LOC = D27 | IOSTANDARD = LVCMOS25; |
| 214 | NET "RFC_AD_reset_n_pin" LOC = B27 | IOSTANDARD = LVCMOS25; |
| 215 | |
| 216 | NET "RFC_AD_TRXCLK" LOC = C28 | IOSTANDARD = LVCMOS25; |
| 217 | NET "RFC_AD_TRXIQ" LOC = D29 | IOSTANDARD = LVCMOS25; |
| 218 | |
| 219 | NET "RFC_AD_TRXD<0>" LOC = C29 | IOSTANDARD = LVCMOS25; |
| 220 | NET "RFC_AD_TRXD<1>" LOC = C24 | IOSTANDARD = LVCMOS25; |
| 221 | NET "RFC_AD_TRXD<2>" LOC = C22 | IOSTANDARD = LVCMOS25; |
| 222 | NET "RFC_AD_TRXD<3>" LOC = G27 | IOSTANDARD = LVCMOS25; |
| 223 | NET "RFC_AD_TRXD<4>" LOC = G28 | IOSTANDARD = LVCMOS25; |
| 224 | NET "RFC_AD_TRXD<5>" LOC = D22 | IOSTANDARD = LVCMOS25; |
| 225 | NET "RFC_AD_TRXD<6>" LOC = G26 | IOSTANDARD = LVCMOS25; |
| 226 | NET "RFC_AD_TRXD<7>" LOC = A25 | IOSTANDARD = LVCMOS25; |
| 227 | NET "RFC_AD_TRXD<8>" LOC = A26 | IOSTANDARD = LVCMOS25; |
| 228 | NET "RFC_AD_TRXD<9>" LOC = H27 | IOSTANDARD = LVCMOS25; |
| 229 | NET "RFC_AD_TRXD<10>" LOC = E27 | IOSTANDARD = LVCMOS25; |
| 230 | NET "RFC_AD_TRXD<11>" LOC = B26 | IOSTANDARD = LVCMOS25; |
| 231 | |
| 232 | NET "RFC_AD_TXCLK" LOC = C27 | IOSTANDARD = LVCMOS25; |
| 233 | NET "RFC_AD_TXIQ" LOC = C30 | IOSTANDARD = LVCMOS25; |
| 234 | |
| 235 | NET "RFC_AD_TXD<0>" LOC = F26 | IOSTANDARD = LVCMOS25; |
| 236 | NET "RFC_AD_TXD<1>" LOC = K21 | IOSTANDARD = LVCMOS25; |
| 237 | NET "RFC_AD_TXD<2>" LOC = E24 | IOSTANDARD = LVCMOS25; |
| 238 | NET "RFC_AD_TXD<3>" LOC = G25 | IOSTANDARD = LVCMOS25; |
| 239 | NET "RFC_AD_TXD<4>" LOC = F25 | IOSTANDARD = LVCMOS25; |
| 240 | NET "RFC_AD_TXD<5>" LOC = E26 | IOSTANDARD = LVCMOS25; |
| 241 | NET "RFC_AD_TXD<6>" LOC = A19 | IOSTANDARD = LVCMOS25; |
| 242 | NET "RFC_AD_TXD<7>" LOC = D24 | IOSTANDARD = LVCMOS25; |
| 243 | NET "RFC_AD_TXD<8>" LOC = A18 | IOSTANDARD = LVCMOS25; |
| 244 | NET "RFC_AD_TXD<9>" LOC = L21 | IOSTANDARD = LVCMOS25; |
| 245 | NET "RFC_AD_TXD<10>" LOC = L20 | IOSTANDARD = LVCMOS25; |
| 246 | NET "RFC_AD_TXD<11>" LOC = D30 | IOSTANDARD = LVCMOS25; |
| 247 | |
| 248 | #Front end |
| 249 | NET "RFC_PAEn_24_pin" LOC = D14 | IOSTANDARD = LVCMOS25; |
| 250 | NET "RFC_PAEn_5_pin" LOC = M12 | IOSTANDARD = LVCMOS25; |
| 251 | NET "RFC_AntSw_pin<0>" LOC = M11 | IOSTANDARD = LVCMOS25; |
| 252 | NET "RFC_AntSw_pin<1>" LOC = A13 | IOSTANDARD = LVCMOS25; |
| 253 | |
| 254 | #Transceiver |
| 255 | NET "RFC_B_pin<0>" LOC = B30 | IOSTANDARD = LVCMOS25; |
| 256 | NET "RFC_B_pin<1>" LOC = F28 | IOSTANDARD = LVCMOS25; |
| 257 | NET "RFC_B_pin<2>" LOC = B31 | IOSTANDARD = LVCMOS25; |
| 258 | NET "RFC_B_pin<3>" LOC = E28 | IOSTANDARD = LVCMOS25; |
| 259 | NET "RFC_B_pin<4>" LOC = D25 | IOSTANDARD = LVCMOS25; |
| 260 | NET "RFC_B_pin<5>" LOC = A30 | IOSTANDARD = LVCMOS25; |
| 261 | NET "RFC_B_pin<6>" LOC = A31 | IOSTANDARD = LVCMOS25; |
| 262 | |
| 263 | NET "RFC_SPI_SCLK_pin" LOC = A29 | IOSTANDARD = LVCMOS25; |
| 264 | NET "RFC_SPI_CSn_pin" LOC = B18 | IOSTANDARD = LVCMOS25; |
| 265 | NET "RFC_SPI_MOSI_pin" LOC = J22 | IOSTANDARD = LVCMOS25; |
| 266 | NET "RFC_RXEN_pin" LOC = H22 | IOSTANDARD = LVCMOS25; |
| 267 | NET "RFC_RXHP_pin" LOC = B28 | IOSTANDARD = LVCMOS25; |
| 268 | NET "RFC_SHDN_pin" LOC = K22 | IOSTANDARD = LVCMOS25; |
| 269 | NET "RFC_TXEN_pin" LOC = C18 | IOSTANDARD = LVCMOS25; |
| 270 | NET "RFC_LD_pin" LOC = A28 | IOSTANDARD = LVCMOS25; |
| 271 | |
| 272 | #FMC module RF B pins (probably renamed RF D in user project) |
| 273 | |
| 274 | #ADC/DAC |
| 275 | NET "RFD_AD_spi_sclk_pin" LOC = K17 | IOSTANDARD = LVCMOS25; |
| 276 | NET "RFD_AD_SPI_SDIO" LOC = B17 | IOSTANDARD = LVCMOS25 | PULLDOWN; |
| 277 | NET "RFD_AD_spi_cs_n_pin" LOC = D15 | IOSTANDARD = LVCMOS25; |
| 278 | NET "RFD_AD_reset_n_pin" LOC = G15 | IOSTANDARD = LVCMOS25; |
| 279 | |
| 280 | NET "RFD_AD_TRXCLK" LOC = L15 | IOSTANDARD = LVCMOS25; |
| 281 | NET "RFD_AD_TRXIQ" LOC = K18 | IOSTANDARD = LVCMOS25; |
| 282 | |
| 283 | NET "RFD_AD_TRXD<0>" LOC = J16 | IOSTANDARD = LVCMOS25; |
| 284 | NET "RFD_AD_TRXD<1>" LOC = H17 | IOSTANDARD = LVCMOS25; |
| 285 | NET "RFD_AD_TRXD<2>" LOC = J17 | IOSTANDARD = LVCMOS25; |
| 286 | NET "RFD_AD_TRXD<3>" LOC = L16 | IOSTANDARD = LVCMOS25; |
| 287 | NET "RFD_AD_TRXD<4>" LOC = G18 | IOSTANDARD = LVCMOS25; |
| 288 | NET "RFD_AD_TRXD<5>" LOC = M18 | IOSTANDARD = LVCMOS25; |
| 289 | NET "RFD_AD_TRXD<6>" LOC = H18 | IOSTANDARD = LVCMOS25; |
| 290 | NET "RFD_AD_TRXD<7>" LOC = M17 | IOSTANDARD = LVCMOS25; |
| 291 | NET "RFD_AD_TRXD<8>" LOC = D17 | IOSTANDARD = LVCMOS25; |
| 292 | NET "RFD_AD_TRXD<9>" LOC = J19 | IOSTANDARD = LVCMOS25; |
| 293 | NET "RFD_AD_TRXD<10>" LOC = K19 | IOSTANDARD = LVCMOS25; |
| 294 | NET "RFD_AD_TRXD<11>" LOC = E18 | IOSTANDARD = LVCMOS25; |
| 295 | |
| 296 | NET "RFD_AD_TXCLK" LOC = C17 | IOSTANDARD = LVCMOS25; |
| 297 | NET "RFD_AD_TXIQ" LOC = E17 | IOSTANDARD = LVCMOS25; |
| 298 | |
| 299 | NET "RFD_AD_TXD<0>" LOC = B16 | IOSTANDARD = LVCMOS25; |
| 300 | NET "RFD_AD_TXD<1>" LOC = J15 | IOSTANDARD = LVCMOS25; |
| 301 | NET "RFD_AD_TXD<2>" LOC = A16 | IOSTANDARD = LVCMOS25; |
| 302 | NET "RFD_AD_TXD<3>" LOC = H15 | IOSTANDARD = LVCMOS25; |
| 303 | NET "RFD_AD_TXD<4>" LOC = M15 | IOSTANDARD = LVCMOS25; |
| 304 | NET "RFD_AD_TXD<5>" LOC = F15 | IOSTANDARD = LVCMOS25; |
| 305 | NET "RFD_AD_TXD<6>" LOC = C15 | IOSTANDARD = LVCMOS25; |
| 306 | NET "RFD_AD_TXD<7>" LOC = M16 | IOSTANDARD = LVCMOS25; |
| 307 | NET "RFD_AD_TXD<8>" LOC = B15 | IOSTANDARD = LVCMOS25; |
| 308 | NET "RFD_AD_TXD<9>" LOC = G16 | IOSTANDARD = LVCMOS25; |
| 309 | NET "RFD_AD_TXD<10>" LOC = F18 | IOSTANDARD = LVCMOS25; |
| 310 | NET "RFD_AD_TXD<11>" LOC = F16 | IOSTANDARD = LVCMOS25; |
| 311 | |
| 312 | #Front end |
| 313 | NET "RFD_PAEn_24_pin" LOC = A14 | IOSTANDARD = LVCMOS25; |
| 314 | NET "RFD_PAEn_5_pin" LOC = B13 | IOSTANDARD = LVCMOS25; |
| 315 | NET "RFD_AntSw_pin<0>" LOC = C14 | IOSTANDARD = LVCMOS25; |
| 316 | NET "RFD_AntSw_pin<1>" LOC = B12 | IOSTANDARD = LVCMOS25; |
| 317 | |
| 318 | #Transceiver |
| 319 | NET "RFD_B_pin<0>" LOC = H12 | IOSTANDARD = LVCMOS25; |
| 320 | NET "RFD_B_pin<1>" LOC = H13 | IOSTANDARD = LVCMOS25; |
| 321 | NET "RFD_B_pin<2>" LOC = M13 | IOSTANDARD = LVCMOS25; |
| 322 | NET "RFD_B_pin<3>" LOC = G12 | IOSTANDARD = LVCMOS25; |
| 323 | NET "RFD_B_pin<4>" LOC = F14 | IOSTANDARD = LVCMOS25; |
| 324 | NET "RFD_B_pin<5>" LOC = H14 | IOSTANDARD = LVCMOS25; |
| 325 | NET "RFD_B_pin<6>" LOC = J12 | IOSTANDARD = LVCMOS25; |
| 326 | NET "RFD_SPI_SCLK_pin" LOC = G10 | IOSTANDARD = LVCMOS25; |
| 327 | NET "RFD_SPI_CSn_pin" LOC = K13 | IOSTANDARD = LVCMOS25; |
| 328 | NET "RFD_SPI_MOSI_pin" LOC = F11 | IOSTANDARD = LVCMOS25; |
| 329 | NET "RFD_RXEN_pin" LOC = K12 | IOSTANDARD = LVCMOS25; |
| 330 | NET "RFD_RXHP_pin" LOC = L13 | IOSTANDARD = LVCMOS25; |
| 331 | NET "RFD_SHDN_pin" LOC = K11 | IOSTANDARD = LVCMOS25; |
| 332 | NET "RFD_TXEN_pin" LOC = H10 | IOSTANDARD = LVCMOS25; |
| 333 | NET "RFD_LD_pin" LOC = L11 | IOSTANDARD = LVCMOS25; |
| 334 | |
| 335 | #Timing |
| 336 | Net RFC_AD_TRXCLK TNM_NET = TNM_RFC_AD_TRXCLK; |
| 337 | Net RFD_AD_TRXCLK TNM_NET = TNM_RFD_AD_TRXCLK; |
| 338 | |
| 339 | #TRXCLK runs at 20MHz (using decimation in AD9963s) |
| 340 | TIMESPEC TS_RFC_AD_TRXCLK = PERIOD TNM_RFC_AD_TRXCLK TS_samp_clk_pin*4; |
| 341 | TIMESPEC TS_RFD_AD_TRXCLK = PERIOD TNM_RFD_AD_TRXCLK TS_samp_clk_pin*4; |
| 342 | |
| 343 | #TRXCLK -> clk20 is first stage of registers (IDDR -> 2xDFF) |
| 344 | TIMESPEC TS_RFC_TRX_TO_20M = FROM "TNM_RFC_AD_TRXCLK" to "TNM_clk_20MHz" 40ns; |
| 345 | TIMESPEC TS_RFD_TRX_TO_20M = FROM "TNM_RFD_AD_TRXCLK" to "TNM_clk_20MHz" 40ns; |
| 346 | |
| 347 | #clk20 -> clk160 is paths from ad_bridge to sample-consuming PHY cores |
| 348 | TIMESPEC TS_RFC_20M_TO_160M = FROM "TNM_clk_20MHz" to "TNM_clk_160" 6.2ns; |
| 349 | TIMESPEC TS_RFD_20M_TO_160M = FROM "TNM_clk_20MHz" to "TNM_clk_160" 6.2ns; |
| 350 | |
| 351 | |
| 352 | INST "RFC_AD_TRXD<*>" TNM = RFC_AD_TRXD_group; |
| 353 | NET "RFC_AD_TRXCLK" TNM_NET = RFC_AD_TRXCLK; |
| 354 | TIMEGRP "RFC_AD_TRXD_group" OFFSET = IN 0.7 ns VALID 22 ns BEFORE "RFC_AD_TRXCLK" RISING; |
| 355 | TIMEGRP "RFC_AD_TRXD_group" OFFSET = IN 0.7 ns VALID 22 ns BEFORE "RFC_AD_TRXCLK" FALLING; |
| 356 | |
| 357 | INST "RFD_AD_TRXD<*>" TNM = RFD_AD_TRXD_group; |
| 358 | NET "RFD_AD_TRXCLK" TNM_NET = RFD_AD_TRXCLK; |
| 359 | TIMEGRP "RFD_AD_TRXD_group" OFFSET = IN 0.7 ns VALID 22 ns BEFORE "RFD_AD_TRXCLK" RISING; |
| 360 | TIMEGRP "RFD_AD_TRXD_group" OFFSET = IN 0.7 ns VALID 22 ns BEFORE "RFD_AD_TRXCLK" FALLING; |
| 361 | |
| 362 | #Mark TRX-samp_clk_rx paths as fully async, with short max route (use DFFs near ILOGIC.IDDRs) |
| 363 | INST "ad_bridge_FMC/ad_bridge_FMC/DDR_REGS_RFA_RFB[*].IDDR*" TNM = "AD_TRXCLK_IDDRS_FMC"; |
| 364 | INST "ad_bridge_FMC/ad_bridge_FMC/DDR_REGS_RFA_RFB[*].DFF2*" TNM = "AD_SYSCLK_FFS_FMC"; |
| 365 | |
| 366 | TIMESPEC TS_async_rx_samp_clks_FMC_IN = FROM "AD_TRXCLK_IDDRS_FMC" TO "AD_SYSCLK_FFS_FMC" 2 ns DATAPATHONLY; |
| 367 | TIMESPEC TS_async_rx_samp_clks_FMC_OUT = FROM "AD_SYSCLK_FFS_FMC" TO "AD_TRXCLK_IDDRS_FMC" 2 ns DATAPATHONLY; |
| 368 | |
| 369 | }}} |