Changes between Version 2 and Version 3 of Analog Board


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Timestamp:
Feb 15, 2007, 2:44:42 AM (17 years ago)
Author:
sgupta
Comment:

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  • Analog Board

    v2 v3  
    11= WARP Analog Board =
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    3 The WARP Analog Board is a debug daughtercard that has 4 channels of Digital-to-Analog conversion and 2 channels of Analog-to-Digital conversion. All six channels are 14-bit buses with direct connection to the FPGA. The analog interface is handled by MCX jacks with an output voltage swing of 2Vp-p.
     3The WARP Analog Board is a debug daughtercard that has 4 channels of Digital-to-Analog conversion and 2 channels of Analog-to-Digital conversion. The digitial-to-analog conversion is done by two dual-port, 14-bit, 125MSPS DACs ([http://www.analog.com/en/prod/0%2C2877%2CAD9767%2C00.html AD9767]). The analog-to-digital conversion uses a dual-port, 14-bit, 65MSPS ADC ([http://www.analog.com/en/prod/0%2C2877%2CAD9248%2C00.html AD9248]). The analog interface is handled by MCX jacks with a maximum output voltage swing of 2Vp-p. All necessary clocks are generated locally on the board as well.
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     5Additionally, we provide a [http://warp.rice.edu/trac/browser/PlatformSupport/CustomPeripherals/pcores/analog_bridge_v1_00_a hardware] bridge core to ease the use of this daughtercard when used in conjunction with the WARP FPGA board. The cores implement all necessary details, with input and output ports visible in Xilinx Platform Studio for the user to connect to.
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    57[[Image(WARPImages:AnalogBoard_sm.jpg)]]
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    7 Additionally, an interface for a subsequent card is provided if needed for use of further I/O.
     9An interface for a subsequent card is also provided, if needed, for use of further I/O.
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    911= WARP Analog Board Design Files =