High Throughput, Parallel, Scalable LDPC Encoder/Decoder Architecture for OFDM Systems

2006 IEEE Dallas Circuits and Systems Workshop

Authors: Yang Sun, Marjan Karkooti, and Joseph R. Cavallaro

Abstract

This paper presents a high throughput, parallel, scalable and irregular LDPC coding and decoding system hardware implementation that supports twelve combinations of block lengths 648, 1296, 1944 bits and code rates 1/2, 2/3, 3/4, 5/6 based on IEEE 802.11n standard. Based on architecture-aware LDPC codes, we propose an efficient joint LDPC coding and decoding hardware architecture. The prototype architecture is being implemented on FPGA and tested over the air on our wireless OFDM testbed, which is a highly capable, scalable and extensible platform for advanced wireless research. The ASIC resource requirements of the decoder are reported and a trade-off between pipelined and non-pipelined implementation is described.

Citation

@inproceedings{Sun:2006,
	Author = {Y. Sun and M. Karkooti and J. R. Cavallaro},
	Booktitle = {IEEE Dallas Circuits and Systems Workshop},
	Title = {High Throughput, Parallel, Scalable LDPC Encoder/Decoder Architecture for OFDM Systems},
	Year = {2006}}