Changes between Version 1 and Version 2 of DaughtercardSpec

Timestamp:

Dec 28, 2006, 12:14:08 AM (17 years ago)

Author:

murphpo

Comment:

--

DaughtercardSpec

@@ -4 +4 @@
 
 [[Image(WARPImages:DaughtercardSlotSchematic.png)]]
-
 
 ----
@@ -21 +20 @@
  * øG = 0.1" (diameter before plating); plated mounting hole (connected to ground)
 
-WARP daughtercards use two 80 pin 4mm headers with metal fittings from the DF17 series of connectors from Hirose. The Hirose part number is DF17(4.0)-80DP-0.5V(51). See [attachment:wiki:WARPFiles:Hirose_DF17_Connectors_Datasheet.pdf?format=raw Hirose DF17 Connectors Datasheet] for the full mechanical and PCB footprint details.
+A PDF version of this drawing is also available: [attachment:wiki:WARPFiles:Daughtercard_Mech_Drawing.pdf?format=raw Daughtercard Mechanical Drawing PDF].
+
+WARP daughtercards use two 80 pin headers per daughtercard slot. The connectors are 0.5mm pitch, 4mm height headers with metal fittings from the Hirose DF17 series of connectors. The Hirose part number is DF17(4.0)-80DP-0.5V(57). See the [attachment:wiki:WARPFiles:Hirose_DF17_Connectors_Datasheet.pdf?format=raw Hirose DF17 Connectors Datasheet] for the full mechanical details (pg 6) and recommended PCB footprint (pg 8). 
+
+The parts are available from [http://www.digikey.com Digikey]; search for Digikey part number [http://www.digikey.com/scripts/DkSearch/dksus.dll?Detail?Ref=13424&Row=476393&Site=US H11148CT-ND].
 
 === Reference Designs ===
 [attachment:wiki:WARPFiles:Daughtercard_Template_Schematic.zip?format=raw Daughtercard_Template_Schematic.zip]
+  Cadence Capture CIS 15.7 project, schematic design and parts library.
 
 [attachment:wiki:WARPFiles:Daughtercard_Template_Board.zip?format=raw Daughtercard_Template_Board.zip]
+  Cadence Allegro PCB Editor 15.7 padstacks, package symbols and sample board.