Changes between Version 4 and Version 5 of Exercises/13_4/SysGenExport


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Timestamp:
Aug 22, 2012, 4:21:33 PM (12 years ago)
Author:
chunter
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  • Exercises/13_4/SysGenExport

    v4 v5  
    22''(compatible with WARP v2 and WARP v3)''
    33
     4In the [wiki:Exercises/13_4/IntroToXPS Introduction to XPS] project, a peripheral core is provided and users connect it to the rest of the system specified in a WARP template XPS design. In this exercise, users will learn how to create this peripheral core from a tool known as Xilinx System Generator (SysGen).
    45
    56== Prerequisites ==
    6  * You have a WARP v3 board
     7 * You have a WARP v2 or WARP v3 board
    78 * ESD protection for the WARP board (wrist strap, etc)
    8  * External USB JTAG cable and a micro USB cable for UART
     9 * WARP v2: USB cable for programming and USB cable for UART
     10 * WARP v3: External USB JTAG cable and a micro USB cable for UART
    911 * Complete installation of ISE System Edition 13.4
    10  * Checked out a local copy of the [wiki:edk_user_repository WARP Repository]
    1112 * Set up a terminal on your computer using PuTTY or an alternative. Instructions to do this are available [wiki:HowTo/SetUpPuTTY instructions here].
    12  * Familiarity with the Xilinx SDK. Make sure you have completed the [wiki:Exercises/13_4/IntroToSDK Introduction to the SDK] exercise.
    1313
    1414== Overview ==