CM-MMCX User Guide: Configuration

The CM-MMCX module includes a 2-position SIP switch connected to FPGA I/O. This switch can be used to configure per-node clocking in user applications at run time. The function of each switch is undefined by default. User applications must access the corresponding FPGA I/O and update clock configurations as needed.

FPGA Contraints

The CM-MMCX PCB does not include pull-up resistors on the FPGA I/O connected to the switches. When a switch is closed the corresponding FPGA I/O is tied to ground. When a switch is open the FPGA I/O is floating. The user FPGA design must include a PULLUP constraint on the corresponding net to ensure valid logic levels in both switch positions. See the UCF snippet below for an example.

NET "cm_mmcx_sw<0>" LOC = V30 | IOSTANDARD = LVCMOS25 | PULLUP; #CLKHDR_CTRL12 in schematics
NET "cm_mmcx_sw<1>" LOC = R34 | IOSTANDARD = LVCMOS25 | PULLUP; #CLKHDR_CTRL13 in schematics