Changes between Version 9 and Version 10 of HardwareUsersGuides/CM-PLL/Connectors


Ignore:
Timestamp:
Sep 11, 2015, 10:29:48 AM (9 years ago)
Author:
murphpo
Comment:

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  • HardwareUsersGuides/CM-PLL/Connectors

    v9 v10  
    4848[[BR]]
    4949
     50{{{#!comment
     51Pin map for CM-PLL v1.0 hardware - remove once we're sure the mapping is correct and works for v1.1 hardware
    5052||||||=  '''Out''' Header  =||
    5153||= Pin =||= Function =||= Specs =||
    … …  
    5456|| 5 || HDR_OUT<1> || FPGA Pin W34 ||
    5557|| 7 || HDR_OUT<0> || FPGA Pin W30 ||
     58|| 9 || Reference Clock Output || Single-ended clock signal, 3.3v max ||
     59|| 2,4,6,8,10 || Ground ||||
     60}}}
     61
     62||||||=  '''Out''' Header  =||
     63||= Pin =||= Function =||= Specs =||
     64|| 1 || HDR_OUT<3> || FPGA Pin W29 ||
     65|| 3 || HDR_OUT<2> || FPGA Pin W30 ||
     66|| 5 || HDR_OUT<1> || FPGA Pin W34 ||
     67|| 7 || HDR_OUT<0> || FPGA Pin V32 ||
    5668|| 9 || Reference Clock Output || Single-ended clock signal, 3.3v max ||
    5769|| 2,4,6,8,10 || Ground ||||