Changes between Version 7 and Version 8 of HardwareUsersGuides/CM-PLL/Connectors
- Timestamp:
- Mar 2, 2015, 9:01:01 PM (9 years ago)
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HardwareUsersGuides/CM-PLL/Connectors
v7 v8 38 38 39 39 ||||||= '''In''' Header =|| 40 || Pin || Function || Specs||40 ||= Pin =||= Function =||= Specs =|| 41 41 || 1 || Reference Clock Input || Single-ended clock signal, 3.3v max || 42 42 || 3 || HDR_IN<0> || FPGA Pin V28 || … … 49 49 50 50 ||||||= '''Out''' Header =|| 51 || Pin || Function || Specs||51 ||= Pin =||= Function =||= Specs =|| 52 52 || 1 || HDR_OUT<3> || FPGA Pin W29 || 53 53 || 3 || HDR_OUT<2> || FPGA Pin V32 || … … 57 57 || 2,4,6,8,10 || Ground |||| 58 58 59 A cable which connects the '''Out''' header of one board to the In header of another board should implement thismapping:59 A cable which connects the '''Out''' header of one board to the '''In''' header of another board should implement mapping: 60 60 61 61 || '''In''' Pin || '''Out''' Pin || Note ||
