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== WARP Clock Board Configuration ==

The AD9510 clock buffers have serial interfaces for configuring their internal register banks. We provide a custom hardware core which implements the necessary logic to drive these interfaces. The [source:/PlatformSupport/CustomPeripherals/pcores/clock_board_config_v1_02_a clock_board_config] core automatically configures the clock board when included in an FPGA design. This core requires a clock input which does not come from the clock board; the FPGA board's 100 MHz oscillator works well. Most of the core's other ports must be tied to the clock board connector's data pins, according to the following table. This assignment is handled automatically if you build your project using Base System Builder and the WARP FPGA Board's [source:/PlatformSupport/XBD/boards/ XBD].

|| '''clock_board_config[[BR]]Port''' || '''Clock Board[[BR]]Header Pin''' || '''FPGA[[BR]]Pin''' ||
|| cfg_radio_dat_out || 13 || AN25 ||
|| cfg_radio_csb_out || 12 || AK26 ||
|| cfg_radio_en_out || 11 || AJ25 ||
|| cfg_radio_clk_out || 15 || AL26 ||
|| cfg_logic_dat_out || 19 || AT27 ||
|| cfg_logic_csb_out || 18 || AR27 ||
|| cfg_logic_en_out || 16 || AN27 ||
|| cfg_logic_clk_out || 20 || AM27 ||

By default, the clock_board_config port selects the on-board oscillators as the clock sources for both AD9510 buffers. This selection can be overridden using a top-level parameter when instantiating the core. In XPS, you can right-click the clk_board_configurator core, choose Configure IP, then select MMCX or Oscillator for both clock inputs. You will need to resynthesize your hardware design after changing this parameter.