Changes between Version 1 and Version 2 of HardwareUsersGuides/FMC-BB-4DA/DACs
- Timestamp:
- Feb 18, 2013, 1:41:52 PM (11 years ago)
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HardwareUsersGuides/FMC-BB-4DA/DACs
v1 v2 6 6 All digital signals from both AD9116 are tied to FMC I/O pins. The user's FPGA design is responsible for all control, clocking and data input to the DACs. 7 7 8 Note: The FMC-BB-4DA PCB is designed to support all of the AD9114/AD9115/AD9116/AD9117 pin-compatible DACs. The schematics refer to the 14-bit AD9117. The PCB connects all 14 bits of the AD9117 data bus to the FMC header. The two LSB (DB[1:0], AD9117 pins [14,15]) are unused on boards assembled with the 12-bit AD0116. 9 8 10 == Data == 9 The two AD9116's can be clocked at different frequencies by the user design. The digital sample interface for each AD9116 is a 12-bit DDR bus, with samples for the two DACs presented on opposite edges of the clock.11 The digital sample interface for each AD9116 is a 12-bit DDR bus, with samples for the two DACs presented on alternating clock edges. Refer to the [http://www.analog.com/static/imported-files/data_sheets/AD9114_9115_9116_9117.pdf AD9116] datasheet for timing specifications of the DDR interface. The [wiki:cores/fmc_bb_4da_bridge fmc_bb_4da_bridge core] demonstrates how to use ODDR primitives in a Virtex-6 FPGA to interface two 12-bit signals in the FPGA to one 12-bit DDR output. 10 12 11 13 == Clocking == 12 Each AD9116 has one clock input. The input clock is used by both DACs in the IC. The sample rate of the two DACs in each AD9116 is equal to the input clock frequency. The two AD9116's on the FMC-BB-4DA can be clocked at different frequencies, if desired.14 Each AD9116 has one clock input. The input clock is used by both DACs in the IC. The digital and analog sample rates of the two DACs in each AD9116 are equal to the input clock frequency. The two AD9116's on the FMC-BB-4DA can be clocked at different frequencies, if desired. In order to meet setup/hold requirements at the AD9116 the user FPGA design should shift the clock signal (ideally by 90 degrees) away from transitions in the data signals. 13 15 14 16 == Control == … … 24 26 25 27 26
