| | 1 | [[TracNav(HardwareUsersGuides/FMC-BB-4DA/TOC)]] |
| | 2 | = FMC-BB-4DA User Guide: FMC LPC Interface = |
| | 3 | |
| | 4 | The FMC-BB-4DA module is designed (with a few deviations, explained below) to the [http://www.vita.com/fmc.html VITA 57.1 FMC] specification. This module has been tested in the FMC slot on WARP v3 kits. The details below will help determine compatibility with third-party FMC carriers. |
| | 5 | |
| | 6 | == Power == |
| | 7 | The FMC-BB-4DA module draws all its power from the FMC carrier. The required power supplies are: |
| | 8 | ||= FMC Net =||= Supported Voltages =|| |
| | 9 | || VADJ || 1.8v - 2.5v [[BR]] (see notes) || |
| | 10 | || 3P3V || 3.3v || |
| | 11 | || 3P3VAUX || 3.3v || |
| | 12 | |
| | 13 | || 12P0V || 12.0v || |
| | 14 | |
| | 15 | Other power connections on the FMC-RF-2X245 module: |
| | 16 | * 12P0V is not used |
| | 17 | * 3P3VAUX is only used for the EEPROM |
| | 18 | * VIO_B_M2C is tied to VADJ (on HPC carriers this will power VCCO for Bank B with VADJ, even though this module does not use any HB I/O) |
| | 19 | * VREF_A_M2C/VREF_B_M2C are unconnected |
| | 20 | * PG_M2C is tied to PG_C2M |
| | 21 | |
| | 22 | '''VADJ note''': the FMC VADJ net is tied to the digital interface power supplies of multiple circuits on the FMC-BB-4DA module. These interfaces are all specified over the range 1.8-2.5v. However, we have only tested this module on the WARP v3 kit, which ties VADJ to 2.5v. |
| | 23 | |
| | 24 | == FPGA I/O == |
| | 25 | The FMC-BB-4DA module uses I/O from the LA bank and will function with either LPC or HPC FMC carriers. |
| | 26 | |
| | 27 | Four I/O in the HA bank are tied to ground, for routing improvements on the PCB. All I/O in the HB bank are unconnected. |
| | 28 | |
| | 29 | The module does not generate any clock signals. Occupied CC signals in the LA bank are used for general I/O. |
| | 30 | |
| | 31 | == MGTs == |
| | 32 | The FMC-BB-4DA leaves all FMC MGT interfaces (the DPx and GBTCLKx signals) unconnected. |
| | 33 | |
| | 34 | == Misc I/O == |
| | 35 | '''JTAG''': The FMC JTAG signals are not used by circuits on the FMC-BB-4DA module. The module ties TDI to TDO to complete the carrier JTAG chain. TCK and TMS are not connected on the module. |
| | 36 | |
| | 37 | '''EEPROM''': A Microchip 24AA128 I2C 128Kb EEPROM is connected to the FMC I2C signals (SCL, SDA). Refer to the [wiki:../EEPROM EEPROM page] of this guide for details on the default EEPROM contents. |
| | 38 | |
| | 39 | == Mechanical == |
| | 40 | FMC-BB-4DA modules are built with either the MC-LPC-10 or MC-HPC-10 connector options (lead-free, LPC/HPC, 10mm stacking height). The module includes two mounting holes on either side of the FMC connector at the locations specified in the FMC standard. The module ships with 10mm standoffs pre-installed and mating screws for securing the module on the FMC carrier. |
| | 41 | |
| | 42 | The FMC-BB-4DA module dimensions are not strictly compliant with the mechanical specifications for FMC modules in VITA 57.1. |
| | 43 | |
| | 44 | The module dimensions are compliant in the region around the FMC connector. This is sufficient for mechanical compatibility with many FPGA carriers (including WARP v3) which orient their FMC slots with modules extending away from the carrier board. |
| | 45 | |
| | 46 | The FMC-BB-4DA module deviates from the standard at the other end of the board. The FMC-BB-4DA module is a rectangular PCB, while the FMC standard specifies a more complex shape which narrows at the connector end. This module is also shorter than a standard module. |
| | 47 | |
| | 48 | The deviations from the FMC outline specifications are not an issue when using this module on WARP v3 kits, nor on many other FMC-equipped FPGA development platforms we have seen. However the drawing below and electrical/IO/clocking details above should be carefully considered before using the FMC-RF-2X245 module on a third-party FMC carrier. |
| | 49 | |
| | 50 | [[Image(wiki:HardwareUsersGuides/FMC-BB-4DA/files:FMc-BB-4DA_mech.png, nolink)]][[BR]] |
| | 51 | '''FMC-BB-4DA Mechanical Drawing''' ([attachment:wiki:HardwareUsersGuides/FMC-BB-4DA/files:Mango_FMC-BB-4DA_Mech.pdf?format=raw PDF version]) |
| | 52 | |
| | 53 | == Pinout == |
| | 54 | Two pinout files are available to help with using the FMC-BB-4DA module. |
| | 55 | |
| | 56 | * [export:/Hardware/FMC-BB-4DA/Mango_FMC-BB-4DA_rev1p0_FMC-nets.xls FMC-nets.xls]: this spreadsheet provides the mapping of net name in the FMC-BB-4DA to the name of the corresponding FMC signal, using the names given in the FMC standard (e.g. HA00, LA10, etc.). |
| | 57 | |
| | 58 | * [source:/Hardware/FMC-BB-4DA/FMC-BB-4DA_WARPv3_Pinout.ucf FMC-BB-4DA_WARPv3_Pinout.ucf]: this text file provides the mapping of FMC-BB-4DA signals to FPGA pins on the WARP v3 kit, using the standard Xilinx UCF syntax. |
