Changes between Version 1 and Version 2 of HardwareUsersGuides/FMC-RF-2X245/RF
- Timestamp:
- Dec 11, 2012, 11:45:44 AM (11 years ago)
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HardwareUsersGuides/FMC-RF-2X245/RF
v1 v2 11 11 [[Image(wiki:HardwareUsersGuides/WARPv3/files:w3_RF_blkDiag.png, nolink)]] 12 12 13 On the FMC-RF-2X245 board and in our reference designs, these interfaces are labeled RF A and RF B, where RF A is nearer the top edge of the board (closer to the hex displays).13 On the FMC-RF-2X245 board these interfaces are labeled RF A and RF B. When used on a WARP v3 board, these interfaces will generally be referred to as RF C and RF D, to avoid conflicting with the WARP v3 on-board RF interfaces. 14 14 15 15 == AD9963 ADC/DAC == … … 17 17 The conversion between the analog I/Q and digital I/Q domains is handled by the Analog Devices AD9963 MxFE. The AD9963 integrates two 100MSps 12-bit ADCs, two 170MSps 12-bit DACs, interpolation and decimation filters and programmable analog gain and offset adjustments. Refer to the ADI [http://www.analog.com/static/imported-files/data_sheets/AD9961_9963.pdf AD9963 datasheet] for full specifications. 18 18 19 The AD9963 is very flexible and includes a register bank to control various functions on the chip. The registers are accessed via a dedicated SPI interface. We have designed the [wiki:/cores/w3_ad_controller w3_ad_controller] core to access the AD9963 registers via the SPI interface .19 The AD9963 is very flexible and includes a register bank to control various functions on the chip. The registers are accessed via a dedicated SPI interface. We have designed the [wiki:/cores/w3_ad_controller w3_ad_controller] core to access the AD9963 registers via the SPI interface when using this FMC module on a WARP v3 kit. 20 20 21 The digital I/Q ports on the AD9963 operate at double data rate, with I/Q interleaved. We have designed the [wiki:/cores/w3_ad_bridge w3_ad_bridge] core to connect these DDR ports to separate internal I/Q busses in user designs. 21 The digital I/Q ports on the AD9963 operate at double data rate, with I/Q interleaved. We have designed the [wiki:/cores/w3_ad_bridge w3_ad_bridge] core to connect these DDR ports to separate internal I/Q busses in user designs. One instance of the w3_ad_bridge core implements the interface to both RF interfaces. WARP v3 designs with four antennas will use two instances of the w3_ad_bridge bridge. 22 22 23 23 === Tx Data Path === … … 55 55 56 56 === Clocking === 57 The clocking configuration of the AD9963 is flexible and, as a result, complicated. There are t o main clock domains in the AD9963: data clocks, connected to the FPGA, and converter clocks, used by the ADC/DAC cores.57 The clocking configuration of the AD9963 is flexible and, as a result, complicated. There are two main clock domains in the AD9963: data clocks, connected to the FPGA, and converter clocks, used by the ADC/DAC cores. 58 58 59 59 The converter clocks are illustrated below.
