Changes between Initial Version and Version 1 of HardwareUsersGuides/FPGABoard_v2.2/Clocking

Timestamp:

Oct 17, 2009, 10:20:51 PM (15 years ago)

Author:

murphpo

Comment:

--

HardwareUsersGuides/FPGABoard_v2.2/Clocking

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+[[TracNav(HardwareUsersGuides/FPGABoard_v2.2/TOC)]]
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+== WARP FPGA Board Clocking ==
+
+=== On-board Oscillators ===
+The FPGA board has two oscillator footprints for general clocks. By default, one 100MHz oscillator is mounted (component Y7) and one footprint is left empty (component Y9) for future customization. Both oscillator footprints are connected to global clock (GCLK) pins on the FPGA.
+
+|| '''Clock''' || '''Component''' || '''FPGA Pin''' ||
+|| 100MHz || Y7 || AM21 ||
+|| NM || Y9 || AL20 ||
+
+=== Off-board Clock Sources ===
+The FPGA board has a header dedicated to off-board clocks. This header (component  J25) is used by the [wiki:HardwareUsersGuides/ClockBoard WARP Clock Board]. The header connects to four global clock (GCLK) pins on the FPGA, the 3.3v power plane and 8 general FPGA I/O.
+
+|| '''Header Pin''' || '''FPGA GCLK''' || '''FPGA Pin''' ||
+|| 3 || AP22 ||
+|| 4 || AP21 ||
+|| 7 || AN20 ||
+|| 8 || AP20 ||
+
+=== SystemACE CF Clocking ===
+The SystemACE CF controller requires a 33MHz clock which runs at all times. The FPGA requires a copy of this clock in order to use the SystemACE controller's microprocessor interface. A dedicated 33MHz oscillator (component Y6) is used on the FPGA board to supply this clock. The oscillator's output is split and driven to both the FPGA and the SystemACE CF controller.
+
+|| '''Clock''' || '''Component''' || '''FPGA''' '''Pin''' ||
+|| 33MHz || Y4 || AJ21 ||
+
+=== MGT Clocking ===
+Please see [wiki:HardwareUsersGuides/FPGABoard_v2.2/MGTs#MGTClocking MGTs] for details on clocking the FPGA's multi-gigabit transceivers.
+
+=== Other References ===
+ * [http://direct.xilinx.com/bvdocs/publications/ds083.pdf Xilinx Virtex-II Pro Datasheet] (Module 3: DC & Switching Characteristics)
+ * [http://direct.xilinx.com/bvdocs/userguides/ug012.pdf Xilinx Virtex-II Pro Users Guide] (Chapter 2: Timing Models and Chapter 3: Digital Clock Managers)
+ * [source:/Hardware/FPGA_Board/Rev1.2/Schematics_FPGABoard_1.2.pdf WARP FPGA Board Schematics] (pg. 2)