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Clocking

-                      v1
+                      v2
 === Off-board Clock Sources ===
 The FPGA board has a header dedicated to off-board clocks. This header (component  J25) is used by the [wiki:HardwareUsersGuides/ClockBoard WARP Clock Board]. The header connects to four global clock (GCLK) pins on the FPGA, the 3.3v power plane and 8 general FPGA I/O.
+The FPGA board has a header dedicated to off-board clocks. This header (component  J25) is used by the [wiki:HardwareUsersGuides/ClockBoard WARP Clock Board]. The header connects to two global clock (GCLK) pairs on the FPGA (allowing for differential clocks), the 3.3v power plane and 8 general FPGA I/O.
 || '''Header Pin''' || '''FPGA GCLK''' || '''FPGA Pin''' ||
+|| '''Header Pin''' || '''FPGA Pin''' ||
 || 3 || AP22 ||
 || 4 || AP21 ||
 …
 The SystemACE CF controller requires a 33MHz clock which runs at all times. The FPGA requires a copy of this clock in order to use the SystemACE controller's microprocessor interface. A dedicated 33MHz oscillator (component Y6) is used on the FPGA board to supply this clock. The oscillator's output is split and driven to both the FPGA and the SystemACE CF controller.
 || '''Clock''' || '''Component''' || '''FPGA''' '''Pin''' ||
+|| '''Clock''' || '''Component''' || '''FPGA Pin''' ||
 || 33MHz || Y4 || AJ21 ||