Changes between Version 1 and Version 2 of HardwareUsersGuides/FPGABoard_v2.2/Memory

Timestamp:

Oct 17, 2009, 10:43:38 PM (15 years ago)

Author:

murphpo

Comment:

--

HardwareUsersGuides/FPGABoard_v2.2/Memory

@@ -9 +9 @@
 The WARP FPGA Board v2.2 includes a DDR2 SO-DIMM slot. This connector is routed to dedicated FPGA I/O and clocking resources and supports up to 2GB modules.
 
-In order to use a SO-DIMM, the user FPGA design must include a DDR2 memory controller. Thankfully, Xilinx provides (and maintains) a high performance controller as part of their Multi-Port Memory Controller (MPMC).
+'''FPGA Board SO-DIMM slot''' (shown with 2GB SO-DIMM installed)
+[[Image(HardwareUsersGuides/FPGABoard_v2.2/Files:FPGABoard_Memory.jpg, align=right)]]
 
-[[Image(HardwareUsersGuides/FPGABoard_v1.2/Images:FPGA_Board_SRAM.jpg, align=right)]]
+In order to use the SO-DIMM, the user FPGA design must include a DDR2 memory controller. Thankfully, Xilinx provides (and maintains) a high performance controller as part of their Multi-Port Memory Controller (MPMC).
+
+We have verified the MPMC in EDK 10.1.03 and 11.3 using a 2GB SO-DIMM from Crucial (part [http://www.crucial.com/store/partspecs.aspx?imodule=CT25664AC667 CT25664AC667]). Other modules should be compatible, but may require customization of the MPMC parameters.
+
+There are a large number of pins and parameters involved in instantiating the MPMC in a design. We strongly recommend using Base System builder and our [source:/PlatformSupport/XBD/boards/Rice_University_WARP_FPGA_V4FX100_v22_ClkBoard/data XBD file] to generate MPMC designs. The MHS snippet below is an example instantiation (for EDK 10.1.03).
+
+{{{
+#!sh
+EGIN mpmc
+ PARAMETER INSTANCE = DDR2_SDRAM_2GB
+ PARAMETER HW_VER = 4.03.a
+ PARAMETER C_NUM_PORTS = 2
+ PARAMETER C_MEM_PARTNO = MT16HTF25664H-667
+ PARAMETER C_MEM_TYPE = DDR2
+ PARAMETER C_NUM_IDELAYCTRL = 4
+ PARAMETER C_IDELAYCTRL_LOC = IDELAYCTRL_X0Y0-IDELAYCTRL_X0Y1-IDELAYCTRL_X2Y1-IDELAYCTRL_X2Y0
+ PARAMETER C_MEM_DQS_WIDTH = 8
+ PARAMETER C_MEM_DM_WIDTH = 8
+ PARAMETER C_MEM_ADDR_WIDTH = 14
+ PARAMETER C_MEM_BANKADDR_WIDTH = 3
+ PARAMETER C_PIM0_BASETYPE = 2
+ PARAMETER C_PIM1_BASETYPE = 2
+ PARAMETER C_MPMC_CLK0_PERIOD_PS = 6250
+ PARAMETER C_MPMC_BASEADDR = 0x00000000
+ PARAMETER C_MPMC_HIGHADDR = 0x7fffffff
+ BUS_INTERFACE SPLB0 = ppc405_0_iplb1
+ BUS_INTERFACE SPLB1 = ppc405_0_dplb1
+ PORT DDR2_Addr = fpga_0_DDR2_SDRAM_2GB_DDR2_Addr
+ PORT DDR2_BankAddr = fpga_0_DDR2_SDRAM_2GB_DDR2_BankAddr
+ PORT DDR2_CAS_n = fpga_0_DDR2_SDRAM_2GB_DDR2_CAS_n
+ PORT DDR2_CE = fpga_0_DDR2_SDRAM_2GB_DDR2_CE
+ PORT DDR2_CS_n = fpga_0_DDR2_SDRAM_2GB_DDR2_CS_n
+ PORT DDR2_RAS_n = fpga_0_DDR2_SDRAM_2GB_DDR2_RAS_n
+ PORT DDR2_WE_n = fpga_0_DDR2_SDRAM_2GB_DDR2_WE_n
+ PORT DDR2_DM = fpga_0_DDR2_SDRAM_2GB_DDR2_DM
+ PORT DDR2_DQS = fpga_0_DDR2_SDRAM_2GB_DDR2_DQS
+ PORT DDR2_DQS_n = fpga_0_DDR2_SDRAM_2GB_DDR2_DQS_n
+ PORT DDR2_DQ = fpga_0_DDR2_SDRAM_2GB_DDR2_DQ
+ PORT DDR2_Clk = fpga_0_DDR2_SDRAM_2GB_DDR2_Clk
+ PORT DDR2_Clk_n = fpga_0_DDR2_SDRAM_2GB_DDR2_Clk_n
+ PORT DDR2_ODT = fpga_0_DDR2_SDRAM_2GB_DDR2_ODT
+ PORT MPMC_Clk0 = proc_clk_s
+ PORT MPMC_Clk90 = DDR2_SDRAM_2GB_mpmc_clk_90_s
+ PORT MPMC_Clk_200MHz = clk_200mhz_s
+ PORT MPMC_Rst = sys_periph_reset
+END
+}}}
+
+