| | 1 | [[TracNav(HardwareUsersGuides/FPGABoard_v2.2/TOC)]] |
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| | 3 | == WARP FPGA Board I/O == |
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| | 5 | === USB UART === |
| | 6 | The FPGA board includes a USB-UART interface, built around the FTDI [http://www.ftdichip.com/Products/FT232R.htm FT232R transceiver]. You can connect this port to a PC via a standard USB cable, and your OS will regonize a new serial port. You will need the [http://www.ftdichip.com/Drivers/VCP.htm Virtual COM Port drivers] from FTDI. The transceiver presents a 2-wire (Tx/Rx) UART interface to the FPGA, which can be used with the Xilinx UART transceiver cores. |
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| | 8 | === RS-232 UART === |
| | 9 | The FPGA board also includes a standard RS-232 serial port. The board's female DB9 port is configured just like a PC, with Tx on pin 3, Rx on pin 2 and GND on pin 5. The rest of the signals are unconnected. You must use a null-modem (i.e. crossover) cable to connect this port directly to a PC. |
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| | 11 | The LVTTL-RS232 level shifting is handled on the FPGA board by a MAX3319 (from [www.maxim-ic.com/quick_view2.cfm/qv_pk/2288 Maxim]. |
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| | 15 | === Digital I/O === |
| | 16 | [[Image(HardwareUsersGuides/FPGABoard_v2.2/Images:FPGA_Board_DebugIO.jpg)]] |
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| | 18 | There are 16-bits of unbuffered 3.3v I/O connected directly to FPGA I/O pins, routed to standard male 100mil header. The header has four ground pins in the corner positions. The 16 I/O signals are labeled at the header. Bits 0-7 are in the top row, bits 8-15 in the bottom, both arranged right-to-left. |
