Changes between Version 7 and Version 8 of HardwareUsersGuides/FPGABoard_v2.2/UserIO/warp_v4_userio


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Timestamp:
Oct 18, 2009, 11:17:00 PM (15 years ago)
Author:
sgupta
Comment:

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  • HardwareUsersGuides/FPGABoard_v2.2/UserIO/warp_v4_userio

    v7 v8  
    66
    77The core has 5 registers that enable the I/O functionality. Register 0 and 1 are the output and input registers for the dedicated I/O, namely the LEDs, the push buttons and the DIP switch.
    8 
    9 [[Image(HardwareUsersGuides/FPGABoard_v2.2/Files:reg0reg1.jpg)]]
    10 
    118
    129== Functions ==
     
    5552}}}
    5653
    57 Once configured for number mode, the number to be written is controlled by the following:
     54Once configured for number mode, the display will show the number written by the following function:
    5855
    5956{{{
     
    6259
    6360where ''number'' is the number desired at the display and ''decimal'' is to toggle the decimal point. If ''decimal'' is 1 then the decimal point in on.
     61
     62In addition, the number written can be read out by:
     63
     64{{{
     65WarpV4_UserIO_ReadNumber_[LeftHex|MiddleHex|RightHex](baseaddress)
     66}}}
     67
     68where the return value is the four bit value corresponding to the last number written. Additionally, as 0x0 corresponds to a number zero being displayed instead of turning the displays off, the following functions toggle the visibility of the numbers:
     69
     70{{{
     71WarpV4_UserIO_[LeftHex|MiddleHex|RightHex]_Off(baseaddress)
     72WarpV4_UserIO_[LeftHex|MiddleHex|RightHex]_On(baseaddress)
     73}}}
     74
     75Toggling the visibility will not alter the values to be shown. Note: these function only works in Number Mode.
     76
     77The second mode for the hex displays is raw mode where each segment in the display can be controlled independently. To enable raw mode the following functions are used:
     78
     79{{{
     80WarpV4_UserIO_RawMode_All(baseaddress)
     81WarpV4_UserIO_RawMode_[LeftHex|MiddleHex|RightHex](baseaddress)
     82}}}
     83
     84[[Image(attachment:HardwareUsersGuides/FPGABoard_v2.2/Files:hex_display.jpg)]]