| | 1 | [[TracNav(HardwareUsersGuides/RadioBoard_v1.4/TOC)]] |
| | 2 | |
| | 3 | == WARP Radio Board Antenna Ports == |
| | 4 | |
| | 5 | [[Image(HardwareUsersGuides/RadioBoard_v1.4/Images:Radio_Board_AntPorts.jpg, 500)]] |
| | 6 | |
| | 7 | The radio board has two antenna ports. Both are fitted with SMA jacks (standard polarity female connectors). The two ports are connected to a DPDT RF switch. The other side of the switch is connected to the transmit and receive paths leading back to the RF transceiver. The antenna switch is controlled by a 2-bit digital signal, driven by the FPGA. The switch has two valid states, illustrated below. |
| | 8 | |
| | 9 | || '''AntSw![1:0] = [1 0]''' || '''AntSw![1:0] = [0 1]''' || |
| | 10 | || [[Image(HardwareUsersGuides/RadioBoard_v1.4/Images:Radio_Board_AntPorts_State0.jpg, 300)]] || [[Image(HardwareUsersGuides/RadioBoard_v1.4/Images:Radio_Board_AntPorts_State1.jpg, 300)]] || |
| | 11 | |
| | 12 | In the default configuration, Port 1 is used for both transmit and receive and Port 2 is unused. This configuration requires the antenna switch's state be changed every thing the radio changes between receive and transmit modes. This behavior is implemented in the radio controller driver and hardware ([source:/PlatformSupport/CustomPeripherals/pcores/radio_controller_v1_08_a/hdl/verilog/user_logic.v@L#L392 user_logic.v] and [source:/PlatformSupport/CustomPeripherals/drivers/radio_controller_v1_08_a/src/radio_controller_basic.c@L#L112 radio_controller_basic.c]). |
