Changes between Initial Version and Version 1 of HardwareUsersGuides/WARPv3/Ethernet


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Timestamp:
Jul 28, 2012, 7:15:07 PM (12 years ago)
Author:
murphpo
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  • HardwareUsersGuides/WARPv3/Ethernet

    v1 v1  
     1[[TracNav(HardwareUsersGuides/WARPv3/TOC)]]
     2= WARP v3 User Guide: Ethernet =
     3
     4The WARP v3 board includes two Ethernet ports, labeled '''ETH A''' and '''ETH B''' on the board.
     5
     6== Ethernet PHY ==
     7Both Ethernet ports are connected a Marvell 88E1121R dual Ethernet PHY. The 88E1121R implements two tri-speed Ethernet PHY cores. Each PHY core has a dedicated MII port, connected to the RJ-45 jack on the board, and RGMII port, connected to the FPGA.
     8
     9Each PHY also has a dedicated MDIO port for exchanging configuration information with the Ethernet MAC. Each MDIO port is connected to dedicated FPGA pins for totally independent operation of the two interfaces. MDIO access requires a 5-bit address, which is different for the two PHYs:
     10 * ETH A MDIO address: 0b00110
     11 * ETH B MDIO address: 0b00111
     12
     13The FPGA pin constraints for the Ethernet interfaces are listed below.
     14
     15{{{
     16#!sh
     17#Common control - shared by PHY ports 0 and 1
     18NET "ETH_PHY_COMA" LOC = "C8" | IOSTANDARD = "LVCMOS25";
     19NET "ETH_PHY_RESETN" LOC = "L9" | IOSTANDARD = "LVCMOS25";
     20
     21#88E1121R PHY 1 = ETH A on WARP v3 Board
     22NET "ETH_A_INT" LOC = "C10" | IOSTANDARD = "LVCMOS25";
     23NET "ETH_A_MDC" LOC = "AP9" | IOSTANDARD = "LVCMOS25";
     24NET "ETH_A_PD" LOC = "K9" | IOSTANDARD = "LVCMOS25";
     25NET "ETH_A_MDIO" LOC = "AK8" | IOSTANDARD = "LVCMOS25";
     26NET "ETH_A_RX_CLK" LOC = "AC10" | IOSTANDARD = "LVCMOS25";
     27NET "ETH_A_RX_CTRL" LOC = "AL9" | IOSTANDARD = "LVCMOS25";
     28NET "ETH_A_RXD<0>" LOC = "AK9" | IOSTANDARD = "LVCMOS25";
     29NET "ETH_A_RXD<1>" LOC = "AJ9" | IOSTANDARD = "LVCMOS25";
     30NET "ETH_A_RXD<2>" LOC = "AH8" | IOSTANDARD = "LVCMOS25";
     31NET "ETH_A_RXD<3>" LOC = "AH9" | IOSTANDARD = "LVCMOS25";
     32NET "ETH_A_TX_CLK" LOC = "AE9" | IOSTANDARD = "LVCMOS25";
     33NET "ETH_A_TX_CTRL" LOC = "AG8" | IOSTANDARD = "LVCMOS25";
     34NET "ETH_A_TXD<0>" LOC = "AF9" | IOSTANDARD = "LVCMOS25";
     35NET "ETH_A_TXD<1>" LOC = "AF10" | IOSTANDARD = "LVCMOS25";
     36NET "ETH_A_TXD<2>" LOC = "AD9" | IOSTANDARD = "LVCMOS25";
     37NET "ETH_A_TXD<3>" LOC = "AD10" | IOSTANDARD = "LVCMOS25";
     38
     39#88E1121R PHY 0 = ETH B on WARP v3 Board
     40NET "ETH_B_INT" LOC = "F9" | IOSTANDARD = "LVCMOS25";
     41NET "ETH_B_MDC" LOC = "AN9" | IOSTANDARD = "LVCMOS25";
     42NET "ETH_B_PD" LOC = "E8" | IOSTANDARD = "LVCMOS25";
     43NET "ETH_B_MDIO" LOC = "AL8" | IOSTANDARD = "LVCMOS25";
     44NET "ETH_B_RX_CLK" LOC = "L10" | IOSTANDARD = "LVCMOS25";
     45NET "ETH_B_RX_CTRL" LOC = "A8" | IOSTANDARD = "LVCMOS25";
     46NET "ETH_B_RXD<0>" LOC = "A9" | IOSTANDARD = "LVCMOS25";
     47NET "ETH_B_RXD<1>" LOC = "D9" | IOSTANDARD = "LVCMOS25";
     48NET "ETH_B_RXD<2>" LOC = "C9" | IOSTANDARD = "LVCMOS25";
     49NET "ETH_B_RXD<3>" LOC = "F10" | IOSTANDARD = "LVCMOS25";
     50NET "ETH_B_TX_CLK" LOC = "AB10" | IOSTANDARD = "LVCMOS25";
     51NET "ETH_B_TX_CTRL" LOC = "D10" | IOSTANDARD = "LVCMOS25";
     52NET "ETH_B_TXD<0>" LOC = "M10" | IOSTANDARD = "LVCMOS25";
     53NET "ETH_B_TXD<1>" LOC = "B8" | IOSTANDARD = "LVCMOS25";
     54NET "ETH_B_TXD<2>" LOC = "AC9" | IOSTANDARD = "LVCMOS25";
     55NET "ETH_B_TXD<3>" LOC = "E9" | IOSTANDARD = "LVCMOS25";
     56}}}
     57
     58== Ethernet MAC ==
     59The Virtex-6 FPGA includes hard TEMAC cores which implement a tri-speed Ethernet MAC compatible with the Marvell PHY on the WARP v3 board. Each PHY requires its own TEMAC. The Virtex-6 TEMAC is fully documented in the [http://www.xilinx.com/support/documentation/user_guides/ug368.pdf Xilinx V6 TEMAC user guide].
     60
     61The sections below detail how to properly constrain the TEMAC instances in your FPGA design. These examples are based on our reference projects built in Xilinx Platform Studio (XPS) and assume the Ethernet interfaces are connected as peripherals in a processor-based design. It is certainly possible to use the TEMAC from custom logic, bypassing any processor. The placement and timing constraints below would be valid in such a design, but the net and instance names would likely change.
     62
     63The constraints below are based on the Xilinx-provided examples for implementing RGMII interfaces with the V6 TEMAC in XPS. See [http://www.xilinx.com/support/answers/32713.htm Xilinx Answer Record 32713] for the original Xilinx reference designs.
     64
     65When using the TEMAC in XPS, you may get warnings like
     66{{{
     67Hardware Evaluation license for component <soft_temac_wrap_v2> found. The generated design will cease to function in the programmed device after operating for some period of time.
     68}}}
     69This is normal. The hardware design will actually use the hard TEMAC and will not cease functioning after a timeout. According to Xilinx the warning is a "[http://www.xilinx.com/support/answers/29828.htm tool limitation]" and can be safely ignored.
     70
     71=== IDELAYCTRL Instances ===
     72The reference RGMII implementation uses IDELAY and ODELAY primitives to improve timing of the RGMII signals. These primitives require an IDELAYCTRL instance in the appropriate location in the FPGA.
     73
     74The Xilinx tools will automatically replicate and instantiate the proper IDELAYCTRL blocks as long as your design includes a single IDELAYCTRL instance whose location is unspecified. See [http://www.xilinx.com/support/answers/39966.htm Xilinx Answer Record 39966] for more details.
     75
     76To use this auto-replication feature, you should configure one TEMAC wrapper to include an IDELAYCTRL but leave its location unconstrained. Then configure the second TEMAC wrapper (and any other cores which utilize I/ODELAYs) to exclude an IDELAYCTRL.
     77
     78=== XPS_LL_TEMAC ===
     79An MHS snippet for instantiating two XPS_LL_TEMAC cores is given below. The xps_ll_temac core requires a LocalLink-equipped core to Tx/Rx packets. You can either use the SDMA port of the MPMC or the xps_ll_fifo core for direct access to packet data from the PLB. Our reference projects use the xps_ll_fifo option.
     80
     81Notice the IDELAYCTRL parameters, configured to instantiate one un-located IDELAYCTRL in the ETH_A wrapper. If you only need ETH A, you can omit the ETH B instance entirely. If you only need ETH B, you should omit ETH A but change {{{C_NUM_IDELAYCTRL}}} to {{{1}}} for ETH B.
     82{{{
     83#!sh
     84
     85#Leave C_IDELAYCTRL_LOC unspecified to auto-place/replicate
     86BEGIN xps_ll_temac
     87 PARAMETER INSTANCE = ETH_A
     88 PARAMETER C_NUM_IDELAYCTRL = 1
     89# PARAMETER C_IDELAYCTRL_LOC =
     90 PARAMETER C_PHY_TYPE = 3
     91 PARAMETER C_TEMAC1_ENABLED = 0
     92 PARAMETER C_BUS2CORE_CLK_RATIO = 1
     93 PARAMETER C_TEMAC_TYPE = 3
     94 PARAMETER C_TEMAC0_PHYADDR = 0b00001
     95 PARAMETER HW_VER = 2.03.a
     96 PARAMETER C_BASEADDR = 0xFFFFFFFF
     97 PARAMETER C_HIGHADDR = 0x00000000
     98 BUS_INTERFACE SPLB = mb_plb
     99 BUS_INTERFACE LLINK0 = ETH_A_llink0
     100 PORT TemacPhy_RST_n = ETH_A_TemacPhy_RST_n_pin
     101 PORT GTX_CLK_0 = clk_125_0000MHz
     102 PORT REFCLK = clk_200_0000MHz
     103 PORT LlinkTemac0_CLK = clk_160_0000MHz
     104 PORT RGMII_TXD_0 = ETH_A_RGMII_TXD_0_pin
     105 PORT RGMII_TX_CTL_0 = ETH_A_RGMII_TX_CTL_0_pin
     106 PORT RGMII_TXC_0 = ETH_A_RGMII_TXC_0_pin
     107 PORT RGMII_RXD_0 = ETH_A_RGMII_RXD_0_pin
     108 PORT RGMII_RX_CTL_0 = ETH_A_RGMII_RX_CTL_0_pin
     109 PORT RGMII_RXC_0 = ETH_A_RGMII_RXC_0_pin
     110 PORT MDC_0 = ETH_A_MDC_0_pin
     111 PORT MDIO_0 = ETH_A_MDIO_0_pin
     112END
     113
     114#Let ETH_A instantiate the unconstrained IDELAYCTRL
     115BEGIN xps_ll_temac
     116 PARAMETER INSTANCE = ETH_B
     117 PARAMETER C_NUM_IDELAYCTRL = 0
     118 PARAMETER C_PHY_TYPE = 3
     119 PARAMETER C_TEMAC1_ENABLED = 0
     120 PARAMETER C_BUS2CORE_CLK_RATIO = 1
     121 PARAMETER C_TEMAC_TYPE = 3
     122 PARAMETER C_TEMAC0_PHYADDR = 0b00001
     123 PARAMETER HW_VER = 2.03.a
     124 PARAMETER C_BASEADDR = 0xFFFFFFFF
     125 PARAMETER C_HIGHADDR = 0x00000000
     126 BUS_INTERFACE SPLB = mb_plb
     127 BUS_INTERFACE LLINK0 = ETH_B_llink0
     128 PORT GTX_CLK_0 = clk_125_0000MHz
     129 PORT REFCLK = clk_200_0000MHz
     130 PORT LlinkTemac0_CLK = clk_160_0000MHz
     131 PORT RGMII_TXD_0 = ETH_B_RGMII_TXD_0_pin
     132 PORT RGMII_TX_CTL_0 = ETH_B_RGMII_TX_CTL_0_pin
     133 PORT RGMII_TXC_0 = ETH_B_RGMII_TXC_0_pin
     134 PORT RGMII_RXD_0 = ETH_B_RGMII_RXD_0_pin
     135 PORT RGMII_RX_CTL_0 = ETH_B_RGMII_RX_CTL_0_pin
     136 PORT RGMII_RXC_0 = ETH_B_RGMII_RXC_0_pin
     137 PORT MDC_0 = ETH_B_MDC_0_pin
     138 PORT MDIO_0 = ETH_B_MDIO_0_pin
     139END
     140}}}
     141
     142=== TEMAC Locations ===
     143The two RGMII interfaces are assigned to FPGA I/O banks which optimize connections to two TEMAC cores. You should explicitly constrain the TEMAC instance locations to the optimal TEMAC for each Ethernet interface. The recommended INST/LOC constraints are listed below. The instance names in your design may be different.
     144{{{
     145#!sh
     146
     147#Assumes TEMAC wrapper instance name includes "ETH_A"
     148INST "*ETH_A*v6_emac" LOC = "TEMAC_X0Y0";
     149
     150#Assumes TEMAC wrapper instance name includes "ETH_B"
     151INST "*ETH_B*v6_emac" LOC = "TEMAC_X0Y1";
     152}}}
     153
     154=== Timing Constraints ===
     155The RGMII interface requires special timing constraints to ensure the IODELAY blocks are configured correctly. The constraints from our reference projects are included below. These are based on the Xilinx reference implementation from [http://www.xilinx.com/support/answers/32713.htm AR32713].
     156
     157There are many "magic" numbers in the constraints below. These have been tweaked to work on the WARP v3 hardware, but may change as we refine the reference projects. In case of differences between the constraints below and those included in a reference project, trust the project's local constraints first.
     158
     159{{{
     160#!sh
     161###### ETH_A
     162###### Hard_Ethernet_MAC
     163# This is a RGMII system
     164# GTX_CLK_0 = 125MHz
     165# LlinkTemac0_CLK = plb_v46 clk = host clock = 100MHz from clock generator
     166# Rx/Tx Client clocks are Rx/Tx PHY clocks so CORE Gen PHY clock constraints propagate to Rx/Tx client clock periods
     167# Time domain crossing constraints (DATAPATHONLY) are set for maximum bus frequency
     168# allowed by IP which is the maximum option in BSB. For lower bus frequency choice in BSB,
     169# the constraints are over constrained. Relaxing them for your system may reduce build time.
     170
     171NET "*ETH_A*/hrst*" TIG;
     172
     173# Locate the Tri-Mode Ethernet MAC instance
     174INST "*ETH_A*v6_emac" LOC = "TEMAC_X0Y0";
     175
     176###############################################################################
     177# CLOCK CONSTRAINTS
     178# The following constraints are required. If you choose to not use the example
     179# design level of wrapper hierarchy, the net names should be translated to
     180# match your design.
     181###############################################################################
     182
     183# Ethernet GTX_CLK high quality 125 MHz reference clock
     184NET "*/GTX_CLK_0" TNM_NET = "ref_gtx_clk";                                                 #name of signal connected to TEMAC GTX_CLK_0 input
     185TIMEGRP "v6_emac_v1_3_clk_ref_gtx" = "ref_gtx_clk";
     186TIMESPEC "TS_v6_emac_v1_3_clk_ref_gtx" = PERIOD "v6_emac_v1_3_clk_ref_gtx" 8 ns HIGH 50 %; #constant value based on constant 125 MHZ GTX clock
     187
     188# Ethernet RGMII PHY-side transmit clock
     189# Changed NET Name - Input to bufg_tx_0
     190#     ___________                                         
     191#    |           |                 |\                     
     192#    | Hard Core |--- tx_clk_0_o --| >---- Tx_Cl_Clk -----
     193#    |___________|                 |/                     
     194#                                 BUFG
     195#
     196NET "*ETH_A*/tx_cl_clk" TNM_NET = "A_phy_clk_tx";
     197TIMEGRP "A_v6_emac_v1_3_clk_phy_tx" = "A_phy_clk_tx";
     198TIMESPEC "TS_A_v6_emac_v1_3_clk_phy_tx" = PERIOD "A_v6_emac_v1_3_clk_phy_tx" 8 ns HIGH 50 %;
     199
     200# Ethernet RGMII PHY-side receive clock
     201# Changed NET Name
     202#  RGMII_RXC_0 is the name of the clock net at the TEMAC Port
     203#     It is the input to the IODELAY
     204#        RxClientClk_0 is the name of the BUFG output clock net
     205#
     206#                     _________      BUFR
     207#                    |         |      |\
     208#  ---RGMII_RXC_0----| IODELAY |------| >----RxClientClk_0------------
     209#                    |_________|      |/
     210#
     211NET "fpga_0_ETH_A_RGMII_RXC_0_pin" TNM_NET = "A_phy_clk_rx";
     212TIMEGRP "A_v6_emac_v1_3_clk_phy_rx" = "A_phy_clk_rx";
     213TIMESPEC "TS_A_v6_emac_v1_3_clk_phy_rx" = PERIOD "A_v6_emac_v1_3_clk_phy_rx" 7.5 ns HIGH 50 %;
     214
     215# IDELAYCTRL 200 MHz reference clock
     216NET "clk_200*MHz*" TNM_NET  = "clk_ref_clk";                                              #name of signal connected to TEMAC REFCLK input   
     217TIMEGRP "ref_clk" = "clk_ref_clk";                                                                                                           
     218TIMESPEC "TS_ref_clk" = PERIOD "ref_clk" 5 ns HIGH 50 %;                                  #constant value based on constant 200 MHZ ref clock
     219
     220# Constrain the DCR interface clock to an example frequency of 100 MHz
     221# Changed NET Name
     222# NET "DCREMACCLK" TNM_NET = "host_clock";
     223#NET "*ETH_A*/SPLB_CLK" TNM_NET = "host_clock";
     224#TIMEGRP "A_clk_host" = "A_host_clock";
     225#TIMESPEC "TS_A_clk_host" = PERIOD "A_clk_host" 10 ns HIGH 50 %;
     226
     227###############################################################################
     228# PHYSICAL INTERFACE CONSTRAINTS
     229# The following constraints are necessary for proper operation, and are tuned
     230# for this example design. They should be modified to suit your design.
     231###############################################################################
     232
     233# RGMII physical interface constraints
     234# -----------------------------------------------------------------------------
     235
     236# Set the IDELAY and ODELAY values, tuned for this example design.
     237# These values should be modified to suit your design.
     238# original assuming equal trace lengths  INST "*rgmii?rgmii_rx_ctl_delay" IDELAY_VALUE = 13;
     239# original assuming equal trace lengths  INST "*rgmii?rgmii_rx_d0_delay"  IDELAY_VALUE = 13;
     240# original assuming equal trace lengths  INST "*rgmii?rgmii_rx_d1_delay"  IDELAY_VALUE = 13;
     241# original assuming equal trace lengths  INST "*rgmii?rgmii_rx_d2_delay"  IDELAY_VALUE = 13;
     242# original assuming equal trace lengths  INST "*rgmii?rgmii_rx_d3_delay"  IDELAY_VALUE = 13;
     243
     244INST "*ETH_A*rgmii?rgmii_rx_ctl_delay" IDELAY_VALUE = 13;
     245INST "*ETH_A*rgmii?rgmii_rx_d0_delay"  IDELAY_VALUE = 13;
     246INST "*ETH_A*rgmii?rgmii_rx_d1_delay"  IDELAY_VALUE = 13;
     247INST "*ETH_A*rgmii?rgmii_rx_d2_delay"  IDELAY_VALUE = 13;
     248INST "*ETH_A*rgmii?rgmii_rx_d3_delay"  IDELAY_VALUE = 13;
     249
     250INST "*ETH_A*rgmii_rxc0_delay"          IDELAY_VALUE = 0;
     251INST "*ETH_A*rgmii_rxc0_delay"          SIGNAL_PATTERN = CLOCK;
     252 
     253INST "*ETH_A*rgmii?rgmii_tx_clk_delay" ODELAY_VALUE = 6;
     254INST "*ETH_A*rgmii?rgmii_tx_clk_delay" SIGNAL_PATTERN = CLOCK;
     255
     256# Group all IODELAY-related blocks to use a single IDELAYCTRL
     257
     258# Change - added TNMs for trace length variations
     259INST "fpga_0_ETH_A_RGMII_RXD_0_pin[0]" TNM = "A_rgmii_rx_d0";
     260INST "fpga_0_ETH_A_RGMII_RXD_0_pin[1]" TNM = "A_rgmii_rx_d1";
     261INST "fpga_0_ETH_A_RGMII_RXD_0_pin[2]" TNM = "A_rgmii_rx_d2";
     262INST "fpga_0_ETH_A_RGMII_RXD_0_pin[3]" TNM = "A_rgmii_rx_d3";
     263INST "fpga_0_ETH_A_RGMII_RX_CTL_0_pin" TNM = "A_rgmii_rx_ctrl";
     264
     265# Spec: 1.2ns setup time, 1.2ns hold time
     266# The internal PHY delays were not used to derive the OFFSET constraints                                                                 
     267# Changed NET Name
     268#  This signal trace is longer than the clock trace, and arrives at the FPGA pin 64 ps after the clock
     269#  Therefore the offset in constraint must have less setup time than nominal
     270TIMEGRP "A_rgmii_rx_d0" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "fpga_0_ETH_A_RGMII_RXC_0_pin" RISING;
     271TIMEGRP "A_rgmii_rx_d0" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "fpga_0_ETH_A_RGMII_RXC_0_pin" FALLING;
     272
     273#  This signal trace is shorter than the clock trace, and arrives at the FPGA pin 376 ps before the clock
     274#  Therefore the offset in constraint must have more setup time than nominal
     275TIMEGRP "A_rgmii_rx_d1" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "fpga_0_ETH_A_RGMII_RXC_0_pin" RISING;
     276TIMEGRP "A_rgmii_rx_d1" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "fpga_0_ETH_A_RGMII_RXC_0_pin" FALLING;
     277
     278#  This signal trace is shorter than the clock trace, and arrives at the FPGA pin 372 ps before the clock
     279#  Therefore the offset in constraint must have more setup time than nominal
     280TIMEGRP "A_rgmii_rx_d2" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "fpga_0_ETH_A_RGMII_RXC_0_pin" RISING;
     281TIMEGRP "A_rgmii_rx_d2" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "fpga_0_ETH_A_RGMII_RXC_0_pin" FALLING;
     282
     283#  This signal trace is shorter than the clock trace, and arrives at the FPGA pin 115 ps before the clock
     284#  Therefore the offset in constraint must have more setup time than nominal
     285TIMEGRP "A_rgmii_rx_d3" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "fpga_0_ETH_A_RGMII_RXC_0_pin" RISING;
     286TIMEGRP "A_rgmii_rx_d3" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "fpga_0_ETH_A_RGMII_RXC_0_pin" FALLING;
     287
     288#  This signal trace is shorter than the clock trace, and arrives at the FPGA pin 292 ps before the clock
     289#  Therefore the offset in constraint must have more setup time than nominal
     290TIMEGRP "A_rgmii_rx_ctrl" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "fpga_0_ETH_A_RGMII_RXC_0_pin" RISING;
     291TIMEGRP "A_rgmii_rx_ctrl" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "fpga_0_ETH_A_RGMII_RXC_0_pin" FALLING;
     292
     293
     294NET "*ETH_A*/LlinkTemac0_CLK" TNM_NET = "A_LLCLK0"; #name of signal connected to TEMAC LlinkTemac0_CLK input
     295NET "*ETH_A*/SPLB_Clk" TNM_NET = "A_PLBCLK"; #name of signal connected to TEMAC SPLB_Clk input
     296NET "*ETH_A*/REFCLK" TNM_NET = "A_REFCLK"; #name of signal connected to TEMAC REFCLK input
     297
     298TIMESPEC "TS_A_LL_CLK0_2_RX_CLIENT_CLK0"  = FROM A_LLCLK0 TO A_phy_clk_rx 8000 ps DATAPATHONLY; #constant value based on Ethernet clock                 
     299TIMESPEC "TS_A_LL_CLK0_2_TX_CLIENT_CLK0"  = FROM A_LLCLK0 TO A_phy_clk_tx 8000 ps DATAPATHONLY; #constant value based on Ethernet clock             
     300TIMESPEC "TS_A_RX_CLIENT_CLK0_2_LL_CLK0"  = FROM A_phy_clk_rx TO A_LLCLK0 8000 ps DATAPATHONLY; #varies based on period of LocalLink clock           
     301TIMESPEC "TS_A_TX_CLIENT_CLK0_2_LL_CLK0"  = FROM A_phy_clk_tx TO A_LLCLK0 8000 ps DATAPATHONLY; #varies based on period of LocalLink clock           
     302
     303TIMESPEC "TS_A_REF_CLK_2_PLB_CLIENT_CLK"  = FROM A_REFCLK TO A_PLBCLK 8000 ps DATAPATHONLY; #varies based on period of PLB clock                       
     304TIMESPEC "TS_A_PLB_CLIENT_CLK_2_REF_CLK"  = FROM A_PLBCLK TO A_REFCLK 5000 ps DATAPATHONLY; #constant value based on constant 200 MHZ ref clock         
     305
     306TIMESPEC "TS_A_REF_CLK_2_TX_CLIENT_CLK0"  = FROM A_REFCLK TO A_phy_clk_tx 8000 ps DATAPATHONLY; #constant value based on Ethernet clock                       
     307TIMESPEC "TS_A_TX_CLIENT_CLK0_2_REF_CLK"  = FROM A_phy_clk_tx TO A_REFCLK 5000 ps DATAPATHONLY; #constant value based on constant 200 MHZ ref clock           
     308
     309TIMESPEC "TS_A_REF_CLK_2_RX_CLIENT_CLK0"  = FROM A_REFCLK TO A_phy_clk_rx 8000 ps DATAPATHONLY; #constant value based on Ethernet clock               
     310TIMESPEC "TS_A_RX_CLIENT_CLK0_2_REF_CLK"  = FROM A_phy_clk_rx TO A_REFCLK 5000 ps DATAPATHONLY; #constant value based on constant 200 MHZ ref clock   
     311
     312
     313
     314###### ETH_B
     315###### Hard_Ethernet_MAC
     316# This is a RGMII system
     317# GTX_CLK_0 = 125MHz
     318# LlinkTemac0_CLK = plb_v46 clk = host clock = 100MHz from clock generator
     319# Rx/Tx Client clocks are Rx/Tx PHY clocks so CORE Gen PHY clock constraints propagate to Rx/Tx client clock periods
     320# Time domain crossing constraints (DATAPATHONLY) are set for maximum bus frequency
     321# allowed by IP which is the maximum option in BSB. For lower bus frequency choice in BSB,
     322# the constraints are over constrained. Relaxing them for your system may reduce build time.
     323
     324NET "*ETH_B*/hrst*" TIG;
     325
     326# Locate the Tri-Mode Ethernet MAC instance
     327INST "*ETH_B*v6_emac" LOC = "TEMAC_X0Y1";
     328
     329###############################################################################
     330# CLOCK CONSTRAINTS
     331# The following constraints are required. If you choose to not use the example
     332# design level of wrapper hierarchy, the net names should be translated to
     333# match your design.
     334###############################################################################
     335
     336# Ethernet RGMII PHY-side transmit clock
     337# Changed NET Name - Input to bufg_tx_0
     338#     ___________                                         
     339#    |           |                 |\                     
     340#    | Hard Core |--- tx_clk_0_o --| >---- Tx_Cl_Clk -----
     341#    |___________|                 |/                     
     342#                                 BUFG
     343#
     344NET "*ETH_B*/tx_cl_clk" TNM_NET = "B_phy_clk_tx";
     345TIMEGRP "B_v6_emac_v1_3_clk_phy_tx" = "B_phy_clk_tx";
     346TIMESPEC "TS_B_v6_emac_v1_3_clk_phy_tx" = PERIOD "B_v6_emac_v1_3_clk_phy_tx" 8 ns HIGH 50 %;
     347
     348# Ethernet RGMII PHY-side receive clock
     349# Changed NET Name
     350#  RGMII_RXC_0 is the name of the clock net at the TEMAC Port
     351#     It is the input to the IODELAY
     352#        RxClientClk_0 is the name of the BUFG output clock net
     353#
     354#                     _________      BUFR
     355#                    |         |      |\
     356#  ---RGMII_RXC_0----| IODELAY |------| >----RxClientClk_0------------
     357#                    |_________|      |/
     358#
     359NET "fpga_0_ETH_B_RGMII_RXC_0_pin" TNM_NET = "B_phy_clk_rx";
     360TIMEGRP "B_v6_emac_v1_3_clk_phy_rx" = "B_phy_clk_rx";
     361TIMESPEC "TS_B_v6_emac_v1_3_clk_phy_rx" = PERIOD "B_v6_emac_v1_3_clk_phy_rx" 7.5 ns HIGH 50 %;
     362
     363# Constrain the DCR interface clock to an example frequency of 100 MHz
     364# Changed NET Name
     365# NET "DCREMACCLK" TNM_NET = "host_clock";
     366NET "*ETH_B*/SPLB_CLK" TNM_NET = "host_clock";
     367TIMEGRP "B_clk_host" = "B_host_clock";
     368TIMESPEC "TS_B_clk_host" = PERIOD "B_clk_host" 10 ns HIGH 50 %;
     369
     370###############################################################################
     371# PHYSICAL INTERFACE CONSTRAINTS
     372# The following constraints are necessary for proper operation, and are tuned
     373# for this example design. They should be modified to suit your design.
     374###############################################################################
     375
     376# RGMII physical interface constraints
     377# -----------------------------------------------------------------------------
     378
     379# Set the IDELAY and ODELAY values, tuned for this example design.
     380# These values should be modified to suit your design.
     381# original assuming equal trace lengths  INST "*rgmii?rgmii_rx_ctl_delay" IDELAY_VALUE = 13;
     382# original assuming equal trace lengths  INST "*rgmii?rgmii_rx_d0_delay"  IDELAY_VALUE = 13;
     383# original assuming equal trace lengths  INST "*rgmii?rgmii_rx_d1_delay"  IDELAY_VALUE = 13;
     384# original assuming equal trace lengths  INST "*rgmii?rgmii_rx_d2_delay"  IDELAY_VALUE = 13;
     385# original assuming equal trace lengths  INST "*rgmii?rgmii_rx_d3_delay"  IDELAY_VALUE = 13;
     386
     387INST "*ETH_B*rgmii?rgmii_rx_ctl_delay" IDELAY_VALUE = 13;
     388INST "*ETH_B*rgmii?rgmii_rx_d0_delay"  IDELAY_VALUE = 13;
     389INST "*ETH_B*rgmii?rgmii_rx_d1_delay"  IDELAY_VALUE = 13;
     390INST "*ETH_B*rgmii?rgmii_rx_d2_delay"  IDELAY_VALUE = 13;
     391INST "*ETH_B*rgmii?rgmii_rx_d3_delay"  IDELAY_VALUE = 13;
     392
     393INST "*ETH_B*rgmii_rxc0_delay"          IDELAY_VALUE = 0;
     394INST "*ETH_B*rgmii_rxc0_delay"          SIGNAL_PATTERN = CLOCK;
     395 
     396INST "*ETH_B*rgmii?rgmii_tx_clk_delay" ODELAY_VALUE = 6;
     397INST "*ETH_B*rgmii?rgmii_tx_clk_delay" SIGNAL_PATTERN = CLOCK;
     398
     399# Group all IODELAY-related blocks to use a single IDELAYCTRL
     400
     401# Change - added TNMs for trace length variations
     402INST "fpga_0_ETH_B_RGMII_RXD_0_pin[0]" TNM = "B_rgmii_rx_d0";
     403INST "fpga_0_ETH_B_RGMII_RXD_0_pin[1]" TNM = "B_rgmii_rx_d1";
     404INST "fpga_0_ETH_B_RGMII_RXD_0_pin[2]" TNM = "B_rgmii_rx_d2";
     405INST "fpga_0_ETH_B_RGMII_RXD_0_pin[3]" TNM = "B_rgmii_rx_d3";
     406INST "fpga_0_ETH_B_RGMII_RX_CTL_0_pin" TNM = "B_rgmii_rx_ctrl";
     407
     408# Spec: 1.2ns setup time, 1.2ns hold time
     409# The internal PHY delays were not used to derive the OFFSET constraints                                                                 
     410# Changed NET Name
     411#  This signal trace is longer than the clock trace, and arrives at the FPGA pin 64 ps after the clock
     412#  Therefore the offset in constraint must have less setup time than nominal
     413TIMEGRP "B_rgmii_rx_d0" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "fpga_0_ETH_B_RGMII_RXC_0_pin" RISING;
     414TIMEGRP "B_rgmii_rx_d0" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "fpga_0_ETH_B_RGMII_RXC_0_pin" FALLING;
     415
     416#  This signal trace is shorter than the clock trace, and arrives at the FPGA pin 376 ps before the clock
     417#  Therefore the offset in constraint must have more setup time than nominal
     418TIMEGRP "B_rgmii_rx_d1" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "fpga_0_ETH_B_RGMII_RXC_0_pin" RISING;
     419TIMEGRP "B_rgmii_rx_d1" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "fpga_0_ETH_B_RGMII_RXC_0_pin" FALLING;
     420
     421#  This signal trace is shorter than the clock trace, and arrives at the FPGA pin 372 ps before the clock
     422#  Therefore the offset in constraint must have more setup time than nominal
     423TIMEGRP "B_rgmii_rx_d2" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "fpga_0_ETH_B_RGMII_RXC_0_pin" RISING;
     424TIMEGRP "B_rgmii_rx_d2" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "fpga_0_ETH_B_RGMII_RXC_0_pin" FALLING;
     425
     426#  This signal trace is shorter than the clock trace, and arrives at the FPGA pin 115 ps before the clock
     427#  Therefore the offset in constraint must have more setup time than nominal
     428TIMEGRP "B_rgmii_rx_d3" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "fpga_0_ETH_B_RGMII_RXC_0_pin" RISING;
     429TIMEGRP "B_rgmii_rx_d3" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "fpga_0_ETH_B_RGMII_RXC_0_pin" FALLING;
     430
     431#  This signal trace is shorter than the clock trace, and arrives at the FPGA pin 292 ps before the clock
     432#  Therefore the offset in constraint must have more setup time than nominal
     433TIMEGRP "B_rgmii_rx_ctrl" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "fpga_0_ETH_B_RGMII_RXC_0_pin" RISING;
     434TIMEGRP "B_rgmii_rx_ctrl" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "fpga_0_ETH_B_RGMII_RXC_0_pin" FALLING;
     435
     436
     437NET "*ETH_B*/LlinkTemac0_CLK" TNM_NET = "B_LLCLK0"; #name of signal connected to TEMAC LlinkTemac0_CLK input
     438NET "*ETH_B*/SPLB_Clk" TNM_NET = "B_PLBCLK"; #name of signal connected to TEMAC SPLB_Clk input
     439
     440TIMESPEC "TS_B_LL_CLK0_2_RX_CLIENT_CLK0"  = FROM B_LLCLK0 TO B_phy_clk_rx 8000 ps DATAPATHONLY; #constant value based on Ethernet clock                 
     441TIMESPEC "TS_B_LL_CLK0_2_TX_CLIENT_CLK0"  = FROM B_LLCLK0 TO B_phy_clk_tx 8000 ps DATAPATHONLY; #constant value based on Ethernet clock             
     442TIMESPEC "TS_B_RX_CLIENT_CLK0_2_LL_CLK0"  = FROM B_phy_clk_rx TO B_LLCLK0 8000 ps DATAPATHONLY; #varies based on period of LocalLink clock           
     443TIMESPEC "TS_B_TX_CLIENT_CLK0_2_LL_CLK0"  = FROM B_phy_clk_tx TO B_LLCLK0 8000 ps DATAPATHONLY; #varies based on period of LocalLink clock
     444}}}