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Ethernet

-                      v2
+                      v3
 Both Ethernet ports are connected a Marvell 88E1121R dual Ethernet PHY. The 88E1121R implements two tri-speed Ethernet PHY cores. Each PHY core has a dedicated MII port, connected to the RJ-45 jack on the board, and RGMII port, connected to the FPGA.
+Each PHY also has a dedicated MDIO port for exchanging configuration information with the Ethernet MAC. Each MDIO port is connected to dedicated FPGA pins for totally independent operation of the two interfaces. MDIO access requires a 5-bit address, which is different for the two PHYs:
+Each PHY also has a dedicated MDIO port for exchanging configuration information with the Ethernet MAC. Each MDIO port is connected to dedicated FPGA pins for totally independent operation of the two interfaces. MDIO access requires a 5-bit address. It is important to use the correct PHY address when accessing registers via MDIO. You should not use address 0, the MDIO broadcast address, to avoid conflicts with Ethernet circuits inside the FPGA that may respond to broadcast MDIO transactions.
+The hard-coded PHY addresses on WARP v3 are:
  * ETH A MDIO address: 0b00110 (0x6)
  * ETH B MDIO address: 0b00111 (0x7)