Changes between Initial Version and Version 1 of HardwareUsersGuides/WARPv3/Memory


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Timestamp:
Jul 28, 2012, 7:14:48 PM (12 years ago)
Author:
murphpo
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  • HardwareUsersGuides/WARPv3/Memory

    v1 v1  
     1[[TracNav(HardwareUsersGuides/WARPv3/TOC)]]
     2== WARP v3 User Guide: Memory ==
     3The WARP v3 board includes a DDR3 SO-DIMM slot routed to dedicated pins on the FPGA. When combined with a DDR3 memory controller core in the FPGA, the SO-DIMM is available to user designs. The SO-DIMM interface on WARP v3 is designed to support modules up to 8GB in size and run at up to 400MHz. Faster speeds may be possible but are not recommended.
     4
     5Every WARP v3 kit ships with a pre-tested 2GB SO-DIMM rated for at least 400MHz operation. If you want to use another SO-DIMM, we recommend using modules from major manufacturers, acquired through authorized (and reputable) channels. All too often cheap modules can be out-of-spec (or outright counterfeits), and debugging flaky RAM in hardware is hard.
     6
     7== Memory Controllers ==
     8Designing a DDR3 memory controller is challenging. Thankfully Xilinx provides the MIG (memory interface generator), which can generate FPGA implementations of known-good DDR3 controllers. MIG can be run from Coregen if you need a memory controller for a custom logic design. You can use the constraints below when running the MIG wizard to generate a controller for use on WARP v3.
     9
     10=== XPS MPMC ===
     11For embedded designs, XPS provides the MPMC, which wraps a MIG-generated DDR3 controller. The MPMC only supports 32-bit DDR3 memories on Virtex-6 devices. The MHS snipped below shows how to configure the MPMC in XPS 13.4 for use with the 2GB SO-DIMM on WARP v3.
     12
     13{{{
     14#!sh
     15BEGIN mpmc
     16 PARAMETER INSTANCE = DDR3_2GB_SODIMM
     17 PARAMETER C_NUM_PORTS = 1
     18 PARAMETER C_MEM_TYPE = DDR3
     19 PARAMETER C_MEM_PARTNO = MT8JSF25664HZ-1G4
     20 PARAMETER C_MEM_ODT_TYPE = 1
     21 PARAMETER C_MEM_REG_DIMM = 0
     22 PARAMETER C_MEM_CLK_WIDTH = 1
     23 PARAMETER C_MEM_ODT_WIDTH = 1
     24 PARAMETER C_MEM_CE_WIDTH = 1
     25 PARAMETER C_MEM_CS_N_WIDTH = 1
     26 PARAMETER C_MEM_DATA_WIDTH = 32
     27 PARAMETER C_MEM_NDQS_COL0 = 4
     28 PARAMETER C_MEM_DQS_LOC_COL0 = 0x000000000000000000000000000003020100
     29 PARAMETER C_PIM0_BASETYPE = 2
     30 PARAMETER HW_VER = 6.05.a
     31 PARAMETER C_FAMILY = virtex6
     32 PARAMETER C_MPMC_BASEADDR = 0x40000000
     33 PARAMETER C_MPMC_HIGHADDR = 0x7fffffff
     34 BUS_INTERFACE SPLB0 = mb_plb
     35 PORT MPMC_Clk0 = clk_150_0000MHzMMCM0
     36 PORT MPMC_Clk_200MHz = clk_200_0000MHz
     37 PORT MPMC_Rst = sys_periph_reset
     38 PORT MPMC_Clk_Mem = clk_300_0000MHzMMCM0
     39 PORT MPMC_Clk_Rd_Base = clk_300_0000MHzMMCM0_nobuf_varphase
     40 PORT MPMC_DCM_PSEN = MPMC_DCM_PSEN
     41 PORT MPMC_DCM_PSINCDEC = MPMC_DCM_PSINCDEC
     42 PORT MPMC_DCM_PSDONE = MPMC_DCM_PSDONE
     43 PORT DDR3_Clk = fpga_0_DDR3_2GB_SODIMM_DDR3_Clk_pin
     44 PORT DDR3_Clk_n = fpga_0_DDR3_2GB_SODIMM_DDR3_Clk_n_pin
     45 PORT DDR3_CE = fpga_0_DDR3_2GB_SODIMM_DDR3_CE_pin
     46 PORT DDR3_CS_n = fpga_0_DDR3_2GB_SODIMM_DDR3_CS_n_pin
     47 PORT DDR3_ODT = fpga_0_DDR3_2GB_SODIMM_DDR3_ODT_pin
     48 PORT DDR3_RAS_n = fpga_0_DDR3_2GB_SODIMM_DDR3_RAS_n_pin
     49 PORT DDR3_CAS_n = fpga_0_DDR3_2GB_SODIMM_DDR3_CAS_n_pin
     50 PORT DDR3_WE_n = fpga_0_DDR3_2GB_SODIMM_DDR3_WE_n_pin
     51 PORT DDR3_BankAddr = fpga_0_DDR3_2GB_SODIMM_DDR3_BankAddr_pin
     52 PORT DDR3_Addr = fpga_0_DDR3_2GB_SODIMM_DDR3_Addr_pin
     53 PORT DDR3_DQ = fpga_0_DDR3_2GB_SODIMM_DDR3_DQ_pin
     54 PORT DDR3_DM = fpga_0_DDR3_2GB_SODIMM_DDR3_DM_pin
     55 PORT DDR3_Reset_n = fpga_0_DDR3_2GB_SODIMM_DDR3_Reset_n_pin
     56 PORT DDR3_DQS = fpga_0_DDR3_2GB_SODIMM_DDR3_DQS_pin
     57 PORT DDR3_DQS_n = fpga_0_DDR3_2GB_SODIMM_DDR3_DQS_n_pin
     58END
     59}}}
     60
     61The UCF entries for timing and logic placement for this parameterization of the MPMC are listed below. The pin location constraints given in the next section are also required. All of these are tailored for the WARP v3 board with a 2GB SO-DIMM clocked at <400MHz.
     62
     63{{{
     64#!sh
     65# Includes placement constraints for upper 32 bits of the 64-bit RAM,
     66#  just in case Xilinx gets around to implementing a 64-bit DDR3 MPMC for V6
     67
     68# These constraints are derived from the template generated by the MIG
     69#  The comments below are all generated by the MIG and are included here for reference
     70
     71
     72# Constrain BUFR clocks used to synchronize data from IOB to fabric logic
     73# Note that ISE cannot infer this from other PERIOD constraints because
     74# of the use of OSERDES blocks in the BUFR clock generation path
     75NET "*/mpmc_core_0/gen_v6_ddr3_phy.mpmc_phy_if_0/clk_rsync[?]" TNM_NET = TNM_clk_rsync;
     76TIMESPEC "TS_clk_rsync" = PERIOD "TNM_clk_rsync" 5000 ps;       # This is over-constraint for 200MHz, user can relax it to match mpmc_clk0
     77 
     78# Paths between DQ/DQS ISERDES.Q outputs and CLB flops clocked by falling
     79# edge of BUFR will by design only be used if DYNCLKDIVSEL is asserted for
     80# that particular flop. Mark this path as being a full-cycle, rather than
     81# a half cycle path for timing purposes. NOTE: This constraint forces full-
     82# cycle timing to be applied globally for all rising->falling edge paths
     83# in all resynchronizaton clock domains. If the user had modified the logic
     84# in the resync clock domain such that other rising->falling edge paths
     85# exist, then constraint below should be modified to utilize pattern
     86# matching to specific affect only the DQ/DQS ISERDES.Q outputs
     87TIMEGRP "TG_clk_rsync_rise" = RISING  "TNM_clk_rsync";
     88TIMEGRP "TG_clk_rsync_fall" = FALLING "TNM_clk_rsync";
     89TIMESPEC "TS_clk_rsync_rise_to_fall" =    FROM "TG_clk_rsync_rise" TO "TG_clk_rsync_fall" 5000 ps;    # This is over-constraint for 200MHz, user can relax it to match mpmc_clk0
     90 
     91# Signal to select between controller and physical layer signals. Four divided by two clock
     92# cycles (4 memory clock cycles) are provided by design for the signal to settle down.
     93# Used only by the phy modules.
     94INST "*/mpmc_core_0/gen_v6_ddr3_phy.mpmc_phy_if_0/u_phy_init/u_ff_phy_init_data_sel" TNM = "TNM_PHY_INIT_SEL";
     95TIMESPEC "TS_MC_PHY_INIT_SEL" = FROM "TNM_PHY_INIT_SEL" TO FFS = 10000 ps;                         # This is over-constraint, user can relax it to match 4 memory clock cycles
     96
     97#Internal Vref
     98CONFIG INTERNAL_VREF_BANK22=0.75;
     99CONFIG INTERNAL_VREF_BANK23=0.75;
     100CONFIG INTERNAL_VREF_BANK33=0.75;
     101
     102#DCI Cascading
     103CONFIG DCI_CASCADE = "23 22";
     104
     105#BUFR IOBs (must be unconnected in FPGA and PCB)
     106CONFIG PROHIBIT = AH17,AP20;
     107
     108#BUFIO IOBs (must be unconnected in FPGA and PCB)
     109CONFIG PROHIBIT = AC13,AD12,AF19,AF20,AH23,AK27,AN27,AP11;
     110
     111######################################################################################
     112##Place RSYNC OSERDES and IODELAY:                                                  ##
     113######################################################################################
     114
     115#MPMC as of EDK 13.4 only supports 32-bit memories
     116##Site: AH17 -- Bank 32
     117#INST "*/u_phy_read/u_phy_rdclk_gen/gen_loop_col1.u_oserdes_rsync" LOC = "OLOGIC_X2Y23";
     118#INST "*/u_phy_read/u_phy_rdclk_gen/gen_loop_col1.u_odelay_rsync" LOC = "IODELAY_X2Y23";
     119#INST "*/u_phy_read/u_phy_rdclk_gen/gen_loop_col1.u_bufr_rsync" LOC = "BUFR_X2Y1";
     120
     121##Site: AP20 -- Bank 22
     122INST "*/u_phy_read/u_phy_rdclk_gen/gen_loop_col0.u_oserdes_rsync" LOC = "OLOGIC_X1Y21";
     123INST "*/u_phy_read/u_phy_rdclk_gen/gen_loop_col0.u_odelay_rsync" LOC = "IODELAY_X1Y21";
     124INST "*/u_phy_read/u_phy_rdclk_gen/gen_loop_col0.u_bufr_rsync" LOC = "BUFR_X1Y1";
     125
     126
     127######################################################################################
     128##Place CPT OSERDES and IODELAY:                                                    ##
     129######################################################################################
     130
     131##Site: AH23 -- Bank 23
     132INST "*/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[0].u_oserdes_cpt" LOC = "OLOGIC_X1Y57";
     133INST "*/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[0].u_odelay_cpt" LOC = "IODELAY_X1Y57";
     134
     135##Site: AK27 -- Bank 23
     136INST "*/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[1].u_oserdes_cpt" LOC = "OLOGIC_X1Y59";
     137INST "*/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[1].u_odelay_cpt" LOC = "IODELAY_X1Y59";
     138
     139##Site: AN27 -- Bank 23
     140INST "*/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[2].u_oserdes_cpt" LOC = "OLOGIC_X1Y61";
     141INST "*/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[2].u_odelay_cpt" LOC = "IODELAY_X1Y61";
     142
     143##Site: AF19 -- Bank 22
     144INST "*/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[3].u_oserdes_cpt" LOC = "OLOGIC_X1Y23";
     145INST "*/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[3].u_odelay_cpt" LOC = "IODELAY_X1Y23";
     146
     147#MPMC as of EDK 13.4 only supports 32-bit memories
     148##Site: AF20 -- Bank 22
     149#INST "*/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[4].u_oserdes_cpt" LOC = "OLOGIC_X1Y17";
     150#INST "*/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[4].u_odelay_cpt" LOC = "IODELAY_X1Y17";
     151
     152##Site: AP11 -- Bank 33
     153#INST "*/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[5].u_oserdes_cpt" LOC = "OLOGIC_X2Y57";
     154#INST "*/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[5].u_odelay_cpt" LOC = "IODELAY_X2Y57";
     155
     156##Site: AC13 -- Bank 33
     157#INST "*/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[6].u_oserdes_cpt" LOC = "OLOGIC_X2Y61";
     158#INST "*/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[6].u_odelay_cpt" LOC = "IODELAY_X2Y61";
     159
     160##Site: AD12 -- Bank 33
     161#INST "*/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[7].u_oserdes_cpt" LOC = "OLOGIC_X2Y59";
     162#INST "*/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[7].u_odelay_cpt" LOC = "IODELAY_X2Y59";
     163}}}
     164
     165=== FPGA Pinout ===
     166
     167The FPGA pin assignments for the DDR3 SO-DIMM connector are listed in the UCF snippet below. The pins listed as {{{PROHIBIT}}} are unconnected on the WARP v3 board. The MIG DDR3 controller uses clocking logic in these IOBs, precluding use of the actual IO on the board.
     168{{{
     169#!sh
     170
     171###DDR3 SO-DIMM
     172
     173#Clocks
     174NET "SODIMM_CK_N<0>" LOC = "AD15" | IOSTANDARD = "IOSTD";
     175NET "SODIMM_CK_P<0>" LOC = "AC15" | IOSTANDARD = "IOSTD";
     176NET "SODIMM_CK_N<1>" LOC = "AM15" | IOSTANDARD = "IOSTD";
     177NET "SODIMM_CK_P<1>" LOC = "AN15" | IOSTANDARD = "IOSTD";
     178
     179#Address/Control
     180NET "SODIMM_ADDR<0>" LOC = "AM17" | IOSTANDARD = "IOSTD";
     181NET "SODIMM_ADDR<1>" LOC = "AF16" | IOSTANDARD = "IOSTD";
     182NET "SODIMM_ADDR<2>" LOC = "AN17" | IOSTANDARD = "IOSTD";
     183NET "SODIMM_ADDR<3>" LOC = "AG17" | IOSTANDARD = "IOSTD";
     184NET "SODIMM_ADDR<4>" LOC = "AK16" | IOSTANDARD = "IOSTD";
     185NET "SODIMM_ADDR<5>" LOC = "AG16" | IOSTANDARD = "IOSTD";
     186NET "SODIMM_ADDR<6>" LOC = "AK17" | IOSTANDARD = "IOSTD";
     187NET "SODIMM_ADDR<7>" LOC = "AG18" | IOSTANDARD = "IOSTD";
     188NET "SODIMM_ADDR<8>" LOC = "AE16" | IOSTANDARD = "IOSTD";
     189NET "SODIMM_ADDR<9>" LOC = "AD16" | IOSTANDARD = "IOSTD";
     190NET "SODIMM_ADDR<10>" LOC = "AH15" | IOSTANDARD = "IOSTD";
     191NET "SODIMM_ADDR<11>" LOC = "AH18" | IOSTANDARD = "IOSTD";
     192NET "SODIMM_ADDR<12>" LOC = "AE17" | IOSTANDARD = "IOSTD";
     193NET "SODIMM_ADDR<13>" LOC = "AJ16" | IOSTANDARD = "IOSTD";
     194NET "SODIMM_ADDR<14>" LOC = "AK18" | IOSTANDARD = "IOSTD";
     195NET "SODIMM_ADDR<15>" LOC = "AH19" | IOSTANDARD = "IOSTD";
     196
     197NET "SODIMM_BA<0>" LOC = "AG15" | IOSTANDARD = "IOSTD";
     198NET "SODIMM_BA<1>" LOC = "AP16" | IOSTANDARD = "IOSTD";
     199NET "SODIMM_BA<2>" LOC = "AD17" | IOSTANDARD = "IOSTD";
     200NET "SODIMM_CAS_N" LOC = "AJ17" | IOSTANDARD = "IOSTD";
     201NET "SODIMM_CKE<0>" LOC = "AF18" | IOSTANDARD = "IOSTD";
     202NET "SODIMM_CKE<1>" LOC = "AJ19" | IOSTANDARD = "IOSTD";
     203NET "SODIMM_CS_N<0>" LOC = "AL16" | IOSTANDARD = "IOSTD";
     204NET "SODIMM_CS_N<1>" LOC = "AJ15" | IOSTANDARD = "IOSTD";
     205NET "SODIMM_EVENT" LOC = "AL14" | IOSTANDARD = "IOSTD";
     206NET "SODIMM_ODT<0>" LOC = "AP15" | IOSTANDARD = "IOSTD";
     207NET "SODIMM_ODT<1>" LOC = "AL15" | IOSTANDARD = "IOSTD";
     208NET "SODIMM_RAS_N" LOC = "AM16" | IOSTANDARD = "IOSTD";
     209NET "SODIMM_RESET_N" LOC = "AP17" | IOSTANDARD = "IOSTD";
     210NET "SODIMM_WE_N" LOC = "AF15" | IOSTANDARD = "IOSTD";
     211
     212#Data Masks
     213NET "SODIMM_DM<0>" LOC = "AM30" | IOSTANDARD = "IOSTD";
     214NET "SODIMM_DM<1>" LOC = "AL26" | IOSTANDARD = "IOSTD";
     215NET "SODIMM_DM<2>" LOC = "AP26" | IOSTANDARD = "IOSTD";
     216NET "SODIMM_DM<3>" LOC = "AJ22" | IOSTANDARD = "IOSTD";
     217NET "SODIMM_DM<4>" LOC = "AN20" | IOSTANDARD = "IOSTD";
     218NET "SODIMM_DM<5>" LOC = "AH14" | IOSTANDARD = "IOSTD";
     219NET "SODIMM_DM<6>" LOC = "AM10" | IOSTANDARD = "IOSTD";
     220NET "SODIMM_DM<7>" LOC = "AG11" | IOSTANDARD = "IOSTD";
     221
     222#DQ
     223NET "SODIMM_DQ<0>" LOC = "AK29" | IOSTANDARD = "IOSTD";
     224NET "SODIMM_DQ<1>" LOC = "AN30" | IOSTANDARD = "IOSTD";
     225NET "SODIMM_DQ<2>" LOC = "AL29" | IOSTANDARD = "IOSTD";
     226NET "SODIMM_DQ<3>" LOC = "AN29" | IOSTANDARD = "IOSTD";
     227NET "SODIMM_DQ<4>" LOC = "AP31" | IOSTANDARD = "IOSTD";
     228NET "SODIMM_DQ<5>" LOC = "AP30" | IOSTANDARD = "IOSTD";
     229NET "SODIMM_DQ<6>" LOC = "AH28" | IOSTANDARD = "IOSTD";
     230NET "SODIMM_DQ<7>" LOC = "AH27" | IOSTANDARD = "IOSTD";
     231NET "SODIMM_DQ<8>" LOC = "AK28" | IOSTANDARD = "IOSTD";
     232NET "SODIMM_DQ<9>" LOC = "AL28" | IOSTANDARD = "IOSTD";
     233NET "SODIMM_DQ<10>" LOC = "AJ27" | IOSTANDARD = "IOSTD";
     234NET "SODIMM_DQ<11>" LOC = "AH25" | IOSTANDARD = "IOSTD";
     235NET "SODIMM_DQ<12>" LOC = "AP29" | IOSTANDARD = "IOSTD";
     236NET "SODIMM_DQ<13>" LOC = "AM27" | IOSTANDARD = "IOSTD";
     237NET "SODIMM_DQ<14>" LOC = "AJ25" | IOSTANDARD = "IOSTD";
     238NET "SODIMM_DQ<15>" LOC = "AH24" | IOSTANDARD = "IOSTD";
     239NET "SODIMM_DQ<16>" LOC = "AJ24" | IOSTANDARD = "IOSTD";
     240NET "SODIMM_DQ<17>" LOC = "AK24" | IOSTANDARD = "IOSTD";
     241NET "SODIMM_DQ<18>" LOC = "AL24" | IOSTANDARD = "IOSTD";
     242NET "SODIMM_DQ<19>" LOC = "AK23" | IOSTANDARD = "IOSTD";
     243NET "SODIMM_DQ<20>" LOC = "AP27" | IOSTANDARD = "IOSTD";
     244NET "SODIMM_DQ<21>" LOC = "AM26" | IOSTANDARD = "IOSTD";
     245NET "SODIMM_DQ<22>" LOC = "AN25" | IOSTANDARD = "IOSTD";
     246NET "SODIMM_DQ<23>" LOC = "AN24" | IOSTANDARD = "IOSTD";
     247NET "SODIMM_DQ<24>" LOC = "AD21" | IOSTANDARD = "IOSTD";
     248NET "SODIMM_DQ<25>" LOC = "AE21" | IOSTANDARD = "IOSTD";
     249NET "SODIMM_DQ<26>" LOC = "AK22" | IOSTANDARD = "IOSTD";
     250NET "SODIMM_DQ<27>" LOC = "AL18" | IOSTANDARD = "IOSTD";
     251NET "SODIMM_DQ<28>" LOC = "AN19" | IOSTANDARD = "IOSTD";
     252NET "SODIMM_DQ<29>" LOC = "AP19" | IOSTANDARD = "IOSTD";
     253NET "SODIMM_DQ<30>" LOC = "AM18" | IOSTANDARD = "IOSTD";
     254NET "SODIMM_DQ<31>" LOC = "AN18" | IOSTANDARD = "IOSTD";
     255NET "SODIMM_DQ<32>" LOC = "AF21" | IOSTANDARD = "IOSTD";
     256NET "SODIMM_DQ<33>" LOC = "AC20" | IOSTANDARD = "IOSTD";
     257NET "SODIMM_DQ<34>" LOC = "AD20" | IOSTANDARD = "IOSTD";
     258NET "SODIMM_DQ<35>" LOC = "AE19" | IOSTANDARD = "IOSTD";
     259NET "SODIMM_DQ<36>" LOC = "AP21" | IOSTANDARD = "IOSTD";
     260NET "SODIMM_DQ<37>" LOC = "AJ20" | IOSTANDARD = "IOSTD";
     261NET "SODIMM_DQ<38>" LOC = "AL19" | IOSTANDARD = "IOSTD";
     262NET "SODIMM_DQ<39>" LOC = "AK19" | IOSTANDARD = "IOSTD";
     263NET "SODIMM_DQ<40>" LOC = "AF14" | IOSTANDARD = "IOSTD";
     264NET "SODIMM_DQ<41>" LOC = "AG12" | IOSTANDARD = "IOSTD";
     265NET "SODIMM_DQ<42>" LOC = "AK13" | IOSTANDARD = "IOSTD";
     266NET "SODIMM_DQ<43>" LOC = "AH12" | IOSTANDARD = "IOSTD";
     267NET "SODIMM_DQ<44>" LOC = "AN14" | IOSTANDARD = "IOSTD";
     268NET "SODIMM_DQ<45>" LOC = "AP14" | IOSTANDARD = "IOSTD";
     269NET "SODIMM_DQ<46>" LOC = "AL13" | IOSTANDARD = "IOSTD";
     270NET "SODIMM_DQ<47>" LOC = "AN12" | IOSTANDARD = "IOSTD";
     271NET "SODIMM_DQ<48>" LOC = "AF11" | IOSTANDARD = "IOSTD";
     272NET "SODIMM_DQ<49>" LOC = "AE11" | IOSTANDARD = "IOSTD";
     273NET "SODIMM_DQ<50>" LOC = "AE13" | IOSTANDARD = "IOSTD";
     274NET "SODIMM_DQ<51>" LOC = "AE12" | IOSTANDARD = "IOSTD";
     275NET "SODIMM_DQ<52>" LOC = "AK12" | IOSTANDARD = "IOSTD";
     276NET "SODIMM_DQ<53>" LOC = "AJ12" | IOSTANDARD = "IOSTD";
     277NET "SODIMM_DQ<54>" LOC = "AK11" | IOSTANDARD = "IOSTD";
     278NET "SODIMM_DQ<55>" LOC = "AJ11" | IOSTANDARD = "IOSTD";
     279NET "SODIMM_DQ<56>" LOC = "AC12" | IOSTANDARD = "IOSTD";
     280NET "SODIMM_DQ<57>" LOC = "AH10" | IOSTANDARD = "IOSTD";
     281NET "SODIMM_DQ<58>" LOC = "AD11" | IOSTANDARD = "IOSTD";
     282NET "SODIMM_DQ<59>" LOC = "AG10" | IOSTANDARD = "IOSTD";
     283NET "SODIMM_DQ<60>" LOC = "AP12" | IOSTANDARD = "IOSTD";
     284NET "SODIMM_DQ<61>" LOC = "AM12" | IOSTANDARD = "IOSTD";
     285NET "SODIMM_DQ<62>" LOC = "AL10" | IOSTANDARD = "IOSTD";
     286NET "SODIMM_DQ<63>" LOC = "AJ10" | IOSTANDARD = "IOSTD";
     287
     288#DQS
     289NET "SODIMM_DQS0_N" LOC = "AG26" | IOSTANDARD = "IOSTD";
     290NET "SODIMM_DQS0_P" LOC = "AG25" | IOSTANDARD = "IOSTD";
     291NET "SODIMM_DQS1_N" LOC = "AM28" | IOSTANDARD = "IOSTD";
     292NET "SODIMM_DQS1_P" LOC = "AN28" | IOSTANDARD = "IOSTD";
     293NET "SODIMM_DQS2_N" LOC = "AL25" | IOSTANDARD = "IOSTD";
     294NET "SODIMM_DQS2_P" LOC = "AM25" | IOSTANDARD = "IOSTD";
     295NET "SODIMM_DQS3_N" LOC = "AH22" | IOSTANDARD = "IOSTD";
     296NET "SODIMM_DQS3_P" LOC = "AG22" | IOSTANDARD = "IOSTD";
     297NET "SODIMM_DQS4_N" LOC = "AL20" | IOSTANDARD = "IOSTD";
     298NET "SODIMM_DQS4_P" LOC = "AM20" | IOSTANDARD = "IOSTD";
     299NET "SODIMM_DQS5_N" LOC = "AM13" | IOSTANDARD = "IOSTD";
     300NET "SODIMM_DQS5_P" LOC = "AN13" | IOSTANDARD = "IOSTD";
     301NET "SODIMM_DQS6_N" LOC = "AC14" | IOSTANDARD = "IOSTD";
     302NET "SODIMM_DQS6_P" LOC = "AD14" | IOSTANDARD = "IOSTD";
     303NET "SODIMM_DQS7_N" LOC = "AM11" | IOSTANDARD = "IOSTD";
     304NET "SODIMM_DQS7_P" LOC = "AL11" | IOSTANDARD = "IOSTD";
     305
     306#SO-DIMM reserved pins when using DDR3 controller based on the Xilinx MIG
     307# (IOB clock logic used internally; must be unconnected on PCB and in FPGA designs)
     308
     309#Bank 22
     310CONFIG PROHIBIT = AF20, AP20, AF19;
     311
     312#Bank 23
     313CONFIG PROHIBIT = AH23, AK27, AN27;
     314
     315#Bank 32
     316CONFIG PROHIBIT = AH17;
     317
     318#Bank 33
     319CONFIG PROHIBIT = AP11, AD12, AC13;
     320}}}