Changes between Version 3 and Version 4 of HardwareUsersGuides/WARPv3/Porting_to_v3


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Timestamp:
Aug 26, 2012, 8:59:21 PM (12 years ago)
Author:
murphpo
Comment:

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  • HardwareUsersGuides/WARPv3/Porting_to_v3

    v3 v4  
    99 * The V6 doesn't have an embedded processor, so processor-based designs need to port to MicroBlaze. We're working on the OFDM and WARPLab reference designs and are (so far) impressed by how seamless the PPC->MB transition was. All of the Xilinx-supplied pcores/drivers are agnostic to the underlying processor. The only code changes we made were to accomodate driver changes from XPS 10.1 to 13.4.
    1010
     11 * The MicroBlaze processor doesn't allow unaligned memory access by default. For example:
     12{{{
     13#!C
     14u32* ptr_int = 0x80000002;
     15}}}
     16will have unpredictable results. The compiler won't complain, but in hardware the processor seems to ignore the LSB of the address and treat the resulting (wrong) address as the specified data type. But the MB core can be configured to handle unaligned accesses by adding a parameter {{{ PARAMETER C_UNALIGNED_EXCEPTIONS = 1}}} to the MB instance in the MHS file. With this enabled we've observed the MB core successfully read/write 2 and 4-byte values at unaligned addresses. We enable this parameter by default in our reference and template projects, to avoid really-hard-to-debug behavior in user code.
     17
    1118 * The release of new hardware seemed like a good time to redesign some of the WARP-specific pcores/drivers that we'd developed over the years. The radio controller driver, for example, was in desperate need of re-design. The old driver worked, but had a very inconsistent API (the natural result of having been written by multiple people over over the course of many years, as the WARP reference designs became more advanced). The new radio controller and driver provide the same functionality but with a much more compact and consistent API. Same goes for the user IO and EEPROM pcores/drivers.
    1219