Changes between Version 4 and Version 5 of HardwareUsersGuides/WARPv3/Porting_to_v3


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Timestamp:
Aug 26, 2012, 9:00:02 PM (7 years ago)
Author:
murphpo
Comment:

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  • HardwareUsersGuides/WARPv3/Porting_to_v3

    v4 v5  
    1313#!C
    1414u32* ptr_int = 0x80000002;
     15*ptr_int = 0x01234567;
     16xil_printf("The int value is %d\n", *ptr_int);
    1517}}}
    1618will have unpredictable results. The compiler won't complain, but in hardware the processor seems to ignore the LSB of the address and treat the resulting (wrong) address as the specified data type. But the MB core can be configured to handle unaligned accesses by adding a parameter {{{ PARAMETER C_UNALIGNED_EXCEPTIONS = 1}}} to the MB instance in the MHS file. With this enabled we've observed the MB core successfully read/write 2 and 4-byte values at unaligned addresses. We enable this parameter by default in our reference and template projects, to avoid really-hard-to-debug behavior in user code.