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UserIO

-                      v2
+                      v3
 There are two 7-segment displays (a.k.a. hex displays). Each display has 8 LED elements- 7 comprising the digit plus a decimal point. All 16 LEDs are tied to individual FPGA pins. The WARP v3 board supports either common anode or common cathode displays. All current WARP v3 boards are build with a common cathode part. As a result, driving a FPGA pin low will illuminate the corresponding LED segment.
+The seven LED segments in each display are individually controlled. The w3_userio core implements a 4-bit to 7-bit mapping block that translates a 4-bit value to the 7-bit pattern best approximating the corresponding hexadecimal character. This mapping logic is enabled by default. When disabled the seven segments are mapped to bits in w3_userio output register according to the pattern below.
+[[Image(wiki:HardwareUsersGuides/WARPv3/files:seven_seg_bit_map.jpg)]]
 = User I/O Control =
 We have written the [wiki:/cores/w3_userio w3_userio core] to provide easy access to all user I/O elements on the WARP v3 board. Refer to the w3_userio page and our reference projects for examples.