| | 1 | == Clocks == |
| | 2 | The entire MIMO OFDM model is driven by a single clock and has one top-level clock enable. The clock signal connected to '''opb_clk''' must be the same clock which drives the ADC/DACs on the radio daughtercards. |
| | 3 | ||'''Port'''||'''Default'''||'''Direction'''||'''Width'''|| |
| | 4 | ||opb_clk||sys_clk_s||Input||1|| |
| | 5 | ||ce||net_vcc||Input||1|| |
| | 6 | |
| | 7 | == OPB Interface Ports == |
| | 8 | The model includes a standard OPB slave interface. This interface is used to connect the OFDM core to an embedded PowerPC or Microblaze processor in the FPGA. This interface must be connected to a processor in order to use the OFDM core in hardware. |
| | 9 | ||'''Port'''||'''Default'''||'''Direction'''||'''Width'''|| |
| | 10 | ||opb_abus||OPB_ABus||Input||32|| |
| | 11 | ||opb_be||OPB_BE||Input||4|| |
| | 12 | ||opb_dbus||OPB_DBus||Input||32|| |
| | 13 | ||opb_rnw||OPB_RNW||Input||1|| |
| | 14 | ||opb_rst||OPB_Rst||Input||1|| |
| | 15 | ||opb_select||OPB_select||Input||1|| |
| | 16 | ||opb_seqaddr||OPB_seqAddr||Input||1|| |
| | 17 | ||sgp_dbus||Sl_DBus||Output||32|| |
| | 18 | ||sgp_errack||Sl_errAck||Output||1|| |
| | 19 | ||sgp_retry||Sl_retry||Output||1|| |
| | 20 | ||sgp_toutsup||Sl_toutSup||Output||1|| |
| | 21 | ||sgp_xferack||Sl_xferAck||Output||1|| |
| | 22 | |
| | 23 | == OFDM Core == |
| | 24 | The OFDM core uses dedicated top-level ports to interface with other peripheral cores. Some of these signals are connected to radio bridges, which route the signals off-chip to radio daughtercards. The rest connect to other custom cores for radio-specific PHY functions like AGC and packet detection. |
| | 25 | ||'''Port'''||'''Default'''||'''Direction'''||'''Width'''||'''Notes'''|| |
| | 26 | ||rx_anta_adci_dv4||||Input||14||I channel ADC input from antenna A; data must be donwsampled to 1/4 the master clock|| |
| | 27 | ||rx_anta_adcq_dv4||||Input||14||Q channel ADC input from antenna A; data must be donwsampled to 1/4 the master clock|| |
| | 28 | ||rx_antb_adci_dv4||||Input||14||I channel ADC input from antenna B; data must be donwsampled to 1/4 the master clock|| |
| | 29 | ||rx_antb_adcq_dv4||||Input||14||Q channel ADC input from antenna B; data must be donwsampled to 1/4 the master clock|| |
| | 30 | ||rx_extpktdet ||||Input||1||External packet detection input; high input indicates a probable arriving packet|| |
| | 31 | ||rx_int_badpkt||||Output||1||Interrupt output signaling a received packet failed CRC|| |
| | 32 | ||rx_int_goodpkt||||Output||1||Interrupt output signaling a received packet passed CRC and is ready for higher-layer processing|| |
| | 33 | ||rx_pktdetreset ||||Output||1||Active-high output indicating that packet detection events should be ignored while the PHY is busy|| |
| | 34 | ||rx_reset ||||Input||1||Active-high global reset input; clears all internal state in the receiver model; does not clear register values|| |
| | 35 | ||tx_anta_dac_i||||Output||16||I channel DAC output for antenna A; output runs at same rate as master clock|| |
| | 36 | ||tx_anta_dac_q||||Output||16||Q channel DAC output for antenna A; output runs at same rate as master clock|| |
| | 37 | ||tx_antb_dac_i||||Output||16||I channel DAC output for antenna B; output runs at same rate as master clock|| |
| | 38 | ||tx_antb_dac_q||||Output||16||Q channel DAC output for antenna B; output runs at same rate as master clock|| |
| | 39 | ||tx_reset||||Input||1||Active-high global reset input; clears all internal state in the transmitter model; does not clear register values|| |
| | 40 | ||tx_starttransmit ||||Input||1||Active-high trigger to begin transmission of a packet; usually tied to one of the radio controller's TxStart outputs|| |
| | 41 | |
| | 42 | == Debugging Ports == |
| | 43 | ||'''Port'''||'''Default'''||'''Direction'''||'''Width'''||'''Notes'''|| |
| | 44 | ||debug_chipscopetrig ||||Input||1||External active-high trigger for ChipScope ILA core in the receiver|| |
| | 45 | ||rx_debug_eq_i||||Ouput||14||I channel of equalized symbols; usually tied to an analog daughtercard for real-time debugging|| |
| | 46 | ||rx_debug_eq_q||||Ouput||14||Q channel of equalized symbols; usually tied to an analog daughtercard for real-time debugging|| |
| | 47 | ||rx_debug_payload ||||Output||1||Copy of receiver's Payload signal; indicates receiver is currently processing a packet|| |
| | 48 | ||rx_debug_pktdone ||||Output||1||Copy of receiver's PktDone signal; indicates receiver has finished processing a packet|| |
| | 49 | ||tx_debug_pktrunning ||||Output||1||Copy of transmitter's PktRunning signa; indicates transmitter is actively transmitting a packet|| |
