| | 2 | |
| | 3 | == OFDM Reference Design v12.0 (2009-Apr-9) == |
| | 4 | The code and models for this design correspond to [source:/@1170 svn rev 1170]. |
| | 5 | [[BR]] |
| | 6 | This project requires the latest versions of the Xilinx tools (ISE 10.1.03 + IP2, EDK 10.1.03, Sysgen 10.1.3.1386). |
| | 7 | [[BR]] |
| | 8 | Download the full XPS project: [http://warp.rice.edu/bigFiles/OFDM_ReferenceDesign_v12_0.zip OFDM_ReferenceDesign_v12_0.zip] |
| | 9 | |
| | 10 | '''Hardware Changes''' |
| | 11 | * Packet detector updates |
| | 12 | * Integrated the RSSI-based packet detector core into the OFDM transceiver. |
| | 13 | * The integrated detector's registers were rearranged (relative to the older separate detector core) |
| | 14 | * Added a minimum duration requirement to the packet detector. This block requires the average RSSI exceed the programmed energy threshold for a minimum number of cycles before the packet detecting output is asserted. The required minimum duration is programmable via a register. |
| | 15 | * Added logic to de-assert the IDLE for DIFS output whenever the transceiver is actively transmitting or receiving a packet. When either Tx or Rx is active, the medium is known to be busy, so the IDLE signal can safely be forced low, independent of RSSI readings. |
| | 16 | * Interrupt changes |
| | 17 | * Removed all interrupts in the hardware design |
| | 18 | * The transceiver now asserts register bits for reception events (good/bad header, good/bad packet); the MAC polls this register. |
| | 19 | * The user I/O and UART interrupts were replaced by polling the GPIO and UARTLITE registers. |
| | 20 | * The OFDM timer interrupts were replaced by polling the status of each timer in the core. |
| | 21 | * Upgraded EEPROM controller core HDL with better clocking design. Instead of generating a slow clock, the core generates a slow clock enable and uses the fast clock for all synchronous elements. This fixes the long-standing, intermittent timing error. |
| | 22 | * Fixed the PHY's handling of packet errors when all received bytes are zero. Previously this caused an erroneous good packet interrupt; now it correctly asserts the bad header and bad packet status bits. |
| | 23 | |
| | 24 | '''Software Changes''' |
| | 25 | * Updated WARPPHY and WARPMAC with register map for integrated transceiver and packet detector. |
| | 26 | * Updated EEPROM driver to match new hardware. |
| | 27 | |
