Changes between Version 64 and Version 65 of OFDMReferenceDesign/Changelog

Timestamp:

Jan 8, 2010, 2:18:03 PM (14 years ago)

Author:

sgupta

Comment:

--

OFDMReferenceDesign/Changelog

@@ -8 +8 @@
 This project requires the latest versions of the 10.1 release of the Xilinx tools (ISE 10.1.03 + IP2, EDK 10.1.03, Sysgen 10.1.3.1386).
 
-'''Minor Revision:''' The Virtex-4 design has been updated to include the MGT Protector Core.
+Download the full XPS project:
+ * Virtex-II Pro (WARP FPGA Board v1.2): [http://warp.rice.edu/bigFiles/OFDM_ReferenceDesign_FPGAv1_v14.1_public.zip OFDM_ReferenceDesign_FPGAv1_v14.1_public.zip] (86 MB)
+ * Virtex-4 (WARP FPGA Board v2.2): [http://warp.rice.edu/bigFiles/OFDM_ReferenceDesign_FPGAv2_v14.1_public.zip OFDM_ReferenceDesign_FPGAv2_v14.1_public.zip] (87MB)
+
+'''Hardware Changes'''
+ * Updated the version of the Radio Bridge and Radio Controller cores to v1.22.a
+ * Added the MGT Protector core to the Virtex-4 design to make sure the MGT tiles are always powered on. This is a requirement of the Virtex-4 (see 'Designing with MGTs' in [wiki:HardwareUsersGuides/FPGABoard_v2.2/MGTs Virtex-4 User Guide).
+
+'''Software Changes'''
+ * No software changes
+
+'''Using the Design'''
+ * Same as v14.0. See below.
+
+
+== OFDM Reference Design v14.0 (2009-Nov-15) ==
+The code and models for this design correspond to [source:/@1400 svn rev 1400].
+[[BR]]
+This project requires the latest versions of the 10.1 release of the Xilinx tools (ISE 10.1.03 + IP2, EDK 10.1.03, Sysgen 10.1.3.1386).
 
 Download the full XPS project:
  * Virtex-II Pro (WARP FPGA Board v1.2): [http://warp.rice.edu/bigFiles/OFDM_ReferenceDesign_FPGAv1_v14.0_public.zip OFDM_ReferenceDesign_FPGAv1_v14.0_public.zip] (88 MB)
- * Virtex-4 (WARP FPGA Board v2.2): [http://warp.rice.edu/bigFiles/OFDM_ReferenceDesign_FPGAv2_v14.1_public.zip OFDM_ReferenceDesign_FPGAv2_v14.1_public.zip] (89MB)
+ * Virtex-4 (WARP FPGA Board v2.2): [http://warp.rice.edu/bigFiles/OFDM_ReferenceDesign_FPGAv2_v14.0_public.zip OFDM_ReferenceDesign_FPGAv2_v14.0_public.zip] (89MB)
 
 [[BR]]
@@ -24 +42 @@
  * Fixed phase tracking bug in the PHY; the bug caused packet errors when imperfect phase estimates were used mid-packet
  * Switched to TEMAC + LL_FIFO for the Ethernet interface (replacing ethernet_lite). This hardware design works on both FPGA Board v1 and v2, using a soft TEMAC for v1 and hard TEMAC for v2. The TEMAC and LL_FIFO together provide storage for 4 received packets, which improves the overall performance in systems where many packets may be received at once (like TCP).
- * '''Version 14.1:''' Upgraded Radio Bridge and Radio Controller to version 1.22. Added MGT Protector cores for Virtex-4 MGTs.
 
 '''Software Changes'''