| | 4 | |
| | 5 | == OFDM Reference Design v16.0 (2011-Feb-17) == |
| | 6 | The code and models for this design correspond to [source:/@X svn rev X]. |
| | 7 | |
| | 8 | Download the full XPS projects: |
| | 9 | * Virtex-II Pro (WARP FPGA Board v1.2): [http://warp.rice.edu/bigFiles/OFDM_ReferenceDesign_FPGAv1_public_v16.0.zip OFDM_ReferenceDesign_FPGAv1_public_v16.0.zip] (100MB) |
| | 10 | * Virtex-4 (WARP FPGA Board v2.2): [http://warp.rice.edu/bigFiles/OFDM_ReferenceDesign_FPGAv2_public_v16.0.zip OFDM_ReferenceDesign_FPGAv2_public_v16.0.zip] (100MB) |
| | 11 | |
| | 12 | Both projects were built using the latest versions of the 10.1 release of the Xilinx tools (ISE 10.1.03 + IP3, EDK 10.1.03, Sysgen 10.1.3.1386). |
| | 13 | |
| | 14 | '''Notes (please read!)'''[[BR]] |
| | 15 | The OFDM Reference Design now includes channel coding. The PHY implements a K=7 convolutional code with support for four code rates (1/2, 2/3, 3/4 and 1). This is the same code used by 802.11a/g. When coding is enabled, packet headers are sent as 1/2 rate coded QPSK, and payloads are encoded according to the codeRate field in the header. The payload code rate is configured per-packet; the receiver configures its decoder based on the codeRate field in the header. Payloads can be modulated with BPSK, QPSK or 16-QAM (all 12 combinations of payload modulation/code rate are supported). |
| | 16 | |
| | 17 | The PHY is identical for FPGA v1 and v2. The same .mdl file (ofdm_txrx_supermimo_coded.mdl) is used to generate the pcores for both versions. The only difference is the target device selected in the System Generator token (XC2VP70-FF1517-6 for v1 and XC4VFX100-FF1517-11 for v2). |
| | 18 | |
| | 19 | Because of limitations in the number of multipliers in the Virtex-4 FPGA, the decimation filters in the rate_change_filters pcore use non-embedded multipliers (i.e. implemented in fabric) in the v2 design. The rate_change_filter source model is in the repository ([source:/ResearchApps/PHY/MIMO_OFDM/Rate%20Change%20Filters /ResearchApps/PHY/MIMO_OFDM/Rate Change Filters]), along with a .m script which enables/disables embedded multipliers in the decimation filters. |
| | 20 | |
| | 21 | We have tested the coded PHY with every combination of code and modulation rate and many packet lengths. We found some bugs in earlier iterations and believe they are all fixed. We have not used this design for extensive over-the-air experiments yet (these are ongoing, part of our current research work). We don't expect any problems, and are eager to hear any feedback from other groups using the design in their work. |
| | 22 | |
| | 23 | '''Hardware Changes''' |
| | 24 | * Integrated convolutional channel coding, with configurable coding rate per packet |
| | 25 | * Added decimation filters to PHY I/Q input |
| | 26 | * Relocated rate change filters to separate pcore (sits between radio_bridges and AGC/PHY) |
| | 27 | |
| | 28 | '''Software Changes''' |
| | 29 | * Added codeRate field in packet transmission functions |
| | 30 | * Updated warpphy/warpmac to reflect changes to registers in the PHY |
| | 31 | |
| | 32 | '''Using the Design''' |
| | 33 | * The included download-csmamac.bit file implements CSMAMAC; download-nomac.bit implements NOMAC. Both are ready to download to WARP SISO or MIMO Kits. |
| | 34 | * The included download-csmamac.ace or download-nomac.ace can be copied directly to a CompactFlash card (without using iMPACT) to program kits via the SystemACE CF interface. |
| | 35 | * The CSMAMAC code uses the UART to control various parameters at run time. Use a terminal emulator set to 57600bps. The following commands are implemented by default: |
| | 36 | * '''P'''/'''p''' : Increase/decrease the packet detection energy threshold by 100 |
| | 37 | * '''D'''/'''d''' : Increase/decrease the packet detection required minimum energy duration by 1 |
| | 38 | * '''C'''/'''c''' : Increase/decrease the carrier sensing energy threshold by 100 |
| | 39 | * '''F'''/'''f''' : Increase/decrease the 2.4GHz center frequency by 1 channel |
| | 40 | * '''S'''/'''s''' : Use SISO via the radio in slot 3/2 |
| | 41 | * '''A''' : Use Alamouti 2x2 (2 transmit antennas, selection diversity between 2 receive antennas) |
| | 42 | * '''1'''/'''2'''/'''4''' : Use BPSK/QPSK/16-QAM for the full-rate modulation scheme for all transmitted payloads |
| | 43 | * '''7'''/'''8'''/'''9'''/'''0''' : Use ![1/2, 2/3, 3/4, 1] coding rate for all transmitted payloads (rate 1 = no coding) |
| | 44 | * You can add other commands to tweak your own parameters in uartRecv_callback function |
| | 45 | * The four user LEDs are programmed by default to toggle based on packet receptions. The top two LEDs will toggle for each good packet received. The bottom two LEDs will toggle for each bad header or bad payload received. |
| | 46 | * The right seven-segment display is programmed to show the node's ID on boot (set by the DIP switch); the left displays shows the sequence number of received packets. |
| | 47 | |
| | 48 | ---- |
| 36 | | == OFDM Reference Design v14.1 (2010-Jan-08) == |
| 37 | | The code and models for this design correspond to [source:/@1400 svn rev 1400]. |
| 38 | | [[BR]] |
| 39 | | This project requires the latest versions of the 10.1 release of the Xilinx tools (ISE 10.1.03 + IP2, EDK 10.1.03, Sysgen 10.1.3.1386). |
| 40 | | |
| 41 | | Download the full XPS project: |
| 42 | | * Virtex-II Pro (WARP FPGA Board v1.2): [http://warp.rice.edu/bigFiles/OFDM_ReferenceDesign_FPGAv1_v14.1_public.zip OFDM_ReferenceDesign_FPGAv1_v14.1_public.zip] (87 MB) |
| 43 | | * Virtex-4 (WARP FPGA Board v2.2): [http://warp.rice.edu/bigFiles/OFDM_ReferenceDesign_FPGAv2_v14.1_public.zip OFDM_ReferenceDesign_FPGAv2_v14.1_public.zip] (87MB) |
| 44 | | |
| 45 | | '''Hardware Changes''' |
| 46 | | * Updated the version of the Radio Bridge and Radio Controller cores to v1.22.a |
| 47 | | * Added the MGT Protector core to the Virtex-4 design to make sure the MGT tiles are always powered on. This is a requirement of the Virtex-4 (see 'Designing with MGTs' in [wiki:HardwareUsersGuides/FPGABoard_v2.2/MGTs Virtex-4 User Guide]). |
| 48 | | |
| 49 | | '''Software Changes''' |
| 50 | | * No software changes |
| 51 | | |
| 52 | | '''Using the Design''' |
| 53 | | * Same as v14.0. See below. |
| 54 | | |
| 55 | | ---- |
| 56 | | |
| 57 | | == OFDM Reference Design v14.0 (2009-Nov-15) == |
| 58 | | The code and models for this design correspond to [source:/@1400 svn rev 1400]. |
| 59 | | [[BR]] |
| 60 | | This project requires the latest versions of the 10.1 release of the Xilinx tools (ISE 10.1.03 + IP3, EDK 10.1.03, Sysgen 10.1.3.1386). |
| 61 | | |
| 62 | | Download the full XPS project: |
| 63 | | * Virtex-II Pro (WARP FPGA Board v1.2): [http://warp.rice.edu/bigFiles/OFDM_ReferenceDesign_FPGAv1_v14.0_public.zip OFDM_ReferenceDesign_FPGAv1_v14.0_public.zip] (88 MB) |
| 64 | | * Virtex-4 (WARP FPGA Board v2.2): [http://warp.rice.edu/bigFiles/OFDM_ReferenceDesign_FPGAv2_v14.0_public.zip OFDM_ReferenceDesign_FPGAv2_v14.0_public.zip] (89MB) |
| 65 | | |
| 66 | | [[BR]] |
| 67 | | |
| 68 | | '''FPGA Board Version Notes''' [[BR]] |
| 69 | | The OFDM Reference Design uses very similar hardware designs for the two versions of the WARP FPGA Board (v1 and v2). The primary difference is the use of a soft Ethernet MAC in the Virtex-II Pro FPGA and hard TEMAC in the Virtex-4. The custom WARP peripherals (OFDM transceiver, AGC, timer, radio controller, etc.) are identical in both projects. |
| 70 | | |
| 71 | | The software projects are also very similar across boards. The same source files are used for both versions. A few {{{#ifdef}}} statements are used in WARPMAC to include/exclude board-specific code at compile time. The primary difference is support for user I/O. The project for the FPGA Board v1 uses an xps_gpio core as an interface to the LEDs, hex displays, buttons and switches. The FPGA Board v2 project uses the custom [wiki:HardwareUsersGuides/FPGABoard_v2.2/UserIO/warp_v4_userio warp_v4_userio] core and driver for the user I/O. WARPMAC provides a single API for user I/O, so MAC-level code can be fully portable between FPGA Board versions. |
| 72 | | |
| 73 | | '''Hardware Changes''' |
| 74 | | * Fixed phase tracking bug in the PHY; the bug caused packet errors when imperfect phase estimates were used mid-packet |
| 75 | | * Switched to TEMAC + LL_FIFO for the Ethernet interface (replacing ethernet_lite). This hardware design works on both FPGA Board v1 and v2, using a soft TEMAC for v1 and hard TEMAC for v2. The TEMAC and LL_FIFO together provide storage for 4 received packets, which improves the overall performance in systems where many packets may be received at once (like TCP). |
| 76 | | |
| 77 | | '''Software Changes''' |
| 78 | | * Updated WARPMAC to use new Ethernet hardware |
| 79 | | * Updated WARPMAC with new user I/O code for FPGA Board v2. One code file works for both versions, using just a few !#ifdef to compile the correct code. |
| 80 | | |
| 81 | | '''Using the Design''' |
| 82 | | * The included download-csmamac.bit file implements CSMAMAC; download-nomac.bit implements NOMAC. Both are ready to download to WARP SISO or MIMO Kits. |
| 83 | | * The included download-csmamac.ace or download-nomac.ace can be copied directly to a CompactFlash card (without using iMPACT) to program kits via the SystemACE CF interface. |
| 84 | | * The CSMAMAC code uses the UART to control various parameters at run time. Use a terminal emulator set to 57600bps. The following commands are implemented by default: |
| 85 | | * '''P'''/'''p''' : Increase/decrease the packet detection energy threshold by 100 |
| 86 | | * '''D'''/'''d''' : Increase/decrease the packet detection required minimum energy duration by 1 |
| 87 | | * '''C'''/'''c''' : Increase/decrease the carrier sensing energy threshold by 100 |
| 88 | | * '''F'''/'''f''' : Increase/decrease the 2.4GHz center frequency by 1 channel |
| 89 | | * '''S'''/'''s''' : Use SISO via the radio in slot 3/2 |
| 90 | | * '''A''' : Use Alamouti 2x1 (2 transmit antennas, selection diversity between 2 receive antennas) |
| 91 | | * '''1'''/'''2'''/'''4'''/'''6''' : Use BPSK/QPSK/16-QAM/64-QAM for the full-rate modulation scheme for all transmitted payloads |
| 92 | | * You can add other commands to tweak your own parameters in uartRecv_callback function |
| 93 | | * The four user LEDs are programmed by default to toggle based on packet receptions. The top two LEDs will toggle for each good packet received. The bottom two LEDs will toggle for each bad header or bad payload received. |
| 94 | | * The right seven-segment display is programmed to show the node's ID on boot (set by the DIP switch); the left displays shows the sequence number of received packets. |
| 95 | | |
| 96 | | ---- |
| 97 | | |
