OFDM Reference Design History

OFDM Reference Design v10 (2008-Jul-17)

• Download the XPS project: ​OFDM_ReferenceDesign_v10.zip
• Built using cores and code as of repository revision 1010
• This design requires version 10.1.02 of the Xilinx tools
• Data-ACK turnaround time is now 23µs (as measured by the fall of data Tx to rise of ACK Tx)

Hardware Changes

• Xilinx deprecated the OPB and PLB34 busses. PLB46 is the new (and only) bus standard used in this design
• The System Generator cores (OFDM transceiver, timer, packet detector & AGC) were created using Sysgen's new PLB46 export flow; sysgen2opb is no longer required
• Xilinx did not port the plb_ethernet EMAC forward to PLB46. This design uses the xps_ethernetlite EMAC instead, customized to enable promiscuous mode (i.e. no receive address filtering)
• The xps_centraldma pcore is used to handle DMA (since the EMAC no longer provides its own DMA)
• The OFDM transceiver has a new interrupt output indicating the reception of a bad header
• Fixed a few logic bugs in the transceiver's handling of multiple interrupts
• Merged all user I/O into single GPIO core (LEDs, hex displays, push buttons & DIP switch); a header file​ helps with the required bit masking/shifting

Software Changes

• Ethernet is now operated exclusively in a polling mode for increased performance
• WARPMAC/WARPPHY re-architected and cleaned; the code flows for transmitting and receiving packets are now consistent across various packet types
• A layer of register access macros was added between WARPPHY and the OFDM cores; these macros adapt the old sysgen2opb register access code to the new Sysgen PLB46 export code. These macros will retired in a future revision.

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OFDM Reference Design v09 (2008-Jun-11)

• Download the XPS project: ​OFDM_ReferenceDesign_v09.zip
• Built using cores and code as of repository revision 906
• This version assumes a different location for TxDCO calibration information in the EEPROM of the radios. Please re-calibrate before running (instructions are here)
• This will be the last reference design that will use the version 9 Xilinx tools. Reference Design v10 will use the version 10 Xilinx tools.
• Updated warpmac/warpphy & csmamac
  • Header interrupts are used to pipeline receive processions (i.e. an ACK is constructed and loaded into a PHY before the packet is even completely received)
  • Fall of Tx data to rise of Tx ACK turn-around time reduced from 80 microseconds to 30 microseconds
  • By default, left and right push buttons use left and right radios respectively (only for MIMO WARP kits)
  • Numerous tweaks to MAC timing parameters

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OFDM Reference Design v08 (2008-Feb-08)

• Download the XPS project: ​OFDM_ReferenceDesign_v08.zip
• Built using cores and code as of repository revision 834
• Updated OFDM PHY
  • Added support for header-only packets (like ACKs); numFullRateSymbols can be zero
  • Last two bytes of header are now a 16-bit CRC of just the header
  • Added new interrupt output for good header; asserts for non-header-only packets when header CRC passes
  • Added TxDone interrupt output; asserts when a packet transmission finishes
  • Fixed bugs in dynamic modulation mask usage
• Updated warpmac/warpphy & csmamac
  • Changes to support new PHY features
  • Added TxDone & GoodHeader interrupt handlers; unused in this version
  • Added lots of comments to the source code to better explain various MAC/PHY interactions