[[TracNav(WARPLab/TOC)]] = WARPLab Reference Design: Downloads = The latest WARPLab Reference Design is available for download below. The source and binary files are distributed under the terms of the [wiki:license WARP License]. Previous releases of the reference design are available in the [wiki:../Changelog WARPLab change log]. Refer to the [wiki:../QuickStart Quick Start guide] to get started with the reference design. == 7.3.0 Release: == '''Download: [http://warpproject.org/dl/refdes/warplab/v7/release/WARPLab_Reference_Design_7.3.0.zip WARPLab_Reference_Design_7.3.0.zip]''' Release Details: ||= Hardware =||= Release =||= Date Posted =||= SVN Rev. =||= ISE Ver. =||= Arch =||= MATLAB Ver. =||= RF Interface Support =|| || WARP v3 || 7.3.0 || 26-Aug-2013 || [browser:ResearchApps/PHY/WARPLAB/WARPLab7?rev=2180 2180] || 14.4 || MB/AXI || 2009b or later || 1-2: WARP v3 on-board interfaces [[BR]] 3-4: Requires [wiki:HardwareUsersGuides/FMC-RF-2X245 FMC-RF-2X245] || || WARP v2 || 7.3.0 || 26-Aug-2013 || [browser:ResearchApps/PHY/WARPLAB/WARPLab7?rev=2180 2180] || 14.4 || PPC/PLB || 2009b or later || 1-2: Radios in slots 2 & 3 [[BR]] 3-4: Radios in slots 1 & 4 || * '''Requires use of WARPXilnet library 3.02.a''' * '''Improved Read IQ / Write IQ performance by over 10x''' with a new Transport layer: [source:ResearchApps/PHY/WARPLAB/WARPLab7/M_Code_Reference/classes/wl_transport_eth_udp_mex.m wl_transport_eth_udp_mex]. * This uses the MATLAB EXecutable format, or MEX. To compile the transport for your platform, please refer to the [wiki:WARPLab/MEX MEX Compilation Guide]. * To see the performance improvements, please refer to the [wiki:WARPLab/Benchmarks benchmarks] * Updated [wiki:WARPLab/FPGAArchitecture/WARPLAB_7_3_0 FPGA HW design] * Updated the WARPLab Buffers core (w3_warplab_buffers_axiw_v2_03_a) which moved the memories outside of the core for the Read / Write IQ samples * Allowed for the use of the DMA for sample transfers vs memcpy * Updated bus architecture to improve performance * Added [wiki:WARPLab/Reference/Utility#wl_benchmark wl_benchmark] utility * Allows user to do performance testing of Read IQ / Write IQ on their system * Fixed bugs: * Addressed WARPLab 7.2.0 issue where there were checksum mismatches in Write IQ which would revert the Transport to "slow write" and reduce performance. * NOTE: * PNET will be deprecated in the WARPLab 7.4.0 release. Please use the new wl_mex_udp_transport instead. ---- == Reference Design Archive == The WARPLab reference design is packaged as a .zip file with the full source code and compiled bitstreams for the reference design. You can view the latest source code in the repository ([source:/ResearchApps/PHY/WARPLAB/WARPLab7]). Please note the code in the repository is under active development. The contents of the WARPLab reference design .zip file are explained below. === Bitstreams_Reference === Bitstreams are fully-built designs that are ready to be downloaded onto WARP hardware. Files ending with the extension '.bit' may be downloaded using the Xilinx tool iMPACT. Files ending with the extension .bin may loaded onto an SD card so that the WARP v3 hardware will automatically be programmed whenever it is powered on and has the SD card inserted. Details on how to configure an SD card with a '.bin' file are [wiki:howto/SD_Config provided here]. For WARP v2 hardware, compact flash cards may be loaded with the provided .ace files for similar functionality (instructions provided [wiki:howto/CF_Config here]). * '''w3''': WARP v3 FPGA bitstreams (see [wiki:howto/SD_Config SD config howto] for help using the .bin file) * '''w2''': WARP v2 FPGA bitstreams (see [wiki:howto/CF_Config CF config howto] for help using the .ace file) === EDK_Projects === This folder contains EDK projects for various hardware configurations. The WARPLab FPGA design is built with the Xilinx Embedded Development Kit (EDK) software. The hardware design is constructed and implemented in EDK Xilinx Platform Studio (XPS). The software design, running in the MicroBlaze processor, is built in the Xilinx SDK. Opening these EDK projects requires a copy of the [wiki:edk_user_repository WARP edk_user_repository] at the SVN revision in the table above. If you want to use (but not modify) the reference FPGA design, you only need a bitstream and the reference M code. If you want to modify the MicroBlaze/PPC C code, you can download an EDK project in this folder, but only modify the SDK project contained therein. To modify the FPGA hardware design, you will need to modify the XPS project. The WARPLab FPGA design uses custom peripherals designed in Xilinx System Generator, including the warplab_buffers core. You will need MATLAB, Simulink and System Generator to modify these cores. Each of these EDK projects are a combination of an XPS project along with Eclipse software projects that can be imported into an SDK workspace. These software projects are present in the 'SDK_Workspace' subfolder of every XPS project -- we recommend using this folder as the location of the SDK Workspace. These projects can then be imported "in place" and will not need to be copied. * '''w3''': WARP v3 EDK projects for the 2-radio (2RF) and 4-radio (4RF) WARPLab Reference Designs * '''w2''': WARP v2 EDK projects for the 2-radio (2RF) and 4-radio (4RF) WARPLab Reference Designs === M_Code_Examples === This folder contains example WARPLab scripts that are compatible with this release of WARPLab. Explanations of these scripts are [wiki:../Examples available here]. === M_Code_Reference === This folder contains all of the supporting files needed for WARPLab to run on a host PC with MATLAB. When downloading a new Reference Design Release, users will need to run the [wiki:../Reference/Utility#wl_setup wl_setup.m] script in this folder.