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= WARPLab Reference Design: Downloads =

The latest WARPLab Reference Design is available for download below. The source and binary files are distributed under the terms of the [wiki:license WARP License].

Previous releases of the reference design are available in the [wiki:../Changelog WARPLab change log].

Refer to the [wiki:../QuickStart Quick Start guide] to get started with the reference design.

== 7.5.0 Release: ==
'''Download: [http://warpproject.org/dl/refdes/warplab/v7/release/WARPLab_Reference_Design_7.5.0.zip WARPLab_Reference_Design_7.5.0.zip]'''

Release Details:
||= Hardware =||= Release =||= Date Posted =||= SVN Rev. =||= ISE Ver. =||= Arch =||=  MATLAB Ver.  =||=  RF Interface Support =||
||  WARP v3  ||  7.5.0  ||  25-Feb-2014  ||  [browser:ResearchApps/PHY/WARPLAB/WARPLab7?rev=XXX XXX]  ||  14.4  ||  MB/AXI  ||  2009b or later  || 1-2: WARP v3 on-board interfaces [[BR]] 3-4: Requires [wiki:HardwareUsersGuides/FMC-RF-2X245 FMC-RF-2X245] ||
||  WARP v2  ||  7.5.0  ||||||||||||||  Coming Soon  ||

 * '''Requires use of WARPXilnet library 3.03.a''' - [wiki:edk_user_repository update your edk_user_repository] before compiling the reference software project

WARPLab 7.5 for WARP v3 adds support for storing Tx/Rx samples in the on-board 2GB DRAM. Using the DRAM enables Tx and Rx waveforms with more than 1000x the number of samples as previous WARPLab releases. See the [wiki:../BufferSizes Sample Buffer Sizes] page for details on the new waveform length limits.

Other changes:

 * Updated the [wiki:WARPLab/Porting#NewScriptConventionsinWARPLab7.5andBeyond Porting Guide] with new scripting conventions. In 7.5, these changes are optional so old scripts will work as-is. In future releases, these changes will be enforced.
 * Replaced the old WARPLab AGC core with a new core derived from the wlan_agc core in the 802.11 Reference Design. The System Generator model for the new core is available in the repository: [browser:ResearchApps/PHY/WARPLAB/WARPLab7/Sysgen_Reference/w3/warplab_agc_v3 warplab_agc_v3].
 * Added new spectrogram Rx example ([wiki:WARPLab/Examples/Spectrogram WARPLab Spectrogram Example])
 * Updated all other examples to adopt new conventions for setting Tx/Rx waveform lengths
 * Added support for receiving Ethernet triggers on ETH B on WARP v3 hardware
 * Tweaked mex auto-compilation code to not require specific version of Microsoft tools
 * Updated mapping of debug pins - see the WARPLab [wiki:../HardwareConfiguration/WARPv3 WARP v3 hardware] usage for details
 * Added support for the CM-PLL clock module
 * Upgraded to the latest [wiki:cores/w3_clock_controller w3_clock_controller_axi] core
  * WARPLab assumes you have not written custom clock configurations to the EEPROM (see [wiki:cores/w3_clock_controller#Pre-BootConfiguration w3_clock_controller]). If you have customized the clock configurations in the EEPROM be sure to update {{{node_clk_initialize()}}} in [browser:/ResearchApps/PHY/WARPLAB/WARPLab7/C_Code_Reference/wl_node.c#L544 wl_node.c] to match.
  * '''NOTE:''' the updated core changes the interpretation of the clock module switches! See the WARPLab [wiki:../HardwareConfiguration/WARPv3 WARP v3 hardware] usage page for details on the new interpretation of the CM-PLL and CM-MMCX switches.
 * Added trigger inputs/outputs for the CM-PLL board-to-board cables. The 4 inputs and 4 outputs mirror the corresponding trigger signals on the debug header.

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== 7.4.0 Release: ==
'''Download: [http://warpproject.org/dl/refdes/warplab/v7/release/WARPLab_Reference_Design_7.4.0.zip WARPLab_Reference_Design_7.4.0.zip]'''

Release Details:
||= Hardware =||= Release =||= Date Posted =||= SVN Rev. =||= ISE Ver. =||= Arch =||=  MATLAB Ver.  =||=  RF Interface Support =||
||  WARP v3  ||  7.4.0  ||  25-Feb-2014  ||  [browser:ResearchApps/PHY/WARPLAB/WARPLab7?rev=2886 2886]  ||  14.4  ||  MB/AXI  ||  2009b or later  || 1-2: WARP v3 on-board interfaces [[BR]] 3-4: Requires [wiki:HardwareUsersGuides/FMC-RF-2X245 FMC-RF-2X245] ||
||  WARP v2  ||  7.4.0  ||  25-Feb-2014  ||  [browser:ResearchApps/PHY/WARPLAB/WARPLab7?rev=2886 2886]  ||  14.4  ||  PPC/PLB  ||  2009b or later  || 1-2: Radios in slots 2 & 3 [[BR]] 3-4: Radios in slots 1 & 4 ||

 * '''Requires use of WARPXilnet library 3.03.a''' - [wiki:edk_user_repository update your edk_user_repository] before compiling the reference software project


 * '''Added [wiki:WARPLab/Examples/OFDM OFDM Comm Example]'''
   * Implements a simple OFDM transmitter and receiver. 
   * Can run with or without WARP hardware in the loop and does not require any extra MATLAB toolboxes.
 * Updates to WARPLab cores:
   * Updated the WARPLab Buffers core in both WARP v2 and v3 (w2_warplab_buffers_plbw_v2_04_a and w3_warplab_buffers_axiw_v2_04_a) to honor the TxLength field in continuous transmit mode.
   * Updated the WARPLab AGC core in both WARP v2 and v3 (w2_warplab_agc_plbw_v2_01_a and w3_warplab_agc_axiw_v2_01_a) to allow for finer control of when the AGC resets.  
     * Added MATLAB commands:
       * {{{wl_basebandCmd(nodes, 'agc_reset_on_timeout', <true, false>);}}}
       * {{{wl_basebandCmd(nodes, 'agc_reset_timeout_value', <time in microseconds>);}}}
     * By default, the AGC will reset on timeout and the timeout value is set to be just longer than a IQ receive.  This is the same behavior as previous WARPLab releases.
   * Updated WARPLab User IO core in WARP v3 (w3_userio_axi_v1_01_a) to add a PWM for autonomous control of LEDs.
 * Updates to MEX transport:
   * '''If using the MEX transport, WARPLab 7.4.0 requires MEX 1.0.1a'''
   * Fixed some minor bugs in Read IQ fragmentation for small rx buffers.
   * Added ability from M to throttle Read / Write IQ and suppress timeout warnings for the transport.
     * {{{wl_mex_udp_transport('write_iq_set_pkt_wait_time', wait_time)}}}
       * Sets the inter-packet wait time for Write IQ to slow it down
     * {{{wl_mex_udp_transport('read_iq_set_max_request_size', size)}}}
       * Sets the maximum Read IQ request size in bytes to allow the transport to fragment Read IQ requests.
     * {{{wl_mex_udp_transport('suppress_iq_warnings')}}}
       * Suppresses all Read IQ / Write IQ timeout warnings.
   * NOTE:  All of the new functions affect the global state of the MEX transport (ie all nodes will be affected that use the MEX transport).  Also, the only way to turn them off is to terminate and reload the MEX transport (can be done using {{{clear all}}}).
 * Fixed bugs:
   * Fixed trigger manager reset / hold issue described [http://warpproject.org/forums/viewtopic.php?pid=10126#p10126 here]
   * Added warning when Write IQ sees samples vector with abs(I) or abs(Q) > 1.0 (can be turned off using: {{{node.baseband.check_write_iq_clipping = 0}}})
   * Added checks in C for valid DMA buffers (issue when sections are not placed correctly when regenerating linker command files)

 * NOTE:
   * PNET was removed in the WARPLab 7.4.0 release.  Please use the new wl_mex_udp_transport instead.


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== Reference Design Archive ==

The WARPLab reference design is packaged as a .zip file with the full source code and compiled bitstreams for the reference design. You can view the latest source code in the repository ([source:/ResearchApps/PHY/WARPLAB/WARPLab7]). Please note the code in the repository is under active development.

The contents of the WARPLab reference design .zip file are explained below.

=== Bitstreams_Reference ===
Bitstreams are fully-built designs that are ready to be downloaded onto WARP hardware. Files ending with the extension '.bit' may be downloaded using the Xilinx tool iMPACT. Files ending with the extension .bin may loaded onto an SD card so that the WARP v3 hardware will automatically be programmed whenever it is powered on and has the SD card inserted. Details on how to configure an SD card with a '.bin' file are [wiki:howto/SD_Config provided here]. For WARP v2 hardware, compact flash cards may be loaded with the provided .ace files for similar functionality (instructions provided [wiki:howto/CF_Config here]).
 * '''w3''': WARP v3 FPGA bitstreams (see [wiki:howto/SD_Config SD config howto] for help using the .bin file)
 * '''w2''': WARP v2 FPGA bitstreams (see [wiki:howto/CF_Config CF config howto] for help using the .ace file)

=== EDK_Projects ===
This folder contains EDK projects for various hardware configurations. The WARPLab FPGA design is built with the Xilinx Embedded Development Kit (EDK) software. The hardware design is constructed and implemented in EDK Xilinx Platform Studio (XPS). The software design, running in the MicroBlaze processor, is built in the Xilinx SDK. Opening these EDK projects requires a copy of the [wiki:edk_user_repository WARP edk_user_repository] at the SVN revision in the table above.

If you want to use (but not modify) the reference FPGA design, you only need a bitstream and the reference M code. If you want to modify the MicroBlaze/PPC C code, you can download an EDK project in this folder, but only modify the SDK project contained therein. To modify the FPGA hardware design, you will need to modify the XPS project. The WARPLab FPGA design uses custom peripherals designed in Xilinx System Generator, including the warplab_buffers core. You will need MATLAB, Simulink and System Generator to modify these cores.

Each of these EDK projects are a combination of an XPS project along with Eclipse software projects that can be imported into an SDK workspace. These software projects are present in the 'SDK_Workspace' subfolder of every XPS project -- we recommend using this folder as the location of the SDK Workspace. These projects can then be imported "in place" and will not need to be copied.
 * '''w3''': WARP v3 EDK projects for the 2-radio (2RF) and 4-radio (4RF) WARPLab Reference Designs
 * '''w2''': WARP v2 EDK projects for the 2-radio (2RF) and 4-radio (4RF) WARPLab Reference Designs

=== M_Code_Examples ===
This folder contains example WARPLab scripts that are compatible with this release of WARPLab. Explanations of these scripts are [wiki:../Examples available here].

=== M_Code_Reference ===
This folder contains all of the supporting files needed for WARPLab to run on a host PC with MATLAB. When downloading a new Reference Design Release, users will need to run the [wiki:../Reference/Utility#wl_setup wl_setup.m] script in this folder.