[[TracNav(WARPLab/TOC)]] = WARPLab Reference Design: Downloads = The latest WARPLab Reference Design is available for download below. The source and binary files are distributed under the terms of the [wiki:license WARP License]. Previous releases of the reference design are available in the [wiki:../Changelog WARPLab change log]. Refer to the [wiki:../QuickStart Quick Start guide] to get started with the reference design. == 7.6.0 Release: == '''Download: [http://warpproject.org/dl/refdes/warplab/v7/release/WARPLab_Reference_Design_7.6.0.zip WARPLab_Reference_Design_7.6.0.zip]''' Release Details: ||= Hardware =||= Release =||= Date Posted =||= SVN Rev. =||= ISE Ver. =||= Arch =||= MATLAB Ver. =||= RF Interface Support =|| || WARP v3 || 7.6.0 || 14-Sept-2015 || [browser:ResearchApps/PHY/WARPLAB/WARPLab7?rev=4713 4713] || 14.4 || MB/AXI || 2009b or later || 1-2: WARP v3 on-board interfaces [[BR]] 3-4: Requires [wiki:HardwareUsersGuides/FMC-RF-2X245 FMC-RF-2X245] || '''WARPLab 7.6.0 requires an SVN update to your [wiki:edk_user_repository edk_user_repository] before compiling the reference software project''' '''WARPLab 7.6.0''' provides transport improvements to the existing WARPLab 7.5.1 design and better M compatibility with earlier WARPLab releases. Other changes: * Added [wiki:WARPLab/Examples/MIMO_OFDM MIMO OFDM Communication Example] * Updated transport infrastructure on the node * Allows Read IQ / Write IQ commands to be processed while the node is transmitting or receiving (removes the restriction introduced in WARPLab 7.5.x) * Replaced WARPxilnet with [http://warpproject.org/trac/browser/edk_user_repository/WARP/sw_services/WARP_ip_udp_v1_00_a?rev=4713 '''WARP IP/UDP v1.00a'''] Ethernet packet processing library. * Updated MEX transport (see [wiki:WARPLab/Benchmarks Benchmarks]) - '''WARPLab 7.6.0 requires MEX 1.0.3a''' * Updated radio controller core to fix minor bugs * Changed default parameters to match the 802.11 reference design * Updated Ethernet behaviour * By default, nodes do not link with non-1000BASE-T Ethernet devices. * WARPLab waits for Ethernet device to be ready before completing boot. * Consolidated Ethernet behaviour options in [http://warpproject.org/trac/browser/ResearchApps/PHY/WARPLAB/WARPLab7/C_Code_Reference/include/wl_common.h?rev=4708 wl_common.h] * Added WARPLab command to control the [wiki:WARPLab/Reference/Interface/X245#rx_hpf_corn_freq RX HPF cutoff frequency] * Fixed bug when using CM-PLL input / output triggers * Introduced new syntax for trigger and interface IDs; refer (see [wiki:WARPLab/Porting#ChangesinWARPLab7.6 Porting guide] for more information) * Cleaned up C code and added more comments * Cleaned up M code examples ---- == 7.5.1 Release: == '''Download: [http://warpproject.org/dl/refdes/warplab/v7/release/WARPLab_Reference_Design_7.5.1.zip WARPLab_Reference_Design_7.5.1.zip]''' Release Details: ||= Hardware =||= Release =||= Date Posted =||= SVN Rev. =||= ISE Ver. =||= Arch =||= MATLAB Ver. =||= RF Interface Support =|| || WARP v3 || 7.5.1 || 12-Mar-2015 || [browser:ResearchApps/PHY/WARPLAB/WARPLab7?rev=4487 4487] || 14.4 || MB/AXI || 2009b or later || 1-2: WARP v3 on-board interfaces [[BR]] 3-4: Requires [wiki:HardwareUsersGuides/FMC-RF-2X245 FMC-RF-2X245] || || WARP v2 || 7.5.1 || 12-Mar-2015 || [browser:ResearchApps/PHY/WARPLAB/WARPLab7?rev=4487 4487] || 14.4 || PPC/PLB || 2009b or later || 1-2: Radios in slots 2 & 3 [[BR]] 3-4: Radios in slots 1 & 4 || '''WARPLab 7.5.1 for WARP v2''' aligns the WARP v2 peripherals with the WARPLab 7.5.0 WARP v3 peripherals. * Updated the [wiki:WARPLab/Porting#NewScriptConventionsinWARPLab7.5andBeyond Porting Guide] with new scripting conventions. In 7.5, these changes are optional so old scripts will work as-is. In future releases, these changes will be enforced. * Replaced the old WARPLab AGC core with a new core derived from the wlan_agc core in the 802.11 Reference Design. The System Generator model for the new core is available in the repository: [browser:ResearchApps/PHY/WARPLAB/WARPLab7/Sysgen_Reference/w2/warplab_agc_v3 warplab_agc_v3]. * Updated to version 3.04.a of the WARPxilnet library - be sure to update your [wiki:edk_user_repository edk_user_repository] before compiling the reference software project * NOTE: When rebuilding the BSP with the WARPxilnet library, in the Board Support Package Settings, the "ETH_B_uses_xilnet" should be set to zero (0) under the WARPxilnet settings since WARP v2 does not have a second Ethernet port. * Updated mapping of debug pins - see the WARPLab [wiki:../HardwareConfiguration/WARPv2 WARP v2 hardware] usage for details * Due to hardware limitations, WARP v2 still only supports 16 kB [wiki:WARPLab/BufferSizes buffer sizes] '''WARPLab 7.5.1 for WARP v3''' provides transport improvements to the existing WARPLab 7.5.0 design. Other changes: * Updated the radio controller core - be sure to update your [wiki:edk_user_repository edk_user_repository] before compiling the reference software project * Updated the Tigger Manager to split Ethernet and SW triggers. The SW trigger is not used by the reference design and is dedicated for use by custom user C code. * Updated MEX transport (see [wiki:WARPLab/Benchmarks Benchmarks]) - '''WARPLab 7.5.x requires MEX 1.0.2a''' * Improved Write IQ performance * Removed performance penalty when calling 'read_IQ' / 'write_IQ' with multiple buffers (ie when the transport had to iterate over multiple buffers in one call) * Updated Java transport (see [wiki:WARPLab/Benchmarks Benchmarks]) * Improved Write IQ performance * Improved Read IQ performance and removed performance issue for larger buffers * Added ability to auto-negotiate the Ethernet link speed. This feature is disabled by default because it added 1 to 2 seconds for the node to boot. To enable the feature, change the WL_NEGOTIATE_ETH_LINK_SPEED define to 1 in [http://warpproject.org/trac/browser/ResearchApps/PHY/WARPLAB/WARPLab7/C_Code_Reference/wl_node.c?rev=4487#L46 node.c] * Implemented fix for AXI Ethernet v3.01.a bug detailed in [http://www.xilinx.com/support/answers/56158.html Xilinx AR# 56158]. If rebuilding, the WARP v3 XPS project, it is suggested that users patch the AXI Ethernet core in their installation. The diff of the changes in the Ethernet core are: {{{ $ diff axi_ethernet_v3_01_a_v6_rx_axi_intf.v axi_ethernet_v3_01_a_v6_rx_axi_intf.orig 155c155 < if ((rx_good_frame | rx_bad_frame) && (rx_state != IDLE)) begin --- > if (rx_good_frame | rx_bad_frame) begin }}} * Cleaned up the code split between WARP v3 and WARP v2 hardware within the [http://warpproject.org/trac/browser/ResearchApps/PHY/WARPLAB/WARPLab7/C_Code_Reference?rev=4487 C code] * Cleaned up code examples and added more comments ---- == Reference Design Archive == The WARPLab reference design is packaged as a .zip file with the full source code and compiled bitstreams for the reference design. You can view the latest source code in the repository ([source:/ResearchApps/PHY/WARPLAB/WARPLab7]). Please note the code in the repository is under active development. The contents of the WARPLab reference design .zip file are explained below. === Bitstreams_Reference === Bitstreams are fully-built designs that are ready to be downloaded onto WARP hardware. Files ending with the extension '.bit' may be downloaded using the Xilinx tool iMPACT. Files ending with the extension .bin may loaded onto an SD card so that the WARP v3 hardware will automatically be programmed whenever it is powered on and has the SD card inserted. Details on how to configure an SD card with a '.bin' file are [wiki:howto/SD_Config provided here]. For WARP v2 hardware, compact flash cards may be loaded with the provided .ace files for similar functionality (instructions provided [wiki:howto/CF_Config here]). * '''w3''': WARP v3 FPGA bitstreams (see [wiki:howto/SD_Config SD config howto] for help using the .bin file) * '''w2''': WARP v2 FPGA bitstreams (see [wiki:howto/CF_Config CF config howto] for help using the .ace file) === EDK_Projects === This folder contains EDK projects for various hardware configurations. The WARPLab FPGA design is built with the Xilinx Embedded Development Kit (EDK) software. The hardware design is constructed and implemented in EDK Xilinx Platform Studio (XPS). The software design, running in the MicroBlaze processor, is built in the Xilinx SDK. Opening these EDK projects requires a copy of the [wiki:edk_user_repository WARP edk_user_repository] at the SVN revision in the table above. If you want to use (but not modify) the reference FPGA design, you only need a bitstream and the reference M code. If you want to modify the MicroBlaze/PPC C code, you can download an EDK project in this folder, but only modify the SDK project contained therein. To modify the FPGA hardware design, you will need to modify the XPS project. The WARPLab FPGA design uses custom peripherals designed in Xilinx System Generator, including the warplab_buffers core. You will need MATLAB, Simulink and System Generator to modify these cores. Each of these EDK projects are a combination of an XPS project along with Eclipse software projects that can be imported into an SDK workspace. These software projects are present in the 'SDK_Workspace' subfolder of every XPS project -- we recommend using this folder as the location of the SDK Workspace. These projects can then be imported "in place" and will not need to be copied. * '''w3''': WARP v3 EDK projects for the 2-radio (2RF) and 4-radio (4RF) WARPLab Reference Designs * '''w2''': WARP v2 EDK projects for the 2-radio (2RF) and 4-radio (4RF) WARPLab Reference Designs === M_Code_Examples === This folder contains example WARPLab scripts that are compatible with this release of WARPLab. Explanations of these scripts are [wiki:../Examples available here]. === M_Code_Reference === This folder contains all of the supporting files needed for WARPLab to run on a host PC with MATLAB. When downloading a new Reference Design Release, users will need to run the [wiki:../Reference/Utility#wl_setup wl_setup.m] script in this folder.