Version 1 (modified by welsh, 11 years ago) (diff) |
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WARPLab 7
- Downloads
Getting Started
- Sample Buffer Sizes
- Automatic Gain Control
- Examples
- Extending WARPLab
- Debugging Errors
- Porting Code
- Benchmarks
WARPLab 7 Framework
WARPLab 7 Reference Design
Reference Design Modules
- Node
Interface Group
Baseband
Transport
Trigger Manager
Hardware
WARPLab 7.3.0 FPGA Architecture for WARP v3 Hardware
The WARPLab 7.3.0 design for WARP v3 makes changes to the underlying FPGA architecture in order to improve performance for Read / Write IQ. This includes:
- Updates to the WARPLab Buffers core to move the Read / Write IQ memories out to the AXI interconnect
- Updates to the AXI Interconnect to allow DMA access to all the WARPLab Buffers
Interconnect Architecture
Address Map
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- WARPLab_7_3_0_interconnect_architecture.png (170.7 KB) - added by welsh 11 years ago.
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