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= WARPLab Reference Design Hardware Config: WARP v3 =

[[Image(WARP_v3_labelled.png)]]


=== Radio Interface ===

  * In the 2 RF Node configuration (ie only RF A and RF B are populated), you should only use the '''2RF bitstream''' in the [wiki:WARPLab/Downloads download].
  * In the 4 RF Node configuration (ie all RF interfaces are populated), you should only use the '''4RF bitstream''' in the [wiki:WARPLab/Downloads download]. 


=== Dip Switches ===

  * In WARPLab 7.1 and later, the dip switch value of 0xF (ie all switches set to '1'), is reserved for [wiki:WARPLab/Reference/NodesConfig dynamic node configuration].


=== Debug Header ===

''Updated for WARPLab 7.5'''

The [wiki:HardwareUsersGuides/WARPv3/DebugHeader debug header] is configured by default to map to the following pins:


[[Image(Debug_Header_Diagram.png)]]

|| [[Image(wiki:HardwareUsersGuides/WARPv3/files:important.png,nolink,valign=middle)]] || '''These pins are not 3.3v compatible! ''' You must use external level shifting to interface with non-2.5v signals. ||

[[Image(Debug_Header_Connections.png)]]

'''NOTE:''' The Debug Header is defined in the system.ucf and the connections are defined in the system.mhs

  * The Trigger output and Trigger input pins above are used with the [wiki:WARPLab/Reference/TriggerManager Trigger Manager]
  * The  [wiki:HardwareUsersGuides/CM-PLL CM-PLL Clock Module] shares FPGA I/O between boards as well as a clock reference. This allows easy node synchronization with a single cable. In WARPLab 7.5, the 4 trigger outputs are duplicated and sent to both the CM-PLL board as well as the debug header. The 4 trigger inputs are digitally ORed from pins connecting both the CM-PLL board as well as the debug header.


=== Clock Configuration ===

''Updated for WARPLab 7.5'''

The WARPLab reference design does not require any external clock connections. By default the reference design will use the oscillators on the WARP v3 board for all system and RF clocking. The reference design does support both sourcing and sinking external clocks for synchronization of multiple nodes. There are two hardware options for this synchronization: the [wiki:HardwareUsersGuides/CM-MMCX CM-MMCX Clock Module] and the [wiki:HardwareUsersGuides/CM-PLL CM-PLL Clock Module] 

'''[wiki:HardwareUsersGuides/CM-MMCX CM-MMCX Clock Module:]'''

The CM-MMCX is capable of sourcing and/or sinking RF and sampling clocks. This clock module can be used in a daisy chain configuration, where a single primary node shares its internal clocks with a chain of secondary nodes that adopt and forward the clocks. The role of each node is configured via the 2-position SIP switch on the CM-MMCX, according to the figure below.

  * Detailed information on the WARP v3 Clocking configuration can be found [wiki:HardwareUsersGuides/WARPv3/Clocking here].
  * To adjust the functionality, please use the following SIP switch settings:

[[Image(MMCX_v1_labelled.png)]]

'''[wiki:HardwareUsersGuides/CM-PLL CM-PLL Clock Module:] '''

The CM-MMCX is capable of sourcing and/or sinking a clock referenced used to discipline a PLL on each node. This clock module can be used in a daisy chain configuration, where a single primary node shares its clock reference with a chain of secondary nodes that adopt and forward the clock reference. The role of each node is configured via the 6-position SIP switch on the CM-PLL, according to the figure below.

  * Detailed information on the WARP v3 Clocking configuration can be found [wiki:HardwareUsersGuides/WARPv3/Clocking here].
  * To adjust the functionality, please use the following SIP switch settings:

[[Image(PLL_v1_labelled.png)]]

=== Ethernet ===

  * By default, only Ethernet connection A (Eth A) is used.